Macros
#define	ADC_MULTIMODE_SUPPORT

#define	ADC_ISR_ADRDY_Pos (0U)

#define	ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos)

#define	ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk

#define	ADC_ISR_EOSMP_Pos (1U)

#define	ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos)

#define	ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk

#define	ADC_ISR_EOC_Pos (2U)

#define	ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos)

#define	ADC_ISR_EOC ADC_ISR_EOC_Msk

#define	ADC_ISR_EOS_Pos (3U)

#define	ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos)

#define	ADC_ISR_EOS ADC_ISR_EOS_Msk

#define	ADC_ISR_OVR_Pos (4U)

#define	ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos)

#define	ADC_ISR_OVR ADC_ISR_OVR_Msk

#define	ADC_ISR_JEOC_Pos (5U)

#define	ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos)

#define	ADC_ISR_JEOC ADC_ISR_JEOC_Msk

#define	ADC_ISR_JEOS_Pos (6U)

#define	ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos)

#define	ADC_ISR_JEOS ADC_ISR_JEOS_Msk

#define	ADC_ISR_AWD1_Pos (7U)

#define	ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos)

#define	ADC_ISR_AWD1 ADC_ISR_AWD1_Msk

#define	ADC_ISR_AWD2_Pos (8U)

#define	ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos)

#define	ADC_ISR_AWD2 ADC_ISR_AWD2_Msk

#define	ADC_ISR_AWD3_Pos (9U)

#define	ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos)

#define	ADC_ISR_AWD3 ADC_ISR_AWD3_Msk

#define	ADC_ISR_JQOVF_Pos (10U)

#define	ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos)

#define	ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk

#define	ADC_IER_ADRDYIE_Pos (0U)

#define	ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos)

#define	ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk

#define	ADC_IER_EOSMPIE_Pos (1U)

#define	ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos)

#define	ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk

#define	ADC_IER_EOCIE_Pos (2U)

#define	ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos)

#define	ADC_IER_EOCIE ADC_IER_EOCIE_Msk

#define	ADC_IER_EOSIE_Pos (3U)

#define	ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos)

#define	ADC_IER_EOSIE ADC_IER_EOSIE_Msk

#define	ADC_IER_OVRIE_Pos (4U)

#define	ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos)

#define	ADC_IER_OVRIE ADC_IER_OVRIE_Msk

#define	ADC_IER_JEOCIE_Pos (5U)

#define	ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos)

#define	ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk

#define	ADC_IER_JEOSIE_Pos (6U)

#define	ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos)

#define	ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk

#define	ADC_IER_AWD1IE_Pos (7U)

#define	ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos)

#define	ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk

#define	ADC_IER_AWD2IE_Pos (8U)

#define	ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos)

#define	ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk

#define	ADC_IER_AWD3IE_Pos (9U)

#define	ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos)

#define	ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk

#define	ADC_IER_JQOVFIE_Pos (10U)

#define	ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos)

#define	ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk

#define	ADC_CR_ADEN_Pos (0U)

#define	ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos)

#define	ADC_CR_ADEN ADC_CR_ADEN_Msk

#define	ADC_CR_ADDIS_Pos (1U)

#define	ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos)

#define	ADC_CR_ADDIS ADC_CR_ADDIS_Msk

#define	ADC_CR_ADSTART_Pos (2U)

#define	ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos)

#define	ADC_CR_ADSTART ADC_CR_ADSTART_Msk

#define	ADC_CR_JADSTART_Pos (3U)

#define	ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos)

#define	ADC_CR_JADSTART ADC_CR_JADSTART_Msk

#define	ADC_CR_ADSTP_Pos (4U)

#define	ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos)

#define	ADC_CR_ADSTP ADC_CR_ADSTP_Msk

#define	ADC_CR_JADSTP_Pos (5U)

#define	ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos)

#define	ADC_CR_JADSTP ADC_CR_JADSTP_Msk

#define	ADC_CR_ADVREGEN_Pos (28U)

#define	ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos)

#define	ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk

#define	ADC_CR_DEEPPWD_Pos (29U)

#define	ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos)

#define	ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk

#define	ADC_CR_ADCALDIF_Pos (30U)

#define	ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos)

#define	ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk

#define	ADC_CR_ADCAL_Pos (31U)

#define	ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos)

#define	ADC_CR_ADCAL ADC_CR_ADCAL_Msk

#define	ADC_CFGR_DMAEN_Pos (0U)

#define	ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos)

#define	ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk

#define	ADC_CFGR_DMACFG_Pos (1U)

#define	ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos)

#define	ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk

#define	ADC_CFGR_RES_Pos (3U)

#define	ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos)

#define	ADC_CFGR_RES ADC_CFGR_RES_Msk

#define	ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos)

#define	ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos)

#define	ADC_CFGR_EXTSEL_Pos (5U)

#define	ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos)

#define	ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk

#define	ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos)

#define	ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos)

#define	ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos)

#define	ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos)

#define	ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos)

#define	ADC_CFGR_EXTEN_Pos (10U)

#define	ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos)

#define	ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk

#define	ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos)

#define	ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos)

#define	ADC_CFGR_OVRMOD_Pos (12U)

#define	ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos)

#define	ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk

#define	ADC_CFGR_CONT_Pos (13U)

#define	ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos)

#define	ADC_CFGR_CONT ADC_CFGR_CONT_Msk

#define	ADC_CFGR_AUTDLY_Pos (14U)

#define	ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos)

#define	ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk

#define	ADC_CFGR_ALIGN_Pos (15U)

#define	ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos)

#define	ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk

#define	ADC_CFGR_DISCEN_Pos (16U)

#define	ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos)

#define	ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk

#define	ADC_CFGR_DISCNUM_Pos (17U)

#define	ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos)

#define	ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk

#define	ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos)

#define	ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos)

#define	ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos)

#define	ADC_CFGR_JDISCEN_Pos (20U)

#define	ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos)

#define	ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk

#define	ADC_CFGR_JQM_Pos (21U)

#define	ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos)

#define	ADC_CFGR_JQM ADC_CFGR_JQM_Msk

#define	ADC_CFGR_AWD1SGL_Pos (22U)

#define	ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos)

#define	ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk

#define	ADC_CFGR_AWD1EN_Pos (23U)

#define	ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos)

#define	ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk

#define	ADC_CFGR_JAWD1EN_Pos (24U)

#define	ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos)

#define	ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk

#define	ADC_CFGR_JAUTO_Pos (25U)

#define	ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos)

#define	ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk

#define	ADC_CFGR_AWD1CH_Pos (26U)

#define	ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos)

#define	ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk

#define	ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos)

#define	ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos)

#define	ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos)

#define	ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos)

#define	ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos)

#define	ADC_CFGR_JQDIS_Pos (31U)

#define	ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos)

#define	ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk

#define	ADC_CFGR2_ROVSE_Pos (0U)

#define	ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos)

#define	ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk

#define	ADC_CFGR2_JOVSE_Pos (1U)

#define	ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos)

#define	ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk

#define	ADC_CFGR2_OVSR_Pos (2U)

#define	ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos)

#define	ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk

#define	ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos)

#define	ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos)

#define	ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos)

#define	ADC_CFGR2_OVSS_Pos (5U)

#define	ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos)

#define	ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk

#define	ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos)

#define	ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos)

#define	ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos)

#define	ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos)

#define	ADC_CFGR2_TROVS_Pos (9U)

#define	ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos)

#define	ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk

#define	ADC_CFGR2_ROVSM_Pos (10U)

#define	ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos)

#define	ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk

#define	ADC_CFGR2_GCOMP_Pos (16U)

#define	ADC_CFGR2_GCOMP_Msk (0x1UL << ADC_CFGR2_GCOMP_Pos)

#define	ADC_CFGR2_GCOMP ADC_CFGR2_GCOMP_Msk

#define	ADC_CFGR2_SWTRIG_Pos (25U)

#define	ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos)

#define	ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk

#define	ADC_CFGR2_BULB_Pos (26U)

#define	ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos)

#define	ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk

#define	ADC_CFGR2_SMPTRIG_Pos (27U)

#define	ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos)

#define	ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk

#define	ADC_SMPR1_SMP0_Pos (0U)

#define	ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos)

#define	ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk

#define	ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos)

#define	ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos)

#define	ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos)

#define	ADC_SMPR1_SMP1_Pos (3U)

#define	ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos)

#define	ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk

#define	ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos)

#define	ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos)

#define	ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos)

#define	ADC_SMPR1_SMP2_Pos (6U)

#define	ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos)

#define	ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk

#define	ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos)

#define	ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos)

#define	ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos)

#define	ADC_SMPR1_SMP3_Pos (9U)

#define	ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos)

#define	ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk

#define	ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos)

#define	ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos)

#define	ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos)

#define	ADC_SMPR1_SMP4_Pos (12U)

#define	ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos)

#define	ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk

#define	ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos)

#define	ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos)

#define	ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos)

#define	ADC_SMPR1_SMP5_Pos (15U)

#define	ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos)

#define	ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk

#define	ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos)

#define	ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos)

#define	ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos)

#define	ADC_SMPR1_SMP6_Pos (18U)

#define	ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos)

#define	ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk

#define	ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos)

#define	ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos)

#define	ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos)

#define	ADC_SMPR1_SMP7_Pos (21U)

#define	ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos)

#define	ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk

#define	ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos)

#define	ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos)

#define	ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos)

#define	ADC_SMPR1_SMP8_Pos (24U)

#define	ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos)

#define	ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk

#define	ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos)

#define	ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos)

#define	ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos)

#define	ADC_SMPR1_SMP9_Pos (27U)

#define	ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos)

#define	ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk

#define	ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos)

#define	ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos)

#define	ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos)

#define	ADC_SMPR1_SMPPLUS_Pos (31U)

#define	ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos)

#define	ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk

#define	ADC_SMPR2_SMP10_Pos (0U)

#define	ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos)

#define	ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk

#define	ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos)

#define	ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos)

#define	ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos)

#define	ADC_SMPR2_SMP11_Pos (3U)

#define	ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos)

#define	ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk

#define	ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos)

#define	ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos)

#define	ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos)

#define	ADC_SMPR2_SMP12_Pos (6U)

#define	ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos)

#define	ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk

#define	ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos)

#define	ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos)

#define	ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos)

#define	ADC_SMPR2_SMP13_Pos (9U)

#define	ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos)

#define	ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk

#define	ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos)

#define	ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos)

#define	ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos)

#define	ADC_SMPR2_SMP14_Pos (12U)

#define	ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos)

#define	ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk

#define	ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos)

#define	ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos)

#define	ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos)

#define	ADC_SMPR2_SMP15_Pos (15U)

#define	ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos)

#define	ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk

#define	ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos)

#define	ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos)

#define	ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos)

#define	ADC_SMPR2_SMP16_Pos (18U)

#define	ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos)

#define	ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk

#define	ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos)

#define	ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos)

#define	ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos)

#define	ADC_SMPR2_SMP17_Pos (21U)

#define	ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos)

#define	ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk

#define	ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos)

#define	ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos)

#define	ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos)

#define	ADC_SMPR2_SMP18_Pos (24U)

#define	ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos)

#define	ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk

#define	ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos)

#define	ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos)

#define	ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos)

#define	ADC_TR1_LT1_Pos (0U)

#define	ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos)

#define	ADC_TR1_LT1 ADC_TR1_LT1_Msk

#define	ADC_TR1_AWDFILT_Pos (12U)

#define	ADC_TR1_AWDFILT_Msk (0x7UL << ADC_TR1_AWDFILT_Pos)

#define	ADC_TR1_AWDFILT ADC_TR1_AWDFILT_Msk

#define	ADC_TR1_AWDFILT_0 (0x1UL << ADC_TR1_AWDFILT_Pos)

#define	ADC_TR1_AWDFILT_1 (0x2UL << ADC_TR1_AWDFILT_Pos)

#define	ADC_TR1_AWDFILT_2 (0x4UL << ADC_TR1_AWDFILT_Pos)

#define	ADC_TR1_HT1_Pos (16U)

#define	ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos)

#define	ADC_TR1_HT1 ADC_TR1_HT1_Msk

#define	ADC_TR2_LT2_Pos (0U)

#define	ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos)

#define	ADC_TR2_LT2 ADC_TR2_LT2_Msk

#define	ADC_TR2_HT2_Pos (16U)

#define	ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos)

#define	ADC_TR2_HT2 ADC_TR2_HT2_Msk

#define	ADC_TR3_LT3_Pos (0U)

#define	ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos)

#define	ADC_TR3_LT3 ADC_TR3_LT3_Msk

#define	ADC_TR3_HT3_Pos (16U)

#define	ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos)

#define	ADC_TR3_HT3 ADC_TR3_HT3_Msk

#define	ADC_SQR1_L_Pos (0U)

#define	ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos)

#define	ADC_SQR1_L ADC_SQR1_L_Msk

#define	ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos)

#define	ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos)

#define	ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos)

#define	ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos)

#define	ADC_SQR1_SQ1_Pos (6U)

#define	ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos)

#define	ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk

#define	ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos)

#define	ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos)

#define	ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos)

#define	ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos)

#define	ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos)

#define	ADC_SQR1_SQ2_Pos (12U)

#define	ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos)

#define	ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk

#define	ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos)

#define	ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos)

#define	ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos)

#define	ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos)

#define	ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos)

#define	ADC_SQR1_SQ3_Pos (18U)

#define	ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos)

#define	ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk

#define	ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos)

#define	ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos)

#define	ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos)

#define	ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos)

#define	ADC_SQR1_SQ3_4 (0x10UL<< ADC_SQR1_SQ3_Pos)

#define	ADC_SQR1_SQ4_Pos (24U)

#define	ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos)

#define	ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk

#define	ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos)

#define	ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos)

#define	ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos)

#define	ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos)

#define	ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos)

#define	ADC_SQR2_SQ5_Pos (0U)

#define	ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos)

#define	ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk

#define	ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos)

#define	ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos)

#define	ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos)

#define	ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos)

#define	ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos)

#define	ADC_SQR2_SQ6_Pos (6U)

#define	ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos)

#define	ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk

#define	ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos)

#define	ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos)

#define	ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos)

#define	ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos)

#define	ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos)

#define	ADC_SQR2_SQ7_Pos (12U)

#define	ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos)

#define	ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk

#define	ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos)

#define	ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos)

#define	ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos)

#define	ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos)

#define	ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos)

#define	ADC_SQR2_SQ8_Pos (18U)

#define	ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos)

#define	ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk

#define	ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos)

#define	ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos)

#define	ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos)

#define	ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos)

#define	ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos)

#define	ADC_SQR2_SQ9_Pos (24U)

#define	ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos)

#define	ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk

#define	ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos)

#define	ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos)

#define	ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos)

#define	ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos)

#define	ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos)

#define	ADC_SQR3_SQ10_Pos (0U)

#define	ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos)

#define	ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk

#define	ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos)

#define	ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos)

#define	ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos)

#define	ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos)

#define	ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos)

#define	ADC_SQR3_SQ11_Pos (6U)

#define	ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos)

#define	ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk

#define	ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos)

#define	ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos)

#define	ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos)

#define	ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos)

#define	ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos)

#define	ADC_SQR3_SQ12_Pos (12U)

#define	ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos)

#define	ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk

#define	ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos)

#define	ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos)

#define	ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos)

#define	ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos)

#define	ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos)

#define	ADC_SQR3_SQ13_Pos (18U)

#define	ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos)

#define	ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk

#define	ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos)

#define	ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos)

#define	ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos)

#define	ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos)

#define	ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos)

#define	ADC_SQR3_SQ14_Pos (24U)

#define	ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos)

#define	ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk

#define	ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos)

#define	ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos)

#define	ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos)

#define	ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos)

#define	ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos)

#define	ADC_SQR4_SQ15_Pos (0U)

#define	ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos)

#define	ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk

#define	ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos)

#define	ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos)

#define	ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos)

#define	ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos)

#define	ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos)

#define	ADC_SQR4_SQ16_Pos (6U)

#define	ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos)

#define	ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk

#define	ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos)

#define	ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos)

#define	ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos)

#define	ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos)

#define	ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos)

#define	ADC_DR_RDATA_Pos (0U)

#define	ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos)

#define	ADC_DR_RDATA ADC_DR_RDATA_Msk

#define	ADC_JSQR_JL_Pos (0U)

#define	ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos)

#define	ADC_JSQR_JL ADC_JSQR_JL_Msk

#define	ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos)

#define	ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos)

#define	ADC_JSQR_JEXTSEL_Pos (2U)

#define	ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos)

#define	ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk

#define	ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos)

#define	ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos)

#define	ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos)

#define	ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos)

#define	ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos)

#define	ADC_JSQR_JEXTEN_Pos (7U)

#define	ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos)

#define	ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk

#define	ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos)

#define	ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos)

#define	ADC_JSQR_JSQ1_Pos (9U)

#define	ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos)

#define	ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk

#define	ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos)

#define	ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos)

#define	ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos)

#define	ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos)

#define	ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos)

#define	ADC_JSQR_JSQ2_Pos (15U)

#define	ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos)

#define	ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk

#define	ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos)

#define	ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos)

#define	ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos)

#define	ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos)

#define	ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos)

#define	ADC_JSQR_JSQ3_Pos (21U)

#define	ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos)

#define	ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk

#define	ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos)

#define	ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos)

#define	ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos)

#define	ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos)

#define	ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos)

#define	ADC_JSQR_JSQ4_Pos (27U)

#define	ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos)

#define	ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk

#define	ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos)

#define	ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos)

#define	ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos)

#define	ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos)

#define	ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos)

#define	ADC_OFR1_OFFSET1_Pos (0U)

#define	ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos)

#define	ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk

#define	ADC_OFR1_OFFSETPOS_Pos (24U)

#define	ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos)

#define	ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk

#define	ADC_OFR1_SATEN_Pos (25U)

#define	ADC_OFR1_SATEN_Msk (0x1UL << ADC_OFR1_SATEN_Pos)

#define	ADC_OFR1_SATEN ADC_OFR1_SATEN_Msk

#define	ADC_OFR1_OFFSET1_CH_Pos (26U)

#define	ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)

#define	ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk

#define	ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)

#define	ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)

#define	ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)

#define	ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)

#define	ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)

#define	ADC_OFR1_OFFSET1_EN_Pos (31U)

#define	ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos)

#define	ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk

#define	ADC_OFR2_OFFSET2_Pos (0U)

#define	ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos)

#define	ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk

#define	ADC_OFR2_OFFSETPOS_Pos (24U)

#define	ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos)

#define	ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk

#define	ADC_OFR2_SATEN_Pos (25U)

#define	ADC_OFR2_SATEN_Msk (0x1UL << ADC_OFR2_SATEN_Pos)

#define	ADC_OFR2_SATEN ADC_OFR2_SATEN_Msk

#define	ADC_OFR2_OFFSET2_CH_Pos (26U)

#define	ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)

#define	ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk

#define	ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)

#define	ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)

#define	ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)

#define	ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)

#define	ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)

#define	ADC_OFR2_OFFSET2_EN_Pos (31U)

#define	ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos)

#define	ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk

#define	ADC_OFR3_OFFSET3_Pos (0U)

#define	ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos)

#define	ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk

#define	ADC_OFR3_OFFSETPOS_Pos (24U)

#define	ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos)

#define	ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk

#define	ADC_OFR3_SATEN_Pos (25U)

#define	ADC_OFR3_SATEN_Msk (0x1UL << ADC_OFR3_SATEN_Pos)

#define	ADC_OFR3_SATEN ADC_OFR3_SATEN_Msk

#define	ADC_OFR3_OFFSET3_CH_Pos (26U)

#define	ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)

#define	ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk

#define	ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)

#define	ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)

#define	ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)

#define	ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)

#define	ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)

#define	ADC_OFR3_OFFSET3_EN_Pos (31U)

#define	ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos)

#define	ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk

#define	ADC_OFR4_OFFSET4_Pos (0U)

#define	ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos)

#define	ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk

#define	ADC_OFR4_OFFSETPOS_Pos (24U)

#define	ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos)

#define	ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk

#define	ADC_OFR4_SATEN_Pos (25U)

#define	ADC_OFR4_SATEN_Msk (0x1UL << ADC_OFR4_SATEN_Pos)

#define	ADC_OFR4_SATEN ADC_OFR4_SATEN_Msk

#define	ADC_OFR4_OFFSET4_CH_Pos (26U)

#define	ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)

#define	ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk

#define	ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)

#define	ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)

#define	ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)

#define	ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)

#define	ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)

#define	ADC_OFR4_OFFSET4_EN_Pos (31U)

#define	ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos)

#define	ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk

#define	ADC_JDR1_JDATA_Pos (0U)

#define	ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos)

#define	ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk

#define	ADC_JDR2_JDATA_Pos (0U)

#define	ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos)

#define	ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk

#define	ADC_JDR3_JDATA_Pos (0U)

#define	ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos)

#define	ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk

#define	ADC_JDR4_JDATA_Pos (0U)

#define	ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos)

#define	ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk

#define	ADC_AWD2CR_AWD2CH_Pos (0U)

#define	ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk

#define	ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)

#define	ADC_AWD3CR_AWD3CH_Pos (0U)

#define	ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk

#define	ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)

#define	ADC_DIFSEL_DIFSEL_Pos (0U)

#define	ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk

#define	ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)

#define	ADC_CALFACT_CALFACT_S_Pos (0U)

#define	ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos)

#define	ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk

#define	ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos)

#define	ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos)

#define	ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos)

#define	ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos)

#define	ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos)

#define	ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos)

#define	ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos)

#define	ADC_CALFACT_CALFACT_D_Pos (16U)

#define	ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos)

#define	ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk

#define	ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos)

#define	ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos)

#define	ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos)

#define	ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos)

#define	ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos)

#define	ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos)

#define	ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos)

#define	ADC_GCOMP_GCOMPCOEFF_Pos (0U)

#define	ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos)

#define	ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk

#define	ADC_CSR_ADRDY_MST_Pos (0U)

#define	ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos)

#define	ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk

#define	ADC_CSR_EOSMP_MST_Pos (1U)

#define	ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos)

#define	ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk

#define	ADC_CSR_EOC_MST_Pos (2U)

#define	ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos)

#define	ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk

#define	ADC_CSR_EOS_MST_Pos (3U)

#define	ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos)

#define	ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk

#define	ADC_CSR_OVR_MST_Pos (4U)

#define	ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos)

#define	ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk

#define	ADC_CSR_JEOC_MST_Pos (5U)

#define	ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos)

#define	ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk

#define	ADC_CSR_JEOS_MST_Pos (6U)

#define	ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos)

#define	ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk

#define	ADC_CSR_AWD1_MST_Pos (7U)

#define	ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos)

#define	ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk

#define	ADC_CSR_AWD2_MST_Pos (8U)

#define	ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos)

#define	ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk

#define	ADC_CSR_AWD3_MST_Pos (9U)

#define	ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos)

#define	ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk

#define	ADC_CSR_JQOVF_MST_Pos (10U)

#define	ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos)

#define	ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk

#define	ADC_CSR_ADRDY_SLV_Pos (16U)

#define	ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos)

#define	ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk

#define	ADC_CSR_EOSMP_SLV_Pos (17U)

#define	ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos)

#define	ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk

#define	ADC_CSR_EOC_SLV_Pos (18U)

#define	ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos)

#define	ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk

#define	ADC_CSR_EOS_SLV_Pos (19U)

#define	ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos)

#define	ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk

#define	ADC_CSR_OVR_SLV_Pos (20U)

#define	ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos)

#define	ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk

#define	ADC_CSR_JEOC_SLV_Pos (21U)

#define	ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos)

#define	ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk

#define	ADC_CSR_JEOS_SLV_Pos (22U)

#define	ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos)

#define	ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk

#define	ADC_CSR_AWD1_SLV_Pos (23U)

#define	ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos)

#define	ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk

#define	ADC_CSR_AWD2_SLV_Pos (24U)

#define	ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos)

#define	ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk

#define	ADC_CSR_AWD3_SLV_Pos (25U)

#define	ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos)

#define	ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk

#define	ADC_CSR_JQOVF_SLV_Pos (26U)

#define	ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos)

#define	ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk

#define	ADC_CCR_DUAL_Pos (0U)

#define	ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos)

#define	ADC_CCR_DUAL ADC_CCR_DUAL_Msk

#define	ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos)

#define	ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos)

#define	ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos)

#define	ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos)

#define	ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos)

#define	ADC_CCR_DELAY_Pos (8U)

#define	ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos)

#define	ADC_CCR_DELAY ADC_CCR_DELAY_Msk

#define	ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos)

#define	ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos)

#define	ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos)

#define	ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos)

#define	ADC_CCR_DMACFG_Pos (13U)

#define	ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos)

#define	ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk

#define	ADC_CCR_MDMA_Pos (14U)

#define	ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos)

#define	ADC_CCR_MDMA ADC_CCR_MDMA_Msk

#define	ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos)

#define	ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos)

#define	ADC_CCR_CKMODE_Pos (16U)

#define	ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos)

#define	ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk

#define	ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos)

#define	ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos)

#define	ADC_CCR_PRESC_Pos (18U)

#define	ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos)

#define	ADC_CCR_PRESC ADC_CCR_PRESC_Msk

#define	ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos)

#define	ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos)

#define	ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos)

#define	ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos)

#define	ADC_CCR_VREFEN_Pos (22U)

#define	ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos)

#define	ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk

#define	ADC_CCR_VSENSESEL_Pos (23U)

#define	ADC_CCR_VSENSESEL_Msk (0x1UL << ADC_CCR_VSENSESEL_Pos)

#define	ADC_CCR_VSENSESEL ADC_CCR_VSENSESEL_Msk

#define	ADC_CCR_VBATSEL_Pos (24U)

#define	ADC_CCR_VBATSEL_Msk (0x1UL << ADC_CCR_VBATSEL_Pos)

#define	ADC_CCR_VBATSEL ADC_CCR_VBATSEL_Msk

#define	ADC_CDR_RDATA_MST_Pos (0U)

#define	ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)

#define	ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk

#define	ADC_CDR_RDATA_SLV_Pos (16U)

#define	ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)

#define	ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk

#define	COMP_CSR_EN_Pos (0U)

#define	COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos)

#define	COMP_CSR_EN COMP_CSR_EN_Msk

#define	COMP_CSR_INMSEL_Pos (4U)

#define	COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos)

#define	COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk

#define	COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos)

#define	COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos)

#define	COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos)

#define	COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos)

#define	COMP_CSR_INPSEL_Pos (8U)

#define	COMP_CSR_INPSEL_Msk (0x1UL << COMP_CSR_INPSEL_Pos)

#define	COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk

#define	COMP_CSR_POLARITY_Pos (15U)

#define	COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos)

#define	COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk

#define	COMP_CSR_HYST_Pos (16U)

#define	COMP_CSR_HYST_Msk (0x7UL << COMP_CSR_HYST_Pos)

#define	COMP_CSR_HYST COMP_CSR_HYST_Msk

#define	COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos)

#define	COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos)

#define	COMP_CSR_HYST_2 (0x4UL << COMP_CSR_HYST_Pos)

#define	COMP_CSR_BLANKING_Pos (19U)

#define	COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos)

#define	COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk

#define	COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos)

#define	COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos)

#define	COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos)

#define	COMP_CSR_BRGEN_Pos (22U)

#define	COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos)

#define	COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk

#define	COMP_CSR_SCALEN_Pos (23U)

#define	COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos)

#define	COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk

#define	COMP_CSR_VALUE_Pos (30U)

#define	COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos)

#define	COMP_CSR_VALUE COMP_CSR_VALUE_Msk

#define	COMP_CSR_LOCK_Pos (31U)

#define	COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos)

#define	COMP_CSR_LOCK COMP_CSR_LOCK_Msk

#define	CORDIC_CSR_FUNC_Pos (0U)

#define	CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos)

#define	CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk

#define	CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos)

#define	CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos)

#define	CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos)

#define	CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos)

#define	CORDIC_CSR_PRECISION_Pos (4U)

#define	CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos)

#define	CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk

#define	CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos)

#define	CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos)

#define	CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos)

#define	CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos)

#define	CORDIC_CSR_SCALE_Pos (8U)

#define	CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos)

#define	CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk

#define	CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos)

#define	CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos)

#define	CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos)

#define	CORDIC_CSR_IEN_Pos (16U)

#define	CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos)

#define	CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk

#define	CORDIC_CSR_DMAREN_Pos (17U)

#define	CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos)

#define	CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk

#define	CORDIC_CSR_DMAWEN_Pos (18U)

#define	CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos)

#define	CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk

#define	CORDIC_CSR_NRES_Pos (19U)

#define	CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos)

#define	CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk

#define	CORDIC_CSR_NARGS_Pos (20U)

#define	CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos)

#define	CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk

#define	CORDIC_CSR_RESSIZE_Pos (21U)

#define	CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos)

#define	CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk

#define	CORDIC_CSR_ARGSIZE_Pos (22U)

#define	CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos)

#define	CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk

#define	CORDIC_CSR_RRDY_Pos (31U)

#define	CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos)

#define	CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk

#define	CORDIC_WDATA_ARG_Pos (0U)

#define	CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos)

#define	CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk

#define	CORDIC_RDATA_RES_Pos (0U)

#define	CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos)

#define	CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk

#define	CRC_DR_DR_Pos (0U)

#define	CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos)

#define	CRC_DR_DR CRC_DR_DR_Msk

#define	CRC_IDR_IDR_Pos (0U)

#define	CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)

#define	CRC_IDR_IDR CRC_IDR_IDR_Msk

#define	CRC_CR_RESET_Pos (0U)

#define	CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos)

#define	CRC_CR_RESET CRC_CR_RESET_Msk

#define	CRC_CR_POLYSIZE_Pos (3U)

#define	CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos)

#define	CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk

#define	CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos)

#define	CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos)

#define	CRC_CR_REV_IN_Pos (5U)

#define	CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos)

#define	CRC_CR_REV_IN CRC_CR_REV_IN_Msk

#define	CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos)

#define	CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos)

#define	CRC_CR_REV_OUT_Pos (7U)

#define	CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos)

#define	CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk

#define	CRC_INIT_INIT_Pos (0U)

#define	CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)

#define	CRC_INIT_INIT CRC_INIT_INIT_Msk

#define	CRC_POL_POL_Pos (0U)

#define	CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos)

#define	CRC_POL_POL CRC_POL_POL_Msk

#define	CRS_CR_SYNCOKIE_Pos (0U)

#define	CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos)

#define	CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk

#define	CRS_CR_SYNCWARNIE_Pos (1U)

#define	CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos)

#define	CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk

#define	CRS_CR_ERRIE_Pos (2U)

#define	CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos)

#define	CRS_CR_ERRIE CRS_CR_ERRIE_Msk

#define	CRS_CR_ESYNCIE_Pos (3U)

#define	CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos)

#define	CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk

#define	CRS_CR_CEN_Pos (5U)

#define	CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos)

#define	CRS_CR_CEN CRS_CR_CEN_Msk

#define	CRS_CR_AUTOTRIMEN_Pos (6U)

#define	CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos)

#define	CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk

#define	CRS_CR_SWSYNC_Pos (7U)

#define	CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos)

#define	CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk

#define	CRS_CR_TRIM_Pos (8U)

#define	CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos)

#define	CRS_CR_TRIM CRS_CR_TRIM_Msk

#define	CRS_CFGR_RELOAD_Pos (0U)

#define	CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos)

#define	CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk

#define	CRS_CFGR_FELIM_Pos (16U)

#define	CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos)

#define	CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk

#define	CRS_CFGR_SYNCDIV_Pos (24U)

#define	CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos)

#define	CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk

#define	CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos)

#define	CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos)

#define	CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos)

#define	CRS_CFGR_SYNCSRC_Pos (28U)

#define	CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos)

#define	CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk

#define	CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos)

#define	CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos)

#define	CRS_CFGR_SYNCPOL_Pos (31U)

#define	CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos)

#define	CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk

#define	CRS_ISR_SYNCOKF_Pos (0U)

#define	CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos)

#define	CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk

#define	CRS_ISR_SYNCWARNF_Pos (1U)

#define	CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos)

#define	CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk

#define	CRS_ISR_ERRF_Pos (2U)

#define	CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos)

#define	CRS_ISR_ERRF CRS_ISR_ERRF_Msk

#define	CRS_ISR_ESYNCF_Pos (3U)

#define	CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos)

#define	CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk

#define	CRS_ISR_SYNCERR_Pos (8U)

#define	CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos)

#define	CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk

#define	CRS_ISR_SYNCMISS_Pos (9U)

#define	CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos)

#define	CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk

#define	CRS_ISR_TRIMOVF_Pos (10U)

#define	CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos)

#define	CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk

#define	CRS_ISR_FEDIR_Pos (15U)

#define	CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos)

#define	CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk

#define	CRS_ISR_FECAP_Pos (16U)

#define	CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos)

#define	CRS_ISR_FECAP CRS_ISR_FECAP_Msk

#define	CRS_ICR_SYNCOKC_Pos (0U)

#define	CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos)

#define	CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk

#define	CRS_ICR_SYNCWARNC_Pos (1U)

#define	CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos)

#define	CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk

#define	CRS_ICR_ERRC_Pos (2U)

#define	CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos)

#define	CRS_ICR_ERRC CRS_ICR_ERRC_Msk

#define	CRS_ICR_ESYNCC_Pos (3U)

#define	CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos)

#define	CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk

#define	DAC_CHANNEL2_SUPPORT

#define	DAC_CR_EN1_Pos (0U)

#define	DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos)

#define	DAC_CR_EN1 DAC_CR_EN1_Msk

#define	DAC_CR_TEN1_Pos (1U)

#define	DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos)

#define	DAC_CR_TEN1 DAC_CR_TEN1_Msk

#define	DAC_CR_TSEL1_Pos (2U)

#define	DAC_CR_TSEL1_Msk (0xFUL << DAC_CR_TSEL1_Pos)

#define	DAC_CR_TSEL1 DAC_CR_TSEL1_Msk

#define	DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos)

#define	DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos)

#define	DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos)

#define	DAC_CR_TSEL1_3 (0x8UL << DAC_CR_TSEL1_Pos)

#define	DAC_CR_WAVE1_Pos (6U)

#define	DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos)

#define	DAC_CR_WAVE1 DAC_CR_WAVE1_Msk

#define	DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos)

#define	DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos)

#define	DAC_CR_MAMP1_Pos (8U)

#define	DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos)

#define	DAC_CR_MAMP1 DAC_CR_MAMP1_Msk

#define	DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos)

#define	DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos)

#define	DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos)

#define	DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos)

#define	DAC_CR_DMAEN1_Pos (12U)

#define	DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos)

#define	DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk

#define	DAC_CR_DMAUDRIE1_Pos (13U)

#define	DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos)

#define	DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk

#define	DAC_CR_CEN1_Pos (14U)

#define	DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos)

#define	DAC_CR_CEN1 DAC_CR_CEN1_Msk

#define	DAC_CR_HFSEL_Pos (15U)

#define	DAC_CR_HFSEL_Msk (0x1UL << DAC_CR_HFSEL_Pos)

#define	DAC_CR_HFSEL DAC_CR_HFSEL_Msk

#define	DAC_CR_EN2_Pos (16U)

#define	DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos)

#define	DAC_CR_EN2 DAC_CR_EN2_Msk

#define	DAC_CR_TEN2_Pos (17U)

#define	DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos)

#define	DAC_CR_TEN2 DAC_CR_TEN2_Msk

#define	DAC_CR_TSEL2_Pos (18U)

#define	DAC_CR_TSEL2_Msk (0xFUL << DAC_CR_TSEL2_Pos)

#define	DAC_CR_TSEL2 DAC_CR_TSEL2_Msk

#define	DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos)

#define	DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos)

#define	DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos)

#define	DAC_CR_TSEL2_3 (0x8UL << DAC_CR_TSEL2_Pos)

#define	DAC_CR_WAVE2_Pos (22U)

#define	DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos)

#define	DAC_CR_WAVE2 DAC_CR_WAVE2_Msk

#define	DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos)

#define	DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos)

#define	DAC_CR_MAMP2_Pos (24U)

#define	DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos)

#define	DAC_CR_MAMP2 DAC_CR_MAMP2_Msk

#define	DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos)

#define	DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos)

#define	DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos)

#define	DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos)

#define	DAC_CR_DMAEN2_Pos (28U)

#define	DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos)

#define	DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk

#define	DAC_CR_DMAUDRIE2_Pos (29U)

#define	DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos)

#define	DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk

#define	DAC_CR_CEN2_Pos (30U)

#define	DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos)

#define	DAC_CR_CEN2 DAC_CR_CEN2_Msk

#define	DAC_SWTRIGR_SWTRIG1_Pos (0U)

#define	DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)

#define	DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk

#define	DAC_SWTRIGR_SWTRIG2_Pos (1U)

#define	DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)

#define	DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk

#define	DAC_SWTRIGR_SWTRIGB1_Pos (16U)

#define	DAC_SWTRIGR_SWTRIGB1_Msk (0x1UL << DAC_SWTRIGR_SWTRIGB1_Pos)

#define	DAC_SWTRIGR_SWTRIGB1 DAC_SWTRIGR_SWTRIGB1_Msk

#define	DAC_SWTRIGR_SWTRIGB2_Pos (17U)

#define	DAC_SWTRIGR_SWTRIGB2_Msk (0x1UL << DAC_SWTRIGR_SWTRIGB2_Pos)

#define	DAC_SWTRIGR_SWTRIGB2 DAC_SWTRIGR_SWTRIGB2_Msk

#define	DAC_DHR12R1_DACC1DHR_Pos (0U)

#define	DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)

#define	DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk

#define	DAC_DHR12R1_DACC1DHRB_Pos (16U)

#define	DAC_DHR12R1_DACC1DHRB_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHRB_Pos)

#define	DAC_DHR12R1_DACC1DHRB DAC_DHR12R1_DACC1DHRB_Msk

#define	DAC_DHR12L1_DACC1DHR_Pos (4U)

#define	DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)

#define	DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk

#define	DAC_DHR12L1_DACC1DHRB_Pos (20U)

#define	DAC_DHR12L1_DACC1DHRB_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHRB_Pos)

#define	DAC_DHR12L1_DACC1DHRB DAC_DHR12L1_DACC1DHRB_Msk

#define	DAC_DHR8R1_DACC1DHR_Pos (0U)

#define	DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)

#define	DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk

#define	DAC_DHR8R1_DACC1DHRB_Pos (8U)

#define	DAC_DHR8R1_DACC1DHRB_Msk (0xFFUL << DAC_DHR8R1_DACC1DHRB_Pos)

#define	DAC_DHR8R1_DACC1DHRB DAC_DHR8R1_DACC1DHRB_Msk

#define	DAC_DHR12R2_DACC2DHR_Pos (0U)

#define	DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)

#define	DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk

#define	DAC_DHR12R2_DACC2DHRB_Pos (16U)

#define	DAC_DHR12R2_DACC2DHRB_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHRB_Pos)

#define	DAC_DHR12R2_DACC2DHRB DAC_DHR12R2_DACC2DHRB_Msk

#define	DAC_DHR12L2_DACC2DHR_Pos (4U)

#define	DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)

#define	DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk

#define	DAC_DHR12L2_DACC2DHRB_Pos (20U)

#define	DAC_DHR12L2_DACC2DHRB_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHRB_Pos)

#define	DAC_DHR12L2_DACC2DHRB DAC_DHR12L2_DACC2DHRB_Msk

#define	DAC_DHR8R2_DACC2DHR_Pos (0U)

#define	DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)

#define	DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk

#define	DAC_DHR8R2_DACC2DHRB_Pos (8U)

#define	DAC_DHR8R2_DACC2DHRB_Msk (0xFFUL << DAC_DHR8R2_DACC2DHRB_Pos)

#define	DAC_DHR8R2_DACC2DHRB DAC_DHR8R2_DACC2DHRB_Msk

#define	DAC_DHR12RD_DACC1DHR_Pos (0U)

#define	DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)

#define	DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk

#define	DAC_DHR12RD_DACC2DHR_Pos (16U)

#define	DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)

#define	DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk

#define	DAC_DHR12LD_DACC1DHR_Pos (4U)

#define	DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)

#define	DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk

#define	DAC_DHR12LD_DACC2DHR_Pos (20U)

#define	DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)

#define	DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk

#define	DAC_DHR8RD_DACC1DHR_Pos (0U)

#define	DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)

#define	DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk

#define	DAC_DHR8RD_DACC2DHR_Pos (8U)

#define	DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)

#define	DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk

#define	DAC_DOR1_DACC1DOR_Pos (0U)

#define	DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)

#define	DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk

#define	DAC_DOR1_DACC1DORB_Pos (16U)

#define	DAC_DOR1_DACC1DORB_Msk (0xFFFUL << DAC_DOR1_DACC1DORB_Pos)

#define	DAC_DOR1_DACC1DORB DAC_DOR1_DACC1DORB_Msk

#define	DAC_DOR2_DACC2DOR_Pos (0U)

#define	DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)

#define	DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk

#define	DAC_DOR2_DACC2DORB_Pos (16U)

#define	DAC_DOR2_DACC2DORB_Msk (0xFFFUL << DAC_DOR2_DACC2DORB_Pos)

#define	DAC_DOR2_DACC2DORB DAC_DOR2_DACC2DORB_Msk

#define	DAC_SR_DAC1RDY_Pos (11U)

#define	DAC_SR_DAC1RDY_Msk (0x1UL << DAC_SR_DAC1RDY_Pos)

#define	DAC_SR_DAC1RDY DAC_SR_DAC1RDY_Msk

#define	DAC_SR_DORSTAT1_Pos (12U)

#define	DAC_SR_DORSTAT1_Msk (0x1UL << DAC_SR_DORSTAT1_Pos)

#define	DAC_SR_DORSTAT1 DAC_SR_DORSTAT1_Msk

#define	DAC_SR_DMAUDR1_Pos (13U)

#define	DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos)

#define	DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk

#define	DAC_SR_CAL_FLAG1_Pos (14U)

#define	DAC_SR_CAL_FLAG1_Msk (0x1UL << DAC_SR_CAL_FLAG1_Pos)

#define	DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk

#define	DAC_SR_BWST1_Pos (15U)

#define	DAC_SR_BWST1_Msk (0x1UL << DAC_SR_BWST1_Pos)

#define	DAC_SR_BWST1 DAC_SR_BWST1_Msk

#define	DAC_SR_DAC2RDY_Pos (27U)

#define	DAC_SR_DAC2RDY_Msk (0x1UL << DAC_SR_DAC2RDY_Pos)

#define	DAC_SR_DAC2RDY DAC_SR_DAC2RDY_Msk

#define	DAC_SR_DORSTAT2_Pos (28U)

#define	DAC_SR_DORSTAT2_Msk (0x1UL << DAC_SR_DORSTAT2_Pos)

#define	DAC_SR_DORSTAT2 DAC_SR_DORSTAT2_Msk

#define	DAC_SR_DMAUDR2_Pos (29U)

#define	DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos)

#define	DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk

#define	DAC_SR_CAL_FLAG2_Pos (30U)

#define	DAC_SR_CAL_FLAG2_Msk (0x1UL << DAC_SR_CAL_FLAG2_Pos)

#define	DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk

#define	DAC_SR_BWST2_Pos (31U)

#define	DAC_SR_BWST2_Msk (0x1UL << DAC_SR_BWST2_Pos)

#define	DAC_SR_BWST2 DAC_SR_BWST2_Msk

#define	DAC_CCR_OTRIM1_Pos (0U)

#define	DAC_CCR_OTRIM1_Msk (0x1FUL << DAC_CCR_OTRIM1_Pos)

#define	DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk

#define	DAC_CCR_OTRIM2_Pos (16U)

#define	DAC_CCR_OTRIM2_Msk (0x1FUL << DAC_CCR_OTRIM2_Pos)

#define	DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk

#define	DAC_MCR_MODE1_Pos (0U)

#define	DAC_MCR_MODE1_Msk (0x7UL << DAC_MCR_MODE1_Pos)

#define	DAC_MCR_MODE1 DAC_MCR_MODE1_Msk

#define	DAC_MCR_MODE1_0 (0x1UL << DAC_MCR_MODE1_Pos)

#define	DAC_MCR_MODE1_1 (0x2UL << DAC_MCR_MODE1_Pos)

#define	DAC_MCR_MODE1_2 (0x4UL << DAC_MCR_MODE1_Pos)

#define	DAC_MCR_DMADOUBLE1_Pos (8U)

#define	DAC_MCR_DMADOUBLE1_Msk (0x1UL << DAC_MCR_DMADOUBLE1_Pos)

#define	DAC_MCR_DMADOUBLE1 DAC_MCR_DMADOUBLE1_Msk

#define	DAC_MCR_SINFORMAT1_Pos (9U)

#define	DAC_MCR_SINFORMAT1_Msk (0x1UL << DAC_MCR_SINFORMAT1_Pos)

#define	DAC_MCR_SINFORMAT1 DAC_MCR_SINFORMAT1_Msk

#define	DAC_MCR_HFSEL_Pos (14U)

#define	DAC_MCR_HFSEL_Msk (0x3UL << DAC_MCR_HFSEL_Pos)

#define	DAC_MCR_HFSEL DAC_MCR_HFSEL_Msk

#define	DAC_MCR_HFSEL_0 (0x1UL << DAC_MCR_HFSEL_Pos)

#define	DAC_MCR_HFSEL_1 (0x2UL << DAC_MCR_HFSEL_Pos)

#define	DAC_MCR_MODE2_Pos (16U)

#define	DAC_MCR_MODE2_Msk (0x7UL << DAC_MCR_MODE2_Pos)

#define	DAC_MCR_MODE2 DAC_MCR_MODE2_Msk

#define	DAC_MCR_MODE2_0 (0x1UL << DAC_MCR_MODE2_Pos)

#define	DAC_MCR_MODE2_1 (0x2UL << DAC_MCR_MODE2_Pos)

#define	DAC_MCR_MODE2_2 (0x4UL << DAC_MCR_MODE2_Pos)

#define	DAC_MCR_DMADOUBLE2_Pos (24U)

#define	DAC_MCR_DMADOUBLE2_Msk (0x1UL << DAC_MCR_DMADOUBLE2_Pos)

#define	DAC_MCR_DMADOUBLE2 DAC_MCR_DMADOUBLE2_Msk

#define	DAC_MCR_SINFORMAT2_Pos (25U)

#define	DAC_MCR_SINFORMAT2_Msk (0x1UL << DAC_MCR_SINFORMAT2_Pos)

#define	DAC_MCR_SINFORMAT2 DAC_MCR_SINFORMAT2_Msk

#define	DAC_SHSR1_TSAMPLE1_Pos (0U)

#define	DAC_SHSR1_TSAMPLE1_Msk (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)

#define	DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk

#define	DAC_SHSR2_TSAMPLE2_Pos (0U)

#define	DAC_SHSR2_TSAMPLE2_Msk (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)

#define	DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk

#define	DAC_SHHR_THOLD1_Pos (0U)

#define	DAC_SHHR_THOLD1_Msk (0x3FFUL << DAC_SHHR_THOLD1_Pos)

#define	DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk

#define	DAC_SHHR_THOLD2_Pos (16U)

#define	DAC_SHHR_THOLD2_Msk (0x3FFUL << DAC_SHHR_THOLD2_Pos)

#define	DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk

#define	DAC_SHRR_TREFRESH1_Pos (0U)

#define	DAC_SHRR_TREFRESH1_Msk (0xFFUL << DAC_SHRR_TREFRESH1_Pos)

#define	DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk

#define	DAC_SHRR_TREFRESH2_Pos (16U)

#define	DAC_SHRR_TREFRESH2_Msk (0xFFUL << DAC_SHRR_TREFRESH2_Pos)

#define	DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk

#define	DAC_STR1_STRSTDATA1_Pos (0U)

#define	DAC_STR1_STRSTDATA1_Msk (0xFFFUL << DAC_STR1_STRSTDATA1_Pos)

#define	DAC_STR1_STRSTDATA1 DAC_STR1_STRSTDATA1_Msk

#define	DAC_STR1_STDIR1_Pos (12U)

#define	DAC_STR1_STDIR1_Msk (0x1UL << DAC_STR1_STDIR1_Pos)

#define	DAC_STR1_STDIR1 DAC_STR1_STDIR1_Msk

#define	DAC_STR1_STINCDATA1_Pos (16U)

#define	DAC_STR1_STINCDATA1_Msk (0xFFFFUL << DAC_STR1_STINCDATA1_Pos)

#define	DAC_STR1_STINCDATA1 DAC_STR1_STINCDATA1_Msk

#define	DAC_STR2_STRSTDATA2_Pos (0U)

#define	DAC_STR2_STRSTDATA2_Msk (0xFFFUL << DAC_STR2_STRSTDATA2_Pos)

#define	DAC_STR2_STRSTDATA2 DAC_STR2_STRSTDATA2_Msk

#define	DAC_STR2_STDIR2_Pos (12U)

#define	DAC_STR2_STDIR2_Msk (0x1UL << DAC_STR2_STDIR2_Pos)

#define	DAC_STR2_STDIR2 DAC_STR2_STDIR2_Msk

#define	DAC_STR2_STINCDATA2_Pos (16U)

#define	DAC_STR2_STINCDATA2_Msk (0xFFFFUL << DAC_STR2_STINCDATA2_Pos)

#define	DAC_STR2_STINCDATA2 DAC_STR2_STINCDATA2_Msk

#define	DAC_STMODR_STRSTTRIGSEL1_Pos (0U)

#define	DAC_STMODR_STRSTTRIGSEL1_Msk (0xFUL << DAC_STMODR_STRSTTRIGSEL1_Pos)

#define	DAC_STMODR_STRSTTRIGSEL1 DAC_STMODR_STRSTTRIGSEL1_Msk

#define	DAC_STMODR_STRSTTRIGSEL1_0 (0x1UL << DAC_STMODR_STRSTTRIGSEL1_Pos)

#define	DAC_STMODR_STRSTTRIGSEL1_1 (0x2UL << DAC_STMODR_STRSTTRIGSEL1_Pos)

#define	DAC_STMODR_STRSTTRIGSEL1_2 (0x4UL << DAC_STMODR_STRSTTRIGSEL1_Pos)

#define	DAC_STMODR_STRSTTRIGSEL1_3 (0x8UL << DAC_STMODR_STRSTTRIGSEL1_Pos)

#define	DAC_STMODR_STINCTRIGSEL1_Pos (8U)

#define	DAC_STMODR_STINCTRIGSEL1_Msk (0xFUL << DAC_STMODR_STINCTRIGSEL1_Pos)

#define	DAC_STMODR_STINCTRIGSEL1 DAC_STMODR_STINCTRIGSEL1_Msk

#define	DAC_STMODR_STINCTRIGSEL1_0 (0x1UL << DAC_STMODR_STINCTRIGSEL1_Pos)

#define	DAC_STMODR_STINCTRIGSEL1_1 (0x2UL << DAC_STMODR_STINCTRIGSEL1_Pos)

#define	DAC_STMODR_STINCTRIGSEL1_2 (0x4UL << DAC_STMODR_STINCTRIGSEL1_Pos)

#define	DAC_STMODR_STINCTRIGSEL1_3 (0x8UL << DAC_STMODR_STINCTRIGSEL1_Pos)

#define	DAC_STMODR_STRSTTRIGSEL2_Pos (16U)

#define	DAC_STMODR_STRSTTRIGSEL2_Msk (0xFUL << DAC_STMODR_STRSTTRIGSEL2_Pos)

#define	DAC_STMODR_STRSTTRIGSEL2 DAC_STMODR_STRSTTRIGSEL2_Msk

#define	DAC_STMODR_STRSTTRIGSEL2_0 (0x1UL << DAC_STMODR_STRSTTRIGSEL2_Pos)

#define	DAC_STMODR_STRSTTRIGSEL2_1 (0x2UL << DAC_STMODR_STRSTTRIGSEL2_Pos)

#define	DAC_STMODR_STRSTTRIGSEL2_2 (0x4UL << DAC_STMODR_STRSTTRIGSEL2_Pos)

#define	DAC_STMODR_STRSTTRIGSEL2_3 (0x8UL << DAC_STMODR_STRSTTRIGSEL2_Pos)

#define	DAC_STMODR_STINCTRIGSEL2_Pos (24U)

#define	DAC_STMODR_STINCTRIGSEL2_Msk (0xFUL << DAC_STMODR_STINCTRIGSEL2_Pos)

#define	DAC_STMODR_STINCTRIGSEL2 DAC_STMODR_STINCTRIGSEL2_Msk

#define	DAC_STMODR_STINCTRIGSEL2_0 (0x1UL << DAC_STMODR_STINCTRIGSEL2_Pos)

#define	DAC_STMODR_STINCTRIGSEL2_1 (0x2UL << DAC_STMODR_STINCTRIGSEL2_Pos)

#define	DAC_STMODR_STINCTRIGSEL2_2 (0x4UL << DAC_STMODR_STINCTRIGSEL2_Pos)

#define	DAC_STMODR_STINCTRIGSEL2_3 (0x8UL << DAC_STMODR_STINCTRIGSEL2_Pos)

#define	DBGMCU_IDCODE_DEV_ID_Pos (0U)

#define	DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)

#define	DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk

#define	DBGMCU_IDCODE_REV_ID_Pos (16U)

#define	DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)

#define	DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk

#define	DBGMCU_CR_DBG_SLEEP_Pos (0U)

#define	DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)

#define	DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk

#define	DBGMCU_CR_DBG_STOP_Pos (1U)

#define	DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos)

#define	DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk

#define	DBGMCU_CR_DBG_STANDBY_Pos (2U)

#define	DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)

#define	DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk

#define	DBGMCU_CR_TRACE_IOEN_Pos (5U)

#define	DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)

#define	DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk

#define	DBGMCU_CR_TRACE_MODE_Pos (6U)

#define	DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)

#define	DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk

#define	DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)

#define	DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)

#define	DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U)

#define	DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos)

#define	DBGMCU_APB1FZR1_DBG_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk

#define	DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos (1U)

#define	DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos)

#define	DBGMCU_APB1FZR1_DBG_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk

#define	DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos (2U)

#define	DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos)

#define	DBGMCU_APB1FZR1_DBG_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk

#define	DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos (4U)

#define	DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos)

#define	DBGMCU_APB1FZR1_DBG_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk

#define	DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos (5U)

#define	DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos)

#define	DBGMCU_APB1FZR1_DBG_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk

#define	DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos (10U)

#define	DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos)

#define	DBGMCU_APB1FZR1_DBG_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk

#define	DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos (11U)

#define	DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos)

#define	DBGMCU_APB1FZR1_DBG_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk

#define	DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos (12U)

#define	DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos)

#define	DBGMCU_APB1FZR1_DBG_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk

#define	DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos (21U)

#define	DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos)

#define	DBGMCU_APB1FZR1_DBG_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk

#define	DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos (22U)

#define	DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos)

#define	DBGMCU_APB1FZR1_DBG_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk

#define	DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos (30U)

#define	DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos)

#define	DBGMCU_APB1FZR1_DBG_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk

#define	DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos (31U)

#define	DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos)

#define	DBGMCU_APB1FZR1_DBG_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk

#define	DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos (11U)

#define	DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos)

#define	DBGMCU_APB2FZ_DBG_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk

#define	DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos (13U)

#define	DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos)

#define	DBGMCU_APB2FZ_DBG_TIM8_STOP DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk

#define	DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos (16U)

#define	DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos)

#define	DBGMCU_APB2FZ_DBG_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk

#define	DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos (17U)

#define	DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos)

#define	DBGMCU_APB2FZ_DBG_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk

#define	DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos (18U)

#define	DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos)

#define	DBGMCU_APB2FZ_DBG_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk

#define	DMA_ISR_GIF1_Pos (0U)

#define	DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos)

#define	DMA_ISR_GIF1 DMA_ISR_GIF1_Msk

#define	DMA_ISR_TCIF1_Pos (1U)

#define	DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos)

#define	DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk

#define	DMA_ISR_HTIF1_Pos (2U)

#define	DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos)

#define	DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk

#define	DMA_ISR_TEIF1_Pos (3U)

#define	DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos)

#define	DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk

#define	DMA_ISR_GIF2_Pos (4U)

#define	DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos)

#define	DMA_ISR_GIF2 DMA_ISR_GIF2_Msk

#define	DMA_ISR_TCIF2_Pos (5U)

#define	DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos)

#define	DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk

#define	DMA_ISR_HTIF2_Pos (6U)

#define	DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos)

#define	DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk

#define	DMA_ISR_TEIF2_Pos (7U)

#define	DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos)

#define	DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk

#define	DMA_ISR_GIF3_Pos (8U)

#define	DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos)

#define	DMA_ISR_GIF3 DMA_ISR_GIF3_Msk

#define	DMA_ISR_TCIF3_Pos (9U)

#define	DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos)

#define	DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk

#define	DMA_ISR_HTIF3_Pos (10U)

#define	DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos)

#define	DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk

#define	DMA_ISR_TEIF3_Pos (11U)

#define	DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos)

#define	DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk

#define	DMA_ISR_GIF4_Pos (12U)

#define	DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos)

#define	DMA_ISR_GIF4 DMA_ISR_GIF4_Msk

#define	DMA_ISR_TCIF4_Pos (13U)

#define	DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos)

#define	DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk

#define	DMA_ISR_HTIF4_Pos (14U)

#define	DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos)

#define	DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk

#define	DMA_ISR_TEIF4_Pos (15U)

#define	DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos)

#define	DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk

#define	DMA_ISR_GIF5_Pos (16U)

#define	DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos)

#define	DMA_ISR_GIF5 DMA_ISR_GIF5_Msk

#define	DMA_ISR_TCIF5_Pos (17U)

#define	DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos)

#define	DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk

#define	DMA_ISR_HTIF5_Pos (18U)

#define	DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos)

#define	DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk

#define	DMA_ISR_TEIF5_Pos (19U)

#define	DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos)

#define	DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk

#define	DMA_ISR_GIF6_Pos (20U)

#define	DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos)

#define	DMA_ISR_GIF6 DMA_ISR_GIF6_Msk

#define	DMA_ISR_TCIF6_Pos (21U)

#define	DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos)

#define	DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk

#define	DMA_ISR_HTIF6_Pos (22U)

#define	DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos)

#define	DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk

#define	DMA_ISR_TEIF6_Pos (23U)

#define	DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos)

#define	DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk

#define	DMA_IFCR_CGIF1_Pos (0U)

#define	DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos)

#define	DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk

#define	DMA_IFCR_CTCIF1_Pos (1U)

#define	DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos)

#define	DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk

#define	DMA_IFCR_CHTIF1_Pos (2U)

#define	DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos)

#define	DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk

#define	DMA_IFCR_CTEIF1_Pos (3U)

#define	DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos)

#define	DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk

#define	DMA_IFCR_CGIF2_Pos (4U)

#define	DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos)

#define	DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk

#define	DMA_IFCR_CTCIF2_Pos (5U)

#define	DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos)

#define	DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk

#define	DMA_IFCR_CHTIF2_Pos (6U)

#define	DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos)

#define	DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk

#define	DMA_IFCR_CTEIF2_Pos (7U)

#define	DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos)

#define	DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk

#define	DMA_IFCR_CGIF3_Pos (8U)

#define	DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos)

#define	DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk

#define	DMA_IFCR_CTCIF3_Pos (9U)

#define	DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos)

#define	DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk

#define	DMA_IFCR_CHTIF3_Pos (10U)

#define	DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos)

#define	DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk

#define	DMA_IFCR_CTEIF3_Pos (11U)

#define	DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos)

#define	DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk

#define	DMA_IFCR_CGIF4_Pos (12U)

#define	DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos)

#define	DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk

#define	DMA_IFCR_CTCIF4_Pos (13U)

#define	DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos)

#define	DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk

#define	DMA_IFCR_CHTIF4_Pos (14U)

#define	DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos)

#define	DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk

#define	DMA_IFCR_CTEIF4_Pos (15U)

#define	DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos)

#define	DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk

#define	DMA_IFCR_CGIF5_Pos (16U)

#define	DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos)

#define	DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk

#define	DMA_IFCR_CTCIF5_Pos (17U)

#define	DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos)

#define	DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk

#define	DMA_IFCR_CHTIF5_Pos (18U)

#define	DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos)

#define	DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk

#define	DMA_IFCR_CTEIF5_Pos (19U)

#define	DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos)

#define	DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk

#define	DMA_IFCR_CGIF6_Pos (20U)

#define	DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos)

#define	DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk

#define	DMA_IFCR_CTCIF6_Pos (21U)

#define	DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos)

#define	DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk

#define	DMA_IFCR_CHTIF6_Pos (22U)

#define	DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos)

#define	DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk

#define	DMA_IFCR_CTEIF6_Pos (23U)

#define	DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos)

#define	DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk

#define	DMA_CCR_EN_Pos (0U)

#define	DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos)

#define	DMA_CCR_EN DMA_CCR_EN_Msk

#define	DMA_CCR_TCIE_Pos (1U)

#define	DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos)

#define	DMA_CCR_TCIE DMA_CCR_TCIE_Msk

#define	DMA_CCR_HTIE_Pos (2U)

#define	DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos)

#define	DMA_CCR_HTIE DMA_CCR_HTIE_Msk

#define	DMA_CCR_TEIE_Pos (3U)

#define	DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos)

#define	DMA_CCR_TEIE DMA_CCR_TEIE_Msk

#define	DMA_CCR_DIR_Pos (4U)

#define	DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos)

#define	DMA_CCR_DIR DMA_CCR_DIR_Msk

#define	DMA_CCR_CIRC_Pos (5U)

#define	DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos)

#define	DMA_CCR_CIRC DMA_CCR_CIRC_Msk

#define	DMA_CCR_PINC_Pos (6U)

#define	DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos)

#define	DMA_CCR_PINC DMA_CCR_PINC_Msk

#define	DMA_CCR_MINC_Pos (7U)

#define	DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos)

#define	DMA_CCR_MINC DMA_CCR_MINC_Msk

#define	DMA_CCR_PSIZE_Pos (8U)

#define	DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos)

#define	DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk

#define	DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos)

#define	DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos)

#define	DMA_CCR_MSIZE_Pos (10U)

#define	DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos)

#define	DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk

#define	DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos)

#define	DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos)

#define	DMA_CCR_PL_Pos (12U)

#define	DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos)

#define	DMA_CCR_PL DMA_CCR_PL_Msk

#define	DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos)

#define	DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos)

#define	DMA_CCR_MEM2MEM_Pos (14U)

#define	DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos)

#define	DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk

#define	DMA_CNDTR_NDT_Pos (0U)

#define	DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos)

#define	DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk

#define	DMA_CPAR_PA_Pos (0U)

#define	DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)

#define	DMA_CPAR_PA DMA_CPAR_PA_Msk

#define	DMA_CMAR_MA_Pos (0U)

#define	DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)

#define	DMA_CMAR_MA DMA_CMAR_MA_Msk

#define	DMAMUX_CxCR_DMAREQ_ID_Pos (0U)

#define	DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)

#define	DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk

#define	DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)

#define	DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)

#define	DMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)

#define	DMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)

#define	DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)

#define	DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)

#define	DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)

#define	DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)

#define	DMAMUX_CxCR_SOIE_Pos (8U)

#define	DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos)

#define	DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk

#define	DMAMUX_CxCR_EGE_Pos (9U)

#define	DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos)

#define	DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk

#define	DMAMUX_CxCR_SE_Pos (16U)

#define	DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos)

#define	DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk

#define	DMAMUX_CxCR_SPOL_Pos (17U)

#define	DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos)

#define	DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk

#define	DMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos)

#define	DMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos)

#define	DMAMUX_CxCR_NBREQ_Pos (19U)

#define	DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)

#define	DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk

#define	DMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos)

#define	DMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos)

#define	DMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos)

#define	DMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos)

#define	DMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos)

#define	DMAMUX_CxCR_SYNC_ID_Pos (24U)

#define	DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)

#define	DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk

#define	DMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)

#define	DMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)

#define	DMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)

#define	DMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)

#define	DMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)

#define	DMAMUX_CSR_SOF0_Pos (0U)

#define	DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos)

#define	DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk

#define	DMAMUX_CSR_SOF1_Pos (1U)

#define	DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos)

#define	DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk

#define	DMAMUX_CSR_SOF2_Pos (2U)

#define	DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos)

#define	DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk

#define	DMAMUX_CSR_SOF3_Pos (3U)

#define	DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos)

#define	DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk

#define	DMAMUX_CSR_SOF4_Pos (4U)

#define	DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos)

#define	DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk

#define	DMAMUX_CSR_SOF5_Pos (5U)

#define	DMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos)

#define	DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk

#define	DMAMUX_CSR_SOF6_Pos (6U)

#define	DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos)

#define	DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk

#define	DMAMUX_CSR_SOF7_Pos (7U)

#define	DMAMUX_CSR_SOF7_Msk (0x1UL << DMAMUX_CSR_SOF7_Pos)

#define	DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7_Msk

#define	DMAMUX_CSR_SOF8_Pos (8U)

#define	DMAMUX_CSR_SOF8_Msk (0x1UL << DMAMUX_CSR_SOF8_Pos)

#define	DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8_Msk

#define	DMAMUX_CSR_SOF9_Pos (9U)

#define	DMAMUX_CSR_SOF9_Msk (0x1UL << DMAMUX_CSR_SOF9_Pos)

#define	DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9_Msk

#define	DMAMUX_CSR_SOF10_Pos (10U)

#define	DMAMUX_CSR_SOF10_Msk (0x1UL << DMAMUX_CSR_SOF10_Pos)

#define	DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10_Msk

#define	DMAMUX_CSR_SOF11_Pos (11U)

#define	DMAMUX_CSR_SOF11_Msk (0x1UL << DMAMUX_CSR_SOF11_Pos)

#define	DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11_Msk

#define	DMAMUX_CFR_CSOF0_Pos (0U)

#define	DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos)

#define	DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk

#define	DMAMUX_CFR_CSOF1_Pos (1U)

#define	DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos)

#define	DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk

#define	DMAMUX_CFR_CSOF2_Pos (2U)

#define	DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos)

#define	DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk

#define	DMAMUX_CFR_CSOF3_Pos (3U)

#define	DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos)

#define	DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk

#define	DMAMUX_CFR_CSOF4_Pos (4U)

#define	DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos)

#define	DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk

#define	DMAMUX_CFR_CSOF5_Pos (5U)

#define	DMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos)

#define	DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk

#define	DMAMUX_CFR_CSOF6_Pos (6U)

#define	DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos)

#define	DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk

#define	DMAMUX_CFR_CSOF7_Pos (7U)

#define	DMAMUX_CFR_CSOF7_Msk (0x1UL << DMAMUX_CFR_CSOF7_Pos)

#define	DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7_Msk

#define	DMAMUX_CFR_CSOF8_Pos (8U)

#define	DMAMUX_CFR_CSOF8_Msk (0x1UL << DMAMUX_CFR_CSOF8_Pos)

#define	DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8_Msk

#define	DMAMUX_CFR_CSOF9_Pos (9U)

#define	DMAMUX_CFR_CSOF9_Msk (0x1UL << DMAMUX_CFR_CSOF9_Pos)

#define	DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9_Msk

#define	DMAMUX_CFR_CSOF10_Pos (10U)

#define	DMAMUX_CFR_CSOF10_Msk (0x1UL << DMAMUX_CFR_CSOF10_Pos)

#define	DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10_Msk

#define	DMAMUX_CFR_CSOF11_Pos (11U)

#define	DMAMUX_CFR_CSOF11_Msk (0x1UL << DMAMUX_CFR_CSOF11_Pos)

#define	DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11_Msk

#define	DMAMUX_RGxCR_SIG_ID_Pos (0U)

#define	DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)

#define	DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk

#define	DMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)

#define	DMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)

#define	DMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)

#define	DMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)

#define	DMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)

#define	DMAMUX_RGxCR_OIE_Pos (8U)

#define	DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos)

#define	DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk

#define	DMAMUX_RGxCR_GE_Pos (16U)

#define	DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos)

#define	DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk

#define	DMAMUX_RGxCR_GPOL_Pos (17U)

#define	DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos)

#define	DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk

#define	DMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos)

#define	DMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos)

#define	DMAMUX_RGxCR_GNBREQ_Pos (19U)

#define	DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)

#define	DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk

#define	DMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)

#define	DMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)

#define	DMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)

#define	DMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)

#define	DMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)

#define	DMAMUX_RGSR_OF0_Pos (0U)

#define	DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos)

#define	DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk

#define	DMAMUX_RGSR_OF1_Pos (1U)

#define	DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos)

#define	DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk

#define	DMAMUX_RGSR_OF2_Pos (2U)

#define	DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos)

#define	DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk

#define	DMAMUX_RGSR_OF3_Pos (3U)

#define	DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos)

#define	DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk

#define	DMAMUX_RGCFR_COF0_Pos (0U)

#define	DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos)

#define	DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk

#define	DMAMUX_RGCFR_COF1_Pos (1U)

#define	DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos)

#define	DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk

#define	DMAMUX_RGCFR_COF2_Pos (2U)

#define	DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos)

#define	DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk

#define	DMAMUX_RGCFR_COF3_Pos (3U)

#define	DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos)

#define	DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk

#define	DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Pos (0U)

#define	DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Pos)

#define	DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Msk

#define	DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Pos (1U)

#define	DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Pos)

#define	DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Msk

#define	DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Pos (2U)

#define	DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Pos)

#define	DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Msk

#define	DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Pos (3U)

#define	DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Pos)

#define	DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Msk

#define	DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Pos (4U)

#define	DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Pos)

#define	DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Msk

#define	DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Pos (5U)

#define	DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Pos)

#define	DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Msk

#define	DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Pos (6U)

#define	DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Pos)

#define	DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Msk

#define	DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Pos (7U)

#define	DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Pos)

#define	DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Msk

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Pos (0U)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Pos)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Msk

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Pos (1U)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Pos)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Msk

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Pos (2U)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Pos)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Msk

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Pos (3U)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Pos)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Msk

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Pos (4U)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Pos)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Msk

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Pos (5U)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Pos)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Msk

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Pos (6U)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Pos)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Msk

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Pos (7U)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Pos)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Msk

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Pos (8U)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Pos)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Msk

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Pos (9U)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Pos)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Msk

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Pos (10U)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Pos)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Msk

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Pos (11U)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Pos)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Msk

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Pos (12U)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Pos)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Msk

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Pos (13U)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Pos)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Msk

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Pos (14U)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Pos)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Msk

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Pos (15U)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Pos)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Msk

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Pos (16U)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Pos)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Msk

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Pos (17U)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Pos)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Msk

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Pos (18U)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Pos)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Msk

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Pos (19U)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Pos)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Msk

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Pos (20U)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Pos)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Msk

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Pos (21U)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Pos)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Msk

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Pos (22U)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Pos)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Msk

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Pos (23U)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Pos)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Msk

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Pos (24U)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Pos)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Msk

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Pos (25U)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Pos)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Msk

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Pos (26U)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Pos)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Msk

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Pos (27U)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Pos)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Msk

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Pos (28U)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Pos)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Msk

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Pos (29U)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Pos)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Msk

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Pos (30U)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Pos)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Msk

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Pos (31U)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Pos)

#define	DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Msk

#define	EXTI_IMR1_IM0_Pos (0U)

#define	EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos)

#define	EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk

#define	EXTI_IMR1_IM1_Pos (1U)

#define	EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos)

#define	EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk

#define	EXTI_IMR1_IM2_Pos (2U)

#define	EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos)

#define	EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk

#define	EXTI_IMR1_IM3_Pos (3U)

#define	EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos)

#define	EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk

#define	EXTI_IMR1_IM4_Pos (4U)

#define	EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos)

#define	EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk

#define	EXTI_IMR1_IM5_Pos (5U)

#define	EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos)

#define	EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk

#define	EXTI_IMR1_IM6_Pos (6U)

#define	EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos)

#define	EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk

#define	EXTI_IMR1_IM7_Pos (7U)

#define	EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos)

#define	EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk

#define	EXTI_IMR1_IM8_Pos (8U)

#define	EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos)

#define	EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk

#define	EXTI_IMR1_IM9_Pos (9U)

#define	EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos)

#define	EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk

#define	EXTI_IMR1_IM10_Pos (10U)

#define	EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos)

#define	EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk

#define	EXTI_IMR1_IM11_Pos (11U)

#define	EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos)

#define	EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk

#define	EXTI_IMR1_IM12_Pos (12U)

#define	EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos)

#define	EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk

#define	EXTI_IMR1_IM13_Pos (13U)

#define	EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos)

#define	EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk

#define	EXTI_IMR1_IM14_Pos (14U)

#define	EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos)

#define	EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk

#define	EXTI_IMR1_IM15_Pos (15U)

#define	EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos)

#define	EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk

#define	EXTI_IMR1_IM16_Pos (16U)

#define	EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos)

#define	EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk

#define	EXTI_IMR1_IM17_Pos (17U)

#define	EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos)

#define	EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk

#define	EXTI_IMR1_IM18_Pos (18U)

#define	EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos)

#define	EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk

#define	EXTI_IMR1_IM19_Pos (19U)

#define	EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos)

#define	EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk

#define	EXTI_IMR1_IM20_Pos (20U)

#define	EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos)

#define	EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk

#define	EXTI_IMR1_IM21_Pos (21U)

#define	EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos)

#define	EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk

#define	EXTI_IMR1_IM22_Pos (22U)

#define	EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos)

#define	EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk

#define	EXTI_IMR1_IM23_Pos (23U)

#define	EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos)

#define	EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk

#define	EXTI_IMR1_IM24_Pos (24U)

#define	EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos)

#define	EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk

#define	EXTI_IMR1_IM25_Pos (25U)

#define	EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos)

#define	EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk

#define	EXTI_IMR1_IM26_Pos (26U)

#define	EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos)

#define	EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk

#define	EXTI_IMR1_IM27_Pos (27U)

#define	EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos)

#define	EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk

#define	EXTI_IMR1_IM28_Pos (28U)

#define	EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos)

#define	EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk

#define	EXTI_IMR1_IM29_Pos (29U)

#define	EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos)

#define	EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk

#define	EXTI_IMR1_IM30_Pos (30U)

#define	EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos)

#define	EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk

#define	EXTI_IMR1_IM_Pos (0U)

#define	EXTI_IMR1_IM_Msk (0x7FFFFFFFUL << EXTI_IMR1_IM_Pos)

#define	EXTI_IMR1_IM EXTI_IMR1_IM_Msk

#define	EXTI_EMR1_EM0_Pos (0U)

#define	EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos)

#define	EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk

#define	EXTI_EMR1_EM1_Pos (1U)

#define	EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos)

#define	EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk

#define	EXTI_EMR1_EM2_Pos (2U)

#define	EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos)

#define	EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk

#define	EXTI_EMR1_EM3_Pos (3U)

#define	EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos)

#define	EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk

#define	EXTI_EMR1_EM4_Pos (4U)

#define	EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos)

#define	EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk

#define	EXTI_EMR1_EM5_Pos (5U)

#define	EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos)

#define	EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk

#define	EXTI_EMR1_EM6_Pos (6U)

#define	EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos)

#define	EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk

#define	EXTI_EMR1_EM7_Pos (7U)

#define	EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos)

#define	EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk

#define	EXTI_EMR1_EM8_Pos (8U)

#define	EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos)

#define	EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk

#define	EXTI_EMR1_EM9_Pos (9U)

#define	EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos)

#define	EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk

#define	EXTI_EMR1_EM10_Pos (10U)

#define	EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos)

#define	EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk

#define	EXTI_EMR1_EM11_Pos (11U)

#define	EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos)

#define	EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk

#define	EXTI_EMR1_EM12_Pos (12U)

#define	EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos)

#define	EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk

#define	EXTI_EMR1_EM13_Pos (13U)

#define	EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos)

#define	EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk

#define	EXTI_EMR1_EM14_Pos (14U)

#define	EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos)

#define	EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk

#define	EXTI_EMR1_EM15_Pos (15U)

#define	EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos)

#define	EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk

#define	EXTI_EMR1_EM16_Pos (16U)

#define	EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos)

#define	EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk

#define	EXTI_EMR1_EM17_Pos (17U)

#define	EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos)

#define	EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk

#define	EXTI_EMR1_EM18_Pos (18U)

#define	EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos)

#define	EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk

#define	EXTI_EMR1_EM19_Pos (19U)

#define	EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos)

#define	EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk

#define	EXTI_EMR1_EM20_Pos (20U)

#define	EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos)

#define	EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk

#define	EXTI_EMR1_EM21_Pos (21U)

#define	EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos)

#define	EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk

#define	EXTI_EMR1_EM22_Pos (22U)

#define	EXTI_EMR1_EM22_Msk (0x1UL << EXTI_EMR1_EM22_Pos)

#define	EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk

#define	EXTI_EMR1_EM23_Pos (23U)

#define	EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos)

#define	EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk

#define	EXTI_EMR1_EM24_Pos (24U)

#define	EXTI_EMR1_EM24_Msk (0x1UL << EXTI_EMR1_EM24_Pos)

#define	EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk

#define	EXTI_EMR1_EM25_Pos (25U)

#define	EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos)

#define	EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk

#define	EXTI_EMR1_EM26_Pos (26U)

#define	EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos)

#define	EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk

#define	EXTI_EMR1_EM27_Pos (27U)

#define	EXTI_EMR1_EM27_Msk (0x1UL << EXTI_EMR1_EM27_Pos)

#define	EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk

#define	EXTI_EMR1_EM28_Pos (28U)

#define	EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos)

#define	EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk

#define	EXTI_EMR1_EM29_Pos (29U)

#define	EXTI_EMR1_EM29_Msk (0x1UL << EXTI_EMR1_EM29_Pos)

#define	EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk

#define	EXTI_EMR1_EM30_Pos (30U)

#define	EXTI_EMR1_EM30_Msk (0x1UL << EXTI_EMR1_EM30_Pos)

#define	EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk

#define	EXTI_RTSR1_RT0_Pos (0U)

#define	EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos)

#define	EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk

#define	EXTI_RTSR1_RT1_Pos (1U)

#define	EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos)

#define	EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk

#define	EXTI_RTSR1_RT2_Pos (2U)

#define	EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos)

#define	EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk

#define	EXTI_RTSR1_RT3_Pos (3U)

#define	EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos)

#define	EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk

#define	EXTI_RTSR1_RT4_Pos (4U)

#define	EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos)

#define	EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk

#define	EXTI_RTSR1_RT5_Pos (5U)

#define	EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos)

#define	EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk

#define	EXTI_RTSR1_RT6_Pos (6U)

#define	EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos)

#define	EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk

#define	EXTI_RTSR1_RT7_Pos (7U)

#define	EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos)

#define	EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk

#define	EXTI_RTSR1_RT8_Pos (8U)

#define	EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos)

#define	EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk

#define	EXTI_RTSR1_RT9_Pos (9U)

#define	EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos)

#define	EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk

#define	EXTI_RTSR1_RT10_Pos (10U)

#define	EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos)

#define	EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk

#define	EXTI_RTSR1_RT11_Pos (11U)

#define	EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos)

#define	EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk

#define	EXTI_RTSR1_RT12_Pos (12U)

#define	EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos)

#define	EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk

#define	EXTI_RTSR1_RT13_Pos (13U)

#define	EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos)

#define	EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk

#define	EXTI_RTSR1_RT14_Pos (14U)

#define	EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos)

#define	EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk

#define	EXTI_RTSR1_RT15_Pos (15U)

#define	EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos)

#define	EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk

#define	EXTI_RTSR1_RT16_Pos (16U)

#define	EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos)

#define	EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk

#define	EXTI_RTSR1_RT17_Pos (17U)

#define	EXTI_RTSR1_RT17_Msk (0x1UL << EXTI_RTSR1_RT17_Pos)

#define	EXTI_RTSR1_RT17 EXTI_RTSR1_RT17_Msk

#define	EXTI_RTSR1_RT19_Pos (19U)

#define	EXTI_RTSR1_RT19_Msk (0x1UL << EXTI_RTSR1_RT19_Pos)

#define	EXTI_RTSR1_RT19 EXTI_RTSR1_RT19_Msk

#define	EXTI_RTSR1_RT20_Pos (20U)

#define	EXTI_RTSR1_RT20_Msk (0x1UL << EXTI_RTSR1_RT20_Pos)

#define	EXTI_RTSR1_RT20 EXTI_RTSR1_RT20_Msk

#define	EXTI_RTSR1_RT21_Pos (21U)

#define	EXTI_RTSR1_RT21_Msk (0x1UL << EXTI_RTSR1_RT21_Pos)

#define	EXTI_RTSR1_RT21 EXTI_RTSR1_RT21_Msk

#define	EXTI_RTSR1_RT22_Pos (22U)

#define	EXTI_RTSR1_RT22_Msk (0x1UL << EXTI_RTSR1_RT22_Pos)

#define	EXTI_RTSR1_RT22 EXTI_RTSR1_RT22_Msk

#define	EXTI_RTSR1_RT29_Pos (29U)

#define	EXTI_RTSR1_RT29_Msk (0x1UL << EXTI_RTSR1_RT29_Pos)

#define	EXTI_RTSR1_RT29 EXTI_RTSR1_RT29_Msk

#define	EXTI_RTSR1_RT30_Pos (30U)

#define	EXTI_RTSR1_RT30_Msk (0x1UL << EXTI_RTSR1_RT30_Pos)

#define	EXTI_RTSR1_RT30 EXTI_RTSR1_RT30_Msk

#define	EXTI_FTSR1_FT0_Pos (0U)

#define	EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos)

#define	EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk

#define	EXTI_FTSR1_FT1_Pos (1U)

#define	EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos)

#define	EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk

#define	EXTI_FTSR1_FT2_Pos (2U)

#define	EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos)

#define	EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk

#define	EXTI_FTSR1_FT3_Pos (3U)

#define	EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos)

#define	EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk

#define	EXTI_FTSR1_FT4_Pos (4U)

#define	EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos)

#define	EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk

#define	EXTI_FTSR1_FT5_Pos (5U)

#define	EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos)

#define	EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk

#define	EXTI_FTSR1_FT6_Pos (6U)

#define	EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos)

#define	EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk

#define	EXTI_FTSR1_FT7_Pos (7U)

#define	EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos)

#define	EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk

#define	EXTI_FTSR1_FT8_Pos (8U)

#define	EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos)

#define	EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk

#define	EXTI_FTSR1_FT9_Pos (9U)

#define	EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos)

#define	EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk

#define	EXTI_FTSR1_FT10_Pos (10U)

#define	EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos)

#define	EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk

#define	EXTI_FTSR1_FT11_Pos (11U)

#define	EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos)

#define	EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk

#define	EXTI_FTSR1_FT12_Pos (12U)

#define	EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos)

#define	EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk

#define	EXTI_FTSR1_FT13_Pos (13U)

#define	EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos)

#define	EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk

#define	EXTI_FTSR1_FT14_Pos (14U)

#define	EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos)

#define	EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk

#define	EXTI_FTSR1_FT15_Pos (15U)

#define	EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos)

#define	EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk

#define	EXTI_FTSR1_FT16_Pos (16U)

#define	EXTI_FTSR1_FT16_Msk (0x1UL << EXTI_FTSR1_FT16_Pos)

#define	EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk

#define	EXTI_FTSR1_FT17_Pos (17U)

#define	EXTI_FTSR1_FT17_Msk (0x1UL << EXTI_FTSR1_FT17_Pos)

#define	EXTI_FTSR1_FT17 EXTI_FTSR1_FT17_Msk

#define	EXTI_FTSR1_FT19_Pos (19U)

#define	EXTI_FTSR1_FT19_Msk (0x1UL << EXTI_FTSR1_FT19_Pos)

#define	EXTI_FTSR1_FT19 EXTI_FTSR1_FT19_Msk

#define	EXTI_FTSR1_FT20_Pos (20U)

#define	EXTI_FTSR1_FT20_Msk (0x1UL << EXTI_FTSR1_FT20_Pos)

#define	EXTI_FTSR1_FT20 EXTI_FTSR1_FT20_Msk

#define	EXTI_FTSR1_FT21_Pos (21U)

#define	EXTI_FTSR1_FT21_Msk (0x1UL << EXTI_FTSR1_FT21_Pos)

#define	EXTI_FTSR1_FT21 EXTI_FTSR1_FT21_Msk

#define	EXTI_FTSR1_FT22_Pos (22U)

#define	EXTI_FTSR1_FT22_Msk (0x1UL << EXTI_FTSR1_FT22_Pos)

#define	EXTI_FTSR1_FT22 EXTI_FTSR1_FT22_Msk

#define	EXTI_FTSR1_FT29_Pos (29U)

#define	EXTI_FTSR1_FT29_Msk (0x1UL << EXTI_FTSR1_FT29_Pos)

#define	EXTI_FTSR1_FT29 EXTI_FTSR1_FT29_Msk

#define	EXTI_FTSR1_FT30_Pos (30U)

#define	EXTI_FTSR1_FT30_Msk (0x1UL << EXTI_FTSR1_FT30_Pos)

#define	EXTI_FTSR1_FT30 EXTI_FTSR1_FT30_Msk

#define	EXTI_SWIER1_SWI0_Pos (0U)

#define	EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos)

#define	EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk

#define	EXTI_SWIER1_SWI1_Pos (1U)

#define	EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos)

#define	EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk

#define	EXTI_SWIER1_SWI2_Pos (2U)

#define	EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos)

#define	EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk

#define	EXTI_SWIER1_SWI3_Pos (3U)

#define	EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos)

#define	EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk

#define	EXTI_SWIER1_SWI4_Pos (4U)

#define	EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos)

#define	EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk

#define	EXTI_SWIER1_SWI5_Pos (5U)

#define	EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos)

#define	EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk

#define	EXTI_SWIER1_SWI6_Pos (6U)

#define	EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos)

#define	EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk

#define	EXTI_SWIER1_SWI7_Pos (7U)

#define	EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos)

#define	EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk

#define	EXTI_SWIER1_SWI8_Pos (8U)

#define	EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos)

#define	EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk

#define	EXTI_SWIER1_SWI9_Pos (9U)

#define	EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos)

#define	EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk

#define	EXTI_SWIER1_SWI10_Pos (10U)

#define	EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos)

#define	EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk

#define	EXTI_SWIER1_SWI11_Pos (11U)

#define	EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos)

#define	EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk

#define	EXTI_SWIER1_SWI12_Pos (12U)

#define	EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos)

#define	EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk

#define	EXTI_SWIER1_SWI13_Pos (13U)

#define	EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos)

#define	EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk

#define	EXTI_SWIER1_SWI14_Pos (14U)

#define	EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos)

#define	EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk

#define	EXTI_SWIER1_SWI15_Pos (15U)

#define	EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos)

#define	EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk

#define	EXTI_SWIER1_SWI16_Pos (16U)

#define	EXTI_SWIER1_SWI16_Msk (0x1UL << EXTI_SWIER1_SWI16_Pos)

#define	EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk

#define	EXTI_SWIER1_SWI17_Pos (17U)

#define	EXTI_SWIER1_SWI17_Msk (0x1UL << EXTI_SWIER1_SWI17_Pos)

#define	EXTI_SWIER1_SWI17 EXTI_SWIER1_SWI17_Msk

#define	EXTI_SWIER1_SWI19_Pos (19U)

#define	EXTI_SWIER1_SWI19_Msk (0x1UL << EXTI_SWIER1_SWI19_Pos)

#define	EXTI_SWIER1_SWI19 EXTI_SWIER1_SWI19_Msk

#define	EXTI_SWIER1_SWI20_Pos (20U)

#define	EXTI_SWIER1_SWI20_Msk (0x1UL << EXTI_SWIER1_SWI20_Pos)

#define	EXTI_SWIER1_SWI20 EXTI_SWIER1_SWI20_Msk

#define	EXTI_SWIER1_SWI21_Pos (21U)

#define	EXTI_SWIER1_SWI21_Msk (0x1UL << EXTI_SWIER1_SWI21_Pos)

#define	EXTI_SWIER1_SWI21 EXTI_SWIER1_SWI21_Msk

#define	EXTI_SWIER1_SWI22_Pos (22U)

#define	EXTI_SWIER1_SWI22_Msk (0x1UL << EXTI_SWIER1_SWI22_Pos)

#define	EXTI_SWIER1_SWI22 EXTI_SWIER1_SWI22_Msk

#define	EXTI_SWIER1_SWI29_Pos (29U)

#define	EXTI_SWIER1_SWI29_Msk (0x1UL << EXTI_SWIER1_SWI29_Pos)

#define	EXTI_SWIER1_SWI29 EXTI_SWIER1_SWI29_Msk

#define	EXTI_SWIER1_SWI30_Pos (30U)

#define	EXTI_SWIER1_SWI30_Msk (0x1UL << EXTI_SWIER1_SWI30_Pos)

#define	EXTI_SWIER1_SWI30 EXTI_SWIER1_SWI30_Msk

#define	EXTI_PR1_PIF0_Pos (0U)

#define	EXTI_PR1_PIF0_Msk (0x1UL << EXTI_PR1_PIF0_Pos)

#define	EXTI_PR1_PIF0 EXTI_PR1_PIF0_Msk

#define	EXTI_PR1_PIF1_Pos (1U)

#define	EXTI_PR1_PIF1_Msk (0x1UL << EXTI_PR1_PIF1_Pos)

#define	EXTI_PR1_PIF1 EXTI_PR1_PIF1_Msk

#define	EXTI_PR1_PIF2_Pos (2U)

#define	EXTI_PR1_PIF2_Msk (0x1UL << EXTI_PR1_PIF2_Pos)

#define	EXTI_PR1_PIF2 EXTI_PR1_PIF2_Msk

#define	EXTI_PR1_PIF3_Pos (3U)

#define	EXTI_PR1_PIF3_Msk (0x1UL << EXTI_PR1_PIF3_Pos)

#define	EXTI_PR1_PIF3 EXTI_PR1_PIF3_Msk

#define	EXTI_PR1_PIF4_Pos (4U)

#define	EXTI_PR1_PIF4_Msk (0x1UL << EXTI_PR1_PIF4_Pos)

#define	EXTI_PR1_PIF4 EXTI_PR1_PIF4_Msk

#define	EXTI_PR1_PIF5_Pos (5U)

#define	EXTI_PR1_PIF5_Msk (0x1UL << EXTI_PR1_PIF5_Pos)

#define	EXTI_PR1_PIF5 EXTI_PR1_PIF5_Msk

#define	EXTI_PR1_PIF6_Pos (6U)

#define	EXTI_PR1_PIF6_Msk (0x1UL << EXTI_PR1_PIF6_Pos)

#define	EXTI_PR1_PIF6 EXTI_PR1_PIF6_Msk

#define	EXTI_PR1_PIF7_Pos (7U)

#define	EXTI_PR1_PIF7_Msk (0x1UL << EXTI_PR1_PIF7_Pos)

#define	EXTI_PR1_PIF7 EXTI_PR1_PIF7_Msk

#define	EXTI_PR1_PIF8_Pos (8U)

#define	EXTI_PR1_PIF8_Msk (0x1UL << EXTI_PR1_PIF8_Pos)

#define	EXTI_PR1_PIF8 EXTI_PR1_PIF8_Msk

#define	EXTI_PR1_PIF9_Pos (9U)

#define	EXTI_PR1_PIF9_Msk (0x1UL << EXTI_PR1_PIF9_Pos)

#define	EXTI_PR1_PIF9 EXTI_PR1_PIF9_Msk

#define	EXTI_PR1_PIF10_Pos (10U)

#define	EXTI_PR1_PIF10_Msk (0x1UL << EXTI_PR1_PIF10_Pos)

#define	EXTI_PR1_PIF10 EXTI_PR1_PIF10_Msk

#define	EXTI_PR1_PIF11_Pos (11U)

#define	EXTI_PR1_PIF11_Msk (0x1UL << EXTI_PR1_PIF11_Pos)

#define	EXTI_PR1_PIF11 EXTI_PR1_PIF11_Msk

#define	EXTI_PR1_PIF12_Pos (12U)

#define	EXTI_PR1_PIF12_Msk (0x1UL << EXTI_PR1_PIF12_Pos)

#define	EXTI_PR1_PIF12 EXTI_PR1_PIF12_Msk

#define	EXTI_PR1_PIF13_Pos (13U)

#define	EXTI_PR1_PIF13_Msk (0x1UL << EXTI_PR1_PIF13_Pos)

#define	EXTI_PR1_PIF13 EXTI_PR1_PIF13_Msk

#define	EXTI_PR1_PIF14_Pos (14U)

#define	EXTI_PR1_PIF14_Msk (0x1UL << EXTI_PR1_PIF14_Pos)

#define	EXTI_PR1_PIF14 EXTI_PR1_PIF14_Msk

#define	EXTI_PR1_PIF15_Pos (15U)

#define	EXTI_PR1_PIF15_Msk (0x1UL << EXTI_PR1_PIF15_Pos)

#define	EXTI_PR1_PIF15 EXTI_PR1_PIF15_Msk

#define	EXTI_PR1_PIF16_Pos (16U)

#define	EXTI_PR1_PIF16_Msk (0x1UL << EXTI_PR1_PIF16_Pos)

#define	EXTI_PR1_PIF16 EXTI_PR1_PIF16_Msk

#define	EXTI_PR1_PIF17_Pos (17U)

#define	EXTI_PR1_PIF17_Msk (0x1UL << EXTI_PR1_PIF17_Pos)

#define	EXTI_PR1_PIF17 EXTI_PR1_PIF17_Msk

#define	EXTI_PR1_PIF19_Pos (19U)

#define	EXTI_PR1_PIF19_Msk (0x1UL << EXTI_PR1_PIF19_Pos)

#define	EXTI_PR1_PIF19 EXTI_PR1_PIF19_Msk

#define	EXTI_PR1_PIF20_Pos (20U)

#define	EXTI_PR1_PIF20_Msk (0x1UL << EXTI_PR1_PIF20_Pos)

#define	EXTI_PR1_PIF20 EXTI_PR1_PIF20_Msk

#define	EXTI_PR1_PIF21_Pos (21U)

#define	EXTI_PR1_PIF21_Msk (0x1UL << EXTI_PR1_PIF21_Pos)

#define	EXTI_PR1_PIF21 EXTI_PR1_PIF21_Msk

#define	EXTI_PR1_PIF22_Pos (22U)

#define	EXTI_PR1_PIF22_Msk (0x1UL << EXTI_PR1_PIF22_Pos)

#define	EXTI_PR1_PIF22 EXTI_PR1_PIF22_Msk

#define	EXTI_PR1_PIF29_Pos (29U)

#define	EXTI_PR1_PIF29_Msk (0x1UL << EXTI_PR1_PIF29_Pos)

#define	EXTI_PR1_PIF29 EXTI_PR1_PIF29_Msk

#define	EXTI_PR1_PIF30_Pos (30U)

#define	EXTI_PR1_PIF30_Msk (0x1UL << EXTI_PR1_PIF30_Pos)

#define	EXTI_PR1_PIF30 EXTI_PR1_PIF30_Msk

#define	EXTI_IMR2_IM34_Pos (2U)

#define	EXTI_IMR2_IM34_Msk (0x1UL << EXTI_IMR2_IM34_Pos)

#define	EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk

#define	EXTI_IMR2_IM36_Pos (4U)

#define	EXTI_IMR2_IM36_Msk (0x1UL << EXTI_IMR2_IM36_Pos)

#define	EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk

#define	EXTI_IMR2_IM37_Pos (5U)

#define	EXTI_IMR2_IM37_Msk (0x1UL << EXTI_IMR2_IM37_Pos)

#define	EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk

#define	EXTI_IMR2_IM38_Pos (6U)

#define	EXTI_IMR2_IM38_Msk (0x1UL << EXTI_IMR2_IM38_Pos)

#define	EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk

#define	EXTI_IMR2_IM39_Pos (7U)

#define	EXTI_IMR2_IM39_Msk (0x1UL << EXTI_IMR2_IM39_Pos)

#define	EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk

#define	EXTI_IMR2_IM40_Pos (8U)

#define	EXTI_IMR2_IM40_Msk (0x1UL << EXTI_IMR2_IM40_Pos)

#define	EXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk

#define	EXTI_IMR2_IM41_Pos (9U)

#define	EXTI_IMR2_IM41_Msk (0x1UL << EXTI_IMR2_IM41_Pos)

#define	EXTI_IMR2_IM41 EXTI_IMR2_IM41_Msk

#define	EXTI_IMR2_IM_Pos (0U)

#define	EXTI_IMR2_IM_Msk (0x3F4UL << EXTI_IMR2_IM_Pos)

#define	EXTI_IMR2_IM EXTI_IMR2_IM_Msk

#define	EXTI_EMR2_EM34_Pos (2U)

#define	EXTI_EMR2_EM34_Msk (0x1UL << EXTI_EMR2_EM34_Pos)

#define	EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk

#define	EXTI_EMR2_EM36_Pos (4U)

#define	EXTI_EMR2_EM36_Msk (0x1UL << EXTI_EMR2_EM36_Pos)

#define	EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk

#define	EXTI_EMR2_EM37_Pos (5U)

#define	EXTI_EMR2_EM37_Msk (0x1UL << EXTI_EMR2_EM37_Pos)

#define	EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk

#define	EXTI_EMR2_EM38_Pos (6U)

#define	EXTI_EMR2_EM38_Msk (0x1UL << EXTI_EMR2_EM38_Pos)

#define	EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk

#define	EXTI_EMR2_EM39_Pos (7U)

#define	EXTI_EMR2_EM39_Msk (0x1UL << EXTI_EMR2_EM39_Pos)

#define	EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk

#define	EXTI_EMR2_EM40_Pos (8U)

#define	EXTI_EMR2_EM40_Msk (0x1UL << EXTI_EMR2_EM40_Pos)

#define	EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk

#define	EXTI_EMR2_EM41_Pos (9U)

#define	EXTI_EMR2_EM41_Msk (0x1UL << EXTI_EMR2_EM41_Pos)

#define	EXTI_EMR2_EM41 EXTI_EMR2_EM41_Msk

#define	EXTI_EMR2_EM_Pos (0U)

#define	EXTI_EMR2_EM_Msk (0x3F4UL << EXTI_EMR2_EM_Pos)

#define	EXTI_EMR2_EM EXTI_EMR2_EM_Msk

#define	EXTI_RTSR2_RT38_Pos (6U)

#define	EXTI_RTSR2_RT38_Msk (0x1UL << EXTI_RTSR2_RT38_Pos)

#define	EXTI_RTSR2_RT38 EXTI_RTSR2_RT38_Msk

#define	EXTI_RTSR2_RT39_Pos (7U)

#define	EXTI_RTSR2_RT39_Msk (0x1UL << EXTI_RTSR2_RT39_Pos)

#define	EXTI_RTSR2_RT39 EXTI_RTSR2_RT39_Msk

#define	EXTI_RTSR2_RT40_Pos (8U)

#define	EXTI_RTSR2_RT40_Msk (0x1UL << EXTI_RTSR2_RT40_Pos)

#define	EXTI_RTSR2_RT40 EXTI_RTSR2_RT40_Msk

#define	EXTI_RTSR2_RT41_Pos (9U)

#define	EXTI_RTSR2_RT41_Msk (0x1UL << EXTI_RTSR2_RT41_Pos)

#define	EXTI_RTSR2_RT41 EXTI_RTSR2_RT41_Msk

#define	EXTI_FTSR2_FT38_Pos (6U)

#define	EXTI_FTSR2_FT38_Msk (0x1UL << EXTI_FTSR2_FT38_Pos)

#define	EXTI_FTSR2_FT38 EXTI_FTSR2_FT38_Msk

#define	EXTI_FTSR2_FT39_Pos (7U)

#define	EXTI_FTSR2_FT39_Msk (0x1UL << EXTI_FTSR2_FT39_Pos)

#define	EXTI_FTSR2_FT39 EXTI_FTSR2_FT39_Msk

#define	EXTI_FTSR2_FT40_Pos (8U)

#define	EXTI_FTSR2_FT40_Msk (0x1UL << EXTI_FTSR2_FT40_Pos)

#define	EXTI_FTSR2_FT40 EXTI_FTSR2_FT40_Msk

#define	EXTI_FTSR2_FT41_Pos (9U)

#define	EXTI_FTSR2_FT41_Msk (0x1UL << EXTI_FTSR2_FT41_Pos)

#define	EXTI_FTSR2_FT41 EXTI_FTSR2_FT41_Msk

#define	EXTI_SWIER2_SWI38_Pos (6U)

#define	EXTI_SWIER2_SWI38_Msk (0x1UL << EXTI_SWIER2_SWI38_Pos)

#define	EXTI_SWIER2_SWI38 EXTI_SWIER2_SWI38_Msk

#define	EXTI_SWIER2_SWI39_Pos (7U)

#define	EXTI_SWIER2_SWI39_Msk (0x1UL << EXTI_SWIER2_SWI39_Pos)

#define	EXTI_SWIER2_SWI39 EXTI_SWIER2_SWI39_Msk

#define	EXTI_SWIER2_SWI40_Pos (8U)

#define	EXTI_SWIER2_SWI40_Msk (0x1UL << EXTI_SWIER2_SWI40_Pos)

#define	EXTI_SWIER2_SWI40 EXTI_SWIER2_SWI40_Msk

#define	EXTI_SWIER2_SWI41_Pos (9U)

#define	EXTI_SWIER2_SWI41_Msk (0x1UL << EXTI_SWIER2_SWI41_Pos)

#define	EXTI_SWIER2_SWI41 EXTI_SWIER2_SWI41_Msk

#define	EXTI_PR2_PIF38_Pos (6U)

#define	EXTI_PR2_PIF38_Msk (0x1UL << EXTI_PR2_PIF38_Pos)

#define	EXTI_PR2_PIF38 EXTI_PR2_PIF38_Msk

#define	EXTI_PR2_PIF39_Pos (7U)

#define	EXTI_PR2_PIF39_Msk (0x1UL << EXTI_PR2_PIF39_Pos)

#define	EXTI_PR2_PIF39 EXTI_PR2_PIF39_Msk

#define	EXTI_PR2_PIF40_Pos (8U)

#define	EXTI_PR2_PIF40_Msk (0x1UL << EXTI_PR2_PIF40_Pos)

#define	EXTI_PR2_PIF40 EXTI_PR2_PIF40_Msk

#define	EXTI_PR2_PIF41_Pos (9U)

#define	EXTI_PR2_PIF41_Msk (0x1UL << EXTI_PR2_PIF41_Pos)

#define	EXTI_PR2_PIF41 EXTI_PR2_PIF41_Msk

#define	FDCAN_CREL_DAY_Pos (0U)

#define	FDCAN_CREL_DAY_Msk (0xFFUL << FDCAN_CREL_DAY_Pos)

#define	FDCAN_CREL_DAY FDCAN_CREL_DAY_Msk

#define	FDCAN_CREL_MON_Pos (8U)

#define	FDCAN_CREL_MON_Msk (0xFFUL << FDCAN_CREL_MON_Pos)

#define	FDCAN_CREL_MON FDCAN_CREL_MON_Msk

#define	FDCAN_CREL_YEAR_Pos (16U)

#define	FDCAN_CREL_YEAR_Msk (0xFUL << FDCAN_CREL_YEAR_Pos)

#define	FDCAN_CREL_YEAR FDCAN_CREL_YEAR_Msk

#define	FDCAN_CREL_SUBSTEP_Pos (20U)

#define	FDCAN_CREL_SUBSTEP_Msk (0xFUL << FDCAN_CREL_SUBSTEP_Pos)

#define	FDCAN_CREL_SUBSTEP FDCAN_CREL_SUBSTEP_Msk

#define	FDCAN_CREL_STEP_Pos (24U)

#define	FDCAN_CREL_STEP_Msk (0xFUL << FDCAN_CREL_STEP_Pos)

#define	FDCAN_CREL_STEP FDCAN_CREL_STEP_Msk

#define	FDCAN_CREL_REL_Pos (28U)

#define	FDCAN_CREL_REL_Msk (0xFUL << FDCAN_CREL_REL_Pos)

#define	FDCAN_CREL_REL FDCAN_CREL_REL_Msk

#define	FDCAN_ENDN_ETV_Pos (0U)

#define	FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos)

#define	FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk

#define	FDCAN_DBTP_DSJW_Pos (0U)

#define	FDCAN_DBTP_DSJW_Msk (0xFUL << FDCAN_DBTP_DSJW_Pos)

#define	FDCAN_DBTP_DSJW FDCAN_DBTP_DSJW_Msk

#define	FDCAN_DBTP_DTSEG2_Pos (4U)

#define	FDCAN_DBTP_DTSEG2_Msk (0xFUL << FDCAN_DBTP_DTSEG2_Pos)

#define	FDCAN_DBTP_DTSEG2 FDCAN_DBTP_DTSEG2_Msk

#define	FDCAN_DBTP_DTSEG1_Pos (8U)

#define	FDCAN_DBTP_DTSEG1_Msk (0x1FUL << FDCAN_DBTP_DTSEG1_Pos)

#define	FDCAN_DBTP_DTSEG1 FDCAN_DBTP_DTSEG1_Msk

#define	FDCAN_DBTP_DBRP_Pos (16U)

#define	FDCAN_DBTP_DBRP_Msk (0x1FUL << FDCAN_DBTP_DBRP_Pos)

#define	FDCAN_DBTP_DBRP FDCAN_DBTP_DBRP_Msk

#define	FDCAN_DBTP_TDC_Pos (23U)

#define	FDCAN_DBTP_TDC_Msk (0x1UL << FDCAN_DBTP_TDC_Pos)

#define	FDCAN_DBTP_TDC FDCAN_DBTP_TDC_Msk

#define	FDCAN_TEST_LBCK_Pos (4U)

#define	FDCAN_TEST_LBCK_Msk (0x1UL << FDCAN_TEST_LBCK_Pos)

#define	FDCAN_TEST_LBCK FDCAN_TEST_LBCK_Msk

#define	FDCAN_TEST_TX_Pos (5U)

#define	FDCAN_TEST_TX_Msk (0x3UL << FDCAN_TEST_TX_Pos)

#define	FDCAN_TEST_TX FDCAN_TEST_TX_Msk

#define	FDCAN_TEST_RX_Pos (7U)

#define	FDCAN_TEST_RX_Msk (0x1UL << FDCAN_TEST_RX_Pos)

#define	FDCAN_TEST_RX FDCAN_TEST_RX_Msk

#define	FDCAN_RWD_WDC_Pos (0U)

#define	FDCAN_RWD_WDC_Msk (0xFFUL << FDCAN_RWD_WDC_Pos)

#define	FDCAN_RWD_WDC FDCAN_RWD_WDC_Msk

#define	FDCAN_RWD_WDV_Pos (8U)

#define	FDCAN_RWD_WDV_Msk (0xFFUL << FDCAN_RWD_WDV_Pos)

#define	FDCAN_RWD_WDV FDCAN_RWD_WDV_Msk

#define	FDCAN_CCCR_INIT_Pos (0U)

#define	FDCAN_CCCR_INIT_Msk (0x1UL << FDCAN_CCCR_INIT_Pos)

#define	FDCAN_CCCR_INIT FDCAN_CCCR_INIT_Msk

#define	FDCAN_CCCR_CCE_Pos (1U)

#define	FDCAN_CCCR_CCE_Msk (0x1UL << FDCAN_CCCR_CCE_Pos)

#define	FDCAN_CCCR_CCE FDCAN_CCCR_CCE_Msk

#define	FDCAN_CCCR_ASM_Pos (2U)

#define	FDCAN_CCCR_ASM_Msk (0x1UL << FDCAN_CCCR_ASM_Pos)

#define	FDCAN_CCCR_ASM FDCAN_CCCR_ASM_Msk

#define	FDCAN_CCCR_CSA_Pos (3U)

#define	FDCAN_CCCR_CSA_Msk (0x1UL << FDCAN_CCCR_CSA_Pos)

#define	FDCAN_CCCR_CSA FDCAN_CCCR_CSA_Msk

#define	FDCAN_CCCR_CSR_Pos (4U)

#define	FDCAN_CCCR_CSR_Msk (0x1UL << FDCAN_CCCR_CSR_Pos)

#define	FDCAN_CCCR_CSR FDCAN_CCCR_CSR_Msk

#define	FDCAN_CCCR_MON_Pos (5U)

#define	FDCAN_CCCR_MON_Msk (0x1UL << FDCAN_CCCR_MON_Pos)

#define	FDCAN_CCCR_MON FDCAN_CCCR_MON_Msk

#define	FDCAN_CCCR_DAR_Pos (6U)

#define	FDCAN_CCCR_DAR_Msk (0x1UL << FDCAN_CCCR_DAR_Pos)

#define	FDCAN_CCCR_DAR FDCAN_CCCR_DAR_Msk

#define	FDCAN_CCCR_TEST_Pos (7U)

#define	FDCAN_CCCR_TEST_Msk (0x1UL << FDCAN_CCCR_TEST_Pos)

#define	FDCAN_CCCR_TEST FDCAN_CCCR_TEST_Msk

#define	FDCAN_CCCR_FDOE_Pos (8U)

#define	FDCAN_CCCR_FDOE_Msk (0x1UL << FDCAN_CCCR_FDOE_Pos)

#define	FDCAN_CCCR_FDOE FDCAN_CCCR_FDOE_Msk

#define	FDCAN_CCCR_BRSE_Pos (9U)

#define	FDCAN_CCCR_BRSE_Msk (0x1UL << FDCAN_CCCR_BRSE_Pos)

#define	FDCAN_CCCR_BRSE FDCAN_CCCR_BRSE_Msk

#define	FDCAN_CCCR_PXHD_Pos (12U)

#define	FDCAN_CCCR_PXHD_Msk (0x1UL << FDCAN_CCCR_PXHD_Pos)

#define	FDCAN_CCCR_PXHD FDCAN_CCCR_PXHD_Msk

#define	FDCAN_CCCR_EFBI_Pos (13U)

#define	FDCAN_CCCR_EFBI_Msk (0x1UL << FDCAN_CCCR_EFBI_Pos)

#define	FDCAN_CCCR_EFBI FDCAN_CCCR_EFBI_Msk

#define	FDCAN_CCCR_TXP_Pos (14U)

#define	FDCAN_CCCR_TXP_Msk (0x1UL << FDCAN_CCCR_TXP_Pos)

#define	FDCAN_CCCR_TXP FDCAN_CCCR_TXP_Msk

#define	FDCAN_CCCR_NISO_Pos (15U)

#define	FDCAN_CCCR_NISO_Msk (0x1UL << FDCAN_CCCR_NISO_Pos)

#define	FDCAN_CCCR_NISO FDCAN_CCCR_NISO_Msk

#define	FDCAN_NBTP_NTSEG2_Pos (0U)

#define	FDCAN_NBTP_NTSEG2_Msk (0x7FUL << FDCAN_NBTP_NTSEG2_Pos)

#define	FDCAN_NBTP_NTSEG2 FDCAN_NBTP_NTSEG2_Msk

#define	FDCAN_NBTP_NTSEG1_Pos (8U)

#define	FDCAN_NBTP_NTSEG1_Msk (0xFFUL << FDCAN_NBTP_NTSEG1_Pos)

#define	FDCAN_NBTP_NTSEG1 FDCAN_NBTP_NTSEG1_Msk

#define	FDCAN_NBTP_NBRP_Pos (16U)

#define	FDCAN_NBTP_NBRP_Msk (0x1FFUL << FDCAN_NBTP_NBRP_Pos)

#define	FDCAN_NBTP_NBRP FDCAN_NBTP_NBRP_Msk

#define	FDCAN_NBTP_NSJW_Pos (25U)

#define	FDCAN_NBTP_NSJW_Msk (0x7FUL << FDCAN_NBTP_NSJW_Pos)

#define	FDCAN_NBTP_NSJW FDCAN_NBTP_NSJW_Msk

#define	FDCAN_TSCC_TSS_Pos (0U)

#define	FDCAN_TSCC_TSS_Msk (0x3UL << FDCAN_TSCC_TSS_Pos)

#define	FDCAN_TSCC_TSS FDCAN_TSCC_TSS_Msk

#define	FDCAN_TSCC_TCP_Pos (16U)

#define	FDCAN_TSCC_TCP_Msk (0xFUL << FDCAN_TSCC_TCP_Pos)

#define	FDCAN_TSCC_TCP FDCAN_TSCC_TCP_Msk

#define	FDCAN_TSCV_TSC_Pos (0U)

#define	FDCAN_TSCV_TSC_Msk (0xFFFFUL << FDCAN_TSCV_TSC_Pos)

#define	FDCAN_TSCV_TSC FDCAN_TSCV_TSC_Msk

#define	FDCAN_TOCC_ETOC_Pos (0U)

#define	FDCAN_TOCC_ETOC_Msk (0x1UL << FDCAN_TOCC_ETOC_Pos)

#define	FDCAN_TOCC_ETOC FDCAN_TOCC_ETOC_Msk

#define	FDCAN_TOCC_TOS_Pos (1U)

#define	FDCAN_TOCC_TOS_Msk (0x3UL << FDCAN_TOCC_TOS_Pos)

#define	FDCAN_TOCC_TOS FDCAN_TOCC_TOS_Msk

#define	FDCAN_TOCC_TOP_Pos (16U)

#define	FDCAN_TOCC_TOP_Msk (0xFFFFUL << FDCAN_TOCC_TOP_Pos)

#define	FDCAN_TOCC_TOP FDCAN_TOCC_TOP_Msk

#define	FDCAN_TOCV_TOC_Pos (0U)

#define	FDCAN_TOCV_TOC_Msk (0xFFFFUL << FDCAN_TOCV_TOC_Pos)

#define	FDCAN_TOCV_TOC FDCAN_TOCV_TOC_Msk

#define	FDCAN_ECR_TEC_Pos (0U)

#define	FDCAN_ECR_TEC_Msk (0xFFUL << FDCAN_ECR_TEC_Pos)

#define	FDCAN_ECR_TEC FDCAN_ECR_TEC_Msk

#define	FDCAN_ECR_REC_Pos (8U)

#define	FDCAN_ECR_REC_Msk (0x7FUL << FDCAN_ECR_REC_Pos)

#define	FDCAN_ECR_REC FDCAN_ECR_REC_Msk

#define	FDCAN_ECR_RP_Pos (15U)

#define	FDCAN_ECR_RP_Msk (0x1UL << FDCAN_ECR_RP_Pos)

#define	FDCAN_ECR_RP FDCAN_ECR_RP_Msk

#define	FDCAN_ECR_CEL_Pos (16U)

#define	FDCAN_ECR_CEL_Msk (0xFFUL << FDCAN_ECR_CEL_Pos)

#define	FDCAN_ECR_CEL FDCAN_ECR_CEL_Msk

#define	FDCAN_PSR_LEC_Pos (0U)

#define	FDCAN_PSR_LEC_Msk (0x7UL << FDCAN_PSR_LEC_Pos)

#define	FDCAN_PSR_LEC FDCAN_PSR_LEC_Msk

#define	FDCAN_PSR_ACT_Pos (3U)

#define	FDCAN_PSR_ACT_Msk (0x3UL << FDCAN_PSR_ACT_Pos)

#define	FDCAN_PSR_ACT FDCAN_PSR_ACT_Msk

#define	FDCAN_PSR_EP_Pos (5U)

#define	FDCAN_PSR_EP_Msk (0x1UL << FDCAN_PSR_EP_Pos)

#define	FDCAN_PSR_EP FDCAN_PSR_EP_Msk

#define	FDCAN_PSR_EW_Pos (6U)

#define	FDCAN_PSR_EW_Msk (0x1UL << FDCAN_PSR_EW_Pos)

#define	FDCAN_PSR_EW FDCAN_PSR_EW_Msk

#define	FDCAN_PSR_BO_Pos (7U)

#define	FDCAN_PSR_BO_Msk (0x1UL << FDCAN_PSR_BO_Pos)

#define	FDCAN_PSR_BO FDCAN_PSR_BO_Msk

#define	FDCAN_PSR_DLEC_Pos (8U)

#define	FDCAN_PSR_DLEC_Msk (0x7UL << FDCAN_PSR_DLEC_Pos)

#define	FDCAN_PSR_DLEC FDCAN_PSR_DLEC_Msk

#define	FDCAN_PSR_RESI_Pos (11U)

#define	FDCAN_PSR_RESI_Msk (0x1UL << FDCAN_PSR_RESI_Pos)

#define	FDCAN_PSR_RESI FDCAN_PSR_RESI_Msk

#define	FDCAN_PSR_RBRS_Pos (12U)

#define	FDCAN_PSR_RBRS_Msk (0x1UL << FDCAN_PSR_RBRS_Pos)

#define	FDCAN_PSR_RBRS FDCAN_PSR_RBRS_Msk

#define	FDCAN_PSR_REDL_Pos (13U)

#define	FDCAN_PSR_REDL_Msk (0x1UL << FDCAN_PSR_REDL_Pos)

#define	FDCAN_PSR_REDL FDCAN_PSR_REDL_Msk

#define	FDCAN_PSR_PXE_Pos (14U)

#define	FDCAN_PSR_PXE_Msk (0x1UL << FDCAN_PSR_PXE_Pos)

#define	FDCAN_PSR_PXE FDCAN_PSR_PXE_Msk

#define	FDCAN_PSR_TDCV_Pos (16U)

#define	FDCAN_PSR_TDCV_Msk (0x7FUL << FDCAN_PSR_TDCV_Pos)

#define	FDCAN_PSR_TDCV FDCAN_PSR_TDCV_Msk

#define	FDCAN_TDCR_TDCF_Pos (0U)

#define	FDCAN_TDCR_TDCF_Msk (0x7FUL << FDCAN_TDCR_TDCF_Pos)

#define	FDCAN_TDCR_TDCF FDCAN_TDCR_TDCF_Msk

#define	FDCAN_TDCR_TDCO_Pos (8U)

#define	FDCAN_TDCR_TDCO_Msk (0x7FUL << FDCAN_TDCR_TDCO_Pos)

#define	FDCAN_TDCR_TDCO FDCAN_TDCR_TDCO_Msk

#define	FDCAN_IR_RF0N_Pos (0U)

#define	FDCAN_IR_RF0N_Msk (0x1UL << FDCAN_IR_RF0N_Pos)

#define	FDCAN_IR_RF0N FDCAN_IR_RF0N_Msk

#define	FDCAN_IR_RF0F_Pos (1U)

#define	FDCAN_IR_RF0F_Msk (0x1UL << FDCAN_IR_RF0F_Pos)

#define	FDCAN_IR_RF0F FDCAN_IR_RF0F_Msk

#define	FDCAN_IR_RF0L_Pos (2U)

#define	FDCAN_IR_RF0L_Msk (0x1UL << FDCAN_IR_RF0L_Pos)

#define	FDCAN_IR_RF0L FDCAN_IR_RF0L_Msk

#define	FDCAN_IR_RF1N_Pos (3U)

#define	FDCAN_IR_RF1N_Msk (0x1UL << FDCAN_IR_RF1N_Pos)

#define	FDCAN_IR_RF1N FDCAN_IR_RF1N_Msk

#define	FDCAN_IR_RF1F_Pos (4U)

#define	FDCAN_IR_RF1F_Msk (0x1UL << FDCAN_IR_RF1F_Pos)

#define	FDCAN_IR_RF1F FDCAN_IR_RF1F_Msk

#define	FDCAN_IR_RF1L_Pos (5U)

#define	FDCAN_IR_RF1L_Msk (0x1UL << FDCAN_IR_RF1L_Pos)

#define	FDCAN_IR_RF1L FDCAN_IR_RF1L_Msk

#define	FDCAN_IR_HPM_Pos (6U)

#define	FDCAN_IR_HPM_Msk (0x1UL << FDCAN_IR_HPM_Pos)

#define	FDCAN_IR_HPM FDCAN_IR_HPM_Msk

#define	FDCAN_IR_TC_Pos (7U)

#define	FDCAN_IR_TC_Msk (0x1UL << FDCAN_IR_TC_Pos)

#define	FDCAN_IR_TC FDCAN_IR_TC_Msk

#define	FDCAN_IR_TCF_Pos (8U)

#define	FDCAN_IR_TCF_Msk (0x1UL << FDCAN_IR_TCF_Pos)

#define	FDCAN_IR_TCF FDCAN_IR_TCF_Msk

#define	FDCAN_IR_TFE_Pos (9U)

#define	FDCAN_IR_TFE_Msk (0x1UL << FDCAN_IR_TFE_Pos)

#define	FDCAN_IR_TFE FDCAN_IR_TFE_Msk

#define	FDCAN_IR_TEFN_Pos (10U)

#define	FDCAN_IR_TEFN_Msk (0x1UL << FDCAN_IR_TEFN_Pos)

#define	FDCAN_IR_TEFN FDCAN_IR_TEFN_Msk

#define	FDCAN_IR_TEFF_Pos (11U)

#define	FDCAN_IR_TEFF_Msk (0x1UL << FDCAN_IR_TEFF_Pos)

#define	FDCAN_IR_TEFF FDCAN_IR_TEFF_Msk

#define	FDCAN_IR_TEFL_Pos (12U)

#define	FDCAN_IR_TEFL_Msk (0x1UL << FDCAN_IR_TEFL_Pos)

#define	FDCAN_IR_TEFL FDCAN_IR_TEFL_Msk

#define	FDCAN_IR_TSW_Pos (13U)

#define	FDCAN_IR_TSW_Msk (0x1UL << FDCAN_IR_TSW_Pos)

#define	FDCAN_IR_TSW FDCAN_IR_TSW_Msk

#define	FDCAN_IR_MRAF_Pos (14U)

#define	FDCAN_IR_MRAF_Msk (0x1UL << FDCAN_IR_MRAF_Pos)

#define	FDCAN_IR_MRAF FDCAN_IR_MRAF_Msk

#define	FDCAN_IR_TOO_Pos (15U)

#define	FDCAN_IR_TOO_Msk (0x1UL << FDCAN_IR_TOO_Pos)

#define	FDCAN_IR_TOO FDCAN_IR_TOO_Msk

#define	FDCAN_IR_ELO_Pos (16U)

#define	FDCAN_IR_ELO_Msk (0x1UL << FDCAN_IR_ELO_Pos)

#define	FDCAN_IR_ELO FDCAN_IR_ELO_Msk

#define	FDCAN_IR_EP_Pos (17U)

#define	FDCAN_IR_EP_Msk (0x1UL << FDCAN_IR_EP_Pos)

#define	FDCAN_IR_EP FDCAN_IR_EP_Msk

#define	FDCAN_IR_EW_Pos (18U)

#define	FDCAN_IR_EW_Msk (0x1UL << FDCAN_IR_EW_Pos)

#define	FDCAN_IR_EW FDCAN_IR_EW_Msk

#define	FDCAN_IR_BO_Pos (19U)

#define	FDCAN_IR_BO_Msk (0x1UL << FDCAN_IR_BO_Pos)

#define	FDCAN_IR_BO FDCAN_IR_BO_Msk

#define	FDCAN_IR_WDI_Pos (20U)

#define	FDCAN_IR_WDI_Msk (0x1UL << FDCAN_IR_WDI_Pos)

#define	FDCAN_IR_WDI FDCAN_IR_WDI_Msk

#define	FDCAN_IR_PEA_Pos (21U)

#define	FDCAN_IR_PEA_Msk (0x1UL << FDCAN_IR_PEA_Pos)

#define	FDCAN_IR_PEA FDCAN_IR_PEA_Msk

#define	FDCAN_IR_PED_Pos (22U)

#define	FDCAN_IR_PED_Msk (0x1UL << FDCAN_IR_PED_Pos)

#define	FDCAN_IR_PED FDCAN_IR_PED_Msk

#define	FDCAN_IR_ARA_Pos (23U)

#define	FDCAN_IR_ARA_Msk (0x1UL << FDCAN_IR_ARA_Pos)

#define	FDCAN_IR_ARA FDCAN_IR_ARA_Msk

#define	FDCAN_IE_RF0NE_Pos (0U)

#define	FDCAN_IE_RF0NE_Msk (0x1UL << FDCAN_IE_RF0NE_Pos)

#define	FDCAN_IE_RF0NE FDCAN_IE_RF0NE_Msk

#define	FDCAN_IE_RF0FE_Pos (1U)

#define	FDCAN_IE_RF0FE_Msk (0x1UL << FDCAN_IE_RF0FE_Pos)

#define	FDCAN_IE_RF0FE FDCAN_IE_RF0FE_Msk

#define	FDCAN_IE_RF0LE_Pos (2U)

#define	FDCAN_IE_RF0LE_Msk (0x1UL << FDCAN_IE_RF0LE_Pos)

#define	FDCAN_IE_RF0LE FDCAN_IE_RF0LE_Msk

#define	FDCAN_IE_RF1NE_Pos (3U)

#define	FDCAN_IE_RF1NE_Msk (0x1UL << FDCAN_IE_RF1NE_Pos)

#define	FDCAN_IE_RF1NE FDCAN_IE_RF1NE_Msk

#define	FDCAN_IE_RF1FE_Pos (4U)

#define	FDCAN_IE_RF1FE_Msk (0x1UL << FDCAN_IE_RF1FE_Pos)

#define	FDCAN_IE_RF1FE FDCAN_IE_RF1FE_Msk

#define	FDCAN_IE_RF1LE_Pos (5U)

#define	FDCAN_IE_RF1LE_Msk (0x1UL << FDCAN_IE_RF1LE_Pos)

#define	FDCAN_IE_RF1LE FDCAN_IE_RF1LE_Msk

#define	FDCAN_IE_HPME_Pos (6U)

#define	FDCAN_IE_HPME_Msk (0x1UL << FDCAN_IE_HPME_Pos)

#define	FDCAN_IE_HPME FDCAN_IE_HPME_Msk

#define	FDCAN_IE_TCE_Pos (7U)

#define	FDCAN_IE_TCE_Msk (0x1UL << FDCAN_IE_TCE_Pos)

#define	FDCAN_IE_TCE FDCAN_IE_TCE_Msk

#define	FDCAN_IE_TCFE_Pos (8U)

#define	FDCAN_IE_TCFE_Msk (0x1UL << FDCAN_IE_TCFE_Pos)

#define	FDCAN_IE_TCFE FDCAN_IE_TCFE_Msk

#define	FDCAN_IE_TFEE_Pos (9U)

#define	FDCAN_IE_TFEE_Msk (0x1UL << FDCAN_IE_TFEE_Pos)

#define	FDCAN_IE_TFEE FDCAN_IE_TFEE_Msk

#define	FDCAN_IE_TEFNE_Pos (10U)

#define	FDCAN_IE_TEFNE_Msk (0x1UL << FDCAN_IE_TEFNE_Pos)

#define	FDCAN_IE_TEFNE FDCAN_IE_TEFNE_Msk

#define	FDCAN_IE_TEFFE_Pos (11U)

#define	FDCAN_IE_TEFFE_Msk (0x1UL << FDCAN_IE_TEFFE_Pos)

#define	FDCAN_IE_TEFFE FDCAN_IE_TEFFE_Msk

#define	FDCAN_IE_TEFLE_Pos (12U)

#define	FDCAN_IE_TEFLE_Msk (0x1UL << FDCAN_IE_TEFLE_Pos)

#define	FDCAN_IE_TEFLE FDCAN_IE_TEFLE_Msk

#define	FDCAN_IE_TSWE_Pos (13U)

#define	FDCAN_IE_TSWE_Msk (0x1UL << FDCAN_IE_TSWE_Pos)

#define	FDCAN_IE_TSWE FDCAN_IE_TSWE_Msk

#define	FDCAN_IE_MRAFE_Pos (14U)

#define	FDCAN_IE_MRAFE_Msk (0x1UL << FDCAN_IE_MRAFE_Pos)

#define	FDCAN_IE_MRAFE FDCAN_IE_MRAFE_Msk

#define	FDCAN_IE_TOOE_Pos (15U)

#define	FDCAN_IE_TOOE_Msk (0x1UL << FDCAN_IE_TOOE_Pos)

#define	FDCAN_IE_TOOE FDCAN_IE_TOOE_Msk

#define	FDCAN_IE_ELOE_Pos (16U)

#define	FDCAN_IE_ELOE_Msk (0x1UL << FDCAN_IE_ELOE_Pos)

#define	FDCAN_IE_ELOE FDCAN_IE_ELOE_Msk

#define	FDCAN_IE_EPE_Pos (17U)

#define	FDCAN_IE_EPE_Msk (0x1UL << FDCAN_IE_EPE_Pos)

#define	FDCAN_IE_EPE FDCAN_IE_EPE_Msk

#define	FDCAN_IE_EWE_Pos (18U)

#define	FDCAN_IE_EWE_Msk (0x1UL << FDCAN_IE_EWE_Pos)

#define	FDCAN_IE_EWE FDCAN_IE_EWE_Msk

#define	FDCAN_IE_BOE_Pos (19U)

#define	FDCAN_IE_BOE_Msk (0x1UL << FDCAN_IE_BOE_Pos)

#define	FDCAN_IE_BOE FDCAN_IE_BOE_Msk

#define	FDCAN_IE_WDIE_Pos (20U)

#define	FDCAN_IE_WDIE_Msk (0x1UL << FDCAN_IE_WDIE_Pos)

#define	FDCAN_IE_WDIE FDCAN_IE_WDIE_Msk

#define	FDCAN_IE_PEAE_Pos (21U)

#define	FDCAN_IE_PEAE_Msk (0x1UL << FDCAN_IE_PEAE_Pos)

#define	FDCAN_IE_PEAE FDCAN_IE_PEAE_Msk

#define	FDCAN_IE_PEDE_Pos (22U)

#define	FDCAN_IE_PEDE_Msk (0x1UL << FDCAN_IE_PEDE_Pos)

#define	FDCAN_IE_PEDE FDCAN_IE_PEDE_Msk

#define	FDCAN_IE_ARAE_Pos (23U)

#define	FDCAN_IE_ARAE_Msk (0x1UL << FDCAN_IE_ARAE_Pos)

#define	FDCAN_IE_ARAE FDCAN_IE_ARAE_Msk

#define	FDCAN_ILS_RXFIFO0_Pos (0U)

#define	FDCAN_ILS_RXFIFO0_Msk (0x1UL << FDCAN_ILS_RXFIFO0_Pos)

#define	FDCAN_ILS_RXFIFO0 FDCAN_ILS_RXFIFO0_Msk

#define	FDCAN_ILS_RXFIFO1_Pos (1U)

#define	FDCAN_ILS_RXFIFO1_Msk (0x1UL << FDCAN_ILS_RXFIFO1_Pos)

#define	FDCAN_ILS_RXFIFO1 FDCAN_ILS_RXFIFO1_Msk

#define	FDCAN_ILS_SMSG_Pos (2U)

#define	FDCAN_ILS_SMSG_Msk (0x1UL << FDCAN_ILS_SMSG_Pos)

#define	FDCAN_ILS_SMSG FDCAN_ILS_SMSG_Msk

#define	FDCAN_ILS_TFERR_Pos (3U)

#define	FDCAN_ILS_TFERR_Msk (0x1UL << FDCAN_ILS_TFERR_Pos)

#define	FDCAN_ILS_TFERR FDCAN_ILS_TFERR_Msk

#define	FDCAN_ILS_MISC_Pos (4U)

#define	FDCAN_ILS_MISC_Msk (0x1UL << FDCAN_ILS_MISC_Pos)

#define	FDCAN_ILS_MISC FDCAN_ILS_MISC_Msk

#define	FDCAN_ILS_BERR_Pos (5U)

#define	FDCAN_ILS_BERR_Msk (0x1UL << FDCAN_ILS_BERR_Pos)

#define	FDCAN_ILS_BERR FDCAN_ILS_BERR_Msk

#define	FDCAN_ILS_PERR_Pos (6U)

#define	FDCAN_ILS_PERR_Msk (0x1UL << FDCAN_ILS_PERR_Pos)

#define	FDCAN_ILS_PERR FDCAN_ILS_PERR_Msk

#define	FDCAN_ILE_EINT0_Pos (0U)

#define	FDCAN_ILE_EINT0_Msk (0x1UL << FDCAN_ILE_EINT0_Pos)

#define	FDCAN_ILE_EINT0 FDCAN_ILE_EINT0_Msk

#define	FDCAN_ILE_EINT1_Pos (1U)

#define	FDCAN_ILE_EINT1_Msk (0x1UL << FDCAN_ILE_EINT1_Pos)

#define	FDCAN_ILE_EINT1 FDCAN_ILE_EINT1_Msk

#define	FDCAN_RXGFC_RRFE_Pos (0U)

#define	FDCAN_RXGFC_RRFE_Msk (0x1UL << FDCAN_RXGFC_RRFE_Pos)

#define	FDCAN_RXGFC_RRFE FDCAN_RXGFC_RRFE_Msk

#define	FDCAN_RXGFC_RRFS_Pos (1U)

#define	FDCAN_RXGFC_RRFS_Msk (0x1UL << FDCAN_RXGFC_RRFS_Pos)

#define	FDCAN_RXGFC_RRFS FDCAN_RXGFC_RRFS_Msk

#define	FDCAN_RXGFC_ANFE_Pos (2U)

#define	FDCAN_RXGFC_ANFE_Msk (0x3UL << FDCAN_RXGFC_ANFE_Pos)

#define	FDCAN_RXGFC_ANFE FDCAN_RXGFC_ANFE_Msk

#define	FDCAN_RXGFC_ANFS_Pos (4U)

#define	FDCAN_RXGFC_ANFS_Msk (0x3UL << FDCAN_RXGFC_ANFS_Pos)

#define	FDCAN_RXGFC_ANFS FDCAN_RXGFC_ANFS_Msk

#define	FDCAN_RXGFC_F1OM_Pos (8U)

#define	FDCAN_RXGFC_F1OM_Msk (0x1UL << FDCAN_RXGFC_F1OM_Pos)

#define	FDCAN_RXGFC_F1OM FDCAN_RXGFC_F1OM_Msk

#define	FDCAN_RXGFC_F0OM_Pos (9U)

#define	FDCAN_RXGFC_F0OM_Msk (0x1UL << FDCAN_RXGFC_F0OM_Pos)

#define	FDCAN_RXGFC_F0OM FDCAN_RXGFC_F0OM_Msk

#define	FDCAN_RXGFC_LSS_Pos (16U)

#define	FDCAN_RXGFC_LSS_Msk (0x1FUL << FDCAN_RXGFC_LSS_Pos)

#define	FDCAN_RXGFC_LSS FDCAN_RXGFC_LSS_Msk

#define	FDCAN_RXGFC_LSE_Pos (24U)

#define	FDCAN_RXGFC_LSE_Msk (0xFUL << FDCAN_RXGFC_LSE_Pos)

#define	FDCAN_RXGFC_LSE FDCAN_RXGFC_LSE_Msk

#define	FDCAN_XIDAM_EIDM_Pos (0U)

#define	FDCAN_XIDAM_EIDM_Msk (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos)

#define	FDCAN_XIDAM_EIDM FDCAN_XIDAM_EIDM_Msk

#define	FDCAN_HPMS_BIDX_Pos (0U)

#define	FDCAN_HPMS_BIDX_Msk (0x7UL << FDCAN_HPMS_BIDX_Pos)

#define	FDCAN_HPMS_BIDX FDCAN_HPMS_BIDX_Msk

#define	FDCAN_HPMS_MSI_Pos (6U)

#define	FDCAN_HPMS_MSI_Msk (0x3UL << FDCAN_HPMS_MSI_Pos)

#define	FDCAN_HPMS_MSI FDCAN_HPMS_MSI_Msk

#define	FDCAN_HPMS_FIDX_Pos (8U)

#define	FDCAN_HPMS_FIDX_Msk (0x1FUL << FDCAN_HPMS_FIDX_Pos)

#define	FDCAN_HPMS_FIDX FDCAN_HPMS_FIDX_Msk

#define	FDCAN_HPMS_FLST_Pos (15U)

#define	FDCAN_HPMS_FLST_Msk (0x1UL << FDCAN_HPMS_FLST_Pos)

#define	FDCAN_HPMS_FLST FDCAN_HPMS_FLST_Msk

#define	FDCAN_RXF0S_F0FL_Pos (0U)

#define	FDCAN_RXF0S_F0FL_Msk (0xFUL << FDCAN_RXF0S_F0FL_Pos)

#define	FDCAN_RXF0S_F0FL FDCAN_RXF0S_F0FL_Msk

#define	FDCAN_RXF0S_F0GI_Pos (8U)

#define	FDCAN_RXF0S_F0GI_Msk (0x3UL << FDCAN_RXF0S_F0GI_Pos)

#define	FDCAN_RXF0S_F0GI FDCAN_RXF0S_F0GI_Msk

#define	FDCAN_RXF0S_F0PI_Pos (16U)

#define	FDCAN_RXF0S_F0PI_Msk (0x3UL << FDCAN_RXF0S_F0PI_Pos)

#define	FDCAN_RXF0S_F0PI FDCAN_RXF0S_F0PI_Msk

#define	FDCAN_RXF0S_F0F_Pos (24U)

#define	FDCAN_RXF0S_F0F_Msk (0x1UL << FDCAN_RXF0S_F0F_Pos)

#define	FDCAN_RXF0S_F0F FDCAN_RXF0S_F0F_Msk

#define	FDCAN_RXF0S_RF0L_Pos (25U)

#define	FDCAN_RXF0S_RF0L_Msk (0x1UL << FDCAN_RXF0S_RF0L_Pos)

#define	FDCAN_RXF0S_RF0L FDCAN_RXF0S_RF0L_Msk

#define	FDCAN_RXF0A_F0AI_Pos (0U)

#define	FDCAN_RXF0A_F0AI_Msk (0x7UL << FDCAN_RXF0A_F0AI_Pos)

#define	FDCAN_RXF0A_F0AI FDCAN_RXF0A_F0AI_Msk

#define	FDCAN_RXF1S_F1FL_Pos (0U)

#define	FDCAN_RXF1S_F1FL_Msk (0xFUL << FDCAN_RXF1S_F1FL_Pos)

#define	FDCAN_RXF1S_F1FL FDCAN_RXF1S_F1FL_Msk

#define	FDCAN_RXF1S_F1GI_Pos (8U)

#define	FDCAN_RXF1S_F1GI_Msk (0x3UL << FDCAN_RXF1S_F1GI_Pos)

#define	FDCAN_RXF1S_F1GI FDCAN_RXF1S_F1GI_Msk

#define	FDCAN_RXF1S_F1PI_Pos (16U)

#define	FDCAN_RXF1S_F1PI_Msk (0x3UL << FDCAN_RXF1S_F1PI_Pos)

#define	FDCAN_RXF1S_F1PI FDCAN_RXF1S_F1PI_Msk

#define	FDCAN_RXF1S_F1F_Pos (24U)

#define	FDCAN_RXF1S_F1F_Msk (0x1UL << FDCAN_RXF1S_F1F_Pos)

#define	FDCAN_RXF1S_F1F FDCAN_RXF1S_F1F_Msk

#define	FDCAN_RXF1S_RF1L_Pos (25U)

#define	FDCAN_RXF1S_RF1L_Msk (0x1UL << FDCAN_RXF1S_RF1L_Pos)

#define	FDCAN_RXF1S_RF1L FDCAN_RXF1S_RF1L_Msk

#define	FDCAN_RXF1A_F1AI_Pos (0U)

#define	FDCAN_RXF1A_F1AI_Msk (0x7UL << FDCAN_RXF1A_F1AI_Pos)

#define	FDCAN_RXF1A_F1AI FDCAN_RXF1A_F1AI_Msk

#define	FDCAN_TXBC_TFQM_Pos (24U)

#define	FDCAN_TXBC_TFQM_Msk (0x1UL << FDCAN_TXBC_TFQM_Pos)

#define	FDCAN_TXBC_TFQM FDCAN_TXBC_TFQM_Msk

#define	FDCAN_TXFQS_TFFL_Pos (0U)

#define	FDCAN_TXFQS_TFFL_Msk (0x7UL << FDCAN_TXFQS_TFFL_Pos)

#define	FDCAN_TXFQS_TFFL FDCAN_TXFQS_TFFL_Msk

#define	FDCAN_TXFQS_TFGI_Pos (8U)

#define	FDCAN_TXFQS_TFGI_Msk (0x3UL << FDCAN_TXFQS_TFGI_Pos)

#define	FDCAN_TXFQS_TFGI FDCAN_TXFQS_TFGI_Msk

#define	FDCAN_TXFQS_TFQPI_Pos (16U)

#define	FDCAN_TXFQS_TFQPI_Msk (0x3UL << FDCAN_TXFQS_TFQPI_Pos)

#define	FDCAN_TXFQS_TFQPI FDCAN_TXFQS_TFQPI_Msk

#define	FDCAN_TXFQS_TFQF_Pos (21U)

#define	FDCAN_TXFQS_TFQF_Msk (0x1UL << FDCAN_TXFQS_TFQF_Pos)

#define	FDCAN_TXFQS_TFQF FDCAN_TXFQS_TFQF_Msk

#define	FDCAN_TXBRP_TRP_Pos (0U)

#define	FDCAN_TXBRP_TRP_Msk (0x7UL << FDCAN_TXBRP_TRP_Pos)

#define	FDCAN_TXBRP_TRP FDCAN_TXBRP_TRP_Msk

#define	FDCAN_TXBAR_AR_Pos (0U)

#define	FDCAN_TXBAR_AR_Msk (0x7UL << FDCAN_TXBAR_AR_Pos)

#define	FDCAN_TXBAR_AR FDCAN_TXBAR_AR_Msk

#define	FDCAN_TXBCR_CR_Pos (0U)

#define	FDCAN_TXBCR_CR_Msk (0x7UL << FDCAN_TXBCR_CR_Pos)

#define	FDCAN_TXBCR_CR FDCAN_TXBCR_CR_Msk

#define	FDCAN_TXBTO_TO_Pos (0U)

#define	FDCAN_TXBTO_TO_Msk (0x7UL << FDCAN_TXBTO_TO_Pos)

#define	FDCAN_TXBTO_TO FDCAN_TXBTO_TO_Msk

#define	FDCAN_TXBCF_CF_Pos (0U)

#define	FDCAN_TXBCF_CF_Msk (0x7UL << FDCAN_TXBCF_CF_Pos)

#define	FDCAN_TXBCF_CF FDCAN_TXBCF_CF_Msk

#define	FDCAN_TXBTIE_TIE_Pos (0U)

#define	FDCAN_TXBTIE_TIE_Msk (0x7UL << FDCAN_TXBTIE_TIE_Pos)

#define	FDCAN_TXBTIE_TIE FDCAN_TXBTIE_TIE_Msk

#define	FDCAN_TXBCIE_CFIE_Pos (0U)

#define	FDCAN_TXBCIE_CFIE_Msk (0x7UL << FDCAN_TXBCIE_CFIE_Pos)

#define	FDCAN_TXBCIE_CFIE FDCAN_TXBCIE_CFIE_Msk

#define	FDCAN_TXEFS_EFFL_Pos (0U)

#define	FDCAN_TXEFS_EFFL_Msk (0x7UL << FDCAN_TXEFS_EFFL_Pos)

#define	FDCAN_TXEFS_EFFL FDCAN_TXEFS_EFFL_Msk

#define	FDCAN_TXEFS_EFGI_Pos (8U)

#define	FDCAN_TXEFS_EFGI_Msk (0x3UL << FDCAN_TXEFS_EFGI_Pos)

#define	FDCAN_TXEFS_EFGI FDCAN_TXEFS_EFGI_Msk

#define	FDCAN_TXEFS_EFPI_Pos (16U)

#define	FDCAN_TXEFS_EFPI_Msk (0x3UL << FDCAN_TXEFS_EFPI_Pos)

#define	FDCAN_TXEFS_EFPI FDCAN_TXEFS_EFPI_Msk

#define	FDCAN_TXEFS_EFF_Pos (24U)

#define	FDCAN_TXEFS_EFF_Msk (0x1UL << FDCAN_TXEFS_EFF_Pos)

#define	FDCAN_TXEFS_EFF FDCAN_TXEFS_EFF_Msk

#define	FDCAN_TXEFS_TEFL_Pos (25U)

#define	FDCAN_TXEFS_TEFL_Msk (0x1UL << FDCAN_TXEFS_TEFL_Pos)

#define	FDCAN_TXEFS_TEFL FDCAN_TXEFS_TEFL_Msk

#define	FDCAN_TXEFA_EFAI_Pos (0U)

#define	FDCAN_TXEFA_EFAI_Msk (0x3UL << FDCAN_TXEFA_EFAI_Pos)

#define	FDCAN_TXEFA_EFAI FDCAN_TXEFA_EFAI_Msk

#define	FDCAN_CKDIV_PDIV_Pos (0U)

#define	FDCAN_CKDIV_PDIV_Msk (0xFUL << FDCAN_CKDIV_PDIV_Pos)

#define	FDCAN_CKDIV_PDIV FDCAN_CKDIV_PDIV_Msk

#define	FLASH_ACR_LATENCY_Pos (0U)

#define	FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos)

#define	FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk

#define	FLASH_ACR_LATENCY_0WS (0x00000000U)

#define	FLASH_ACR_LATENCY_1WS (0x00000001U)

#define	FLASH_ACR_LATENCY_2WS (0x00000002U)

#define	FLASH_ACR_LATENCY_3WS (0x00000003U)

#define	FLASH_ACR_LATENCY_4WS (0x00000004U)

#define	FLASH_ACR_LATENCY_5WS (0x00000005U)

#define	FLASH_ACR_LATENCY_6WS (0x00000006U)

#define	FLASH_ACR_LATENCY_7WS (0x00000007U)

#define	FLASH_ACR_LATENCY_8WS (0x00000008U)

#define	FLASH_ACR_LATENCY_9WS (0x00000009U)

#define	FLASH_ACR_LATENCY_10WS (0x0000000AU)

#define	FLASH_ACR_LATENCY_11WS (0x0000000BU)

#define	FLASH_ACR_LATENCY_12WS (0x0000000CU)

#define	FLASH_ACR_LATENCY_13WS (0x0000000DU)

#define	FLASH_ACR_LATENCY_14WS (0x0000000EU)

#define	FLASH_ACR_LATENCY_15WS (0x0000000FU)

#define	FLASH_ACR_PRFTEN_Pos (8U)

#define	FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos)

#define	FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk

#define	FLASH_ACR_ICEN_Pos (9U)

#define	FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos)

#define	FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk

#define	FLASH_ACR_DCEN_Pos (10U)

#define	FLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos)

#define	FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk

#define	FLASH_ACR_ICRST_Pos (11U)

#define	FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos)

#define	FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk

#define	FLASH_ACR_DCRST_Pos (12U)

#define	FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos)

#define	FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk

#define	FLASH_ACR_RUN_PD_Pos (13U)

#define	FLASH_ACR_RUN_PD_Msk (0x1UL << FLASH_ACR_RUN_PD_Pos)

#define	FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk

#define	FLASH_ACR_SLEEP_PD_Pos (14U)

#define	FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos)

#define	FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk

#define	FLASH_ACR_DBG_SWEN_Pos (18U)

#define	FLASH_ACR_DBG_SWEN_Msk (0x1UL << FLASH_ACR_DBG_SWEN_Pos)

#define	FLASH_ACR_DBG_SWEN FLASH_ACR_DBG_SWEN_Msk

#define	FLASH_SR_EOP_Pos (0U)

#define	FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos)

#define	FLASH_SR_EOP FLASH_SR_EOP_Msk

#define	FLASH_SR_OPERR_Pos (1U)

#define	FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos)

#define	FLASH_SR_OPERR FLASH_SR_OPERR_Msk

#define	FLASH_SR_PROGERR_Pos (3U)

#define	FLASH_SR_PROGERR_Msk (0x1UL << FLASH_SR_PROGERR_Pos)

#define	FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk

#define	FLASH_SR_WRPERR_Pos (4U)

#define	FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos)

#define	FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk

#define	FLASH_SR_PGAERR_Pos (5U)

#define	FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos)

#define	FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk

#define	FLASH_SR_SIZERR_Pos (6U)

#define	FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos)

#define	FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk

#define	FLASH_SR_PGSERR_Pos (7U)

#define	FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos)

#define	FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk

#define	FLASH_SR_MISERR_Pos (8U)

#define	FLASH_SR_MISERR_Msk (0x1UL << FLASH_SR_MISERR_Pos)

#define	FLASH_SR_MISERR FLASH_SR_MISERR_Msk

#define	FLASH_SR_FASTERR_Pos (9U)

#define	FLASH_SR_FASTERR_Msk (0x1UL << FLASH_SR_FASTERR_Pos)

#define	FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk

#define	FLASH_SR_RDERR_Pos (14U)

#define	FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos)

#define	FLASH_SR_RDERR FLASH_SR_RDERR_Msk

#define	FLASH_SR_OPTVERR_Pos (15U)

#define	FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos)

#define	FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk

#define	FLASH_SR_BSY_Pos (16U)

#define	FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos)

#define	FLASH_SR_BSY FLASH_SR_BSY_Msk

#define	FLASH_CR_PG_Pos (0U)

#define	FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos)

#define	FLASH_CR_PG FLASH_CR_PG_Msk

#define	FLASH_CR_PER_Pos (1U)

#define	FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos)

#define	FLASH_CR_PER FLASH_CR_PER_Msk

#define	FLASH_CR_MER1_Pos (2U)

#define	FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos)

#define	FLASH_CR_MER1 FLASH_CR_MER1_Msk

#define	FLASH_CR_PNB_Pos (3U)

#define	FLASH_CR_PNB_Msk (0x3FUL << FLASH_CR_PNB_Pos)

#define	FLASH_CR_PNB FLASH_CR_PNB_Msk

#define	FLASH_CR_STRT_Pos (16U)

#define	FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos)

#define	FLASH_CR_STRT FLASH_CR_STRT_Msk

#define	FLASH_CR_OPTSTRT_Pos (17U)

#define	FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos)

#define	FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk

#define	FLASH_CR_FSTPG_Pos (18U)

#define	FLASH_CR_FSTPG_Msk (0x1UL << FLASH_CR_FSTPG_Pos)

#define	FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk

#define	FLASH_CR_EOPIE_Pos (24U)

#define	FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos)

#define	FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk

#define	FLASH_CR_ERRIE_Pos (25U)

#define	FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos)

#define	FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk

#define	FLASH_CR_RDERRIE_Pos (26U)

#define	FLASH_CR_RDERRIE_Msk (0x1UL << FLASH_CR_RDERRIE_Pos)

#define	FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk

#define	FLASH_CR_OBL_LAUNCH_Pos (27U)

#define	FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos)

#define	FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk

#define	FLASH_CR_SEC_PROT1_Pos (28U)

#define	FLASH_CR_SEC_PROT1_Msk (0x1UL << FLASH_CR_SEC_PROT1_Pos)

#define	FLASH_CR_SEC_PROT1 FLASH_CR_SEC_PROT1_Msk

#define	FLASH_CR_OPTLOCK_Pos (30U)

#define	FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos)

#define	FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk

#define	FLASH_CR_LOCK_Pos (31U)

#define	FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos)

#define	FLASH_CR_LOCK FLASH_CR_LOCK_Msk

#define	FLASH_ECCR_ADDR_ECC_Pos (0U)

#define	FLASH_ECCR_ADDR_ECC_Msk (0x3FFFFUL << FLASH_ECCR_ADDR_ECC_Pos)

#define	FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk

#define	FLASH_ECCR_SYSF_ECC_Pos (22U)

#define	FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos)

#define	FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk

#define	FLASH_ECCR_ECCIE_Pos (24U)

#define	FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos)

#define	FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk

#define	FLASH_ECCR_ECCC_Pos (30U)

#define	FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos)

#define	FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk

#define	FLASH_ECCR_ECCD_Pos (31U)

#define	FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos)

#define	FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk

#define	FLASH_OPTR_RDP_Pos (0U)

#define	FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos)

#define	FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk

#define	FLASH_OPTR_BOR_LEV_Pos (8U)

#define	FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos)

#define	FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk

#define	FLASH_OPTR_BOR_LEV_0 (0x0UL << FLASH_OPTR_BOR_LEV_Pos)

#define	FLASH_OPTR_BOR_LEV_1 (0x1UL << FLASH_OPTR_BOR_LEV_Pos)

#define	FLASH_OPTR_BOR_LEV_2 (0x2UL << FLASH_OPTR_BOR_LEV_Pos)

#define	FLASH_OPTR_BOR_LEV_3 (0x3UL << FLASH_OPTR_BOR_LEV_Pos)

#define	FLASH_OPTR_BOR_LEV_4 (0x4UL << FLASH_OPTR_BOR_LEV_Pos)

#define	FLASH_OPTR_nRST_STOP_Pos (12U)

#define	FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos)

#define	FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk

#define	FLASH_OPTR_nRST_STDBY_Pos (13U)

#define	FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos)

#define	FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk

#define	FLASH_OPTR_nRST_SHDW_Pos (14U)

#define	FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos)

#define	FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk

#define	FLASH_OPTR_IWDG_SW_Pos (16U)

#define	FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos)

#define	FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk

#define	FLASH_OPTR_IWDG_STOP_Pos (17U)

#define	FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos)

#define	FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk

#define	FLASH_OPTR_IWDG_STDBY_Pos (18U)

#define	FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos)

#define	FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk

#define	FLASH_OPTR_WWDG_SW_Pos (19U)

#define	FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos)

#define	FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk

#define	FLASH_OPTR_nBOOT1_Pos (23U)

#define	FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos)

#define	FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk

#define	FLASH_OPTR_SRAM_PE_Pos (24U)

#define	FLASH_OPTR_SRAM_PE_Msk (0x1UL << FLASH_OPTR_SRAM_PE_Pos)

#define	FLASH_OPTR_SRAM_PE FLASH_OPTR_SRAM_PE_Msk

#define	FLASH_OPTR_CCMSRAM_RST_Pos (25U)

#define	FLASH_OPTR_CCMSRAM_RST_Msk (0x1UL << FLASH_OPTR_CCMSRAM_RST_Pos)

#define	FLASH_OPTR_CCMSRAM_RST FLASH_OPTR_CCMSRAM_RST_Msk

#define	FLASH_OPTR_nSWBOOT0_Pos (26U)

#define	FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos)

#define	FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk

#define	FLASH_OPTR_nBOOT0_Pos (27U)

#define	FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos)

#define	FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk

#define	FLASH_OPTR_NRST_MODE_Pos (28U)

#define	FLASH_OPTR_NRST_MODE_Msk (0x3UL << FLASH_OPTR_NRST_MODE_Pos)

#define	FLASH_OPTR_NRST_MODE FLASH_OPTR_NRST_MODE_Msk

#define	FLASH_OPTR_NRST_MODE_0 (0x1UL << FLASH_OPTR_NRST_MODE_Pos)

#define	FLASH_OPTR_NRST_MODE_1 (0x2UL << FLASH_OPTR_NRST_MODE_Pos)

#define	FLASH_OPTR_IRHEN_Pos (30U)

#define	FLASH_OPTR_IRHEN_Msk (0x1UL << FLASH_OPTR_IRHEN_Pos)

#define	FLASH_OPTR_IRHEN FLASH_OPTR_IRHEN_Msk

#define	FLASH_PCROP1SR_PCROP1_STRT_Pos (0U)

#define	FLASH_PCROP1SR_PCROP1_STRT_Msk (0x3FFFUL << FLASH_PCROP1SR_PCROP1_STRT_Pos)

#define	FLASH_PCROP1SR_PCROP1_STRT FLASH_PCROP1SR_PCROP1_STRT_Msk

#define	FLASH_PCROP1ER_PCROP1_END_Pos (0U)

#define	FLASH_PCROP1ER_PCROP1_END_Msk (0x3FFFUL << FLASH_PCROP1ER_PCROP1_END_Pos)

#define	FLASH_PCROP1ER_PCROP1_END FLASH_PCROP1ER_PCROP1_END_Msk

#define	FLASH_PCROP1ER_PCROP_RDP_Pos (31U)

#define	FLASH_PCROP1ER_PCROP_RDP_Msk (0x1UL << FLASH_PCROP1ER_PCROP_RDP_Pos)

#define	FLASH_PCROP1ER_PCROP_RDP FLASH_PCROP1ER_PCROP_RDP_Msk

#define	FLASH_WRP1AR_WRP1A_STRT_Pos (0U)

#define	FLASH_WRP1AR_WRP1A_STRT_Msk (0x3FUL << FLASH_WRP1AR_WRP1A_STRT_Pos)

#define	FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk

#define	FLASH_WRP1AR_WRP1A_END_Pos (16U)

#define	FLASH_WRP1AR_WRP1A_END_Msk (0x3FUL << FLASH_WRP1AR_WRP1A_END_Pos)

#define	FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk

#define	FLASH_WRP1BR_WRP1B_STRT_Pos (0U)

#define	FLASH_WRP1BR_WRP1B_STRT_Msk (0x3FUL << FLASH_WRP1BR_WRP1B_STRT_Pos)

#define	FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk

#define	FLASH_WRP1BR_WRP1B_END_Pos (16U)

#define	FLASH_WRP1BR_WRP1B_END_Msk (0x3FUL << FLASH_WRP1BR_WRP1B_END_Pos)

#define	FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk

#define	FLASH_SEC1R_SEC_SIZE1_Pos (0U)

#define	FLASH_SEC1R_SEC_SIZE1_Msk (0x7FUL << FLASH_SEC1R_SEC_SIZE1_Pos)

#define	FLASH_SEC1R_SEC_SIZE1 FLASH_SEC1R_SEC_SIZE1_Msk

#define	FLASH_SEC1R_BOOT_LOCK_Pos (16U)

#define	FLASH_SEC1R_BOOT_LOCK_Msk (0x1UL << FLASH_SEC1R_BOOT_LOCK_Pos)

#define	FLASH_SEC1R_BOOT_LOCK FLASH_SEC1R_BOOT_LOCK_Msk

#define	FMAC_X1BUFCFG_X1_BASE_Pos (0U)

#define	FMAC_X1BUFCFG_X1_BASE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BASE_Pos)

#define	FMAC_X1BUFCFG_X1_BASE FMAC_X1BUFCFG_X1_BASE_Msk

#define	FMAC_X1BUFCFG_X1_BUF_SIZE_Pos (8U)

#define	FMAC_X1BUFCFG_X1_BUF_SIZE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos)

#define	FMAC_X1BUFCFG_X1_BUF_SIZE FMAC_X1BUFCFG_X1_BUF_SIZE_Msk

#define	FMAC_X1BUFCFG_FULL_WM_Pos (24U)

#define	FMAC_X1BUFCFG_FULL_WM_Msk (0x3UL << FMAC_X1BUFCFG_FULL_WM_Pos)

#define	FMAC_X1BUFCFG_FULL_WM FMAC_X1BUFCFG_FULL_WM_Msk

#define	FMAC_X2BUFCFG_X2_BASE_Pos (0U)

#define	FMAC_X2BUFCFG_X2_BASE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BASE_Pos)

#define	FMAC_X2BUFCFG_X2_BASE FMAC_X2BUFCFG_X2_BASE_Msk

#define	FMAC_X2BUFCFG_X2_BUF_SIZE_Pos (8U)

#define	FMAC_X2BUFCFG_X2_BUF_SIZE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos)

#define	FMAC_X2BUFCFG_X2_BUF_SIZE FMAC_X2BUFCFG_X2_BUF_SIZE_Msk

#define	FMAC_YBUFCFG_Y_BASE_Pos (0U)

#define	FMAC_YBUFCFG_Y_BASE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BASE_Pos)

#define	FMAC_YBUFCFG_Y_BASE FMAC_YBUFCFG_Y_BASE_Msk

#define	FMAC_YBUFCFG_Y_BUF_SIZE_Pos (8U)

#define	FMAC_YBUFCFG_Y_BUF_SIZE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BUF_SIZE_Pos)

#define	FMAC_YBUFCFG_Y_BUF_SIZE FMAC_YBUFCFG_Y_BUF_SIZE_Msk

#define	FMAC_YBUFCFG_EMPTY_WM_Pos (24U)

#define	FMAC_YBUFCFG_EMPTY_WM_Msk (0x3UL << FMAC_YBUFCFG_EMPTY_WM_Pos)

#define	FMAC_YBUFCFG_EMPTY_WM FMAC_YBUFCFG_EMPTY_WM_Msk

#define	FMAC_PARAM_P_Pos (0U)

#define	FMAC_PARAM_P_Msk (0xFFUL << FMAC_PARAM_P_Pos)

#define	FMAC_PARAM_P FMAC_PARAM_P_Msk

#define	FMAC_PARAM_Q_Pos (8U)

#define	FMAC_PARAM_Q_Msk (0xFFUL << FMAC_PARAM_Q_Pos)

#define	FMAC_PARAM_Q FMAC_PARAM_Q_Msk

#define	FMAC_PARAM_R_Pos (16U)

#define	FMAC_PARAM_R_Msk (0xFFUL << FMAC_PARAM_R_Pos)

#define	FMAC_PARAM_R FMAC_PARAM_R_Msk

#define	FMAC_PARAM_FUNC_Pos (24U)

#define	FMAC_PARAM_FUNC_Msk (0x7FUL << FMAC_PARAM_FUNC_Pos)

#define	FMAC_PARAM_FUNC FMAC_PARAM_FUNC_Msk

#define	FMAC_PARAM_FUNC_0 (0x1UL << FMAC_PARAM_FUNC_Pos)

#define	FMAC_PARAM_FUNC_1 (0x2UL << FMAC_PARAM_FUNC_Pos)

#define	FMAC_PARAM_FUNC_2 (0x4UL << FMAC_PARAM_FUNC_Pos)

#define	FMAC_PARAM_FUNC_3 (0x8UL << FMAC_PARAM_FUNC_Pos)

#define	FMAC_PARAM_FUNC_4 (0x10UL << FMAC_PARAM_FUNC_Pos)

#define	FMAC_PARAM_FUNC_5 (0x20UL << FMAC_PARAM_FUNC_Pos)

#define	FMAC_PARAM_FUNC_6 (0x40UL << FMAC_PARAM_FUNC_Pos)

#define	FMAC_PARAM_START_Pos (31U)

#define	FMAC_PARAM_START_Msk (0x1UL << FMAC_PARAM_START_Pos)

#define	FMAC_PARAM_START FMAC_PARAM_START_Msk

#define	FMAC_CR_RIEN_Pos (0U)

#define	FMAC_CR_RIEN_Msk (0x1UL << FMAC_CR_RIEN_Pos)

#define	FMAC_CR_RIEN FMAC_CR_RIEN_Msk

#define	FMAC_CR_WIEN_Pos (1U)

#define	FMAC_CR_WIEN_Msk (0x1UL << FMAC_CR_WIEN_Pos)

#define	FMAC_CR_WIEN FMAC_CR_WIEN_Msk

#define	FMAC_CR_OVFLIEN_Pos (2U)

#define	FMAC_CR_OVFLIEN_Msk (0x1UL << FMAC_CR_OVFLIEN_Pos)

#define	FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN_Msk

#define	FMAC_CR_UNFLIEN_Pos (3U)

#define	FMAC_CR_UNFLIEN_Msk (0x1UL << FMAC_CR_UNFLIEN_Pos)

#define	FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN_Msk

#define	FMAC_CR_SATIEN_Pos (4U)

#define	FMAC_CR_SATIEN_Msk (0x1UL << FMAC_CR_SATIEN_Pos)

#define	FMAC_CR_SATIEN FMAC_CR_SATIEN_Msk

#define	FMAC_CR_DMAREN_Pos (8U)

#define	FMAC_CR_DMAREN_Msk (0x1UL << FMAC_CR_DMAREN_Pos)

#define	FMAC_CR_DMAREN FMAC_CR_DMAREN_Msk

#define	FMAC_CR_DMAWEN_Pos (9U)

#define	FMAC_CR_DMAWEN_Msk (0x1UL << FMAC_CR_DMAWEN_Pos)

#define	FMAC_CR_DMAWEN FMAC_CR_DMAWEN_Msk

#define	FMAC_CR_CLIPEN_Pos (15U)

#define	FMAC_CR_CLIPEN_Msk (0x1UL << FMAC_CR_CLIPEN_Pos)

#define	FMAC_CR_CLIPEN FMAC_CR_CLIPEN_Msk

#define	FMAC_CR_RESET_Pos (16U)

#define	FMAC_CR_RESET_Msk (0x1UL << FMAC_CR_RESET_Pos)

#define	FMAC_CR_RESET FMAC_CR_RESET_Msk

#define	FMAC_SR_YEMPTY_Pos (0U)

#define	FMAC_SR_YEMPTY_Msk (0x1UL << FMAC_SR_YEMPTY_Pos)

#define	FMAC_SR_YEMPTY FMAC_SR_YEMPTY_Msk

#define	FMAC_SR_X1FULL_Pos (1U)

#define	FMAC_SR_X1FULL_Msk (0x1UL << FMAC_SR_X1FULL_Pos)

#define	FMAC_SR_X1FULL FMAC_SR_X1FULL_Msk

#define	FMAC_SR_OVFL_Pos (8U)

#define	FMAC_SR_OVFL_Msk (0x1UL << FMAC_SR_OVFL_Pos)

#define	FMAC_SR_OVFL FMAC_SR_OVFL_Msk

#define	FMAC_SR_UNFL_Pos (9U)

#define	FMAC_SR_UNFL_Msk (0x1UL << FMAC_SR_UNFL_Pos)

#define	FMAC_SR_UNFL FMAC_SR_UNFL_Msk

#define	FMAC_SR_SAT_Pos (10U)

#define	FMAC_SR_SAT_Msk (0x1UL << FMAC_SR_SAT_Pos)

#define	FMAC_SR_SAT FMAC_SR_SAT_Msk

#define	FMAC_WDATA_WDATA_Pos (0U)

#define	FMAC_WDATA_WDATA_Msk (0xFFFFUL << FMAC_WDATA_WDATA_Pos)

#define	FMAC_WDATA_WDATA FMAC_WDATA_WDATA_Msk

#define	FMAC_RDATA_RDATA_Pos (0U)

#define	FMAC_RDATA_RDATA_Msk (0xFFFFUL << FMAC_RDATA_RDATA_Pos)

#define	FMAC_RDATA_RDATA FMAC_RDATA_RDATA_Msk

#define	GPIO_MODER_MODE0_Pos (0U)

#define	GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos)

#define	GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk

#define	GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos)

#define	GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos)

#define	GPIO_MODER_MODE1_Pos (2U)

#define	GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos)

#define	GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk

#define	GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos)

#define	GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos)

#define	GPIO_MODER_MODE2_Pos (4U)

#define	GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos)

#define	GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk

#define	GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos)

#define	GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos)

#define	GPIO_MODER_MODE3_Pos (6U)

#define	GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos)

#define	GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk

#define	GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos)

#define	GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos)

#define	GPIO_MODER_MODE4_Pos (8U)

#define	GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos)

#define	GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk

#define	GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos)

#define	GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos)

#define	GPIO_MODER_MODE5_Pos (10U)

#define	GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos)

#define	GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk

#define	GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos)

#define	GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos)

#define	GPIO_MODER_MODE6_Pos (12U)

#define	GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos)

#define	GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk

#define	GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos)

#define	GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos)

#define	GPIO_MODER_MODE7_Pos (14U)

#define	GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos)

#define	GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk

#define	GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos)

#define	GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos)

#define	GPIO_MODER_MODE8_Pos (16U)

#define	GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos)

#define	GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk

#define	GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos)

#define	GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos)

#define	GPIO_MODER_MODE9_Pos (18U)

#define	GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos)

#define	GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk

#define	GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos)

#define	GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos)

#define	GPIO_MODER_MODE10_Pos (20U)

#define	GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos)

#define	GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk

#define	GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos)

#define	GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos)

#define	GPIO_MODER_MODE11_Pos (22U)

#define	GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos)

#define	GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk

#define	GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos)

#define	GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos)

#define	GPIO_MODER_MODE12_Pos (24U)

#define	GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos)

#define	GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk

#define	GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos)

#define	GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos)

#define	GPIO_MODER_MODE13_Pos (26U)

#define	GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos)

#define	GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk

#define	GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos)

#define	GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos)

#define	GPIO_MODER_MODE14_Pos (28U)

#define	GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos)

#define	GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk

#define	GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos)

#define	GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos)

#define	GPIO_MODER_MODE15_Pos (30U)

#define	GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos)

#define	GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk

#define	GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos)

#define	GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos)

#define	GPIO_MODER_MODER0 GPIO_MODER_MODE0

#define	GPIO_MODER_MODER0_0 GPIO_MODER_MODE0_0

#define	GPIO_MODER_MODER0_1 GPIO_MODER_MODE0_1

#define	GPIO_MODER_MODER1 GPIO_MODER_MODE1

#define	GPIO_MODER_MODER1_0 GPIO_MODER_MODE1_0

#define	GPIO_MODER_MODER1_1 GPIO_MODER_MODE1_1

#define	GPIO_MODER_MODER2 GPIO_MODER_MODE2

#define	GPIO_MODER_MODER2_0 GPIO_MODER_MODE2_0

#define	GPIO_MODER_MODER2_1 GPIO_MODER_MODE2_1

#define	GPIO_MODER_MODER3 GPIO_MODER_MODE3

#define	GPIO_MODER_MODER3_0 GPIO_MODER_MODE3_0

#define	GPIO_MODER_MODER3_1 GPIO_MODER_MODE3_1

#define	GPIO_MODER_MODER4 GPIO_MODER_MODE4

#define	GPIO_MODER_MODER4_0 GPIO_MODER_MODE4_0

#define	GPIO_MODER_MODER4_1 GPIO_MODER_MODE4_1

#define	GPIO_MODER_MODER5 GPIO_MODER_MODE5

#define	GPIO_MODER_MODER5_0 GPIO_MODER_MODE5_0

#define	GPIO_MODER_MODER5_1 GPIO_MODER_MODE5_1

#define	GPIO_MODER_MODER6 GPIO_MODER_MODE6

#define	GPIO_MODER_MODER6_0 GPIO_MODER_MODE6_0

#define	GPIO_MODER_MODER6_1 GPIO_MODER_MODE6_1

#define	GPIO_MODER_MODER7 GPIO_MODER_MODE7

#define	GPIO_MODER_MODER7_0 GPIO_MODER_MODE7_0

#define	GPIO_MODER_MODER7_1 GPIO_MODER_MODE7_1

#define	GPIO_MODER_MODER8 GPIO_MODER_MODE8

#define	GPIO_MODER_MODER8_0 GPIO_MODER_MODE8_0

#define	GPIO_MODER_MODER8_1 GPIO_MODER_MODE8_1

#define	GPIO_MODER_MODER9 GPIO_MODER_MODE9

#define	GPIO_MODER_MODER9_0 GPIO_MODER_MODE9_0

#define	GPIO_MODER_MODER9_1 GPIO_MODER_MODE9_1

#define	GPIO_MODER_MODER10 GPIO_MODER_MODE10

#define	GPIO_MODER_MODER10_0 GPIO_MODER_MODE10_0

#define	GPIO_MODER_MODER10_1 GPIO_MODER_MODE10_1

#define	GPIO_MODER_MODER11 GPIO_MODER_MODE11

#define	GPIO_MODER_MODER11_0 GPIO_MODER_MODE11_0

#define	GPIO_MODER_MODER11_1 GPIO_MODER_MODE11_1

#define	GPIO_MODER_MODER12 GPIO_MODER_MODE12

#define	GPIO_MODER_MODER12_0 GPIO_MODER_MODE12_0

#define	GPIO_MODER_MODER12_1 GPIO_MODER_MODE12_1

#define	GPIO_MODER_MODER13 GPIO_MODER_MODE13

#define	GPIO_MODER_MODER13_0 GPIO_MODER_MODE13_0

#define	GPIO_MODER_MODER13_1 GPIO_MODER_MODE13_1

#define	GPIO_MODER_MODER14 GPIO_MODER_MODE14

#define	GPIO_MODER_MODER14_0 GPIO_MODER_MODE14_0

#define	GPIO_MODER_MODER14_1 GPIO_MODER_MODE14_1

#define	GPIO_MODER_MODER15 GPIO_MODER_MODE15

#define	GPIO_MODER_MODER15_0 GPIO_MODER_MODE15_0

#define	GPIO_MODER_MODER15_1 GPIO_MODER_MODE15_1

#define	GPIO_OTYPER_OT0_Pos (0U)

#define	GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos)

#define	GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk

#define	GPIO_OTYPER_OT1_Pos (1U)

#define	GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos)

#define	GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk

#define	GPIO_OTYPER_OT2_Pos (2U)

#define	GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos)

#define	GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk

#define	GPIO_OTYPER_OT3_Pos (3U)

#define	GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos)

#define	GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk

#define	GPIO_OTYPER_OT4_Pos (4U)

#define	GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos)

#define	GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk

#define	GPIO_OTYPER_OT5_Pos (5U)

#define	GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos)

#define	GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk

#define	GPIO_OTYPER_OT6_Pos (6U)

#define	GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos)

#define	GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk

#define	GPIO_OTYPER_OT7_Pos (7U)

#define	GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos)

#define	GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk

#define	GPIO_OTYPER_OT8_Pos (8U)

#define	GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos)

#define	GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk

#define	GPIO_OTYPER_OT9_Pos (9U)

#define	GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos)

#define	GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk

#define	GPIO_OTYPER_OT10_Pos (10U)

#define	GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos)

#define	GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk

#define	GPIO_OTYPER_OT11_Pos (11U)

#define	GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos)

#define	GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk

#define	GPIO_OTYPER_OT12_Pos (12U)

#define	GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos)

#define	GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk

#define	GPIO_OTYPER_OT13_Pos (13U)

#define	GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos)

#define	GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk

#define	GPIO_OTYPER_OT14_Pos (14U)

#define	GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos)

#define	GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk

#define	GPIO_OTYPER_OT15_Pos (15U)

#define	GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos)

#define	GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk

#define	GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0

#define	GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1

#define	GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2

#define	GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3

#define	GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4

#define	GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5

#define	GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6

#define	GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7

#define	GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8

#define	GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9

#define	GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10

#define	GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11

#define	GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12

#define	GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13

#define	GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14

#define	GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15

#define	GPIO_OSPEEDR_OSPEED0_Pos (0U)

#define	GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)

#define	GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk

#define	GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)

#define	GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)

#define	GPIO_OSPEEDR_OSPEED1_Pos (2U)

#define	GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)

#define	GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk

#define	GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)

#define	GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)

#define	GPIO_OSPEEDR_OSPEED2_Pos (4U)

#define	GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)

#define	GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk

#define	GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)

#define	GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)

#define	GPIO_OSPEEDR_OSPEED3_Pos (6U)

#define	GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)

#define	GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk

#define	GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)

#define	GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)

#define	GPIO_OSPEEDR_OSPEED4_Pos (8U)

#define	GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)

#define	GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk

#define	GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)

#define	GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)

#define	GPIO_OSPEEDR_OSPEED5_Pos (10U)

#define	GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)

#define	GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk

#define	GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)

#define	GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)

#define	GPIO_OSPEEDR_OSPEED6_Pos (12U)

#define	GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)

#define	GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk

#define	GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)

#define	GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)

#define	GPIO_OSPEEDR_OSPEED7_Pos (14U)

#define	GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)

#define	GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk

#define	GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)

#define	GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)

#define	GPIO_OSPEEDR_OSPEED8_Pos (16U)

#define	GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)

#define	GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk

#define	GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)

#define	GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)

#define	GPIO_OSPEEDR_OSPEED9_Pos (18U)

#define	GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)

#define	GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk

#define	GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)

#define	GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)

#define	GPIO_OSPEEDR_OSPEED10_Pos (20U)

#define	GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)

#define	GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk

#define	GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)

#define	GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)

#define	GPIO_OSPEEDR_OSPEED11_Pos (22U)

#define	GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)

#define	GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk

#define	GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)

#define	GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)

#define	GPIO_OSPEEDR_OSPEED12_Pos (24U)

#define	GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)

#define	GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk

#define	GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)

#define	GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)

#define	GPIO_OSPEEDR_OSPEED13_Pos (26U)

#define	GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)

#define	GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk

#define	GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)

#define	GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)

#define	GPIO_OSPEEDR_OSPEED14_Pos (28U)

#define	GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)

#define	GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk

#define	GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)

#define	GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)

#define	GPIO_OSPEEDR_OSPEED15_Pos (30U)

#define	GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)

#define	GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk

#define	GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)

#define	GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)

#define	GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0

#define	GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0

#define	GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1

#define	GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1

#define	GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0

#define	GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1

#define	GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2

#define	GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0

#define	GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1

#define	GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3

#define	GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0

#define	GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1

#define	GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4

#define	GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0

#define	GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1

#define	GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5

#define	GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0

#define	GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1

#define	GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6

#define	GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0

#define	GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1

#define	GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7

#define	GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0

#define	GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1

#define	GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8

#define	GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0

#define	GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1

#define	GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9

#define	GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0

#define	GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1

#define	GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10

#define	GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0

#define	GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1

#define	GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11

#define	GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0

#define	GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1

#define	GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12

#define	GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0

#define	GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1

#define	GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13

#define	GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0

#define	GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1

#define	GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14

#define	GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0

#define	GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1

#define	GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15

#define	GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0

#define	GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1

#define	GPIO_PUPDR_PUPD0_Pos (0U)

#define	GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos)

#define	GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk

#define	GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos)

#define	GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos)

#define	GPIO_PUPDR_PUPD1_Pos (2U)

#define	GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos)

#define	GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk

#define	GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos)

#define	GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos)

#define	GPIO_PUPDR_PUPD2_Pos (4U)

#define	GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos)

#define	GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk

#define	GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos)

#define	GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos)

#define	GPIO_PUPDR_PUPD3_Pos (6U)

#define	GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos)

#define	GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk

#define	GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos)

#define	GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos)

#define	GPIO_PUPDR_PUPD4_Pos (8U)

#define	GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos)

#define	GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk

#define	GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos)

#define	GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos)

#define	GPIO_PUPDR_PUPD5_Pos (10U)

#define	GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos)

#define	GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk

#define	GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos)

#define	GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos)

#define	GPIO_PUPDR_PUPD6_Pos (12U)

#define	GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos)

#define	GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk

#define	GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos)

#define	GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos)

#define	GPIO_PUPDR_PUPD7_Pos (14U)

#define	GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos)

#define	GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk

#define	GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos)

#define	GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos)

#define	GPIO_PUPDR_PUPD8_Pos (16U)

#define	GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos)

#define	GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk

#define	GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos)

#define	GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos)

#define	GPIO_PUPDR_PUPD9_Pos (18U)

#define	GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos)

#define	GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk

#define	GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos)

#define	GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos)

#define	GPIO_PUPDR_PUPD10_Pos (20U)

#define	GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos)

#define	GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk

#define	GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos)

#define	GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos)

#define	GPIO_PUPDR_PUPD11_Pos (22U)

#define	GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos)

#define	GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk

#define	GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos)

#define	GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos)

#define	GPIO_PUPDR_PUPD12_Pos (24U)

#define	GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos)

#define	GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk

#define	GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos)

#define	GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos)

#define	GPIO_PUPDR_PUPD13_Pos (26U)

#define	GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos)

#define	GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk

#define	GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos)

#define	GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos)

#define	GPIO_PUPDR_PUPD14_Pos (28U)

#define	GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos)

#define	GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk

#define	GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos)

#define	GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos)

#define	GPIO_PUPDR_PUPD15_Pos (30U)

#define	GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos)

#define	GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk

#define	GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos)

#define	GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos)

#define	GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0

#define	GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0

#define	GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1

#define	GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1

#define	GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0

#define	GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1

#define	GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2

#define	GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0

#define	GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1

#define	GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3

#define	GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0

#define	GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1

#define	GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4

#define	GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0

#define	GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1

#define	GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5

#define	GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0

#define	GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1

#define	GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6

#define	GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0

#define	GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1

#define	GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7

#define	GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0

#define	GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1

#define	GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8

#define	GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0

#define	GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1

#define	GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9

#define	GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0

#define	GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1

#define	GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10

#define	GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0

#define	GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1

#define	GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11

#define	GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0

#define	GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1

#define	GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12

#define	GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0

#define	GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1

#define	GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13

#define	GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0

#define	GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1

#define	GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14

#define	GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0

#define	GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1

#define	GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15

#define	GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0

#define	GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1

#define	GPIO_IDR_ID0_Pos (0U)

#define	GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos)

#define	GPIO_IDR_ID0 GPIO_IDR_ID0_Msk

#define	GPIO_IDR_ID1_Pos (1U)

#define	GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos)

#define	GPIO_IDR_ID1 GPIO_IDR_ID1_Msk

#define	GPIO_IDR_ID2_Pos (2U)

#define	GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos)

#define	GPIO_IDR_ID2 GPIO_IDR_ID2_Msk

#define	GPIO_IDR_ID3_Pos (3U)

#define	GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos)

#define	GPIO_IDR_ID3 GPIO_IDR_ID3_Msk

#define	GPIO_IDR_ID4_Pos (4U)

#define	GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos)

#define	GPIO_IDR_ID4 GPIO_IDR_ID4_Msk

#define	GPIO_IDR_ID5_Pos (5U)

#define	GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos)

#define	GPIO_IDR_ID5 GPIO_IDR_ID5_Msk

#define	GPIO_IDR_ID6_Pos (6U)

#define	GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos)

#define	GPIO_IDR_ID6 GPIO_IDR_ID6_Msk

#define	GPIO_IDR_ID7_Pos (7U)

#define	GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos)

#define	GPIO_IDR_ID7 GPIO_IDR_ID7_Msk

#define	GPIO_IDR_ID8_Pos (8U)

#define	GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos)

#define	GPIO_IDR_ID8 GPIO_IDR_ID8_Msk

#define	GPIO_IDR_ID9_Pos (9U)

#define	GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos)

#define	GPIO_IDR_ID9 GPIO_IDR_ID9_Msk

#define	GPIO_IDR_ID10_Pos (10U)

#define	GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos)

#define	GPIO_IDR_ID10 GPIO_IDR_ID10_Msk

#define	GPIO_IDR_ID11_Pos (11U)

#define	GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos)

#define	GPIO_IDR_ID11 GPIO_IDR_ID11_Msk

#define	GPIO_IDR_ID12_Pos (12U)

#define	GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos)

#define	GPIO_IDR_ID12 GPIO_IDR_ID12_Msk

#define	GPIO_IDR_ID13_Pos (13U)

#define	GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos)

#define	GPIO_IDR_ID13 GPIO_IDR_ID13_Msk

#define	GPIO_IDR_ID14_Pos (14U)

#define	GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos)

#define	GPIO_IDR_ID14 GPIO_IDR_ID14_Msk

#define	GPIO_IDR_ID15_Pos (15U)

#define	GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos)

#define	GPIO_IDR_ID15 GPIO_IDR_ID15_Msk

#define	GPIO_IDR_IDR_0 GPIO_IDR_ID0

#define	GPIO_IDR_IDR_1 GPIO_IDR_ID1

#define	GPIO_IDR_IDR_2 GPIO_IDR_ID2

#define	GPIO_IDR_IDR_3 GPIO_IDR_ID3

#define	GPIO_IDR_IDR_4 GPIO_IDR_ID4

#define	GPIO_IDR_IDR_5 GPIO_IDR_ID5

#define	GPIO_IDR_IDR_6 GPIO_IDR_ID6

#define	GPIO_IDR_IDR_7 GPIO_IDR_ID7

#define	GPIO_IDR_IDR_8 GPIO_IDR_ID8

#define	GPIO_IDR_IDR_9 GPIO_IDR_ID9

#define	GPIO_IDR_IDR_10 GPIO_IDR_ID10

#define	GPIO_IDR_IDR_11 GPIO_IDR_ID11

#define	GPIO_IDR_IDR_12 GPIO_IDR_ID12

#define	GPIO_IDR_IDR_13 GPIO_IDR_ID13

#define	GPIO_IDR_IDR_14 GPIO_IDR_ID14

#define	GPIO_IDR_IDR_15 GPIO_IDR_ID15

#define	GPIO_OTYPER_IDR_0 GPIO_IDR_ID0

#define	GPIO_OTYPER_IDR_1 GPIO_IDR_ID1

#define	GPIO_OTYPER_IDR_2 GPIO_IDR_ID2

#define	GPIO_OTYPER_IDR_3 GPIO_IDR_ID3

#define	GPIO_OTYPER_IDR_4 GPIO_IDR_ID4

#define	GPIO_OTYPER_IDR_5 GPIO_IDR_ID5

#define	GPIO_OTYPER_IDR_6 GPIO_IDR_ID6

#define	GPIO_OTYPER_IDR_7 GPIO_IDR_ID7

#define	GPIO_OTYPER_IDR_8 GPIO_IDR_ID8

#define	GPIO_OTYPER_IDR_9 GPIO_IDR_ID9

#define	GPIO_OTYPER_IDR_10 GPIO_IDR_ID10

#define	GPIO_OTYPER_IDR_11 GPIO_IDR_ID11

#define	GPIO_OTYPER_IDR_12 GPIO_IDR_ID12

#define	GPIO_OTYPER_IDR_13 GPIO_IDR_ID13

#define	GPIO_OTYPER_IDR_14 GPIO_IDR_ID14

#define	GPIO_OTYPER_IDR_15 GPIO_IDR_ID15

#define	GPIO_ODR_OD0_Pos (0U)

#define	GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos)

#define	GPIO_ODR_OD0 GPIO_ODR_OD0_Msk

#define	GPIO_ODR_OD1_Pos (1U)

#define	GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos)

#define	GPIO_ODR_OD1 GPIO_ODR_OD1_Msk

#define	GPIO_ODR_OD2_Pos (2U)

#define	GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos)

#define	GPIO_ODR_OD2 GPIO_ODR_OD2_Msk

#define	GPIO_ODR_OD3_Pos (3U)

#define	GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos)

#define	GPIO_ODR_OD3 GPIO_ODR_OD3_Msk

#define	GPIO_ODR_OD4_Pos (4U)

#define	GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos)

#define	GPIO_ODR_OD4 GPIO_ODR_OD4_Msk

#define	GPIO_ODR_OD5_Pos (5U)

#define	GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos)

#define	GPIO_ODR_OD5 GPIO_ODR_OD5_Msk

#define	GPIO_ODR_OD6_Pos (6U)

#define	GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos)

#define	GPIO_ODR_OD6 GPIO_ODR_OD6_Msk

#define	GPIO_ODR_OD7_Pos (7U)

#define	GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos)

#define	GPIO_ODR_OD7 GPIO_ODR_OD7_Msk

#define	GPIO_ODR_OD8_Pos (8U)

#define	GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos)

#define	GPIO_ODR_OD8 GPIO_ODR_OD8_Msk

#define	GPIO_ODR_OD9_Pos (9U)

#define	GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos)

#define	GPIO_ODR_OD9 GPIO_ODR_OD9_Msk

#define	GPIO_ODR_OD10_Pos (10U)

#define	GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos)

#define	GPIO_ODR_OD10 GPIO_ODR_OD10_Msk

#define	GPIO_ODR_OD11_Pos (11U)

#define	GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos)

#define	GPIO_ODR_OD11 GPIO_ODR_OD11_Msk

#define	GPIO_ODR_OD12_Pos (12U)

#define	GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos)

#define	GPIO_ODR_OD12 GPIO_ODR_OD12_Msk

#define	GPIO_ODR_OD13_Pos (13U)

#define	GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos)

#define	GPIO_ODR_OD13 GPIO_ODR_OD13_Msk

#define	GPIO_ODR_OD14_Pos (14U)

#define	GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos)

#define	GPIO_ODR_OD14 GPIO_ODR_OD14_Msk

#define	GPIO_ODR_OD15_Pos (15U)

#define	GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos)

#define	GPIO_ODR_OD15 GPIO_ODR_OD15_Msk

#define	GPIO_ODR_ODR_0 GPIO_ODR_OD0

#define	GPIO_ODR_ODR_1 GPIO_ODR_OD1

#define	GPIO_ODR_ODR_2 GPIO_ODR_OD2

#define	GPIO_ODR_ODR_3 GPIO_ODR_OD3

#define	GPIO_ODR_ODR_4 GPIO_ODR_OD4

#define	GPIO_ODR_ODR_5 GPIO_ODR_OD5

#define	GPIO_ODR_ODR_6 GPIO_ODR_OD6

#define	GPIO_ODR_ODR_7 GPIO_ODR_OD7

#define	GPIO_ODR_ODR_8 GPIO_ODR_OD8

#define	GPIO_ODR_ODR_9 GPIO_ODR_OD9

#define	GPIO_ODR_ODR_10 GPIO_ODR_OD10

#define	GPIO_ODR_ODR_11 GPIO_ODR_OD11

#define	GPIO_ODR_ODR_12 GPIO_ODR_OD12

#define	GPIO_ODR_ODR_13 GPIO_ODR_OD13

#define	GPIO_ODR_ODR_14 GPIO_ODR_OD14

#define	GPIO_ODR_ODR_15 GPIO_ODR_OD15

#define	GPIO_OTYPER_ODR_0 GPIO_ODR_OD0

#define	GPIO_OTYPER_ODR_1 GPIO_ODR_OD1

#define	GPIO_OTYPER_ODR_2 GPIO_ODR_OD2

#define	GPIO_OTYPER_ODR_3 GPIO_ODR_OD3

#define	GPIO_OTYPER_ODR_4 GPIO_ODR_OD4

#define	GPIO_OTYPER_ODR_5 GPIO_ODR_OD5

#define	GPIO_OTYPER_ODR_6 GPIO_ODR_OD6

#define	GPIO_OTYPER_ODR_7 GPIO_ODR_OD7

#define	GPIO_OTYPER_ODR_8 GPIO_ODR_OD8

#define	GPIO_OTYPER_ODR_9 GPIO_ODR_OD9

#define	GPIO_OTYPER_ODR_10 GPIO_ODR_OD10

#define	GPIO_OTYPER_ODR_11 GPIO_ODR_OD11

#define	GPIO_OTYPER_ODR_12 GPIO_ODR_OD12

#define	GPIO_OTYPER_ODR_13 GPIO_ODR_OD13

#define	GPIO_OTYPER_ODR_14 GPIO_ODR_OD14

#define	GPIO_OTYPER_ODR_15 GPIO_ODR_OD15

#define	GPIO_BSRR_BS0_Pos (0U)

#define	GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos)

#define	GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk

#define	GPIO_BSRR_BS1_Pos (1U)

#define	GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos)

#define	GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk

#define	GPIO_BSRR_BS2_Pos (2U)

#define	GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos)

#define	GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk

#define	GPIO_BSRR_BS3_Pos (3U)

#define	GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos)

#define	GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk

#define	GPIO_BSRR_BS4_Pos (4U)

#define	GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos)

#define	GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk

#define	GPIO_BSRR_BS5_Pos (5U)

#define	GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos)

#define	GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk

#define	GPIO_BSRR_BS6_Pos (6U)

#define	GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos)

#define	GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk

#define	GPIO_BSRR_BS7_Pos (7U)

#define	GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos)

#define	GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk

#define	GPIO_BSRR_BS8_Pos (8U)

#define	GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos)

#define	GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk

#define	GPIO_BSRR_BS9_Pos (9U)

#define	GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos)

#define	GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk

#define	GPIO_BSRR_BS10_Pos (10U)

#define	GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos)

#define	GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk

#define	GPIO_BSRR_BS11_Pos (11U)

#define	GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos)

#define	GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk

#define	GPIO_BSRR_BS12_Pos (12U)

#define	GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos)

#define	GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk

#define	GPIO_BSRR_BS13_Pos (13U)

#define	GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos)

#define	GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk

#define	GPIO_BSRR_BS14_Pos (14U)

#define	GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos)

#define	GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk

#define	GPIO_BSRR_BS15_Pos (15U)

#define	GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos)

#define	GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk

#define	GPIO_BSRR_BR0_Pos (16U)

#define	GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos)

#define	GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk

#define	GPIO_BSRR_BR1_Pos (17U)

#define	GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos)

#define	GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk

#define	GPIO_BSRR_BR2_Pos (18U)

#define	GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos)

#define	GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk

#define	GPIO_BSRR_BR3_Pos (19U)

#define	GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos)

#define	GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk

#define	GPIO_BSRR_BR4_Pos (20U)

#define	GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos)

#define	GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk

#define	GPIO_BSRR_BR5_Pos (21U)

#define	GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos)

#define	GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk

#define	GPIO_BSRR_BR6_Pos (22U)

#define	GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos)

#define	GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk

#define	GPIO_BSRR_BR7_Pos (23U)

#define	GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos)

#define	GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk

#define	GPIO_BSRR_BR8_Pos (24U)

#define	GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos)

#define	GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk

#define	GPIO_BSRR_BR9_Pos (25U)

#define	GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos)

#define	GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk

#define	GPIO_BSRR_BR10_Pos (26U)

#define	GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos)

#define	GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk

#define	GPIO_BSRR_BR11_Pos (27U)

#define	GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos)

#define	GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk

#define	GPIO_BSRR_BR12_Pos (28U)

#define	GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos)

#define	GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk

#define	GPIO_BSRR_BR13_Pos (29U)

#define	GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos)

#define	GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk

#define	GPIO_BSRR_BR14_Pos (30U)

#define	GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos)

#define	GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk

#define	GPIO_BSRR_BR15_Pos (31U)

#define	GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos)

#define	GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk

#define	GPIO_BSRR_BS_0 GPIO_BSRR_BS0

#define	GPIO_BSRR_BS_1 GPIO_BSRR_BS1

#define	GPIO_BSRR_BS_2 GPIO_BSRR_BS2

#define	GPIO_BSRR_BS_3 GPIO_BSRR_BS3

#define	GPIO_BSRR_BS_4 GPIO_BSRR_BS4

#define	GPIO_BSRR_BS_5 GPIO_BSRR_BS5

#define	GPIO_BSRR_BS_6 GPIO_BSRR_BS6

#define	GPIO_BSRR_BS_7 GPIO_BSRR_BS7

#define	GPIO_BSRR_BS_8 GPIO_BSRR_BS8

#define	GPIO_BSRR_BS_9 GPIO_BSRR_BS9

#define	GPIO_BSRR_BS_10 GPIO_BSRR_BS10

#define	GPIO_BSRR_BS_11 GPIO_BSRR_BS11

#define	GPIO_BSRR_BS_12 GPIO_BSRR_BS12

#define	GPIO_BSRR_BS_13 GPIO_BSRR_BS13

#define	GPIO_BSRR_BS_14 GPIO_BSRR_BS14

#define	GPIO_BSRR_BS_15 GPIO_BSRR_BS15

#define	GPIO_BSRR_BR_0 GPIO_BSRR_BR0

#define	GPIO_BSRR_BR_1 GPIO_BSRR_BR1

#define	GPIO_BSRR_BR_2 GPIO_BSRR_BR2

#define	GPIO_BSRR_BR_3 GPIO_BSRR_BR3

#define	GPIO_BSRR_BR_4 GPIO_BSRR_BR4

#define	GPIO_BSRR_BR_5 GPIO_BSRR_BR5

#define	GPIO_BSRR_BR_6 GPIO_BSRR_BR6

#define	GPIO_BSRR_BR_7 GPIO_BSRR_BR7

#define	GPIO_BSRR_BR_8 GPIO_BSRR_BR8

#define	GPIO_BSRR_BR_9 GPIO_BSRR_BR9

#define	GPIO_BSRR_BR_10 GPIO_BSRR_BR10

#define	GPIO_BSRR_BR_11 GPIO_BSRR_BR11

#define	GPIO_BSRR_BR_12 GPIO_BSRR_BR12

#define	GPIO_BSRR_BR_13 GPIO_BSRR_BR13

#define	GPIO_BSRR_BR_14 GPIO_BSRR_BR14

#define	GPIO_BSRR_BR_15 GPIO_BSRR_BR15

#define	GPIO_LCKR_LCK0_Pos (0U)

#define	GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos)

#define	GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk

#define	GPIO_LCKR_LCK1_Pos (1U)

#define	GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos)

#define	GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk

#define	GPIO_LCKR_LCK2_Pos (2U)

#define	GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos)

#define	GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk

#define	GPIO_LCKR_LCK3_Pos (3U)

#define	GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos)

#define	GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk

#define	GPIO_LCKR_LCK4_Pos (4U)

#define	GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos)

#define	GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk

#define	GPIO_LCKR_LCK5_Pos (5U)

#define	GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos)

#define	GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk

#define	GPIO_LCKR_LCK6_Pos (6U)

#define	GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos)

#define	GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk

#define	GPIO_LCKR_LCK7_Pos (7U)

#define	GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos)

#define	GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk

#define	GPIO_LCKR_LCK8_Pos (8U)

#define	GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos)

#define	GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk

#define	GPIO_LCKR_LCK9_Pos (9U)

#define	GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos)

#define	GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk

#define	GPIO_LCKR_LCK10_Pos (10U)

#define	GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos)

#define	GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk

#define	GPIO_LCKR_LCK11_Pos (11U)

#define	GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos)

#define	GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk

#define	GPIO_LCKR_LCK12_Pos (12U)

#define	GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos)

#define	GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk

#define	GPIO_LCKR_LCK13_Pos (13U)

#define	GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos)

#define	GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk

#define	GPIO_LCKR_LCK14_Pos (14U)

#define	GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos)

#define	GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk

#define	GPIO_LCKR_LCK15_Pos (15U)

#define	GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos)

#define	GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk

#define	GPIO_LCKR_LCKK_Pos (16U)

#define	GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos)

#define	GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk

#define	GPIO_AFRL_AFSEL0_Pos (0U)

#define	GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos)

#define	GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk

#define	GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos)

#define	GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos)

#define	GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos)

#define	GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos)

#define	GPIO_AFRL_AFSEL1_Pos (4U)

#define	GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos)

#define	GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk

#define	GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos)

#define	GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos)

#define	GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos)

#define	GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos)

#define	GPIO_AFRL_AFSEL2_Pos (8U)

#define	GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos)

#define	GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk

#define	GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos)

#define	GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos)

#define	GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos)

#define	GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos)

#define	GPIO_AFRL_AFSEL3_Pos (12U)

#define	GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos)

#define	GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk

#define	GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos)

#define	GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos)

#define	GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos)

#define	GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos)

#define	GPIO_AFRL_AFSEL4_Pos (16U)

#define	GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos)

#define	GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk

#define	GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos)

#define	GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos)

#define	GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos)

#define	GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos)

#define	GPIO_AFRL_AFSEL5_Pos (20U)

#define	GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos)

#define	GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk

#define	GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos)

#define	GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos)

#define	GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos)

#define	GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos)

#define	GPIO_AFRL_AFSEL6_Pos (24U)

#define	GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos)

#define	GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk

#define	GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos)

#define	GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos)

#define	GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos)

#define	GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos)

#define	GPIO_AFRL_AFSEL7_Pos (28U)

#define	GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos)

#define	GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk

#define	GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos)

#define	GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos)

#define	GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos)

#define	GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos)

#define	GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0

#define	GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1

#define	GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2

#define	GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3

#define	GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4

#define	GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5

#define	GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6

#define	GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7

#define	GPIO_AFRH_AFSEL8_Pos (0U)

#define	GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos)

#define	GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk

#define	GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos)

#define	GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos)

#define	GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos)

#define	GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos)

#define	GPIO_AFRH_AFSEL9_Pos (4U)

#define	GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos)

#define	GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk

#define	GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos)

#define	GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos)

#define	GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos)

#define	GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos)

#define	GPIO_AFRH_AFSEL10_Pos (8U)

#define	GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos)

#define	GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk

#define	GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos)

#define	GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos)

#define	GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos)

#define	GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos)

#define	GPIO_AFRH_AFSEL11_Pos (12U)

#define	GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos)

#define	GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk

#define	GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos)

#define	GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos)

#define	GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos)

#define	GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos)

#define	GPIO_AFRH_AFSEL12_Pos (16U)

#define	GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos)

#define	GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk

#define	GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos)

#define	GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos)

#define	GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos)

#define	GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos)

#define	GPIO_AFRH_AFSEL13_Pos (20U)

#define	GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos)

#define	GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk

#define	GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos)

#define	GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos)

#define	GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos)

#define	GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos)

#define	GPIO_AFRH_AFSEL14_Pos (24U)

#define	GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos)

#define	GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk

#define	GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos)

#define	GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos)

#define	GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos)

#define	GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos)

#define	GPIO_AFRH_AFSEL15_Pos (28U)

#define	GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos)

#define	GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk

#define	GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos)

#define	GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos)

#define	GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos)

#define	GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos)

#define	GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8

#define	GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9

#define	GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10

#define	GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11

#define	GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12

#define	GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13

#define	GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14

#define	GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15

#define	GPIO_BRR_BR0_Pos (0U)

#define	GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos)

#define	GPIO_BRR_BR0 GPIO_BRR_BR0_Msk

#define	GPIO_BRR_BR1_Pos (1U)

#define	GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos)

#define	GPIO_BRR_BR1 GPIO_BRR_BR1_Msk

#define	GPIO_BRR_BR2_Pos (2U)

#define	GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos)

#define	GPIO_BRR_BR2 GPIO_BRR_BR2_Msk

#define	GPIO_BRR_BR3_Pos (3U)

#define	GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos)

#define	GPIO_BRR_BR3 GPIO_BRR_BR3_Msk

#define	GPIO_BRR_BR4_Pos (4U)

#define	GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos)

#define	GPIO_BRR_BR4 GPIO_BRR_BR4_Msk

#define	GPIO_BRR_BR5_Pos (5U)

#define	GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos)

#define	GPIO_BRR_BR5 GPIO_BRR_BR5_Msk

#define	GPIO_BRR_BR6_Pos (6U)

#define	GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos)

#define	GPIO_BRR_BR6 GPIO_BRR_BR6_Msk

#define	GPIO_BRR_BR7_Pos (7U)

#define	GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos)

#define	GPIO_BRR_BR7 GPIO_BRR_BR7_Msk

#define	GPIO_BRR_BR8_Pos (8U)

#define	GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos)

#define	GPIO_BRR_BR8 GPIO_BRR_BR8_Msk

#define	GPIO_BRR_BR9_Pos (9U)

#define	GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos)

#define	GPIO_BRR_BR9 GPIO_BRR_BR9_Msk

#define	GPIO_BRR_BR10_Pos (10U)

#define	GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos)

#define	GPIO_BRR_BR10 GPIO_BRR_BR10_Msk

#define	GPIO_BRR_BR11_Pos (11U)

#define	GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos)

#define	GPIO_BRR_BR11 GPIO_BRR_BR11_Msk

#define	GPIO_BRR_BR12_Pos (12U)

#define	GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos)

#define	GPIO_BRR_BR12 GPIO_BRR_BR12_Msk

#define	GPIO_BRR_BR13_Pos (13U)

#define	GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos)

#define	GPIO_BRR_BR13 GPIO_BRR_BR13_Msk

#define	GPIO_BRR_BR14_Pos (14U)

#define	GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos)

#define	GPIO_BRR_BR14 GPIO_BRR_BR14_Msk

#define	GPIO_BRR_BR15_Pos (15U)

#define	GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos)

#define	GPIO_BRR_BR15 GPIO_BRR_BR15_Msk

#define	GPIO_BRR_BR_0 GPIO_BRR_BR0

#define	GPIO_BRR_BR_1 GPIO_BRR_BR1

#define	GPIO_BRR_BR_2 GPIO_BRR_BR2

#define	GPIO_BRR_BR_3 GPIO_BRR_BR3

#define	GPIO_BRR_BR_4 GPIO_BRR_BR4

#define	GPIO_BRR_BR_5 GPIO_BRR_BR5

#define	GPIO_BRR_BR_6 GPIO_BRR_BR6

#define	GPIO_BRR_BR_7 GPIO_BRR_BR7

#define	GPIO_BRR_BR_8 GPIO_BRR_BR8

#define	GPIO_BRR_BR_9 GPIO_BRR_BR9

#define	GPIO_BRR_BR_10 GPIO_BRR_BR10

#define	GPIO_BRR_BR_11 GPIO_BRR_BR11

#define	GPIO_BRR_BR_12 GPIO_BRR_BR12

#define	GPIO_BRR_BR_13 GPIO_BRR_BR13

#define	GPIO_BRR_BR_14 GPIO_BRR_BR14

#define	GPIO_BRR_BR_15 GPIO_BRR_BR15

#define	I2C_CR1_PE_Pos (0U)

#define	I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos)

#define	I2C_CR1_PE I2C_CR1_PE_Msk

#define	I2C_CR1_TXIE_Pos (1U)

#define	I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos)

#define	I2C_CR1_TXIE I2C_CR1_TXIE_Msk

#define	I2C_CR1_RXIE_Pos (2U)

#define	I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos)

#define	I2C_CR1_RXIE I2C_CR1_RXIE_Msk

#define	I2C_CR1_ADDRIE_Pos (3U)

#define	I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos)

#define	I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk

#define	I2C_CR1_NACKIE_Pos (4U)

#define	I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos)

#define	I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk

#define	I2C_CR1_STOPIE_Pos (5U)

#define	I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos)

#define	I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk

#define	I2C_CR1_TCIE_Pos (6U)

#define	I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos)

#define	I2C_CR1_TCIE I2C_CR1_TCIE_Msk

#define	I2C_CR1_ERRIE_Pos (7U)

#define	I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos)

#define	I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk

#define	I2C_CR1_DNF_Pos (8U)

#define	I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos)

#define	I2C_CR1_DNF I2C_CR1_DNF_Msk

#define	I2C_CR1_ANFOFF_Pos (12U)

#define	I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos)

#define	I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk

#define	I2C_CR1_SWRST_Pos (13U)

#define	I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos)

#define	I2C_CR1_SWRST I2C_CR1_SWRST_Msk

#define	I2C_CR1_TXDMAEN_Pos (14U)

#define	I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos)

#define	I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk

#define	I2C_CR1_RXDMAEN_Pos (15U)

#define	I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos)

#define	I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk

#define	I2C_CR1_SBC_Pos (16U)

#define	I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos)

#define	I2C_CR1_SBC I2C_CR1_SBC_Msk

#define	I2C_CR1_NOSTRETCH_Pos (17U)

#define	I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos)

#define	I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk

#define	I2C_CR1_WUPEN_Pos (18U)

#define	I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos)

#define	I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk

#define	I2C_CR1_GCEN_Pos (19U)

#define	I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos)

#define	I2C_CR1_GCEN I2C_CR1_GCEN_Msk

#define	I2C_CR1_SMBHEN_Pos (20U)

#define	I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos)

#define	I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk

#define	I2C_CR1_SMBDEN_Pos (21U)

#define	I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos)

#define	I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk

#define	I2C_CR1_ALERTEN_Pos (22U)

#define	I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos)

#define	I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk

#define	I2C_CR1_PECEN_Pos (23U)

#define	I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos)

#define	I2C_CR1_PECEN I2C_CR1_PECEN_Msk

#define	I2C_CR2_SADD_Pos (0U)

#define	I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos)

#define	I2C_CR2_SADD I2C_CR2_SADD_Msk

#define	I2C_CR2_RD_WRN_Pos (10U)

#define	I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos)

#define	I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk

#define	I2C_CR2_ADD10_Pos (11U)

#define	I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos)

#define	I2C_CR2_ADD10 I2C_CR2_ADD10_Msk

#define	I2C_CR2_HEAD10R_Pos (12U)

#define	I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos)

#define	I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk

#define	I2C_CR2_START_Pos (13U)

#define	I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos)

#define	I2C_CR2_START I2C_CR2_START_Msk

#define	I2C_CR2_STOP_Pos (14U)

#define	I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos)

#define	I2C_CR2_STOP I2C_CR2_STOP_Msk

#define	I2C_CR2_NACK_Pos (15U)

#define	I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos)

#define	I2C_CR2_NACK I2C_CR2_NACK_Msk

#define	I2C_CR2_NBYTES_Pos (16U)

#define	I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos)

#define	I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk

#define	I2C_CR2_RELOAD_Pos (24U)

#define	I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos)

#define	I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk

#define	I2C_CR2_AUTOEND_Pos (25U)

#define	I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos)

#define	I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk

#define	I2C_CR2_PECBYTE_Pos (26U)

#define	I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos)

#define	I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk

#define	I2C_OAR1_OA1_Pos (0U)

#define	I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos)

#define	I2C_OAR1_OA1 I2C_OAR1_OA1_Msk

#define	I2C_OAR1_OA1MODE_Pos (10U)

#define	I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos)

#define	I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk

#define	I2C_OAR1_OA1EN_Pos (15U)

#define	I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos)

#define	I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk

#define	I2C_OAR2_OA2_Pos (1U)

#define	I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos)

#define	I2C_OAR2_OA2 I2C_OAR2_OA2_Msk

#define	I2C_OAR2_OA2MSK_Pos (8U)

#define	I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos)

#define	I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk

#define	I2C_OAR2_OA2NOMASK (0x00000000U)

#define	I2C_OAR2_OA2MASK01_Pos (8U)

#define	I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos)

#define	I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk

#define	I2C_OAR2_OA2MASK02_Pos (9U)

#define	I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos)

#define	I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk

#define	I2C_OAR2_OA2MASK03_Pos (8U)

#define	I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos)

#define	I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk

#define	I2C_OAR2_OA2MASK04_Pos (10U)

#define	I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos)

#define	I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk

#define	I2C_OAR2_OA2MASK05_Pos (8U)

#define	I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos)

#define	I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk

#define	I2C_OAR2_OA2MASK06_Pos (9U)

#define	I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos)

#define	I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk

#define	I2C_OAR2_OA2MASK07_Pos (8U)

#define	I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos)

#define	I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk

#define	I2C_OAR2_OA2EN_Pos (15U)

#define	I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos)

#define	I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk

#define	I2C_TIMINGR_SCLL_Pos (0U)

#define	I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos)

#define	I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk

#define	I2C_TIMINGR_SCLH_Pos (8U)

#define	I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos)

#define	I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk

#define	I2C_TIMINGR_SDADEL_Pos (16U)

#define	I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos)

#define	I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk

#define	I2C_TIMINGR_SCLDEL_Pos (20U)

#define	I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos)

#define	I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk

#define	I2C_TIMINGR_PRESC_Pos (28U)

#define	I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos)

#define	I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk

#define	I2C_TIMEOUTR_TIMEOUTA_Pos (0U)

#define	I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)

#define	I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk

#define	I2C_TIMEOUTR_TIDLE_Pos (12U)

#define	I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)

#define	I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk

#define	I2C_TIMEOUTR_TIMOUTEN_Pos (15U)

#define	I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)

#define	I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk

#define	I2C_TIMEOUTR_TIMEOUTB_Pos (16U)

#define	I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)

#define	I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk

#define	I2C_TIMEOUTR_TEXTEN_Pos (31U)

#define	I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)

#define	I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk

#define	I2C_ISR_TXE_Pos (0U)

#define	I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos)

#define	I2C_ISR_TXE I2C_ISR_TXE_Msk

#define	I2C_ISR_TXIS_Pos (1U)

#define	I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos)

#define	I2C_ISR_TXIS I2C_ISR_TXIS_Msk

#define	I2C_ISR_RXNE_Pos (2U)

#define	I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos)

#define	I2C_ISR_RXNE I2C_ISR_RXNE_Msk

#define	I2C_ISR_ADDR_Pos (3U)

#define	I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos)

#define	I2C_ISR_ADDR I2C_ISR_ADDR_Msk

#define	I2C_ISR_NACKF_Pos (4U)

#define	I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos)

#define	I2C_ISR_NACKF I2C_ISR_NACKF_Msk

#define	I2C_ISR_STOPF_Pos (5U)

#define	I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos)

#define	I2C_ISR_STOPF I2C_ISR_STOPF_Msk

#define	I2C_ISR_TC_Pos (6U)

#define	I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos)

#define	I2C_ISR_TC I2C_ISR_TC_Msk

#define	I2C_ISR_TCR_Pos (7U)

#define	I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos)

#define	I2C_ISR_TCR I2C_ISR_TCR_Msk

#define	I2C_ISR_BERR_Pos (8U)

#define	I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos)

#define	I2C_ISR_BERR I2C_ISR_BERR_Msk

#define	I2C_ISR_ARLO_Pos (9U)

#define	I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos)

#define	I2C_ISR_ARLO I2C_ISR_ARLO_Msk

#define	I2C_ISR_OVR_Pos (10U)

#define	I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos)

#define	I2C_ISR_OVR I2C_ISR_OVR_Msk

#define	I2C_ISR_PECERR_Pos (11U)

#define	I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos)

#define	I2C_ISR_PECERR I2C_ISR_PECERR_Msk

#define	I2C_ISR_TIMEOUT_Pos (12U)

#define	I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos)

#define	I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk

#define	I2C_ISR_ALERT_Pos (13U)

#define	I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos)

#define	I2C_ISR_ALERT I2C_ISR_ALERT_Msk

#define	I2C_ISR_BUSY_Pos (15U)

#define	I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos)

#define	I2C_ISR_BUSY I2C_ISR_BUSY_Msk

#define	I2C_ISR_DIR_Pos (16U)

#define	I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos)

#define	I2C_ISR_DIR I2C_ISR_DIR_Msk

#define	I2C_ISR_ADDCODE_Pos (17U)

#define	I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos)

#define	I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk

#define	I2C_ICR_ADDRCF_Pos (3U)

#define	I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos)

#define	I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk

#define	I2C_ICR_NACKCF_Pos (4U)

#define	I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos)

#define	I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk

#define	I2C_ICR_STOPCF_Pos (5U)

#define	I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos)

#define	I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk

#define	I2C_ICR_BERRCF_Pos (8U)

#define	I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos)

#define	I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk

#define	I2C_ICR_ARLOCF_Pos (9U)

#define	I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos)

#define	I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk

#define	I2C_ICR_OVRCF_Pos (10U)

#define	I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos)

#define	I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk

#define	I2C_ICR_PECCF_Pos (11U)

#define	I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos)

#define	I2C_ICR_PECCF I2C_ICR_PECCF_Msk

#define	I2C_ICR_TIMOUTCF_Pos (12U)

#define	I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos)

#define	I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk

#define	I2C_ICR_ALERTCF_Pos (13U)

#define	I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos)

#define	I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk

#define	I2C_PECR_PEC_Pos (0U)

#define	I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos)

#define	I2C_PECR_PEC I2C_PECR_PEC_Msk

#define	I2C_RXDR_RXDATA_Pos (0U)

#define	I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos)

#define	I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk

#define	I2C_TXDR_TXDATA_Pos (0U)

#define	I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos)

#define	I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk

#define	IWDG_KR_KEY_Pos (0U)

#define	IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos)

#define	IWDG_KR_KEY IWDG_KR_KEY_Msk

#define	IWDG_PR_PR_Pos (0U)

#define	IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos)

#define	IWDG_PR_PR IWDG_PR_PR_Msk

#define	IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos)

#define	IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos)

#define	IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos)

#define	IWDG_RLR_RL_Pos (0U)

#define	IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos)

#define	IWDG_RLR_RL IWDG_RLR_RL_Msk

#define	IWDG_SR_PVU_Pos (0U)

#define	IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos)

#define	IWDG_SR_PVU IWDG_SR_PVU_Msk

#define	IWDG_SR_RVU_Pos (1U)

#define	IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos)

#define	IWDG_SR_RVU IWDG_SR_RVU_Msk

#define	IWDG_SR_WVU_Pos (2U)

#define	IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos)

#define	IWDG_SR_WVU IWDG_SR_WVU_Msk

#define	IWDG_WINR_WIN_Pos (0U)

#define	IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos)

#define	IWDG_WINR_WIN IWDG_WINR_WIN_Msk

#define	OPAMP_CSR_OPAMPxEN_Pos (0U)

#define	OPAMP_CSR_OPAMPxEN_Msk (0x1UL << OPAMP_CSR_OPAMPxEN_Pos)

#define	OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk

#define	OPAMP_CSR_FORCEVP_Pos (1U)

#define	OPAMP_CSR_FORCEVP_Msk (0x1UL << OPAMP_CSR_FORCEVP_Pos)

#define	OPAMP_CSR_FORCEVP OPAMP_CSR_FORCEVP_Msk

#define	OPAMP_CSR_VPSEL_Pos (2U)

#define	OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos)

#define	OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk

#define	OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos)

#define	OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos)

#define	OPAMP_CSR_USERTRIM_Pos (4U)

#define	OPAMP_CSR_USERTRIM_Msk (0x1UL << OPAMP_CSR_USERTRIM_Pos)

#define	OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk

#define	OPAMP_CSR_VMSEL_Pos (5U)

#define	OPAMP_CSR_VMSEL_Msk (0x3UL << OPAMP_CSR_VMSEL_Pos)

#define	OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk

#define	OPAMP_CSR_VMSEL_0 (0x1UL << OPAMP_CSR_VMSEL_Pos)

#define	OPAMP_CSR_VMSEL_1 (0x2UL << OPAMP_CSR_VMSEL_Pos)

#define	OPAMP_CSR_HIGHSPEEDEN_Pos (7U)

#define	OPAMP_CSR_HIGHSPEEDEN_Msk (0x1UL << OPAMP_CSR_HIGHSPEEDEN_Pos)

#define	OPAMP_CSR_HIGHSPEEDEN OPAMP_CSR_HIGHSPEEDEN_Msk

#define	OPAMP_CSR_OPAMPINTEN_Pos (8U)

#define	OPAMP_CSR_OPAMPINTEN_Msk (0x1UL << OPAMP_CSR_OPAMPINTEN_Pos)

#define	OPAMP_CSR_OPAMPINTEN OPAMP_CSR_OPAMPINTEN_Msk

#define	OPAMP_CSR_CALON_Pos (11U)

#define	OPAMP_CSR_CALON_Msk (0x1UL << OPAMP_CSR_CALON_Pos)

#define	OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk

#define	OPAMP_CSR_CALSEL_Pos (12U)

#define	OPAMP_CSR_CALSEL_Msk (0x3UL << OPAMP_CSR_CALSEL_Pos)

#define	OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk

#define	OPAMP_CSR_CALSEL_0 (0x1UL << OPAMP_CSR_CALSEL_Pos)

#define	OPAMP_CSR_CALSEL_1 (0x2UL << OPAMP_CSR_CALSEL_Pos)

#define	OPAMP_CSR_PGGAIN_Pos (14U)

#define	OPAMP_CSR_PGGAIN_Msk (0x1FUL << OPAMP_CSR_PGGAIN_Pos)

#define	OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk

#define	OPAMP_CSR_PGGAIN_0 (0x1UL << OPAMP_CSR_PGGAIN_Pos)

#define	OPAMP_CSR_PGGAIN_1 (0x2UL << OPAMP_CSR_PGGAIN_Pos)

#define	OPAMP_CSR_PGGAIN_2 (0x4UL << OPAMP_CSR_PGGAIN_Pos)

#define	OPAMP_CSR_PGGAIN_3 (0x8UL << OPAMP_CSR_PGGAIN_Pos)

#define	OPAMP_CSR_PGGAIN_4 (0x10UL << OPAMP_CSR_PGGAIN_Pos)

#define	OPAMP_CSR_TRIMOFFSETP_Pos (19U)

#define	OPAMP_CSR_TRIMOFFSETP_Msk (0x1FUL << OPAMP_CSR_TRIMOFFSETP_Pos)

#define	OPAMP_CSR_TRIMOFFSETP OPAMP_CSR_TRIMOFFSETP_Msk

#define	OPAMP_CSR_TRIMOFFSETN_Pos (24U)

#define	OPAMP_CSR_TRIMOFFSETN_Msk (0x1FUL << OPAMP_CSR_TRIMOFFSETN_Pos)

#define	OPAMP_CSR_TRIMOFFSETN OPAMP_CSR_TRIMOFFSETN_Msk

#define	OPAMP_CSR_OUTCAL_Pos (30U)

#define	OPAMP_CSR_OUTCAL_Msk (0x1UL << OPAMP_CSR_OUTCAL_Pos)

#define	OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk

#define	OPAMP_CSR_LOCK_Pos (31U)

#define	OPAMP_CSR_LOCK_Msk (0x1UL << OPAMP_CSR_LOCK_Pos)

#define	OPAMP_CSR_LOCK OPAMP_CSR_LOCK_Msk

#define	OPAMP_TCMR_VMSSEL_Pos (0U)

#define	OPAMP_TCMR_VMSSEL_Msk (0x1UL << OPAMP_TCMR_VMSSEL_Pos)

#define	OPAMP_TCMR_VMSSEL OPAMP_TCMR_VMSSEL_Msk

#define	OPAMP_TCMR_VPSSEL_Pos (1U)

#define	OPAMP_TCMR_VPSSEL_Msk (0x3UL << OPAMP_TCMR_VPSSEL_Pos)

#define	OPAMP_TCMR_VPSSEL OPAMP_TCMR_VPSSEL_Msk

#define	OPAMP_TCMR_VPSSEL_0 (0x1UL << OPAMP_TCMR_VPSSEL_Pos)

#define	OPAMP_TCMR_VPSSEL_1 (0x2UL << OPAMP_TCMR_VPSSEL_Pos)

#define	OPAMP_TCMR_T1CMEN_Pos (3U)

#define	OPAMP_TCMR_T1CMEN_Msk (0x1UL << OPAMP_TCMR_T1CMEN_Pos)

#define	OPAMP_TCMR_T1CMEN OPAMP_TCMR_T1CMEN_Msk

#define	OPAMP_TCMR_T8CMEN_Pos (4U)

#define	OPAMP_TCMR_T8CMEN_Msk (0x1UL << OPAMP_TCMR_T8CMEN_Pos)

#define	OPAMP_TCMR_T8CMEN OPAMP_TCMR_T8CMEN_Msk

#define	OPAMP_TCMR_T20CMEN_Pos (5U)

#define	OPAMP_TCMR_T20CMEN_Msk (0x1UL << OPAMP_TCMR_T20CMEN_Pos)

#define	OPAMP_TCMR_T20CMEN OPAMP_TCMR_T20CMEN_Msk

#define	OPAMP_TCMR_LOCK_Pos (31U)

#define	OPAMP_TCMR_LOCK_Msk (0x1UL << OPAMP_TCMR_LOCK_Pos)

#define	OPAMP_TCMR_LOCK OPAMP_TCMR_LOCK_Msk

#define	PWR_CR1_LPR_Pos (14U)

#define	PWR_CR1_LPR_Msk (0x1UL << PWR_CR1_LPR_Pos)

#define	PWR_CR1_LPR PWR_CR1_LPR_Msk

#define	PWR_CR1_VOS_Pos (9U)

#define	PWR_CR1_VOS_Msk (0x3UL << PWR_CR1_VOS_Pos)

#define	PWR_CR1_VOS PWR_CR1_VOS_Msk

#define	PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_Pos)

#define	PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_Pos)

#define	PWR_CR1_DBP_Pos (8U)

#define	PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos)

#define	PWR_CR1_DBP PWR_CR1_DBP_Msk

#define	PWR_CR1_LPMS_Pos (0U)

#define	PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos)

#define	PWR_CR1_LPMS PWR_CR1_LPMS_Msk

#define	PWR_CR1_LPMS_STOP0 (0x00000000U)

#define	PWR_CR1_LPMS_STOP1_Pos (0U)

#define	PWR_CR1_LPMS_STOP1_Msk (0x1UL << PWR_CR1_LPMS_STOP1_Pos)

#define	PWR_CR1_LPMS_STOP1 PWR_CR1_LPMS_STOP1_Msk

#define	PWR_CR1_LPMS_STANDBY_Pos (0U)

#define	PWR_CR1_LPMS_STANDBY_Msk (0x3UL << PWR_CR1_LPMS_STANDBY_Pos)

#define	PWR_CR1_LPMS_STANDBY PWR_CR1_LPMS_STANDBY_Msk

#define	PWR_CR1_LPMS_SHUTDOWN_Pos (2U)

#define	PWR_CR1_LPMS_SHUTDOWN_Msk (0x1UL << PWR_CR1_LPMS_SHUTDOWN_Pos)

#define	PWR_CR1_LPMS_SHUTDOWN PWR_CR1_LPMS_SHUTDOWN_Msk

#define	PWR_CR2_PVME_Pos (4U)

#define	PWR_CR2_PVME_Msk (0xFUL << PWR_CR2_PVME_Pos)

#define	PWR_CR2_PVME PWR_CR2_PVME_Msk

#define	PWR_CR2_PVME4_Pos (7U)

#define	PWR_CR2_PVME4_Msk (0x1UL << PWR_CR2_PVME4_Pos)

#define	PWR_CR2_PVME4 PWR_CR2_PVME4_Msk

#define	PWR_CR2_PVME3_Pos (6U)

#define	PWR_CR2_PVME3_Msk (0x1UL << PWR_CR2_PVME3_Pos)

#define	PWR_CR2_PVME3 PWR_CR2_PVME3_Msk

#define	PWR_CR2_PVME2_Pos (5U)

#define	PWR_CR2_PVME2_Msk (0x1UL << PWR_CR2_PVME2_Pos)

#define	PWR_CR2_PVME2 PWR_CR2_PVME2_Msk

#define	PWR_CR2_PVME1_Pos (4U)

#define	PWR_CR2_PVME1_Msk (0x1UL << PWR_CR2_PVME1_Pos)

#define	PWR_CR2_PVME1 PWR_CR2_PVME1_Msk

#define	PWR_CR2_PLS_Pos (1U)

#define	PWR_CR2_PLS_Msk (0x7UL << PWR_CR2_PLS_Pos)

#define	PWR_CR2_PLS PWR_CR2_PLS_Msk

#define	PWR_CR2_PLS_LEV0 (0x00000000U)

#define	PWR_CR2_PLS_LEV1_Pos (1U)

#define	PWR_CR2_PLS_LEV1_Msk (0x1UL << PWR_CR2_PLS_LEV1_Pos)

#define	PWR_CR2_PLS_LEV1 PWR_CR2_PLS_LEV1_Msk

#define	PWR_CR2_PLS_LEV2_Pos (2U)

#define	PWR_CR2_PLS_LEV2_Msk (0x1UL << PWR_CR2_PLS_LEV2_Pos)

#define	PWR_CR2_PLS_LEV2 PWR_CR2_PLS_LEV2_Msk

#define	PWR_CR2_PLS_LEV3_Pos (1U)

#define	PWR_CR2_PLS_LEV3_Msk (0x3UL << PWR_CR2_PLS_LEV3_Pos)

#define	PWR_CR2_PLS_LEV3 PWR_CR2_PLS_LEV3_Msk

#define	PWR_CR2_PLS_LEV4_Pos (3U)

#define	PWR_CR2_PLS_LEV4_Msk (0x1UL << PWR_CR2_PLS_LEV4_Pos)

#define	PWR_CR2_PLS_LEV4 PWR_CR2_PLS_LEV4_Msk

#define	PWR_CR2_PLS_LEV5_Pos (1U)

#define	PWR_CR2_PLS_LEV5_Msk (0x5UL << PWR_CR2_PLS_LEV5_Pos)

#define	PWR_CR2_PLS_LEV5 PWR_CR2_PLS_LEV5_Msk

#define	PWR_CR2_PLS_LEV6_Pos (2U)

#define	PWR_CR2_PLS_LEV6_Msk (0x3UL << PWR_CR2_PLS_LEV6_Pos)

#define	PWR_CR2_PLS_LEV6 PWR_CR2_PLS_LEV6_Msk

#define	PWR_CR2_PLS_LEV7_Pos (1U)

#define	PWR_CR2_PLS_LEV7_Msk (0x7UL << PWR_CR2_PLS_LEV7_Pos)

#define	PWR_CR2_PLS_LEV7 PWR_CR2_PLS_LEV7_Msk

#define	PWR_CR2_PVDE_Pos (0U)

#define	PWR_CR2_PVDE_Msk (0x1UL << PWR_CR2_PVDE_Pos)

#define	PWR_CR2_PVDE PWR_CR2_PVDE_Msk

#define	PWR_CR3_EIWF_Pos (15U)

#define	PWR_CR3_EIWF_Msk (0x1UL << PWR_CR3_EIWF_Pos)

#define	PWR_CR3_EIWF PWR_CR3_EIWF_Msk

#define	PWR_CR3_UCPD_DBDIS_Pos (14U)

#define	PWR_CR3_UCPD_DBDIS_Msk (0x1UL << PWR_CR3_UCPD_DBDIS_Pos)

#define	PWR_CR3_UCPD_DBDIS PWR_CR3_UCPD_DBDIS_Msk

#define	PWR_CR3_UCPD_STDBY_Pos (13U)

#define	PWR_CR3_UCPD_STDBY_Msk (0x1UL << PWR_CR3_UCPD_STDBY_Pos)

#define	PWR_CR3_UCPD_STDBY PWR_CR3_UCPD_STDBY_Msk

#define	PWR_CR3_APC_Pos (10U)

#define	PWR_CR3_APC_Msk (0x1UL << PWR_CR3_APC_Pos)

#define	PWR_CR3_APC PWR_CR3_APC_Msk

#define	PWR_CR3_RRS_Pos (8U)

#define	PWR_CR3_RRS_Msk (0x1UL << PWR_CR3_RRS_Pos)

#define	PWR_CR3_RRS PWR_CR3_RRS_Msk

#define	PWR_CR3_EWUP5_Pos (4U)

#define	PWR_CR3_EWUP5_Msk (0x1UL << PWR_CR3_EWUP5_Pos)

#define	PWR_CR3_EWUP5 PWR_CR3_EWUP5_Msk

#define	PWR_CR3_EWUP4_Pos (3U)

#define	PWR_CR3_EWUP4_Msk (0x1UL << PWR_CR3_EWUP4_Pos)

#define	PWR_CR3_EWUP4 PWR_CR3_EWUP4_Msk

#define	PWR_CR3_EWUP3_Pos (2U)

#define	PWR_CR3_EWUP3_Msk (0x1UL << PWR_CR3_EWUP3_Pos)

#define	PWR_CR3_EWUP3 PWR_CR3_EWUP3_Msk

#define	PWR_CR3_EWUP2_Pos (1U)

#define	PWR_CR3_EWUP2_Msk (0x1UL << PWR_CR3_EWUP2_Pos)

#define	PWR_CR3_EWUP2 PWR_CR3_EWUP2_Msk

#define	PWR_CR3_EWUP1_Pos (0U)

#define	PWR_CR3_EWUP1_Msk (0x1UL << PWR_CR3_EWUP1_Pos)

#define	PWR_CR3_EWUP1 PWR_CR3_EWUP1_Msk

#define	PWR_CR3_EWUP_Pos (0U)

#define	PWR_CR3_EWUP_Msk (0x1FUL << PWR_CR3_EWUP_Pos)

#define	PWR_CR3_EWUP PWR_CR3_EWUP_Msk

#define	PWR_CR4_VBRS_Pos (9U)

#define	PWR_CR4_VBRS_Msk (0x1UL << PWR_CR4_VBRS_Pos)

#define	PWR_CR4_VBRS PWR_CR4_VBRS_Msk

#define	PWR_CR4_VBE_Pos (8U)

#define	PWR_CR4_VBE_Msk (0x1UL << PWR_CR4_VBE_Pos)

#define	PWR_CR4_VBE PWR_CR4_VBE_Msk

#define	PWR_CR4_WP5_Pos (4U)

#define	PWR_CR4_WP5_Msk (0x1UL << PWR_CR4_WP5_Pos)

#define	PWR_CR4_WP5 PWR_CR4_WP5_Msk

#define	PWR_CR4_WP4_Pos (3U)

#define	PWR_CR4_WP4_Msk (0x1UL << PWR_CR4_WP4_Pos)

#define	PWR_CR4_WP4 PWR_CR4_WP4_Msk

#define	PWR_CR4_WP3_Pos (2U)

#define	PWR_CR4_WP3_Msk (0x1UL << PWR_CR4_WP3_Pos)

#define	PWR_CR4_WP3 PWR_CR4_WP3_Msk

#define	PWR_CR4_WP2_Pos (1U)

#define	PWR_CR4_WP2_Msk (0x1UL << PWR_CR4_WP2_Pos)

#define	PWR_CR4_WP2 PWR_CR4_WP2_Msk

#define	PWR_CR4_WP1_Pos (0U)

#define	PWR_CR4_WP1_Msk (0x1UL << PWR_CR4_WP1_Pos)

#define	PWR_CR4_WP1 PWR_CR4_WP1_Msk

#define	PWR_SR1_WUFI_Pos (15U)

#define	PWR_SR1_WUFI_Msk (0x1UL << PWR_SR1_WUFI_Pos)

#define	PWR_SR1_WUFI PWR_SR1_WUFI_Msk

#define	PWR_SR1_SBF_Pos (8U)

#define	PWR_SR1_SBF_Msk (0x1UL << PWR_SR1_SBF_Pos)

#define	PWR_SR1_SBF PWR_SR1_SBF_Msk

#define	PWR_SR1_WUF_Pos (0U)

#define	PWR_SR1_WUF_Msk (0x1FUL << PWR_SR1_WUF_Pos)

#define	PWR_SR1_WUF PWR_SR1_WUF_Msk

#define	PWR_SR1_WUF5_Pos (4U)

#define	PWR_SR1_WUF5_Msk (0x1UL << PWR_SR1_WUF5_Pos)

#define	PWR_SR1_WUF5 PWR_SR1_WUF5_Msk

#define	PWR_SR1_WUF4_Pos (3U)

#define	PWR_SR1_WUF4_Msk (0x1UL << PWR_SR1_WUF4_Pos)

#define	PWR_SR1_WUF4 PWR_SR1_WUF4_Msk

#define	PWR_SR1_WUF3_Pos (2U)

#define	PWR_SR1_WUF3_Msk (0x1UL << PWR_SR1_WUF3_Pos)

#define	PWR_SR1_WUF3 PWR_SR1_WUF3_Msk

#define	PWR_SR1_WUF2_Pos (1U)

#define	PWR_SR1_WUF2_Msk (0x1UL << PWR_SR1_WUF2_Pos)

#define	PWR_SR1_WUF2 PWR_SR1_WUF2_Msk

#define	PWR_SR1_WUF1_Pos (0U)

#define	PWR_SR1_WUF1_Msk (0x1UL << PWR_SR1_WUF1_Pos)

#define	PWR_SR1_WUF1 PWR_SR1_WUF1_Msk

#define	PWR_SR2_PVMO4_Pos (15U)

#define	PWR_SR2_PVMO4_Msk (0x1UL << PWR_SR2_PVMO4_Pos)

#define	PWR_SR2_PVMO4 PWR_SR2_PVMO4_Msk

#define	PWR_SR2_PVMO3_Pos (14U)

#define	PWR_SR2_PVMO3_Msk (0x1UL << PWR_SR2_PVMO3_Pos)

#define	PWR_SR2_PVMO3 PWR_SR2_PVMO3_Msk

#define	PWR_SR2_PVMO2_Pos (13U)

#define	PWR_SR2_PVMO2_Msk (0x1UL << PWR_SR2_PVMO2_Pos)

#define	PWR_SR2_PVMO2 PWR_SR2_PVMO2_Msk

#define	PWR_SR2_PVMO1_Pos (12U)

#define	PWR_SR2_PVMO1_Msk (0x1UL << PWR_SR2_PVMO1_Pos)

#define	PWR_SR2_PVMO1 PWR_SR2_PVMO1_Msk

#define	PWR_SR2_PVDO_Pos (11U)

#define	PWR_SR2_PVDO_Msk (0x1UL << PWR_SR2_PVDO_Pos)

#define	PWR_SR2_PVDO PWR_SR2_PVDO_Msk

#define	PWR_SR2_VOSF_Pos (10U)

#define	PWR_SR2_VOSF_Msk (0x1UL << PWR_SR2_VOSF_Pos)

#define	PWR_SR2_VOSF PWR_SR2_VOSF_Msk

#define	PWR_SR2_REGLPF_Pos (9U)

#define	PWR_SR2_REGLPF_Msk (0x1UL << PWR_SR2_REGLPF_Pos)

#define	PWR_SR2_REGLPF PWR_SR2_REGLPF_Msk

#define	PWR_SR2_REGLPS_Pos (8U)

#define	PWR_SR2_REGLPS_Msk (0x1UL << PWR_SR2_REGLPS_Pos)

#define	PWR_SR2_REGLPS PWR_SR2_REGLPS_Msk

#define	PWR_SCR_CSBF_Pos (8U)

#define	PWR_SCR_CSBF_Msk (0x1UL << PWR_SCR_CSBF_Pos)

#define	PWR_SCR_CSBF PWR_SCR_CSBF_Msk

#define	PWR_SCR_CWUF_Pos (0U)

#define	PWR_SCR_CWUF_Msk (0x1FUL << PWR_SCR_CWUF_Pos)

#define	PWR_SCR_CWUF PWR_SCR_CWUF_Msk

#define	PWR_SCR_CWUF5_Pos (4U)

#define	PWR_SCR_CWUF5_Msk (0x1UL << PWR_SCR_CWUF5_Pos)

#define	PWR_SCR_CWUF5 PWR_SCR_CWUF5_Msk

#define	PWR_SCR_CWUF4_Pos (3U)

#define	PWR_SCR_CWUF4_Msk (0x1UL << PWR_SCR_CWUF4_Pos)

#define	PWR_SCR_CWUF4 PWR_SCR_CWUF4_Msk

#define	PWR_SCR_CWUF3_Pos (2U)

#define	PWR_SCR_CWUF3_Msk (0x1UL << PWR_SCR_CWUF3_Pos)

#define	PWR_SCR_CWUF3 PWR_SCR_CWUF3_Msk

#define	PWR_SCR_CWUF2_Pos (1U)

#define	PWR_SCR_CWUF2_Msk (0x1UL << PWR_SCR_CWUF2_Pos)

#define	PWR_SCR_CWUF2 PWR_SCR_CWUF2_Msk

#define	PWR_SCR_CWUF1_Pos (0U)

#define	PWR_SCR_CWUF1_Msk (0x1UL << PWR_SCR_CWUF1_Pos)

#define	PWR_SCR_CWUF1 PWR_SCR_CWUF1_Msk

#define	PWR_PUCRA_PA15_Pos (15U)

#define	PWR_PUCRA_PA15_Msk (0x1UL << PWR_PUCRA_PA15_Pos)

#define	PWR_PUCRA_PA15 PWR_PUCRA_PA15_Msk

#define	PWR_PUCRA_PA13_Pos (13U)

#define	PWR_PUCRA_PA13_Msk (0x1UL << PWR_PUCRA_PA13_Pos)

#define	PWR_PUCRA_PA13 PWR_PUCRA_PA13_Msk

#define	PWR_PUCRA_PA12_Pos (12U)

#define	PWR_PUCRA_PA12_Msk (0x1UL << PWR_PUCRA_PA12_Pos)

#define	PWR_PUCRA_PA12 PWR_PUCRA_PA12_Msk

#define	PWR_PUCRA_PA11_Pos (11U)

#define	PWR_PUCRA_PA11_Msk (0x1UL << PWR_PUCRA_PA11_Pos)

#define	PWR_PUCRA_PA11 PWR_PUCRA_PA11_Msk

#define	PWR_PUCRA_PA10_Pos (10U)

#define	PWR_PUCRA_PA10_Msk (0x1UL << PWR_PUCRA_PA10_Pos)

#define	PWR_PUCRA_PA10 PWR_PUCRA_PA10_Msk

#define	PWR_PUCRA_PA9_Pos (9U)

#define	PWR_PUCRA_PA9_Msk (0x1UL << PWR_PUCRA_PA9_Pos)

#define	PWR_PUCRA_PA9 PWR_PUCRA_PA9_Msk

#define	PWR_PUCRA_PA8_Pos (8U)

#define	PWR_PUCRA_PA8_Msk (0x1UL << PWR_PUCRA_PA8_Pos)

#define	PWR_PUCRA_PA8 PWR_PUCRA_PA8_Msk

#define	PWR_PUCRA_PA7_Pos (7U)

#define	PWR_PUCRA_PA7_Msk (0x1UL << PWR_PUCRA_PA7_Pos)

#define	PWR_PUCRA_PA7 PWR_PUCRA_PA7_Msk

#define	PWR_PUCRA_PA6_Pos (6U)

#define	PWR_PUCRA_PA6_Msk (0x1UL << PWR_PUCRA_PA6_Pos)

#define	PWR_PUCRA_PA6 PWR_PUCRA_PA6_Msk

#define	PWR_PUCRA_PA5_Pos (5U)

#define	PWR_PUCRA_PA5_Msk (0x1UL << PWR_PUCRA_PA5_Pos)

#define	PWR_PUCRA_PA5 PWR_PUCRA_PA5_Msk

#define	PWR_PUCRA_PA4_Pos (4U)

#define	PWR_PUCRA_PA4_Msk (0x1UL << PWR_PUCRA_PA4_Pos)

#define	PWR_PUCRA_PA4 PWR_PUCRA_PA4_Msk

#define	PWR_PUCRA_PA3_Pos (3U)

#define	PWR_PUCRA_PA3_Msk (0x1UL << PWR_PUCRA_PA3_Pos)

#define	PWR_PUCRA_PA3 PWR_PUCRA_PA3_Msk

#define	PWR_PUCRA_PA2_Pos (2U)

#define	PWR_PUCRA_PA2_Msk (0x1UL << PWR_PUCRA_PA2_Pos)

#define	PWR_PUCRA_PA2 PWR_PUCRA_PA2_Msk

#define	PWR_PUCRA_PA1_Pos (1U)

#define	PWR_PUCRA_PA1_Msk (0x1UL << PWR_PUCRA_PA1_Pos)

#define	PWR_PUCRA_PA1 PWR_PUCRA_PA1_Msk

#define	PWR_PUCRA_PA0_Pos (0U)

#define	PWR_PUCRA_PA0_Msk (0x1UL << PWR_PUCRA_PA0_Pos)

#define	PWR_PUCRA_PA0 PWR_PUCRA_PA0_Msk

#define	PWR_PDCRA_PA14_Pos (14U)

#define	PWR_PDCRA_PA14_Msk (0x1UL << PWR_PDCRA_PA14_Pos)

#define	PWR_PDCRA_PA14 PWR_PDCRA_PA14_Msk

#define	PWR_PDCRA_PA12_Pos (12U)

#define	PWR_PDCRA_PA12_Msk (0x1UL << PWR_PDCRA_PA12_Pos)

#define	PWR_PDCRA_PA12 PWR_PDCRA_PA12_Msk

#define	PWR_PDCRA_PA11_Pos (11U)

#define	PWR_PDCRA_PA11_Msk (0x1UL << PWR_PDCRA_PA11_Pos)

#define	PWR_PDCRA_PA11 PWR_PDCRA_PA11_Msk

#define	PWR_PDCRA_PA10_Pos (10U)

#define	PWR_PDCRA_PA10_Msk (0x1UL << PWR_PDCRA_PA10_Pos)

#define	PWR_PDCRA_PA10 PWR_PDCRA_PA10_Msk

#define	PWR_PDCRA_PA9_Pos (9U)

#define	PWR_PDCRA_PA9_Msk (0x1UL << PWR_PDCRA_PA9_Pos)

#define	PWR_PDCRA_PA9 PWR_PDCRA_PA9_Msk

#define	PWR_PDCRA_PA8_Pos (8U)

#define	PWR_PDCRA_PA8_Msk (0x1UL << PWR_PDCRA_PA8_Pos)

#define	PWR_PDCRA_PA8 PWR_PDCRA_PA8_Msk

#define	PWR_PDCRA_PA7_Pos (7U)

#define	PWR_PDCRA_PA7_Msk (0x1UL << PWR_PDCRA_PA7_Pos)

#define	PWR_PDCRA_PA7 PWR_PDCRA_PA7_Msk

#define	PWR_PDCRA_PA6_Pos (6U)

#define	PWR_PDCRA_PA6_Msk (0x1UL << PWR_PDCRA_PA6_Pos)

#define	PWR_PDCRA_PA6 PWR_PDCRA_PA6_Msk

#define	PWR_PDCRA_PA5_Pos (5U)

#define	PWR_PDCRA_PA5_Msk (0x1UL << PWR_PDCRA_PA5_Pos)

#define	PWR_PDCRA_PA5 PWR_PDCRA_PA5_Msk

#define	PWR_PDCRA_PA4_Pos (4U)

#define	PWR_PDCRA_PA4_Msk (0x1UL << PWR_PDCRA_PA4_Pos)

#define	PWR_PDCRA_PA4 PWR_PDCRA_PA4_Msk

#define	PWR_PDCRA_PA3_Pos (3U)

#define	PWR_PDCRA_PA3_Msk (0x1UL << PWR_PDCRA_PA3_Pos)

#define	PWR_PDCRA_PA3 PWR_PDCRA_PA3_Msk

#define	PWR_PDCRA_PA2_Pos (2U)

#define	PWR_PDCRA_PA2_Msk (0x1UL << PWR_PDCRA_PA2_Pos)

#define	PWR_PDCRA_PA2 PWR_PDCRA_PA2_Msk

#define	PWR_PDCRA_PA1_Pos (1U)

#define	PWR_PDCRA_PA1_Msk (0x1UL << PWR_PDCRA_PA1_Pos)

#define	PWR_PDCRA_PA1 PWR_PDCRA_PA1_Msk

#define	PWR_PDCRA_PA0_Pos (0U)

#define	PWR_PDCRA_PA0_Msk (0x1UL << PWR_PDCRA_PA0_Pos)

#define	PWR_PDCRA_PA0 PWR_PDCRA_PA0_Msk

#define	PWR_PUCRB_PB15_Pos (15U)

#define	PWR_PUCRB_PB15_Msk (0x1UL << PWR_PUCRB_PB15_Pos)

#define	PWR_PUCRB_PB15 PWR_PUCRB_PB15_Msk

#define	PWR_PUCRB_PB14_Pos (14U)

#define	PWR_PUCRB_PB14_Msk (0x1UL << PWR_PUCRB_PB14_Pos)

#define	PWR_PUCRB_PB14 PWR_PUCRB_PB14_Msk

#define	PWR_PUCRB_PB13_Pos (13U)

#define	PWR_PUCRB_PB13_Msk (0x1UL << PWR_PUCRB_PB13_Pos)

#define	PWR_PUCRB_PB13 PWR_PUCRB_PB13_Msk

#define	PWR_PUCRB_PB12_Pos (12U)

#define	PWR_PUCRB_PB12_Msk (0x1UL << PWR_PUCRB_PB12_Pos)

#define	PWR_PUCRB_PB12 PWR_PUCRB_PB12_Msk

#define	PWR_PUCRB_PB11_Pos (11U)

#define	PWR_PUCRB_PB11_Msk (0x1UL << PWR_PUCRB_PB11_Pos)

#define	PWR_PUCRB_PB11 PWR_PUCRB_PB11_Msk

#define	PWR_PUCRB_PB10_Pos (10U)

#define	PWR_PUCRB_PB10_Msk (0x1UL << PWR_PUCRB_PB10_Pos)

#define	PWR_PUCRB_PB10 PWR_PUCRB_PB10_Msk

#define	PWR_PUCRB_PB9_Pos (9U)

#define	PWR_PUCRB_PB9_Msk (0x1UL << PWR_PUCRB_PB9_Pos)

#define	PWR_PUCRB_PB9 PWR_PUCRB_PB9_Msk

#define	PWR_PUCRB_PB8_Pos (8U)

#define	PWR_PUCRB_PB8_Msk (0x1UL << PWR_PUCRB_PB8_Pos)

#define	PWR_PUCRB_PB8 PWR_PUCRB_PB8_Msk

#define	PWR_PUCRB_PB7_Pos (7U)

#define	PWR_PUCRB_PB7_Msk (0x1UL << PWR_PUCRB_PB7_Pos)

#define	PWR_PUCRB_PB7 PWR_PUCRB_PB7_Msk

#define	PWR_PUCRB_PB6_Pos (6U)

#define	PWR_PUCRB_PB6_Msk (0x1UL << PWR_PUCRB_PB6_Pos)

#define	PWR_PUCRB_PB6 PWR_PUCRB_PB6_Msk

#define	PWR_PUCRB_PB5_Pos (5U)

#define	PWR_PUCRB_PB5_Msk (0x1UL << PWR_PUCRB_PB5_Pos)

#define	PWR_PUCRB_PB5 PWR_PUCRB_PB5_Msk

#define	PWR_PUCRB_PB4_Pos (4U)

#define	PWR_PUCRB_PB4_Msk (0x1UL << PWR_PUCRB_PB4_Pos)

#define	PWR_PUCRB_PB4 PWR_PUCRB_PB4_Msk

#define	PWR_PUCRB_PB3_Pos (3U)

#define	PWR_PUCRB_PB3_Msk (0x1UL << PWR_PUCRB_PB3_Pos)

#define	PWR_PUCRB_PB3 PWR_PUCRB_PB3_Msk

#define	PWR_PUCRB_PB2_Pos (2U)

#define	PWR_PUCRB_PB2_Msk (0x1UL << PWR_PUCRB_PB2_Pos)

#define	PWR_PUCRB_PB2 PWR_PUCRB_PB2_Msk

#define	PWR_PUCRB_PB1_Pos (1U)

#define	PWR_PUCRB_PB1_Msk (0x1UL << PWR_PUCRB_PB1_Pos)

#define	PWR_PUCRB_PB1 PWR_PUCRB_PB1_Msk

#define	PWR_PUCRB_PB0_Pos (0U)

#define	PWR_PUCRB_PB0_Msk (0x1UL << PWR_PUCRB_PB0_Pos)

#define	PWR_PUCRB_PB0 PWR_PUCRB_PB0_Msk

#define	PWR_PDCRB_PB15_Pos (15U)

#define	PWR_PDCRB_PB15_Msk (0x1UL << PWR_PDCRB_PB15_Pos)

#define	PWR_PDCRB_PB15 PWR_PDCRB_PB15_Msk

#define	PWR_PDCRB_PB14_Pos (14U)

#define	PWR_PDCRB_PB14_Msk (0x1UL << PWR_PDCRB_PB14_Pos)

#define	PWR_PDCRB_PB14 PWR_PDCRB_PB14_Msk

#define	PWR_PDCRB_PB13_Pos (13U)

#define	PWR_PDCRB_PB13_Msk (0x1UL << PWR_PDCRB_PB13_Pos)

#define	PWR_PDCRB_PB13 PWR_PDCRB_PB13_Msk

#define	PWR_PDCRB_PB12_Pos (12U)

#define	PWR_PDCRB_PB12_Msk (0x1UL << PWR_PDCRB_PB12_Pos)

#define	PWR_PDCRB_PB12 PWR_PDCRB_PB12_Msk

#define	PWR_PDCRB_PB11_Pos (11U)

#define	PWR_PDCRB_PB11_Msk (0x1UL << PWR_PDCRB_PB11_Pos)

#define	PWR_PDCRB_PB11 PWR_PDCRB_PB11_Msk

#define	PWR_PDCRB_PB10_Pos (10U)

#define	PWR_PDCRB_PB10_Msk (0x1UL << PWR_PDCRB_PB10_Pos)

#define	PWR_PDCRB_PB10 PWR_PDCRB_PB10_Msk

#define	PWR_PDCRB_PB9_Pos (9U)

#define	PWR_PDCRB_PB9_Msk (0x1UL << PWR_PDCRB_PB9_Pos)

#define	PWR_PDCRB_PB9 PWR_PDCRB_PB9_Msk

#define	PWR_PDCRB_PB8_Pos (8U)

#define	PWR_PDCRB_PB8_Msk (0x1UL << PWR_PDCRB_PB8_Pos)

#define	PWR_PDCRB_PB8 PWR_PDCRB_PB8_Msk

#define	PWR_PDCRB_PB7_Pos (7U)

#define	PWR_PDCRB_PB7_Msk (0x1UL << PWR_PDCRB_PB7_Pos)

#define	PWR_PDCRB_PB7 PWR_PDCRB_PB7_Msk

#define	PWR_PDCRB_PB6_Pos (6U)

#define	PWR_PDCRB_PB6_Msk (0x1UL << PWR_PDCRB_PB6_Pos)

#define	PWR_PDCRB_PB6 PWR_PDCRB_PB6_Msk

#define	PWR_PDCRB_PB5_Pos (5U)

#define	PWR_PDCRB_PB5_Msk (0x1UL << PWR_PDCRB_PB5_Pos)

#define	PWR_PDCRB_PB5 PWR_PDCRB_PB5_Msk

#define	PWR_PDCRB_PB3_Pos (3U)

#define	PWR_PDCRB_PB3_Msk (0x1UL << PWR_PDCRB_PB3_Pos)

#define	PWR_PDCRB_PB3 PWR_PDCRB_PB3_Msk

#define	PWR_PDCRB_PB2_Pos (2U)

#define	PWR_PDCRB_PB2_Msk (0x1UL << PWR_PDCRB_PB2_Pos)

#define	PWR_PDCRB_PB2 PWR_PDCRB_PB2_Msk

#define	PWR_PDCRB_PB1_Pos (1U)

#define	PWR_PDCRB_PB1_Msk (0x1UL << PWR_PDCRB_PB1_Pos)

#define	PWR_PDCRB_PB1 PWR_PDCRB_PB1_Msk

#define	PWR_PDCRB_PB0_Pos (0U)

#define	PWR_PDCRB_PB0_Msk (0x1UL << PWR_PDCRB_PB0_Pos)

#define	PWR_PDCRB_PB0 PWR_PDCRB_PB0_Msk

#define	PWR_PUCRC_PC15_Pos (15U)

#define	PWR_PUCRC_PC15_Msk (0x1UL << PWR_PUCRC_PC15_Pos)

#define	PWR_PUCRC_PC15 PWR_PUCRC_PC15_Msk

#define	PWR_PUCRC_PC14_Pos (14U)

#define	PWR_PUCRC_PC14_Msk (0x1UL << PWR_PUCRC_PC14_Pos)

#define	PWR_PUCRC_PC14 PWR_PUCRC_PC14_Msk

#define	PWR_PUCRC_PC13_Pos (13U)

#define	PWR_PUCRC_PC13_Msk (0x1UL << PWR_PUCRC_PC13_Pos)

#define	PWR_PUCRC_PC13 PWR_PUCRC_PC13_Msk

#define	PWR_PUCRC_PC12_Pos (12U)

#define	PWR_PUCRC_PC12_Msk (0x1UL << PWR_PUCRC_PC12_Pos)

#define	PWR_PUCRC_PC12 PWR_PUCRC_PC12_Msk

#define	PWR_PUCRC_PC11_Pos (11U)

#define	PWR_PUCRC_PC11_Msk (0x1UL << PWR_PUCRC_PC11_Pos)

#define	PWR_PUCRC_PC11 PWR_PUCRC_PC11_Msk

#define	PWR_PUCRC_PC10_Pos (10U)

#define	PWR_PUCRC_PC10_Msk (0x1UL << PWR_PUCRC_PC10_Pos)

#define	PWR_PUCRC_PC10 PWR_PUCRC_PC10_Msk

#define	PWR_PUCRC_PC9_Pos (9U)

#define	PWR_PUCRC_PC9_Msk (0x1UL << PWR_PUCRC_PC9_Pos)

#define	PWR_PUCRC_PC9 PWR_PUCRC_PC9_Msk

#define	PWR_PUCRC_PC8_Pos (8U)

#define	PWR_PUCRC_PC8_Msk (0x1UL << PWR_PUCRC_PC8_Pos)

#define	PWR_PUCRC_PC8 PWR_PUCRC_PC8_Msk

#define	PWR_PUCRC_PC7_Pos (7U)

#define	PWR_PUCRC_PC7_Msk (0x1UL << PWR_PUCRC_PC7_Pos)

#define	PWR_PUCRC_PC7 PWR_PUCRC_PC7_Msk

#define	PWR_PUCRC_PC6_Pos (6U)

#define	PWR_PUCRC_PC6_Msk (0x1UL << PWR_PUCRC_PC6_Pos)

#define	PWR_PUCRC_PC6 PWR_PUCRC_PC6_Msk

#define	PWR_PUCRC_PC5_Pos (5U)

#define	PWR_PUCRC_PC5_Msk (0x1UL << PWR_PUCRC_PC5_Pos)

#define	PWR_PUCRC_PC5 PWR_PUCRC_PC5_Msk

#define	PWR_PUCRC_PC4_Pos (4U)

#define	PWR_PUCRC_PC4_Msk (0x1UL << PWR_PUCRC_PC4_Pos)

#define	PWR_PUCRC_PC4 PWR_PUCRC_PC4_Msk

#define	PWR_PUCRC_PC3_Pos (3U)

#define	PWR_PUCRC_PC3_Msk (0x1UL << PWR_PUCRC_PC3_Pos)

#define	PWR_PUCRC_PC3 PWR_PUCRC_PC3_Msk

#define	PWR_PUCRC_PC2_Pos (2U)

#define	PWR_PUCRC_PC2_Msk (0x1UL << PWR_PUCRC_PC2_Pos)

#define	PWR_PUCRC_PC2 PWR_PUCRC_PC2_Msk

#define	PWR_PUCRC_PC1_Pos (1U)

#define	PWR_PUCRC_PC1_Msk (0x1UL << PWR_PUCRC_PC1_Pos)

#define	PWR_PUCRC_PC1 PWR_PUCRC_PC1_Msk

#define	PWR_PUCRC_PC0_Pos (0U)

#define	PWR_PUCRC_PC0_Msk (0x1UL << PWR_PUCRC_PC0_Pos)

#define	PWR_PUCRC_PC0 PWR_PUCRC_PC0_Msk

#define	PWR_PDCRC_PC15_Pos (15U)

#define	PWR_PDCRC_PC15_Msk (0x1UL << PWR_PDCRC_PC15_Pos)

#define	PWR_PDCRC_PC15 PWR_PDCRC_PC15_Msk

#define	PWR_PDCRC_PC14_Pos (14U)

#define	PWR_PDCRC_PC14_Msk (0x1UL << PWR_PDCRC_PC14_Pos)

#define	PWR_PDCRC_PC14 PWR_PDCRC_PC14_Msk

#define	PWR_PDCRC_PC13_Pos (13U)

#define	PWR_PDCRC_PC13_Msk (0x1UL << PWR_PDCRC_PC13_Pos)

#define	PWR_PDCRC_PC13 PWR_PDCRC_PC13_Msk

#define	PWR_PDCRC_PC12_Pos (12U)

#define	PWR_PDCRC_PC12_Msk (0x1UL << PWR_PDCRC_PC12_Pos)

#define	PWR_PDCRC_PC12 PWR_PDCRC_PC12_Msk

#define	PWR_PDCRC_PC11_Pos (11U)

#define	PWR_PDCRC_PC11_Msk (0x1UL << PWR_PDCRC_PC11_Pos)

#define	PWR_PDCRC_PC11 PWR_PDCRC_PC11_Msk

#define	PWR_PDCRC_PC10_Pos (10U)

#define	PWR_PDCRC_PC10_Msk (0x1UL << PWR_PDCRC_PC10_Pos)

#define	PWR_PDCRC_PC10 PWR_PDCRC_PC10_Msk

#define	PWR_PDCRC_PC9_Pos (9U)

#define	PWR_PDCRC_PC9_Msk (0x1UL << PWR_PDCRC_PC9_Pos)

#define	PWR_PDCRC_PC9 PWR_PDCRC_PC9_Msk

#define	PWR_PDCRC_PC8_Pos (8U)

#define	PWR_PDCRC_PC8_Msk (0x1UL << PWR_PDCRC_PC8_Pos)

#define	PWR_PDCRC_PC8 PWR_PDCRC_PC8_Msk

#define	PWR_PDCRC_PC7_Pos (7U)

#define	PWR_PDCRC_PC7_Msk (0x1UL << PWR_PDCRC_PC7_Pos)

#define	PWR_PDCRC_PC7 PWR_PDCRC_PC7_Msk

#define	PWR_PDCRC_PC6_Pos (6U)

#define	PWR_PDCRC_PC6_Msk (0x1UL << PWR_PDCRC_PC6_Pos)

#define	PWR_PDCRC_PC6 PWR_PDCRC_PC6_Msk

#define	PWR_PDCRC_PC5_Pos (5U)

#define	PWR_PDCRC_PC5_Msk (0x1UL << PWR_PDCRC_PC5_Pos)

#define	PWR_PDCRC_PC5 PWR_PDCRC_PC5_Msk

#define	PWR_PDCRC_PC4_Pos (4U)

#define	PWR_PDCRC_PC4_Msk (0x1UL << PWR_PDCRC_PC4_Pos)

#define	PWR_PDCRC_PC4 PWR_PDCRC_PC4_Msk

#define	PWR_PDCRC_PC3_Pos (3U)

#define	PWR_PDCRC_PC3_Msk (0x1UL << PWR_PDCRC_PC3_Pos)

#define	PWR_PDCRC_PC3 PWR_PDCRC_PC3_Msk

#define	PWR_PDCRC_PC2_Pos (2U)

#define	PWR_PDCRC_PC2_Msk (0x1UL << PWR_PDCRC_PC2_Pos)

#define	PWR_PDCRC_PC2 PWR_PDCRC_PC2_Msk

#define	PWR_PDCRC_PC1_Pos (1U)

#define	PWR_PDCRC_PC1_Msk (0x1UL << PWR_PDCRC_PC1_Pos)

#define	PWR_PDCRC_PC1 PWR_PDCRC_PC1_Msk

#define	PWR_PDCRC_PC0_Pos (0U)

#define	PWR_PDCRC_PC0_Msk (0x1UL << PWR_PDCRC_PC0_Pos)

#define	PWR_PDCRC_PC0 PWR_PDCRC_PC0_Msk

#define	PWR_PUCRD_PD15_Pos (15U)

#define	PWR_PUCRD_PD15_Msk (0x1UL << PWR_PUCRD_PD15_Pos)

#define	PWR_PUCRD_PD15 PWR_PUCRD_PD15_Msk

#define	PWR_PUCRD_PD14_Pos (14U)

#define	PWR_PUCRD_PD14_Msk (0x1UL << PWR_PUCRD_PD14_Pos)

#define	PWR_PUCRD_PD14 PWR_PUCRD_PD14_Msk

#define	PWR_PUCRD_PD13_Pos (13U)

#define	PWR_PUCRD_PD13_Msk (0x1UL << PWR_PUCRD_PD13_Pos)

#define	PWR_PUCRD_PD13 PWR_PUCRD_PD13_Msk

#define	PWR_PUCRD_PD12_Pos (12U)

#define	PWR_PUCRD_PD12_Msk (0x1UL << PWR_PUCRD_PD12_Pos)

#define	PWR_PUCRD_PD12 PWR_PUCRD_PD12_Msk

#define	PWR_PUCRD_PD11_Pos (11U)

#define	PWR_PUCRD_PD11_Msk (0x1UL << PWR_PUCRD_PD11_Pos)

#define	PWR_PUCRD_PD11 PWR_PUCRD_PD11_Msk

#define	PWR_PUCRD_PD10_Pos (10U)

#define	PWR_PUCRD_PD10_Msk (0x1UL << PWR_PUCRD_PD10_Pos)

#define	PWR_PUCRD_PD10 PWR_PUCRD_PD10_Msk

#define	PWR_PUCRD_PD9_Pos (9U)

#define	PWR_PUCRD_PD9_Msk (0x1UL << PWR_PUCRD_PD9_Pos)

#define	PWR_PUCRD_PD9 PWR_PUCRD_PD9_Msk

#define	PWR_PUCRD_PD8_Pos (8U)

#define	PWR_PUCRD_PD8_Msk (0x1UL << PWR_PUCRD_PD8_Pos)

#define	PWR_PUCRD_PD8 PWR_PUCRD_PD8_Msk

#define	PWR_PUCRD_PD7_Pos (7U)

#define	PWR_PUCRD_PD7_Msk (0x1UL << PWR_PUCRD_PD7_Pos)

#define	PWR_PUCRD_PD7 PWR_PUCRD_PD7_Msk

#define	PWR_PUCRD_PD6_Pos (6U)

#define	PWR_PUCRD_PD6_Msk (0x1UL << PWR_PUCRD_PD6_Pos)

#define	PWR_PUCRD_PD6 PWR_PUCRD_PD6_Msk

#define	PWR_PUCRD_PD5_Pos (5U)

#define	PWR_PUCRD_PD5_Msk (0x1UL << PWR_PUCRD_PD5_Pos)

#define	PWR_PUCRD_PD5 PWR_PUCRD_PD5_Msk

#define	PWR_PUCRD_PD4_Pos (4U)

#define	PWR_PUCRD_PD4_Msk (0x1UL << PWR_PUCRD_PD4_Pos)

#define	PWR_PUCRD_PD4 PWR_PUCRD_PD4_Msk

#define	PWR_PUCRD_PD3_Pos (3U)

#define	PWR_PUCRD_PD3_Msk (0x1UL << PWR_PUCRD_PD3_Pos)

#define	PWR_PUCRD_PD3 PWR_PUCRD_PD3_Msk

#define	PWR_PUCRD_PD2_Pos (2U)

#define	PWR_PUCRD_PD2_Msk (0x1UL << PWR_PUCRD_PD2_Pos)

#define	PWR_PUCRD_PD2 PWR_PUCRD_PD2_Msk

#define	PWR_PUCRD_PD1_Pos (1U)

#define	PWR_PUCRD_PD1_Msk (0x1UL << PWR_PUCRD_PD1_Pos)

#define	PWR_PUCRD_PD1 PWR_PUCRD_PD1_Msk

#define	PWR_PUCRD_PD0_Pos (0U)

#define	PWR_PUCRD_PD0_Msk (0x1UL << PWR_PUCRD_PD0_Pos)

#define	PWR_PUCRD_PD0 PWR_PUCRD_PD0_Msk

#define	PWR_PDCRD_PD15_Pos (15U)

#define	PWR_PDCRD_PD15_Msk (0x1UL << PWR_PDCRD_PD15_Pos)

#define	PWR_PDCRD_PD15 PWR_PDCRD_PD15_Msk

#define	PWR_PDCRD_PD14_Pos (14U)

#define	PWR_PDCRD_PD14_Msk (0x1UL << PWR_PDCRD_PD14_Pos)

#define	PWR_PDCRD_PD14 PWR_PDCRD_PD14_Msk

#define	PWR_PDCRD_PD13_Pos (13U)

#define	PWR_PDCRD_PD13_Msk (0x1UL << PWR_PDCRD_PD13_Pos)

#define	PWR_PDCRD_PD13 PWR_PDCRD_PD13_Msk

#define	PWR_PDCRD_PD12_Pos (12U)

#define	PWR_PDCRD_PD12_Msk (0x1UL << PWR_PDCRD_PD12_Pos)

#define	PWR_PDCRD_PD12 PWR_PDCRD_PD12_Msk

#define	PWR_PDCRD_PD11_Pos (11U)

#define	PWR_PDCRD_PD11_Msk (0x1UL << PWR_PDCRD_PD11_Pos)

#define	PWR_PDCRD_PD11 PWR_PDCRD_PD11_Msk

#define	PWR_PDCRD_PD10_Pos (10U)

#define	PWR_PDCRD_PD10_Msk (0x1UL << PWR_PDCRD_PD10_Pos)

#define	PWR_PDCRD_PD10 PWR_PDCRD_PD10_Msk

#define	PWR_PDCRD_PD9_Pos (9U)

#define	PWR_PDCRD_PD9_Msk (0x1UL << PWR_PDCRD_PD9_Pos)

#define	PWR_PDCRD_PD9 PWR_PDCRD_PD9_Msk

#define	PWR_PDCRD_PD8_Pos (8U)

#define	PWR_PDCRD_PD8_Msk (0x1UL << PWR_PDCRD_PD8_Pos)

#define	PWR_PDCRD_PD8 PWR_PDCRD_PD8_Msk

#define	PWR_PDCRD_PD7_Pos (7U)

#define	PWR_PDCRD_PD7_Msk (0x1UL << PWR_PDCRD_PD7_Pos)

#define	PWR_PDCRD_PD7 PWR_PDCRD_PD7_Msk

#define	PWR_PDCRD_PD6_Pos (6U)

#define	PWR_PDCRD_PD6_Msk (0x1UL << PWR_PDCRD_PD6_Pos)

#define	PWR_PDCRD_PD6 PWR_PDCRD_PD6_Msk

#define	PWR_PDCRD_PD5_Pos (5U)

#define	PWR_PDCRD_PD5_Msk (0x1UL << PWR_PDCRD_PD5_Pos)

#define	PWR_PDCRD_PD5 PWR_PDCRD_PD5_Msk

#define	PWR_PDCRD_PD4_Pos (4U)

#define	PWR_PDCRD_PD4_Msk (0x1UL << PWR_PDCRD_PD4_Pos)

#define	PWR_PDCRD_PD4 PWR_PDCRD_PD4_Msk

#define	PWR_PDCRD_PD3_Pos (3U)

#define	PWR_PDCRD_PD3_Msk (0x1UL << PWR_PDCRD_PD3_Pos)

#define	PWR_PDCRD_PD3 PWR_PDCRD_PD3_Msk

#define	PWR_PDCRD_PD2_Pos (2U)

#define	PWR_PDCRD_PD2_Msk (0x1UL << PWR_PDCRD_PD2_Pos)

#define	PWR_PDCRD_PD2 PWR_PDCRD_PD2_Msk

#define	PWR_PDCRD_PD1_Pos (1U)

#define	PWR_PDCRD_PD1_Msk (0x1UL << PWR_PDCRD_PD1_Pos)

#define	PWR_PDCRD_PD1 PWR_PDCRD_PD1_Msk

#define	PWR_PDCRD_PD0_Pos (0U)

#define	PWR_PDCRD_PD0_Msk (0x1UL << PWR_PDCRD_PD0_Pos)

#define	PWR_PDCRD_PD0 PWR_PDCRD_PD0_Msk

#define	PWR_PUCRE_PE15_Pos (15U)

#define	PWR_PUCRE_PE15_Msk (0x1UL << PWR_PUCRE_PE15_Pos)

#define	PWR_PUCRE_PE15 PWR_PUCRE_PE15_Msk

#define	PWR_PUCRE_PE14_Pos (14U)

#define	PWR_PUCRE_PE14_Msk (0x1UL << PWR_PUCRE_PE14_Pos)

#define	PWR_PUCRE_PE14 PWR_PUCRE_PE14_Msk

#define	PWR_PUCRE_PE13_Pos (13U)

#define	PWR_PUCRE_PE13_Msk (0x1UL << PWR_PUCRE_PE13_Pos)

#define	PWR_PUCRE_PE13 PWR_PUCRE_PE13_Msk

#define	PWR_PUCRE_PE12_Pos (12U)

#define	PWR_PUCRE_PE12_Msk (0x1UL << PWR_PUCRE_PE12_Pos)

#define	PWR_PUCRE_PE12 PWR_PUCRE_PE12_Msk

#define	PWR_PUCRE_PE11_Pos (11U)

#define	PWR_PUCRE_PE11_Msk (0x1UL << PWR_PUCRE_PE11_Pos)

#define	PWR_PUCRE_PE11 PWR_PUCRE_PE11_Msk

#define	PWR_PUCRE_PE10_Pos (10U)

#define	PWR_PUCRE_PE10_Msk (0x1UL << PWR_PUCRE_PE10_Pos)

#define	PWR_PUCRE_PE10 PWR_PUCRE_PE10_Msk

#define	PWR_PUCRE_PE9_Pos (9U)

#define	PWR_PUCRE_PE9_Msk (0x1UL << PWR_PUCRE_PE9_Pos)

#define	PWR_PUCRE_PE9 PWR_PUCRE_PE9_Msk

#define	PWR_PUCRE_PE8_Pos (8U)

#define	PWR_PUCRE_PE8_Msk (0x1UL << PWR_PUCRE_PE8_Pos)

#define	PWR_PUCRE_PE8 PWR_PUCRE_PE8_Msk

#define	PWR_PUCRE_PE7_Pos (7U)

#define	PWR_PUCRE_PE7_Msk (0x1UL << PWR_PUCRE_PE7_Pos)

#define	PWR_PUCRE_PE7 PWR_PUCRE_PE7_Msk

#define	PWR_PUCRE_PE6_Pos (6U)

#define	PWR_PUCRE_PE6_Msk (0x1UL << PWR_PUCRE_PE6_Pos)

#define	PWR_PUCRE_PE6 PWR_PUCRE_PE6_Msk

#define	PWR_PUCRE_PE5_Pos (5U)

#define	PWR_PUCRE_PE5_Msk (0x1UL << PWR_PUCRE_PE5_Pos)

#define	PWR_PUCRE_PE5 PWR_PUCRE_PE5_Msk

#define	PWR_PUCRE_PE4_Pos (4U)

#define	PWR_PUCRE_PE4_Msk (0x1UL << PWR_PUCRE_PE4_Pos)

#define	PWR_PUCRE_PE4 PWR_PUCRE_PE4_Msk

#define	PWR_PUCRE_PE3_Pos (3U)

#define	PWR_PUCRE_PE3_Msk (0x1UL << PWR_PUCRE_PE3_Pos)

#define	PWR_PUCRE_PE3 PWR_PUCRE_PE3_Msk

#define	PWR_PUCRE_PE2_Pos (2U)

#define	PWR_PUCRE_PE2_Msk (0x1UL << PWR_PUCRE_PE2_Pos)

#define	PWR_PUCRE_PE2 PWR_PUCRE_PE2_Msk

#define	PWR_PUCRE_PE1_Pos (1U)

#define	PWR_PUCRE_PE1_Msk (0x1UL << PWR_PUCRE_PE1_Pos)

#define	PWR_PUCRE_PE1 PWR_PUCRE_PE1_Msk

#define	PWR_PUCRE_PE0_Pos (0U)

#define	PWR_PUCRE_PE0_Msk (0x1UL << PWR_PUCRE_PE0_Pos)

#define	PWR_PUCRE_PE0 PWR_PUCRE_PE0_Msk

#define	PWR_PDCRE_PE15_Pos (15U)

#define	PWR_PDCRE_PE15_Msk (0x1UL << PWR_PDCRE_PE15_Pos)

#define	PWR_PDCRE_PE15 PWR_PDCRE_PE15_Msk

#define	PWR_PDCRE_PE14_Pos (14U)

#define	PWR_PDCRE_PE14_Msk (0x1UL << PWR_PDCRE_PE14_Pos)

#define	PWR_PDCRE_PE14 PWR_PDCRE_PE14_Msk

#define	PWR_PDCRE_PE13_Pos (13U)

#define	PWR_PDCRE_PE13_Msk (0x1UL << PWR_PDCRE_PE13_Pos)

#define	PWR_PDCRE_PE13 PWR_PDCRE_PE13_Msk

#define	PWR_PDCRE_PE12_Pos (12U)

#define	PWR_PDCRE_PE12_Msk (0x1UL << PWR_PDCRE_PE12_Pos)

#define	PWR_PDCRE_PE12 PWR_PDCRE_PE12_Msk

#define	PWR_PDCRE_PE11_Pos (11U)

#define	PWR_PDCRE_PE11_Msk (0x1UL << PWR_PDCRE_PE11_Pos)

#define	PWR_PDCRE_PE11 PWR_PDCRE_PE11_Msk

#define	PWR_PDCRE_PE10_Pos (10U)

#define	PWR_PDCRE_PE10_Msk (0x1UL << PWR_PDCRE_PE10_Pos)

#define	PWR_PDCRE_PE10 PWR_PDCRE_PE10_Msk

#define	PWR_PDCRE_PE9_Pos (9U)

#define	PWR_PDCRE_PE9_Msk (0x1UL << PWR_PDCRE_PE9_Pos)

#define	PWR_PDCRE_PE9 PWR_PDCRE_PE9_Msk

#define	PWR_PDCRE_PE8_Pos (8U)

#define	PWR_PDCRE_PE8_Msk (0x1UL << PWR_PDCRE_PE8_Pos)

#define	PWR_PDCRE_PE8 PWR_PDCRE_PE8_Msk

#define	PWR_PDCRE_PE7_Pos (7U)

#define	PWR_PDCRE_PE7_Msk (0x1UL << PWR_PDCRE_PE7_Pos)

#define	PWR_PDCRE_PE7 PWR_PDCRE_PE7_Msk

#define	PWR_PDCRE_PE6_Pos (6U)

#define	PWR_PDCRE_PE6_Msk (0x1UL << PWR_PDCRE_PE6_Pos)

#define	PWR_PDCRE_PE6 PWR_PDCRE_PE6_Msk

#define	PWR_PDCRE_PE5_Pos (5U)

#define	PWR_PDCRE_PE5_Msk (0x1UL << PWR_PDCRE_PE5_Pos)

#define	PWR_PDCRE_PE5 PWR_PDCRE_PE5_Msk

#define	PWR_PDCRE_PE4_Pos (4U)

#define	PWR_PDCRE_PE4_Msk (0x1UL << PWR_PDCRE_PE4_Pos)

#define	PWR_PDCRE_PE4 PWR_PDCRE_PE4_Msk

#define	PWR_PDCRE_PE3_Pos (3U)

#define	PWR_PDCRE_PE3_Msk (0x1UL << PWR_PDCRE_PE3_Pos)

#define	PWR_PDCRE_PE3 PWR_PDCRE_PE3_Msk

#define	PWR_PDCRE_PE2_Pos (2U)

#define	PWR_PDCRE_PE2_Msk (0x1UL << PWR_PDCRE_PE2_Pos)

#define	PWR_PDCRE_PE2 PWR_PDCRE_PE2_Msk

#define	PWR_PDCRE_PE1_Pos (1U)

#define	PWR_PDCRE_PE1_Msk (0x1UL << PWR_PDCRE_PE1_Pos)

#define	PWR_PDCRE_PE1 PWR_PDCRE_PE1_Msk

#define	PWR_PDCRE_PE0_Pos (0U)

#define	PWR_PDCRE_PE0_Msk (0x1UL << PWR_PDCRE_PE0_Pos)

#define	PWR_PDCRE_PE0 PWR_PDCRE_PE0_Msk

#define	PWR_PUCRF_PF15_Pos (15U)

#define	PWR_PUCRF_PF15_Msk (0x1UL << PWR_PUCRF_PF15_Pos)

#define	PWR_PUCRF_PF15 PWR_PUCRF_PF15_Msk

#define	PWR_PUCRF_PF14_Pos (14U)

#define	PWR_PUCRF_PF14_Msk (0x1UL << PWR_PUCRF_PF14_Pos)

#define	PWR_PUCRF_PF14 PWR_PUCRF_PF14_Msk

#define	PWR_PUCRF_PF13_Pos (13U)

#define	PWR_PUCRF_PF13_Msk (0x1UL << PWR_PUCRF_PF13_Pos)

#define	PWR_PUCRF_PF13 PWR_PUCRF_PF13_Msk

#define	PWR_PUCRF_PF12_Pos (12U)

#define	PWR_PUCRF_PF12_Msk (0x1UL << PWR_PUCRF_PF12_Pos)

#define	PWR_PUCRF_PF12 PWR_PUCRF_PF12_Msk

#define	PWR_PUCRF_PF11_Pos (11U)

#define	PWR_PUCRF_PF11_Msk (0x1UL << PWR_PUCRF_PF11_Pos)

#define	PWR_PUCRF_PF11 PWR_PUCRF_PF11_Msk

#define	PWR_PUCRF_PF10_Pos (10U)

#define	PWR_PUCRF_PF10_Msk (0x1UL << PWR_PUCRF_PF10_Pos)

#define	PWR_PUCRF_PF10 PWR_PUCRF_PF10_Msk

#define	PWR_PUCRF_PF9_Pos (9U)

#define	PWR_PUCRF_PF9_Msk (0x1UL << PWR_PUCRF_PF9_Pos)

#define	PWR_PUCRF_PF9 PWR_PUCRF_PF9_Msk

#define	PWR_PUCRF_PF8_Pos (8U)

#define	PWR_PUCRF_PF8_Msk (0x1UL << PWR_PUCRF_PF8_Pos)

#define	PWR_PUCRF_PF8 PWR_PUCRF_PF8_Msk

#define	PWR_PUCRF_PF7_Pos (7U)

#define	PWR_PUCRF_PF7_Msk (0x1UL << PWR_PUCRF_PF7_Pos)

#define	PWR_PUCRF_PF7 PWR_PUCRF_PF7_Msk

#define	PWR_PUCRF_PF6_Pos (6U)

#define	PWR_PUCRF_PF6_Msk (0x1UL << PWR_PUCRF_PF6_Pos)

#define	PWR_PUCRF_PF6 PWR_PUCRF_PF6_Msk

#define	PWR_PUCRF_PF5_Pos (5U)

#define	PWR_PUCRF_PF5_Msk (0x1UL << PWR_PUCRF_PF5_Pos)

#define	PWR_PUCRF_PF5 PWR_PUCRF_PF5_Msk

#define	PWR_PUCRF_PF4_Pos (4U)

#define	PWR_PUCRF_PF4_Msk (0x1UL << PWR_PUCRF_PF4_Pos)

#define	PWR_PUCRF_PF4 PWR_PUCRF_PF4_Msk

#define	PWR_PUCRF_PF3_Pos (3U)

#define	PWR_PUCRF_PF3_Msk (0x1UL << PWR_PUCRF_PF3_Pos)

#define	PWR_PUCRF_PF3 PWR_PUCRF_PF3_Msk

#define	PWR_PUCRF_PF2_Pos (2U)

#define	PWR_PUCRF_PF2_Msk (0x1UL << PWR_PUCRF_PF2_Pos)

#define	PWR_PUCRF_PF2 PWR_PUCRF_PF2_Msk

#define	PWR_PUCRF_PF1_Pos (1U)

#define	PWR_PUCRF_PF1_Msk (0x1UL << PWR_PUCRF_PF1_Pos)

#define	PWR_PUCRF_PF1 PWR_PUCRF_PF1_Msk

#define	PWR_PUCRF_PF0_Pos (0U)

#define	PWR_PUCRF_PF0_Msk (0x1UL << PWR_PUCRF_PF0_Pos)

#define	PWR_PUCRF_PF0 PWR_PUCRF_PF0_Msk

#define	PWR_PDCRF_PF10_Pos (10U)

#define	PWR_PDCRF_PF10_Msk (0x1UL << PWR_PDCRF_PF10_Pos)

#define	PWR_PDCRF_PF10 PWR_PDCRF_PF10_Msk

#define	PWR_PDCRF_PF9_Pos (9U)

#define	PWR_PDCRF_PF9_Msk (0x1UL << PWR_PDCRF_PF9_Pos)

#define	PWR_PDCRF_PF9 PWR_PDCRF_PF9_Msk

#define	PWR_PDCRF_PF2_Pos (2U)

#define	PWR_PDCRF_PF2_Msk (0x1UL << PWR_PDCRF_PF2_Pos)

#define	PWR_PDCRF_PF2 PWR_PDCRF_PF2_Msk

#define	PWR_PDCRF_PF1_Pos (1U)

#define	PWR_PDCRF_PF1_Msk (0x1UL << PWR_PDCRF_PF1_Pos)

#define	PWR_PDCRF_PF1 PWR_PDCRF_PF1_Msk

#define	PWR_PDCRF_PF0_Pos (0U)

#define	PWR_PDCRF_PF0_Msk (0x1UL << PWR_PDCRF_PF0_Pos)

#define	PWR_PDCRF_PF0 PWR_PDCRF_PF0_Msk

#define	PWR_PUCRG_PG10_Pos (10U)

#define	PWR_PUCRG_PG10_Msk (0x1UL << PWR_PUCRG_PG10_Pos)

#define	PWR_PUCRG_PG10 PWR_PUCRG_PG10_Msk

#define	PWR_PDCRG_PG10_Pos (10U)

#define	PWR_PDCRG_PG10_Msk (0x1UL << PWR_PDCRG_PG10_Pos)

#define	PWR_PDCRG_PG10 PWR_PDCRG_PG10_Msk

#define	PWR_PDCRG_PG9_Pos (9U)

#define	PWR_PDCRG_PG9_Msk (0x1UL << PWR_PDCRG_PG9_Pos)

#define	PWR_PDCRG_PG9 PWR_PDCRG_PG9_Msk

#define	PWR_PDCRG_PG8_Pos (8U)

#define	PWR_PDCRG_PG8_Msk (0x1UL << PWR_PDCRG_PG8_Pos)

#define	PWR_PDCRG_PG8 PWR_PDCRG_PG8_Msk

#define	PWR_PDCRG_PG7_Pos (7U)

#define	PWR_PDCRG_PG7_Msk (0x1UL << PWR_PDCRG_PG7_Pos)

#define	PWR_PDCRG_PG7 PWR_PDCRG_PG7_Msk

#define	PWR_PDCRG_PG6_Pos (6U)

#define	PWR_PDCRG_PG6_Msk (0x1UL << PWR_PDCRG_PG6_Pos)

#define	PWR_PDCRG_PG6 PWR_PDCRG_PG6_Msk

#define	PWR_PDCRG_PG5_Pos (5U)

#define	PWR_PDCRG_PG5_Msk (0x1UL << PWR_PDCRG_PG5_Pos)

#define	PWR_PDCRG_PG5 PWR_PDCRG_PG5_Msk

#define	PWR_PDCRG_PG4_Pos (4U)

#define	PWR_PDCRG_PG4_Msk (0x1UL << PWR_PDCRG_PG4_Pos)

#define	PWR_PDCRG_PG4 PWR_PDCRG_PG4_Msk

#define	PWR_PDCRG_PG3_Pos (3U)

#define	PWR_PDCRG_PG3_Msk (0x1UL << PWR_PDCRG_PG3_Pos)

#define	PWR_PDCRG_PG3 PWR_PDCRG_PG3_Msk

#define	PWR_PDCRG_PG2_Pos (2U)

#define	PWR_PDCRG_PG2_Msk (0x1UL << PWR_PDCRG_PG2_Pos)

#define	PWR_PDCRG_PG2 PWR_PDCRG_PG2_Msk

#define	PWR_PDCRG_PG1_Pos (1U)

#define	PWR_PDCRG_PG1_Msk (0x1UL << PWR_PDCRG_PG1_Pos)

#define	PWR_PDCRG_PG1 PWR_PDCRG_PG1_Msk

#define	PWR_PDCRG_PG0_Pos (0U)

#define	PWR_PDCRG_PG0_Msk (0x1UL << PWR_PDCRG_PG0_Pos)

#define	PWR_PDCRG_PG0 PWR_PDCRG_PG0_Msk

#define	PWR_CR5_R1MODE_Pos (8U)

#define	PWR_CR5_R1MODE_Msk (0x1U << PWR_CR5_R1MODE_Pos)

#define	PWR_CR5_R1MODE PWR_CR5_R1MODE_Msk

#define	RCC_HSI48_SUPPORT

#define	RCC_PLLP_DIV_2_31_SUPPORT

#define	RCC_CR_HSION_Pos (8U)

#define	RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos)

#define	RCC_CR_HSION RCC_CR_HSION_Msk

#define	RCC_CR_HSIKERON_Pos (9U)

#define	RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos)

#define	RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk

#define	RCC_CR_HSIRDY_Pos (10U)

#define	RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos)

#define	RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk

#define	RCC_CR_HSEON_Pos (16U)

#define	RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos)

#define	RCC_CR_HSEON RCC_CR_HSEON_Msk

#define	RCC_CR_HSERDY_Pos (17U)

#define	RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos)

#define	RCC_CR_HSERDY RCC_CR_HSERDY_Msk

#define	RCC_CR_HSEBYP_Pos (18U)

#define	RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos)

#define	RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk

#define	RCC_CR_CSSON_Pos (19U)

#define	RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos)

#define	RCC_CR_CSSON RCC_CR_CSSON_Msk

#define	RCC_CR_PLLON_Pos (24U)

#define	RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos)

#define	RCC_CR_PLLON RCC_CR_PLLON_Msk

#define	RCC_CR_PLLRDY_Pos (25U)

#define	RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos)

#define	RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk

#define	RCC_ICSCR_HSICAL_Pos (16U)

#define	RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos)

#define	RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk

#define	RCC_ICSCR_HSICAL_0 (0x01UL << RCC_ICSCR_HSICAL_Pos)

#define	RCC_ICSCR_HSICAL_1 (0x02UL << RCC_ICSCR_HSICAL_Pos)

#define	RCC_ICSCR_HSICAL_2 (0x04UL << RCC_ICSCR_HSICAL_Pos)

#define	RCC_ICSCR_HSICAL_3 (0x08UL << RCC_ICSCR_HSICAL_Pos)

#define	RCC_ICSCR_HSICAL_4 (0x10UL << RCC_ICSCR_HSICAL_Pos)

#define	RCC_ICSCR_HSICAL_5 (0x20UL << RCC_ICSCR_HSICAL_Pos)

#define	RCC_ICSCR_HSICAL_6 (0x40UL << RCC_ICSCR_HSICAL_Pos)

#define	RCC_ICSCR_HSICAL_7 (0x80UL << RCC_ICSCR_HSICAL_Pos)

#define	RCC_ICSCR_HSITRIM_Pos (24U)

#define	RCC_ICSCR_HSITRIM_Msk (0x7FUL << RCC_ICSCR_HSITRIM_Pos)

#define	RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk

#define	RCC_ICSCR_HSITRIM_0 (0x01UL << RCC_ICSCR_HSITRIM_Pos)

#define	RCC_ICSCR_HSITRIM_1 (0x02UL << RCC_ICSCR_HSITRIM_Pos)

#define	RCC_ICSCR_HSITRIM_2 (0x04UL << RCC_ICSCR_HSITRIM_Pos)

#define	RCC_ICSCR_HSITRIM_3 (0x08UL << RCC_ICSCR_HSITRIM_Pos)

#define	RCC_ICSCR_HSITRIM_4 (0x10UL << RCC_ICSCR_HSITRIM_Pos)

#define	RCC_ICSCR_HSITRIM_5 (0x20UL << RCC_ICSCR_HSITRIM_Pos)

#define	RCC_ICSCR_HSITRIM_6 (0x40UL << RCC_ICSCR_HSITRIM_Pos)

#define	RCC_CFGR_SW_Pos (0U)

#define	RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos)

#define	RCC_CFGR_SW RCC_CFGR_SW_Msk

#define	RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos)

#define	RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos)

#define	RCC_CFGR_SW_HSI (0x00000001U)

#define	RCC_CFGR_SW_HSE (0x00000002U)

#define	RCC_CFGR_SW_PLL (0x00000003U)

#define	RCC_CFGR_SWS_Pos (2U)

#define	RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos)

#define	RCC_CFGR_SWS RCC_CFGR_SWS_Msk

#define	RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos)

#define	RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos)

#define	RCC_CFGR_SWS_HSI (0x00000004U)

#define	RCC_CFGR_SWS_HSE (0x00000008U)

#define	RCC_CFGR_SWS_PLL (0x0000000CU)

#define	RCC_CFGR_HPRE_Pos (4U)

#define	RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos)

#define	RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk

#define	RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos)

#define	RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos)

#define	RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos)

#define	RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos)

#define	RCC_CFGR_HPRE_DIV1 (0x00000000U)

#define	RCC_CFGR_HPRE_DIV2 (0x00000080U)

#define	RCC_CFGR_HPRE_DIV4 (0x00000090U)

#define	RCC_CFGR_HPRE_DIV8 (0x000000A0U)

#define	RCC_CFGR_HPRE_DIV16 (0x000000B0U)

#define	RCC_CFGR_HPRE_DIV64 (0x000000C0U)

#define	RCC_CFGR_HPRE_DIV128 (0x000000D0U)

#define	RCC_CFGR_HPRE_DIV256 (0x000000E0U)

#define	RCC_CFGR_HPRE_DIV512 (0x000000F0U)

#define	RCC_CFGR_PPRE1_Pos (8U)

#define	RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos)

#define	RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk

#define	RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos)

#define	RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos)

#define	RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos)

#define	RCC_CFGR_PPRE1_DIV1 (0x00000000U)

#define	RCC_CFGR_PPRE1_DIV2 (0x00000400U)

#define	RCC_CFGR_PPRE1_DIV4 (0x00000500U)

#define	RCC_CFGR_PPRE1_DIV8 (0x00000600U)

#define	RCC_CFGR_PPRE1_DIV16 (0x00000700U)

#define	RCC_CFGR_PPRE2_Pos (11U)

#define	RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos)

#define	RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk

#define	RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos)

#define	RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos)

#define	RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos)

#define	RCC_CFGR_PPRE2_DIV1 (0x00000000U)

#define	RCC_CFGR_PPRE2_DIV2 (0x00002000U)

#define	RCC_CFGR_PPRE2_DIV4 (0x00002800U)

#define	RCC_CFGR_PPRE2_DIV8 (0x00003000U)

#define	RCC_CFGR_PPRE2_DIV16 (0x00003800U)

#define	RCC_CFGR_MCOSEL_Pos (24U)

#define	RCC_CFGR_MCOSEL_Msk (0xFUL << RCC_CFGR_MCOSEL_Pos)

#define	RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk

#define	RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos)

#define	RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos)

#define	RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos)

#define	RCC_CFGR_MCOSEL_3 (0x8UL << RCC_CFGR_MCOSEL_Pos)

#define	RCC_CFGR_MCOPRE_Pos (28U)

#define	RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos)

#define	RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk

#define	RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos)

#define	RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos)

#define	RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos)

#define	RCC_CFGR_MCOPRE_DIV1 (0x00000000U)

#define	RCC_CFGR_MCOPRE_DIV2 (0x10000000U)

#define	RCC_CFGR_MCOPRE_DIV4 (0x20000000U)

#define	RCC_CFGR_MCOPRE_DIV8 (0x30000000U)

#define	RCC_CFGR_MCOPRE_DIV16 (0x40000000U)

#define	RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE

#define	RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1

#define	RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2

#define	RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4

#define	RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8

#define	RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16

#define	RCC_PLLCFGR_PLLSRC_Pos (0U)

#define	RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos)

#define	RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk

#define	RCC_PLLCFGR_PLLSRC_0 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)

#define	RCC_PLLCFGR_PLLSRC_1 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos)

#define	RCC_PLLCFGR_PLLSRC_HSI_Pos (1U)

#define	RCC_PLLCFGR_PLLSRC_HSI_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSI_Pos)

#define	RCC_PLLCFGR_PLLSRC_HSI RCC_PLLCFGR_PLLSRC_HSI_Msk

#define	RCC_PLLCFGR_PLLSRC_HSE_Pos (0U)

#define	RCC_PLLCFGR_PLLSRC_HSE_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_HSE_Pos)

#define	RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk

#define	RCC_PLLCFGR_PLLM_Pos (4U)

#define	RCC_PLLCFGR_PLLM_Msk (0xFUL << RCC_PLLCFGR_PLLM_Pos)

#define	RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk

#define	RCC_PLLCFGR_PLLM_0 (0x1UL << RCC_PLLCFGR_PLLM_Pos)

#define	RCC_PLLCFGR_PLLM_1 (0x2UL << RCC_PLLCFGR_PLLM_Pos)

#define	RCC_PLLCFGR_PLLM_2 (0x4UL << RCC_PLLCFGR_PLLM_Pos)

#define	RCC_PLLCFGR_PLLM_3 (0x8UL << RCC_PLLCFGR_PLLM_Pos)

#define	RCC_PLLCFGR_PLLN_Pos (8U)

#define	RCC_PLLCFGR_PLLN_Msk (0x7FUL << RCC_PLLCFGR_PLLN_Pos)

#define	RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk

#define	RCC_PLLCFGR_PLLN_0 (0x01UL << RCC_PLLCFGR_PLLN_Pos)

#define	RCC_PLLCFGR_PLLN_1 (0x02UL << RCC_PLLCFGR_PLLN_Pos)

#define	RCC_PLLCFGR_PLLN_2 (0x04UL << RCC_PLLCFGR_PLLN_Pos)

#define	RCC_PLLCFGR_PLLN_3 (0x08UL << RCC_PLLCFGR_PLLN_Pos)

#define	RCC_PLLCFGR_PLLN_4 (0x10UL << RCC_PLLCFGR_PLLN_Pos)

#define	RCC_PLLCFGR_PLLN_5 (0x20UL << RCC_PLLCFGR_PLLN_Pos)

#define	RCC_PLLCFGR_PLLN_6 (0x40UL << RCC_PLLCFGR_PLLN_Pos)

#define	RCC_PLLCFGR_PLLPEN_Pos (16U)

#define	RCC_PLLCFGR_PLLPEN_Msk (0x1UL << RCC_PLLCFGR_PLLPEN_Pos)

#define	RCC_PLLCFGR_PLLPEN RCC_PLLCFGR_PLLPEN_Msk

#define	RCC_PLLCFGR_PLLP_Pos (17U)

#define	RCC_PLLCFGR_PLLP_Msk (0x1UL << RCC_PLLCFGR_PLLP_Pos)

#define	RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk

#define	RCC_PLLCFGR_PLLQEN_Pos (20U)

#define	RCC_PLLCFGR_PLLQEN_Msk (0x1UL << RCC_PLLCFGR_PLLQEN_Pos)

#define	RCC_PLLCFGR_PLLQEN RCC_PLLCFGR_PLLQEN_Msk

#define	RCC_PLLCFGR_PLLQ_Pos (21U)

#define	RCC_PLLCFGR_PLLQ_Msk (0x3UL << RCC_PLLCFGR_PLLQ_Pos)

#define	RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk

#define	RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos)

#define	RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos)

#define	RCC_PLLCFGR_PLLREN_Pos (24U)

#define	RCC_PLLCFGR_PLLREN_Msk (0x1UL << RCC_PLLCFGR_PLLREN_Pos)

#define	RCC_PLLCFGR_PLLREN RCC_PLLCFGR_PLLREN_Msk

#define	RCC_PLLCFGR_PLLR_Pos (25U)

#define	RCC_PLLCFGR_PLLR_Msk (0x3UL << RCC_PLLCFGR_PLLR_Pos)

#define	RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk

#define	RCC_PLLCFGR_PLLR_0 (0x1UL << RCC_PLLCFGR_PLLR_Pos)

#define	RCC_PLLCFGR_PLLR_1 (0x2UL << RCC_PLLCFGR_PLLR_Pos)

#define	RCC_PLLCFGR_PLLPDIV_Pos (27U)

#define	RCC_PLLCFGR_PLLPDIV_Msk (0x1FUL << RCC_PLLCFGR_PLLPDIV_Pos)

#define	RCC_PLLCFGR_PLLPDIV RCC_PLLCFGR_PLLPDIV_Msk

#define	RCC_PLLCFGR_PLLPDIV_0 (0x01UL << RCC_PLLCFGR_PLLPDIV_Pos)

#define	RCC_PLLCFGR_PLLPDIV_1 (0x02UL << RCC_PLLCFGR_PLLPDIV_Pos)

#define	RCC_PLLCFGR_PLLPDIV_2 (0x04UL << RCC_PLLCFGR_PLLPDIV_Pos)

#define	RCC_PLLCFGR_PLLPDIV_3 (0x08UL << RCC_PLLCFGR_PLLPDIV_Pos)

#define	RCC_PLLCFGR_PLLPDIV_4 (0x10UL << RCC_PLLCFGR_PLLPDIV_Pos)

#define	RCC_CIER_LSIRDYIE_Pos (0U)

#define	RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos)

#define	RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk

#define	RCC_CIER_LSERDYIE_Pos (1U)

#define	RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos)

#define	RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk

#define	RCC_CIER_HSIRDYIE_Pos (3U)

#define	RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos)

#define	RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk

#define	RCC_CIER_HSERDYIE_Pos (4U)

#define	RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos)

#define	RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk

#define	RCC_CIER_PLLRDYIE_Pos (5U)

#define	RCC_CIER_PLLRDYIE_Msk (0x1UL << RCC_CIER_PLLRDYIE_Pos)

#define	RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk

#define	RCC_CIER_LSECSSIE_Pos (9U)

#define	RCC_CIER_LSECSSIE_Msk (0x1UL << RCC_CIER_LSECSSIE_Pos)

#define	RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk

#define	RCC_CIER_HSI48RDYIE_Pos (10U)

#define	RCC_CIER_HSI48RDYIE_Msk (0x1UL << RCC_CIER_HSI48RDYIE_Pos)

#define	RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk

#define	RCC_CIFR_LSIRDYF_Pos (0U)

#define	RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos)

#define	RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk

#define	RCC_CIFR_LSERDYF_Pos (1U)

#define	RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos)

#define	RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk

#define	RCC_CIFR_HSIRDYF_Pos (3U)

#define	RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos)

#define	RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk

#define	RCC_CIFR_HSERDYF_Pos (4U)

#define	RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos)

#define	RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk

#define	RCC_CIFR_PLLRDYF_Pos (5U)

#define	RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos)

#define	RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk

#define	RCC_CIFR_CSSF_Pos (8U)

#define	RCC_CIFR_CSSF_Msk (0x1UL << RCC_CIFR_CSSF_Pos)

#define	RCC_CIFR_CSSF RCC_CIFR_CSSF_Msk

#define	RCC_CIFR_LSECSSF_Pos (9U)

#define	RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos)

#define	RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk

#define	RCC_CIFR_HSI48RDYF_Pos (10U)

#define	RCC_CIFR_HSI48RDYF_Msk (0x1UL << RCC_CIFR_HSI48RDYF_Pos)

#define	RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk

#define	RCC_CICR_LSIRDYC_Pos (0U)

#define	RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos)

#define	RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk

#define	RCC_CICR_LSERDYC_Pos (1U)

#define	RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos)

#define	RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk

#define	RCC_CICR_HSIRDYC_Pos (3U)

#define	RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos)

#define	RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk

#define	RCC_CICR_HSERDYC_Pos (4U)

#define	RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos)

#define	RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk

#define	RCC_CICR_PLLRDYC_Pos (5U)

#define	RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos)

#define	RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk

#define	RCC_CICR_CSSC_Pos (8U)

#define	RCC_CICR_CSSC_Msk (0x1UL << RCC_CICR_CSSC_Pos)

#define	RCC_CICR_CSSC RCC_CICR_CSSC_Msk

#define	RCC_CICR_LSECSSC_Pos (9U)

#define	RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos)

#define	RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk

#define	RCC_CICR_HSI48RDYC_Pos (10U)

#define	RCC_CICR_HSI48RDYC_Msk (0x1UL << RCC_CICR_HSI48RDYC_Pos)

#define	RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk

#define	RCC_AHB1RSTR_DMA1RST_Pos (0U)

#define	RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)

#define	RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk

#define	RCC_AHB1RSTR_DMA2RST_Pos (1U)

#define	RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)

#define	RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk

#define	RCC_AHB1RSTR_DMAMUX1RST_Pos (2U)

#define	RCC_AHB1RSTR_DMAMUX1RST_Msk (0x1UL << RCC_AHB1RSTR_DMAMUX1RST_Pos)

#define	RCC_AHB1RSTR_DMAMUX1RST RCC_AHB1RSTR_DMAMUX1RST_Msk

#define	RCC_AHB1RSTR_CORDICRST_Pos (3U)

#define	RCC_AHB1RSTR_CORDICRST_Msk (0x1UL << RCC_AHB1RSTR_CORDICRST_Pos)

#define	RCC_AHB1RSTR_CORDICRST RCC_AHB1RSTR_CORDICRST_Msk

#define	RCC_AHB1RSTR_FMACRST_Pos (4U)

#define	RCC_AHB1RSTR_FMACRST_Msk (0x1UL << RCC_AHB1RSTR_FMACRST_Pos)

#define	RCC_AHB1RSTR_FMACRST RCC_AHB1RSTR_FMACRST_Msk

#define	RCC_AHB1RSTR_FLASHRST_Pos (8U)

#define	RCC_AHB1RSTR_FLASHRST_Msk (0x1UL << RCC_AHB1RSTR_FLASHRST_Pos)

#define	RCC_AHB1RSTR_FLASHRST RCC_AHB1RSTR_FLASHRST_Msk

#define	RCC_AHB1RSTR_CRCRST_Pos (12U)

#define	RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)

#define	RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk

#define	RCC_AHB2RSTR_GPIOARST_Pos (0U)

#define	RCC_AHB2RSTR_GPIOARST_Msk (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos)

#define	RCC_AHB2RSTR_GPIOARST RCC_AHB2RSTR_GPIOARST_Msk

#define	RCC_AHB2RSTR_GPIOBRST_Pos (1U)

#define	RCC_AHB2RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos)

#define	RCC_AHB2RSTR_GPIOBRST RCC_AHB2RSTR_GPIOBRST_Msk

#define	RCC_AHB2RSTR_GPIOCRST_Pos (2U)

#define	RCC_AHB2RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos)

#define	RCC_AHB2RSTR_GPIOCRST RCC_AHB2RSTR_GPIOCRST_Msk

#define	RCC_AHB2RSTR_GPIODRST_Pos (3U)

#define	RCC_AHB2RSTR_GPIODRST_Msk (0x1UL << RCC_AHB2RSTR_GPIODRST_Pos)

#define	RCC_AHB2RSTR_GPIODRST RCC_AHB2RSTR_GPIODRST_Msk

#define	RCC_AHB2RSTR_GPIOERST_Pos (4U)

#define	RCC_AHB2RSTR_GPIOERST_Msk (0x1UL << RCC_AHB2RSTR_GPIOERST_Pos)

#define	RCC_AHB2RSTR_GPIOERST RCC_AHB2RSTR_GPIOERST_Msk

#define	RCC_AHB2RSTR_GPIOFRST_Pos (5U)

#define	RCC_AHB2RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOFRST_Pos)

#define	RCC_AHB2RSTR_GPIOFRST RCC_AHB2RSTR_GPIOFRST_Msk

#define	RCC_AHB2RSTR_GPIOGRST_Pos (6U)

#define	RCC_AHB2RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOGRST_Pos)

#define	RCC_AHB2RSTR_GPIOGRST RCC_AHB2RSTR_GPIOGRST_Msk

#define	RCC_AHB2RSTR_ADC12RST_Pos (13U)

#define	RCC_AHB2RSTR_ADC12RST_Msk (0x1UL << RCC_AHB2RSTR_ADC12RST_Pos)

#define	RCC_AHB2RSTR_ADC12RST RCC_AHB2RSTR_ADC12RST_Msk

#define	RCC_AHB2RSTR_DAC1RST_Pos (16U)

#define	RCC_AHB2RSTR_DAC1RST_Msk (0x1UL << RCC_AHB2RSTR_DAC1RST_Pos)

#define	RCC_AHB2RSTR_DAC1RST RCC_AHB2RSTR_DAC1RST_Msk

#define	RCC_AHB2RSTR_DAC3RST_Pos (18U)

#define	RCC_AHB2RSTR_DAC3RST_Msk (0x1UL << RCC_AHB2RSTR_DAC3RST_Pos)

#define	RCC_AHB2RSTR_DAC3RST RCC_AHB2RSTR_DAC3RST_Msk

#define	RCC_AHB2RSTR_RNGRST_Pos (26U)

#define	RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)

#define	RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk

#define	RCC_APB1RSTR1_TIM2RST_Pos (0U)

#define	RCC_APB1RSTR1_TIM2RST_Msk (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos)

#define	RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk

#define	RCC_APB1RSTR1_TIM3RST_Pos (1U)

#define	RCC_APB1RSTR1_TIM3RST_Msk (0x1UL << RCC_APB1RSTR1_TIM3RST_Pos)

#define	RCC_APB1RSTR1_TIM3RST RCC_APB1RSTR1_TIM3RST_Msk

#define	RCC_APB1RSTR1_TIM4RST_Pos (2U)

#define	RCC_APB1RSTR1_TIM4RST_Msk (0x1UL << RCC_APB1RSTR1_TIM4RST_Pos)

#define	RCC_APB1RSTR1_TIM4RST RCC_APB1RSTR1_TIM4RST_Msk

#define	RCC_APB1RSTR1_TIM6RST_Pos (4U)

#define	RCC_APB1RSTR1_TIM6RST_Msk (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos)

#define	RCC_APB1RSTR1_TIM6RST RCC_APB1RSTR1_TIM6RST_Msk

#define	RCC_APB1RSTR1_TIM7RST_Pos (5U)

#define	RCC_APB1RSTR1_TIM7RST_Msk (0x1UL << RCC_APB1RSTR1_TIM7RST_Pos)

#define	RCC_APB1RSTR1_TIM7RST RCC_APB1RSTR1_TIM7RST_Msk

#define	RCC_APB1RSTR1_CRSRST_Pos (8U)

#define	RCC_APB1RSTR1_CRSRST_Msk (0x1UL << RCC_APB1RSTR1_CRSRST_Pos)

#define	RCC_APB1RSTR1_CRSRST RCC_APB1RSTR1_CRSRST_Msk

#define	RCC_APB1RSTR1_SPI2RST_Pos (14U)

#define	RCC_APB1RSTR1_SPI2RST_Msk (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos)

#define	RCC_APB1RSTR1_SPI2RST RCC_APB1RSTR1_SPI2RST_Msk

#define	RCC_APB1RSTR1_SPI3RST_Pos (15U)

#define	RCC_APB1RSTR1_SPI3RST_Msk (0x1UL << RCC_APB1RSTR1_SPI3RST_Pos)

#define	RCC_APB1RSTR1_SPI3RST RCC_APB1RSTR1_SPI3RST_Msk

#define	RCC_APB1RSTR1_USART2RST_Pos (17U)

#define	RCC_APB1RSTR1_USART2RST_Msk (0x1UL << RCC_APB1RSTR1_USART2RST_Pos)

#define	RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk

#define	RCC_APB1RSTR1_USART3RST_Pos (18U)

#define	RCC_APB1RSTR1_USART3RST_Msk (0x1UL << RCC_APB1RSTR1_USART3RST_Pos)

#define	RCC_APB1RSTR1_USART3RST RCC_APB1RSTR1_USART3RST_Msk

#define	RCC_APB1RSTR1_UART4RST_Pos (19U)

#define	RCC_APB1RSTR1_UART4RST_Msk (0x1UL << RCC_APB1RSTR1_UART4RST_Pos)

#define	RCC_APB1RSTR1_UART4RST RCC_APB1RSTR1_UART4RST_Msk

#define	RCC_APB1RSTR1_I2C1RST_Pos (21U)

#define	RCC_APB1RSTR1_I2C1RST_Msk (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos)

#define	RCC_APB1RSTR1_I2C1RST RCC_APB1RSTR1_I2C1RST_Msk

#define	RCC_APB1RSTR1_I2C2RST_Pos (22U)

#define	RCC_APB1RSTR1_I2C2RST_Msk (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos)

#define	RCC_APB1RSTR1_I2C2RST RCC_APB1RSTR1_I2C2RST_Msk

#define	RCC_APB1RSTR1_USBRST_Pos (23U)

#define	RCC_APB1RSTR1_USBRST_Msk (0x1UL << RCC_APB1RSTR1_USBRST_Pos)

#define	RCC_APB1RSTR1_USBRST RCC_APB1RSTR1_USBRST_Msk

#define	RCC_APB1RSTR1_FDCANRST_Pos (25U)

#define	RCC_APB1RSTR1_FDCANRST_Msk (0x1UL << RCC_APB1RSTR1_FDCANRST_Pos)

#define	RCC_APB1RSTR1_FDCANRST RCC_APB1RSTR1_FDCANRST_Msk

#define	RCC_APB1RSTR1_PWRRST_Pos (28U)

#define	RCC_APB1RSTR1_PWRRST_Msk (0x1UL << RCC_APB1RSTR1_PWRRST_Pos)

#define	RCC_APB1RSTR1_PWRRST RCC_APB1RSTR1_PWRRST_Msk

#define	RCC_APB1RSTR1_I2C3RST_Pos (30U)

#define	RCC_APB1RSTR1_I2C3RST_Msk (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos)

#define	RCC_APB1RSTR1_I2C3RST RCC_APB1RSTR1_I2C3RST_Msk

#define	RCC_APB1RSTR1_LPTIM1RST_Pos (31U)

#define	RCC_APB1RSTR1_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos)

#define	RCC_APB1RSTR1_LPTIM1RST RCC_APB1RSTR1_LPTIM1RST_Msk

#define	RCC_APB1RSTR2_LPUART1RST_Pos (0U)

#define	RCC_APB1RSTR2_LPUART1RST_Msk (0x1UL << RCC_APB1RSTR2_LPUART1RST_Pos)

#define	RCC_APB1RSTR2_LPUART1RST RCC_APB1RSTR2_LPUART1RST_Msk

#define	RCC_APB1RSTR2_UCPD1RST_Pos (8U)

#define	RCC_APB1RSTR2_UCPD1RST_Msk (0x1UL << RCC_APB1RSTR2_UCPD1RST_Pos)

#define	RCC_APB1RSTR2_UCPD1RST RCC_APB1RSTR2_UCPD1RST_Msk

#define	RCC_APB2RSTR_SYSCFGRST_Pos (0U)

#define	RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)

#define	RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk

#define	RCC_APB2RSTR_TIM1RST_Pos (11U)

#define	RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)

#define	RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk

#define	RCC_APB2RSTR_SPI1RST_Pos (12U)

#define	RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)

#define	RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk

#define	RCC_APB2RSTR_TIM8RST_Pos (13U)

#define	RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)

#define	RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk

#define	RCC_APB2RSTR_USART1RST_Pos (14U)

#define	RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)

#define	RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk

#define	RCC_APB2RSTR_TIM15RST_Pos (16U)

#define	RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos)

#define	RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk

#define	RCC_APB2RSTR_TIM16RST_Pos (17U)

#define	RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos)

#define	RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk

#define	RCC_APB2RSTR_TIM17RST_Pos (18U)

#define	RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)

#define	RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk

#define	RCC_APB2RSTR_SAI1RST_Pos (21U)

#define	RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)

#define	RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk

#define	RCC_AHB1ENR_DMA1EN_Pos (0U)

#define	RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)

#define	RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk

#define	RCC_AHB1ENR_DMA2EN_Pos (1U)

#define	RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)

#define	RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk

#define	RCC_AHB1ENR_DMAMUX1EN_Pos (2U)

#define	RCC_AHB1ENR_DMAMUX1EN_Msk (0x1UL << RCC_AHB1ENR_DMAMUX1EN_Pos)

#define	RCC_AHB1ENR_DMAMUX1EN RCC_AHB1ENR_DMAMUX1EN_Msk

#define	RCC_AHB1ENR_CORDICEN_Pos (3U)

#define	RCC_AHB1ENR_CORDICEN_Msk (0x1UL << RCC_AHB1ENR_CORDICEN_Pos)

#define	RCC_AHB1ENR_CORDICEN RCC_AHB1ENR_CORDICEN_Msk

#define	RCC_AHB1ENR_FMACEN_Pos (4U)

#define	RCC_AHB1ENR_FMACEN_Msk (0x1UL << RCC_AHB1ENR_FMACEN_Pos)

#define	RCC_AHB1ENR_FMACEN RCC_AHB1ENR_FMACEN_Msk

#define	RCC_AHB1ENR_FLASHEN_Pos (8U)

#define	RCC_AHB1ENR_FLASHEN_Msk (0x1UL << RCC_AHB1ENR_FLASHEN_Pos)

#define	RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk

#define	RCC_AHB1ENR_CRCEN_Pos (12U)

#define	RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos)

#define	RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk

#define	RCC_AHB2ENR_GPIOAEN_Pos (0U)

#define	RCC_AHB2ENR_GPIOAEN_Msk (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos)

#define	RCC_AHB2ENR_GPIOAEN RCC_AHB2ENR_GPIOAEN_Msk

#define	RCC_AHB2ENR_GPIOBEN_Pos (1U)

#define	RCC_AHB2ENR_GPIOBEN_Msk (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos)

#define	RCC_AHB2ENR_GPIOBEN RCC_AHB2ENR_GPIOBEN_Msk

#define	RCC_AHB2ENR_GPIOCEN_Pos (2U)

#define	RCC_AHB2ENR_GPIOCEN_Msk (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos)

#define	RCC_AHB2ENR_GPIOCEN RCC_AHB2ENR_GPIOCEN_Msk

#define	RCC_AHB2ENR_GPIODEN_Pos (3U)

#define	RCC_AHB2ENR_GPIODEN_Msk (0x1UL << RCC_AHB2ENR_GPIODEN_Pos)

#define	RCC_AHB2ENR_GPIODEN RCC_AHB2ENR_GPIODEN_Msk

#define	RCC_AHB2ENR_GPIOEEN_Pos (4U)

#define	RCC_AHB2ENR_GPIOEEN_Msk (0x1UL << RCC_AHB2ENR_GPIOEEN_Pos)

#define	RCC_AHB2ENR_GPIOEEN RCC_AHB2ENR_GPIOEEN_Msk

#define	RCC_AHB2ENR_GPIOFEN_Pos (5U)

#define	RCC_AHB2ENR_GPIOFEN_Msk (0x1UL << RCC_AHB2ENR_GPIOFEN_Pos)

#define	RCC_AHB2ENR_GPIOFEN RCC_AHB2ENR_GPIOFEN_Msk

#define	RCC_AHB2ENR_GPIOGEN_Pos (6U)

#define	RCC_AHB2ENR_GPIOGEN_Msk (0x1UL << RCC_AHB2ENR_GPIOGEN_Pos)

#define	RCC_AHB2ENR_GPIOGEN RCC_AHB2ENR_GPIOGEN_Msk

#define	RCC_AHB2ENR_ADC12EN_Pos (13U)

#define	RCC_AHB2ENR_ADC12EN_Msk (0x1UL << RCC_AHB2ENR_ADC12EN_Pos)

#define	RCC_AHB2ENR_ADC12EN RCC_AHB2ENR_ADC12EN_Msk

#define	RCC_AHB2ENR_DAC1EN_Pos (16U)

#define	RCC_AHB2ENR_DAC1EN_Msk (0x1UL << RCC_AHB2ENR_DAC1EN_Pos)

#define	RCC_AHB2ENR_DAC1EN RCC_AHB2ENR_DAC1EN_Msk

#define	RCC_AHB2ENR_DAC3EN_Pos (18U)

#define	RCC_AHB2ENR_DAC3EN_Msk (0x1UL << RCC_AHB2ENR_DAC3EN_Pos)

#define	RCC_AHB2ENR_DAC3EN RCC_AHB2ENR_DAC3EN_Msk

#define	RCC_AHB2ENR_RNGEN_Pos (26U)

#define	RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos)

#define	RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk

#define	RCC_APB1ENR1_TIM2EN_Pos (0U)

#define	RCC_APB1ENR1_TIM2EN_Msk (0x1UL << RCC_APB1ENR1_TIM2EN_Pos)

#define	RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk

#define	RCC_APB1ENR1_TIM3EN_Pos (1U)

#define	RCC_APB1ENR1_TIM3EN_Msk (0x1UL << RCC_APB1ENR1_TIM3EN_Pos)

#define	RCC_APB1ENR1_TIM3EN RCC_APB1ENR1_TIM3EN_Msk

#define	RCC_APB1ENR1_TIM4EN_Pos (2U)

#define	RCC_APB1ENR1_TIM4EN_Msk (0x1UL << RCC_APB1ENR1_TIM4EN_Pos)

#define	RCC_APB1ENR1_TIM4EN RCC_APB1ENR1_TIM4EN_Msk

#define	RCC_APB1ENR1_TIM6EN_Pos (4U)

#define	RCC_APB1ENR1_TIM6EN_Msk (0x1UL << RCC_APB1ENR1_TIM6EN_Pos)

#define	RCC_APB1ENR1_TIM6EN RCC_APB1ENR1_TIM6EN_Msk

#define	RCC_APB1ENR1_TIM7EN_Pos (5U)

#define	RCC_APB1ENR1_TIM7EN_Msk (0x1UL << RCC_APB1ENR1_TIM7EN_Pos)

#define	RCC_APB1ENR1_TIM7EN RCC_APB1ENR1_TIM7EN_Msk

#define	RCC_APB1ENR1_CRSEN_Pos (8U)

#define	RCC_APB1ENR1_CRSEN_Msk (0x1UL << RCC_APB1ENR1_CRSEN_Pos)

#define	RCC_APB1ENR1_CRSEN RCC_APB1ENR1_CRSEN_Msk

#define	RCC_APB1ENR1_RTCAPBEN_Pos (10U)

#define	RCC_APB1ENR1_RTCAPBEN_Msk (0x1UL << RCC_APB1ENR1_RTCAPBEN_Pos)

#define	RCC_APB1ENR1_RTCAPBEN RCC_APB1ENR1_RTCAPBEN_Msk

#define	RCC_APB1ENR1_WWDGEN_Pos (11U)

#define	RCC_APB1ENR1_WWDGEN_Msk (0x1UL << RCC_APB1ENR1_WWDGEN_Pos)

#define	RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk

#define	RCC_APB1ENR1_SPI2EN_Pos (14U)

#define	RCC_APB1ENR1_SPI2EN_Msk (0x1UL << RCC_APB1ENR1_SPI2EN_Pos)

#define	RCC_APB1ENR1_SPI2EN RCC_APB1ENR1_SPI2EN_Msk

#define	RCC_APB1ENR1_SPI3EN_Pos (15U)

#define	RCC_APB1ENR1_SPI3EN_Msk (0x1UL << RCC_APB1ENR1_SPI3EN_Pos)

#define	RCC_APB1ENR1_SPI3EN RCC_APB1ENR1_SPI3EN_Msk

#define	RCC_APB1ENR1_USART2EN_Pos (17U)

#define	RCC_APB1ENR1_USART2EN_Msk (0x1UL << RCC_APB1ENR1_USART2EN_Pos)

#define	RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk

#define	RCC_APB1ENR1_USART3EN_Pos (18U)

#define	RCC_APB1ENR1_USART3EN_Msk (0x1UL << RCC_APB1ENR1_USART3EN_Pos)

#define	RCC_APB1ENR1_USART3EN RCC_APB1ENR1_USART3EN_Msk

#define	RCC_APB1ENR1_UART4EN_Pos (19U)

#define	RCC_APB1ENR1_UART4EN_Msk (0x1UL << RCC_APB1ENR1_UART4EN_Pos)

#define	RCC_APB1ENR1_UART4EN RCC_APB1ENR1_UART4EN_Msk

#define	RCC_APB1ENR1_I2C1EN_Pos (21U)

#define	RCC_APB1ENR1_I2C1EN_Msk (0x1UL << RCC_APB1ENR1_I2C1EN_Pos)

#define	RCC_APB1ENR1_I2C1EN RCC_APB1ENR1_I2C1EN_Msk

#define	RCC_APB1ENR1_I2C2EN_Pos (22U)

#define	RCC_APB1ENR1_I2C2EN_Msk (0x1UL << RCC_APB1ENR1_I2C2EN_Pos)

#define	RCC_APB1ENR1_I2C2EN RCC_APB1ENR1_I2C2EN_Msk

#define	RCC_APB1ENR1_USBEN_Pos (23U)

#define	RCC_APB1ENR1_USBEN_Msk (0x1UL << RCC_APB1ENR1_USBEN_Pos)

#define	RCC_APB1ENR1_USBEN RCC_APB1ENR1_USBEN_Msk

#define	RCC_APB1ENR1_FDCANEN_Pos (25U)

#define	RCC_APB1ENR1_FDCANEN_Msk (0x1UL << RCC_APB1ENR1_FDCANEN_Pos)

#define	RCC_APB1ENR1_FDCANEN RCC_APB1ENR1_FDCANEN_Msk

#define	RCC_APB1ENR1_PWREN_Pos (28U)

#define	RCC_APB1ENR1_PWREN_Msk (0x1UL << RCC_APB1ENR1_PWREN_Pos)

#define	RCC_APB1ENR1_PWREN RCC_APB1ENR1_PWREN_Msk

#define	RCC_APB1ENR1_I2C3EN_Pos (30U)

#define	RCC_APB1ENR1_I2C3EN_Msk (0x1UL << RCC_APB1ENR1_I2C3EN_Pos)

#define	RCC_APB1ENR1_I2C3EN RCC_APB1ENR1_I2C3EN_Msk

#define	RCC_APB1ENR1_LPTIM1EN_Pos (31U)

#define	RCC_APB1ENR1_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos)

#define	RCC_APB1ENR1_LPTIM1EN RCC_APB1ENR1_LPTIM1EN_Msk

#define	RCC_APB1ENR2_LPUART1EN_Pos (0U)

#define	RCC_APB1ENR2_LPUART1EN_Msk (0x1UL << RCC_APB1ENR2_LPUART1EN_Pos)

#define	RCC_APB1ENR2_LPUART1EN RCC_APB1ENR2_LPUART1EN_Msk

#define	RCC_APB1ENR2_UCPD1EN_Pos (8U)

#define	RCC_APB1ENR2_UCPD1EN_Msk (0x1UL << RCC_APB1ENR2_UCPD1EN_Pos)

#define	RCC_APB1ENR2_UCPD1EN RCC_APB1ENR2_UCPD1EN_Msk

#define	RCC_APB2ENR_SYSCFGEN_Pos (0U)

#define	RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)

#define	RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk

#define	RCC_APB2ENR_TIM1EN_Pos (11U)

#define	RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos)

#define	RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk

#define	RCC_APB2ENR_SPI1EN_Pos (12U)

#define	RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos)

#define	RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk

#define	RCC_APB2ENR_TIM8EN_Pos (13U)

#define	RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos)

#define	RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk

#define	RCC_APB2ENR_USART1EN_Pos (14U)

#define	RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)

#define	RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk

#define	RCC_APB2ENR_TIM15EN_Pos (16U)

#define	RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos)

#define	RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk

#define	RCC_APB2ENR_TIM16EN_Pos (17U)

#define	RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos)

#define	RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk

#define	RCC_APB2ENR_TIM17EN_Pos (18U)

#define	RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos)

#define	RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk

#define	RCC_APB2ENR_SAI1EN_Pos (21U)

#define	RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos)

#define	RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk

#define	RCC_AHB1SMENR_DMA1SMEN_Pos (0U)

#define	RCC_AHB1SMENR_DMA1SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMA1SMEN_Pos)

#define	RCC_AHB1SMENR_DMA1SMEN RCC_AHB1SMENR_DMA1SMEN_Msk

#define	RCC_AHB1SMENR_DMA2SMEN_Pos (1U)

#define	RCC_AHB1SMENR_DMA2SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMA2SMEN_Pos)

#define	RCC_AHB1SMENR_DMA2SMEN RCC_AHB1SMENR_DMA2SMEN_Msk

#define	RCC_AHB1SMENR_DMAMUX1SMEN_Pos (2U)

#define	RCC_AHB1SMENR_DMAMUX1SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMAMUX1SMEN_Pos)

#define	RCC_AHB1SMENR_DMAMUX1SMEN RCC_AHB1SMENR_DMAMUX1SMEN_Msk

#define	RCC_AHB1SMENR_CORDICSMEN_Pos (3U)

#define	RCC_AHB1SMENR_CORDICSMEN_Msk (0x1UL << RCC_AHB1SMENR_CORDICSMEN_Pos)

#define	RCC_AHB1SMENR_CORDICSMEN RCC_AHB1SMENR_CORDICSMEN_Msk

#define	RCC_AHB1SMENR_FMACSMEN_Pos (4U)

#define	RCC_AHB1SMENR_FMACSMEN_Msk (0x1UL << RCC_AHB1SMENR_FMACSMEN_Pos)

#define	RCC_AHB1SMENR_FMACSMEN RCC_AHB1SMENR_FMACSMEN_Msk

#define	RCC_AHB1SMENR_FLASHSMEN_Pos (8U)

#define	RCC_AHB1SMENR_FLASHSMEN_Msk (0x1UL << RCC_AHB1SMENR_FLASHSMEN_Pos)

#define	RCC_AHB1SMENR_FLASHSMEN RCC_AHB1SMENR_FLASHSMEN_Msk

#define	RCC_AHB1SMENR_SRAM1SMEN_Pos (9U)

#define	RCC_AHB1SMENR_SRAM1SMEN_Msk (0x1UL << RCC_AHB1SMENR_SRAM1SMEN_Pos)

#define	RCC_AHB1SMENR_SRAM1SMEN RCC_AHB1SMENR_SRAM1SMEN_Msk

#define	RCC_AHB1SMENR_CRCSMEN_Pos (12U)

#define	RCC_AHB1SMENR_CRCSMEN_Msk (0x1UL << RCC_AHB1SMENR_CRCSMEN_Pos)

#define	RCC_AHB1SMENR_CRCSMEN RCC_AHB1SMENR_CRCSMEN_Msk

#define	RCC_AHB2SMENR_GPIOASMEN_Pos (0U)

#define	RCC_AHB2SMENR_GPIOASMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOASMEN_Pos)

#define	RCC_AHB2SMENR_GPIOASMEN RCC_AHB2SMENR_GPIOASMEN_Msk

#define	RCC_AHB2SMENR_GPIOBSMEN_Pos (1U)

#define	RCC_AHB2SMENR_GPIOBSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOBSMEN_Pos)

#define	RCC_AHB2SMENR_GPIOBSMEN RCC_AHB2SMENR_GPIOBSMEN_Msk

#define	RCC_AHB2SMENR_GPIOCSMEN_Pos (2U)

#define	RCC_AHB2SMENR_GPIOCSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOCSMEN_Pos)

#define	RCC_AHB2SMENR_GPIOCSMEN RCC_AHB2SMENR_GPIOCSMEN_Msk

#define	RCC_AHB2SMENR_GPIODSMEN_Pos (3U)

#define	RCC_AHB2SMENR_GPIODSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIODSMEN_Pos)

#define	RCC_AHB2SMENR_GPIODSMEN RCC_AHB2SMENR_GPIODSMEN_Msk

#define	RCC_AHB2SMENR_GPIOESMEN_Pos (4U)

#define	RCC_AHB2SMENR_GPIOESMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOESMEN_Pos)

#define	RCC_AHB2SMENR_GPIOESMEN RCC_AHB2SMENR_GPIOESMEN_Msk

#define	RCC_AHB2SMENR_GPIOFSMEN_Pos (5U)

#define	RCC_AHB2SMENR_GPIOFSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOFSMEN_Pos)

#define	RCC_AHB2SMENR_GPIOFSMEN RCC_AHB2SMENR_GPIOFSMEN_Msk

#define	RCC_AHB2SMENR_GPIOGSMEN_Pos (6U)

#define	RCC_AHB2SMENR_GPIOGSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOGSMEN_Pos)

#define	RCC_AHB2SMENR_GPIOGSMEN RCC_AHB2SMENR_GPIOGSMEN_Msk

#define	RCC_AHB2SMENR_CCMSRAMSMEN_Pos (9U)

#define	RCC_AHB2SMENR_CCMSRAMSMEN_Msk (0x1UL << RCC_AHB2SMENR_CCMSRAMSMEN_Pos)

#define	RCC_AHB2SMENR_CCMSRAMSMEN RCC_AHB2SMENR_CCMSRAMSMEN_Msk

#define	RCC_AHB2SMENR_SRAM2SMEN_Pos (10U)

#define	RCC_AHB2SMENR_SRAM2SMEN_Msk (0x1UL << RCC_AHB2SMENR_SRAM2SMEN_Pos)

#define	RCC_AHB2SMENR_SRAM2SMEN RCC_AHB2SMENR_SRAM2SMEN_Msk

#define	RCC_AHB2SMENR_ADC12SMEN_Pos (13U)

#define	RCC_AHB2SMENR_ADC12SMEN_Msk (0x1UL << RCC_AHB2SMENR_ADC12SMEN_Pos)

#define	RCC_AHB2SMENR_ADC12SMEN RCC_AHB2SMENR_ADC12SMEN_Msk

#define	RCC_AHB2SMENR_DAC1SMEN_Pos (16U)

#define	RCC_AHB2SMENR_DAC1SMEN_Msk (0x1UL << RCC_AHB2SMENR_DAC1SMEN_Pos)

#define	RCC_AHB2SMENR_DAC1SMEN RCC_AHB2SMENR_DAC1SMEN_Msk

#define	RCC_AHB2SMENR_DAC3SMEN_Pos (18U)

#define	RCC_AHB2SMENR_DAC3SMEN_Msk (0x1UL << RCC_AHB2SMENR_DAC3SMEN_Pos)

#define	RCC_AHB2SMENR_DAC3SMEN RCC_AHB2SMENR_DAC3SMEN_Msk

#define	RCC_AHB2SMENR_RNGSMEN_Pos (26U)

#define	RCC_AHB2SMENR_RNGSMEN_Msk (0x1UL << RCC_AHB2SMENR_RNGSMEN_Pos)

#define	RCC_AHB2SMENR_RNGSMEN RCC_AHB2SMENR_RNGSMEN_Msk

#define	RCC_APB1SMENR1_TIM2SMEN_Pos (0U)

#define	RCC_APB1SMENR1_TIM2SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM2SMEN_Pos)

#define	RCC_APB1SMENR1_TIM2SMEN RCC_APB1SMENR1_TIM2SMEN_Msk

#define	RCC_APB1SMENR1_TIM3SMEN_Pos (1U)

#define	RCC_APB1SMENR1_TIM3SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM3SMEN_Pos)

#define	RCC_APB1SMENR1_TIM3SMEN RCC_APB1SMENR1_TIM3SMEN_Msk

#define	RCC_APB1SMENR1_TIM4SMEN_Pos (2U)

#define	RCC_APB1SMENR1_TIM4SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM4SMEN_Pos)

#define	RCC_APB1SMENR1_TIM4SMEN RCC_APB1SMENR1_TIM4SMEN_Msk

#define	RCC_APB1SMENR1_TIM6SMEN_Pos (4U)

#define	RCC_APB1SMENR1_TIM6SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM6SMEN_Pos)

#define	RCC_APB1SMENR1_TIM6SMEN RCC_APB1SMENR1_TIM6SMEN_Msk

#define	RCC_APB1SMENR1_TIM7SMEN_Pos (5U)

#define	RCC_APB1SMENR1_TIM7SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM7SMEN_Pos)

#define	RCC_APB1SMENR1_TIM7SMEN RCC_APB1SMENR1_TIM7SMEN_Msk

#define	RCC_APB1SMENR1_CRSSMEN_Pos (8U)

#define	RCC_APB1SMENR1_CRSSMEN_Msk (0x1UL << RCC_APB1SMENR1_CRSSMEN_Pos)

#define	RCC_APB1SMENR1_CRSSMEN RCC_APB1SMENR1_CRSSMEN_Msk

#define	RCC_APB1SMENR1_RTCAPBSMEN_Pos (10U)

#define	RCC_APB1SMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_APB1SMENR1_RTCAPBSMEN_Pos)

#define	RCC_APB1SMENR1_RTCAPBSMEN RCC_APB1SMENR1_RTCAPBSMEN_Msk

#define	RCC_APB1SMENR1_WWDGSMEN_Pos (11U)

#define	RCC_APB1SMENR1_WWDGSMEN_Msk (0x1UL << RCC_APB1SMENR1_WWDGSMEN_Pos)

#define	RCC_APB1SMENR1_WWDGSMEN RCC_APB1SMENR1_WWDGSMEN_Msk

#define	RCC_APB1SMENR1_SPI2SMEN_Pos (14U)

#define	RCC_APB1SMENR1_SPI2SMEN_Msk (0x1UL << RCC_APB1SMENR1_SPI2SMEN_Pos)

#define	RCC_APB1SMENR1_SPI2SMEN RCC_APB1SMENR1_SPI2SMEN_Msk

#define	RCC_APB1SMENR1_SPI3SMEN_Pos (15U)

#define	RCC_APB1SMENR1_SPI3SMEN_Msk (0x1UL << RCC_APB1SMENR1_SPI3SMEN_Pos)

#define	RCC_APB1SMENR1_SPI3SMEN RCC_APB1SMENR1_SPI3SMEN_Msk

#define	RCC_APB1SMENR1_USART2SMEN_Pos (17U)

#define	RCC_APB1SMENR1_USART2SMEN_Msk (0x1UL << RCC_APB1SMENR1_USART2SMEN_Pos)

#define	RCC_APB1SMENR1_USART2SMEN RCC_APB1SMENR1_USART2SMEN_Msk

#define	RCC_APB1SMENR1_USART3SMEN_Pos (18U)

#define	RCC_APB1SMENR1_USART3SMEN_Msk (0x1UL << RCC_APB1SMENR1_USART3SMEN_Pos)

#define	RCC_APB1SMENR1_USART3SMEN RCC_APB1SMENR1_USART3SMEN_Msk

#define	RCC_APB1SMENR1_UART4SMEN_Pos (19U)

#define	RCC_APB1SMENR1_UART4SMEN_Msk (0x1UL << RCC_APB1SMENR1_UART4SMEN_Pos)

#define	RCC_APB1SMENR1_UART4SMEN RCC_APB1SMENR1_UART4SMEN_Msk

#define	RCC_APB1SMENR1_I2C1SMEN_Pos (21U)

#define	RCC_APB1SMENR1_I2C1SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C1SMEN_Pos)

#define	RCC_APB1SMENR1_I2C1SMEN RCC_APB1SMENR1_I2C1SMEN_Msk

#define	RCC_APB1SMENR1_I2C2SMEN_Pos (22U)

#define	RCC_APB1SMENR1_I2C2SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C2SMEN_Pos)

#define	RCC_APB1SMENR1_I2C2SMEN RCC_APB1SMENR1_I2C2SMEN_Msk

#define	RCC_APB1SMENR1_USBSMEN_Pos (23U)

#define	RCC_APB1SMENR1_USBSMEN_Msk (0x1UL << RCC_APB1SMENR1_USBSMEN_Pos)

#define	RCC_APB1SMENR1_USBSMEN RCC_APB1SMENR1_USBSMEN_Msk

#define	RCC_APB1SMENR1_FDCANSMEN_Pos (25U)

#define	RCC_APB1SMENR1_FDCANSMEN_Msk (0x1UL << RCC_APB1SMENR1_FDCANSMEN_Pos)

#define	RCC_APB1SMENR1_FDCANSMEN RCC_APB1SMENR1_FDCANSMEN_Msk

#define	RCC_APB1SMENR1_PWRSMEN_Pos (28U)

#define	RCC_APB1SMENR1_PWRSMEN_Msk (0x1UL << RCC_APB1SMENR1_PWRSMEN_Pos)

#define	RCC_APB1SMENR1_PWRSMEN RCC_APB1SMENR1_PWRSMEN_Msk

#define	RCC_APB1SMENR1_I2C3SMEN_Pos (30U)

#define	RCC_APB1SMENR1_I2C3SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C3SMEN_Pos)

#define	RCC_APB1SMENR1_I2C3SMEN RCC_APB1SMENR1_I2C3SMEN_Msk

#define	RCC_APB1SMENR1_LPTIM1SMEN_Pos (31U)

#define	RCC_APB1SMENR1_LPTIM1SMEN_Msk (0x1UL << RCC_APB1SMENR1_LPTIM1SMEN_Pos)

#define	RCC_APB1SMENR1_LPTIM1SMEN RCC_APB1SMENR1_LPTIM1SMEN_Msk

#define	RCC_APB1SMENR2_LPUART1SMEN_Pos (0U)

#define	RCC_APB1SMENR2_LPUART1SMEN_Msk (0x1UL << RCC_APB1SMENR2_LPUART1SMEN_Pos)

#define	RCC_APB1SMENR2_LPUART1SMEN RCC_APB1SMENR2_LPUART1SMEN_Msk

#define	RCC_APB1SMENR2_UCPD1SMEN_Pos (8U)

#define	RCC_APB1SMENR2_UCPD1SMEN_Msk (0x1UL << RCC_APB1SMENR2_UCPD1SMEN_Pos)

#define	RCC_APB1SMENR2_UCPD1SMEN RCC_APB1SMENR2_UCPD1SMEN_Msk

#define	RCC_APB2SMENR_SYSCFGSMEN_Pos (0U)

#define	RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos)

#define	RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk

#define	RCC_APB2SMENR_TIM1SMEN_Pos (11U)

#define	RCC_APB2SMENR_TIM1SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos)

#define	RCC_APB2SMENR_TIM1SMEN RCC_APB2SMENR_TIM1SMEN_Msk

#define	RCC_APB2SMENR_SPI1SMEN_Pos (12U)

#define	RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)

#define	RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk

#define	RCC_APB2SMENR_TIM8SMEN_Pos (13U)

#define	RCC_APB2SMENR_TIM8SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM8SMEN_Pos)

#define	RCC_APB2SMENR_TIM8SMEN RCC_APB2SMENR_TIM8SMEN_Msk

#define	RCC_APB2SMENR_USART1SMEN_Pos (14U)

#define	RCC_APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos)

#define	RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk

#define	RCC_APB2SMENR_TIM15SMEN_Pos (16U)

#define	RCC_APB2SMENR_TIM15SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM15SMEN_Pos)

#define	RCC_APB2SMENR_TIM15SMEN RCC_APB2SMENR_TIM15SMEN_Msk

#define	RCC_APB2SMENR_TIM16SMEN_Pos (17U)

#define	RCC_APB2SMENR_TIM16SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos)

#define	RCC_APB2SMENR_TIM16SMEN RCC_APB2SMENR_TIM16SMEN_Msk

#define	RCC_APB2SMENR_TIM17SMEN_Pos (18U)

#define	RCC_APB2SMENR_TIM17SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM17SMEN_Pos)

#define	RCC_APB2SMENR_TIM17SMEN RCC_APB2SMENR_TIM17SMEN_Msk

#define	RCC_APB2SMENR_SAI1SMEN_Pos (21U)

#define	RCC_APB2SMENR_SAI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SAI1SMEN_Pos)

#define	RCC_APB2SMENR_SAI1SMEN RCC_APB2SMENR_SAI1SMEN_Msk

#define	RCC_CCIPR_USART1SEL_Pos (0U)

#define	RCC_CCIPR_USART1SEL_Msk (0x3UL << RCC_CCIPR_USART1SEL_Pos)

#define	RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk

#define	RCC_CCIPR_USART1SEL_0 (0x1UL << RCC_CCIPR_USART1SEL_Pos)

#define	RCC_CCIPR_USART1SEL_1 (0x2UL << RCC_CCIPR_USART1SEL_Pos)

#define	RCC_CCIPR_USART2SEL_Pos (2U)

#define	RCC_CCIPR_USART2SEL_Msk (0x3UL << RCC_CCIPR_USART2SEL_Pos)

#define	RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk

#define	RCC_CCIPR_USART2SEL_0 (0x1UL << RCC_CCIPR_USART2SEL_Pos)

#define	RCC_CCIPR_USART2SEL_1 (0x2UL << RCC_CCIPR_USART2SEL_Pos)

#define	RCC_CCIPR_USART3SEL_Pos (4U)

#define	RCC_CCIPR_USART3SEL_Msk (0x3UL << RCC_CCIPR_USART3SEL_Pos)

#define	RCC_CCIPR_USART3SEL RCC_CCIPR_USART3SEL_Msk

#define	RCC_CCIPR_USART3SEL_0 (0x1UL << RCC_CCIPR_USART3SEL_Pos)

#define	RCC_CCIPR_USART3SEL_1 (0x2UL << RCC_CCIPR_USART3SEL_Pos)

#define	RCC_CCIPR_UART4SEL_Pos (6U)

#define	RCC_CCIPR_UART4SEL_Msk (0x3UL << RCC_CCIPR_UART4SEL_Pos)

#define	RCC_CCIPR_UART4SEL RCC_CCIPR_UART4SEL_Msk

#define	RCC_CCIPR_UART4SEL_0 (0x1UL << RCC_CCIPR_UART4SEL_Pos)

#define	RCC_CCIPR_UART4SEL_1 (0x2UL << RCC_CCIPR_UART4SEL_Pos)

#define	RCC_CCIPR_LPUART1SEL_Pos (10U)

#define	RCC_CCIPR_LPUART1SEL_Msk (0x3UL << RCC_CCIPR_LPUART1SEL_Pos)

#define	RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk

#define	RCC_CCIPR_LPUART1SEL_0 (0x1UL << RCC_CCIPR_LPUART1SEL_Pos)

#define	RCC_CCIPR_LPUART1SEL_1 (0x2UL << RCC_CCIPR_LPUART1SEL_Pos)

#define	RCC_CCIPR_I2C1SEL_Pos (12U)

#define	RCC_CCIPR_I2C1SEL_Msk (0x3UL << RCC_CCIPR_I2C1SEL_Pos)

#define	RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk

#define	RCC_CCIPR_I2C1SEL_0 (0x1UL << RCC_CCIPR_I2C1SEL_Pos)

#define	RCC_CCIPR_I2C1SEL_1 (0x2UL << RCC_CCIPR_I2C1SEL_Pos)

#define	RCC_CCIPR_I2C2SEL_Pos (14U)

#define	RCC_CCIPR_I2C2SEL_Msk (0x3UL << RCC_CCIPR_I2C2SEL_Pos)

#define	RCC_CCIPR_I2C2SEL RCC_CCIPR_I2C2SEL_Msk

#define	RCC_CCIPR_I2C2SEL_0 (0x1UL << RCC_CCIPR_I2C2SEL_Pos)

#define	RCC_CCIPR_I2C2SEL_1 (0x2UL << RCC_CCIPR_I2C2SEL_Pos)

#define	RCC_CCIPR_I2C3SEL_Pos (16U)

#define	RCC_CCIPR_I2C3SEL_Msk (0x3UL << RCC_CCIPR_I2C3SEL_Pos)

#define	RCC_CCIPR_I2C3SEL RCC_CCIPR_I2C3SEL_Msk

#define	RCC_CCIPR_I2C3SEL_0 (0x1UL << RCC_CCIPR_I2C3SEL_Pos)

#define	RCC_CCIPR_I2C3SEL_1 (0x2UL << RCC_CCIPR_I2C3SEL_Pos)

#define	RCC_CCIPR_LPTIM1SEL_Pos (18U)

#define	RCC_CCIPR_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos)

#define	RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk

#define	RCC_CCIPR_LPTIM1SEL_0 (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos)

#define	RCC_CCIPR_LPTIM1SEL_1 (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos)

#define	RCC_CCIPR_SAI1SEL_Pos (20U)

#define	RCC_CCIPR_SAI1SEL_Msk (0x3UL << RCC_CCIPR_SAI1SEL_Pos)

#define	RCC_CCIPR_SAI1SEL RCC_CCIPR_SAI1SEL_Msk

#define	RCC_CCIPR_SAI1SEL_0 (0x1UL << RCC_CCIPR_SAI1SEL_Pos)

#define	RCC_CCIPR_SAI1SEL_1 (0x2UL << RCC_CCIPR_SAI1SEL_Pos)

#define	RCC_CCIPR_I2S23SEL_Pos (22U)

#define	RCC_CCIPR_I2S23SEL_Msk (0x3UL << RCC_CCIPR_I2S23SEL_Pos)

#define	RCC_CCIPR_I2S23SEL RCC_CCIPR_I2S23SEL_Msk

#define	RCC_CCIPR_I2S23SEL_0 (0x1UL << RCC_CCIPR_I2S23SEL_Pos)

#define	RCC_CCIPR_I2S23SEL_1 (0x2UL << RCC_CCIPR_I2S23SEL_Pos)

#define	RCC_CCIPR_FDCANSEL_Pos (24U)

#define	RCC_CCIPR_FDCANSEL_Msk (0x3UL << RCC_CCIPR_FDCANSEL_Pos)

#define	RCC_CCIPR_FDCANSEL RCC_CCIPR_FDCANSEL_Msk

#define	RCC_CCIPR_FDCANSEL_0 (0x1UL << RCC_CCIPR_FDCANSEL_Pos)

#define	RCC_CCIPR_FDCANSEL_1 (0x2UL << RCC_CCIPR_FDCANSEL_Pos)

#define	RCC_CCIPR_CLK48SEL_Pos (26U)

#define	RCC_CCIPR_CLK48SEL_Msk (0x3UL << RCC_CCIPR_CLK48SEL_Pos)

#define	RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk

#define	RCC_CCIPR_CLK48SEL_0 (0x1UL << RCC_CCIPR_CLK48SEL_Pos)

#define	RCC_CCIPR_CLK48SEL_1 (0x2UL << RCC_CCIPR_CLK48SEL_Pos)

#define	RCC_CCIPR_ADC12SEL_Pos (28U)

#define	RCC_CCIPR_ADC12SEL_Msk (0x3UL << RCC_CCIPR_ADC12SEL_Pos)

#define	RCC_CCIPR_ADC12SEL RCC_CCIPR_ADC12SEL_Msk

#define	RCC_CCIPR_ADC12SEL_0 (0x1UL << RCC_CCIPR_ADC12SEL_Pos)

#define	RCC_CCIPR_ADC12SEL_1 (0x2UL << RCC_CCIPR_ADC12SEL_Pos)

#define	RCC_BDCR_LSEON_Pos (0U)

#define	RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos)

#define	RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk

#define	RCC_BDCR_LSERDY_Pos (1U)

#define	RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos)

#define	RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk

#define	RCC_BDCR_LSEBYP_Pos (2U)

#define	RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos)

#define	RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk

#define	RCC_BDCR_LSEDRV_Pos (3U)

#define	RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos)

#define	RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk

#define	RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos)

#define	RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos)

#define	RCC_BDCR_LSECSSON_Pos (5U)

#define	RCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos)

#define	RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk

#define	RCC_BDCR_LSECSSD_Pos (6U)

#define	RCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos)

#define	RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk

#define	RCC_BDCR_RTCSEL_Pos (8U)

#define	RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos)

#define	RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk

#define	RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos)

#define	RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos)

#define	RCC_BDCR_RTCEN_Pos (15U)

#define	RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos)

#define	RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk

#define	RCC_BDCR_BDRST_Pos (16U)

#define	RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos)

#define	RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk

#define	RCC_BDCR_LSCOEN_Pos (24U)

#define	RCC_BDCR_LSCOEN_Msk (0x1UL << RCC_BDCR_LSCOEN_Pos)

#define	RCC_BDCR_LSCOEN RCC_BDCR_LSCOEN_Msk

#define	RCC_BDCR_LSCOSEL_Pos (25U)

#define	RCC_BDCR_LSCOSEL_Msk (0x1UL << RCC_BDCR_LSCOSEL_Pos)

#define	RCC_BDCR_LSCOSEL RCC_BDCR_LSCOSEL_Msk

#define	RCC_CSR_LSION_Pos (0U)

#define	RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos)

#define	RCC_CSR_LSION RCC_CSR_LSION_Msk

#define	RCC_CSR_LSIRDY_Pos (1U)

#define	RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos)

#define	RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk

#define	RCC_CSR_RMVF_Pos (23U)

#define	RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos)

#define	RCC_CSR_RMVF RCC_CSR_RMVF_Msk

#define	RCC_CSR_OBLRSTF_Pos (25U)

#define	RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos)

#define	RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk

#define	RCC_CSR_PINRSTF_Pos (26U)

#define	RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos)

#define	RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk

#define	RCC_CSR_BORRSTF_Pos (27U)

#define	RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos)

#define	RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk

#define	RCC_CSR_SFTRSTF_Pos (28U)

#define	RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos)

#define	RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk

#define	RCC_CSR_IWDGRSTF_Pos (29U)

#define	RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos)

#define	RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk

#define	RCC_CSR_WWDGRSTF_Pos (30U)

#define	RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos)

#define	RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk

#define	RCC_CSR_LPWRRSTF_Pos (31U)

#define	RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos)

#define	RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk

#define	RCC_CRRCR_HSI48ON_Pos (0U)

#define	RCC_CRRCR_HSI48ON_Msk (0x1UL << RCC_CRRCR_HSI48ON_Pos)

#define	RCC_CRRCR_HSI48ON RCC_CRRCR_HSI48ON_Msk

#define	RCC_CRRCR_HSI48RDY_Pos (1U)

#define	RCC_CRRCR_HSI48RDY_Msk (0x1UL << RCC_CRRCR_HSI48RDY_Pos)

#define	RCC_CRRCR_HSI48RDY RCC_CRRCR_HSI48RDY_Msk

#define	RCC_CRRCR_HSI48CAL_Pos (7U)

#define	RCC_CRRCR_HSI48CAL_Msk (0x1FFUL << RCC_CRRCR_HSI48CAL_Pos)

#define	RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk

#define	RCC_CRRCR_HSI48CAL_0 (0x001UL << RCC_CRRCR_HSI48CAL_Pos)

#define	RCC_CRRCR_HSI48CAL_1 (0x002UL << RCC_CRRCR_HSI48CAL_Pos)

#define	RCC_CRRCR_HSI48CAL_2 (0x004UL << RCC_CRRCR_HSI48CAL_Pos)

#define	RCC_CRRCR_HSI48CAL_3 (0x008UL << RCC_CRRCR_HSI48CAL_Pos)

#define	RCC_CRRCR_HSI48CAL_4 (0x010UL << RCC_CRRCR_HSI48CAL_Pos)

#define	RCC_CRRCR_HSI48CAL_5 (0x020UL << RCC_CRRCR_HSI48CAL_Pos)

#define	RCC_CRRCR_HSI48CAL_6 (0x040UL << RCC_CRRCR_HSI48CAL_Pos)

#define	RCC_CRRCR_HSI48CAL_7 (0x080UL << RCC_CRRCR_HSI48CAL_Pos)

#define	RCC_CRRCR_HSI48CAL_8 (0x100UL << RCC_CRRCR_HSI48CAL_Pos)

#define	RNG_CR_RNGEN_Pos (2U)

#define	RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos)

#define	RNG_CR_RNGEN RNG_CR_RNGEN_Msk

#define	RNG_CR_IE_Pos (3U)

#define	RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos)

#define	RNG_CR_IE RNG_CR_IE_Msk

#define	RNG_CR_CED_Pos (5U)

#define	RNG_CR_CED_Msk (0x1UL << RNG_CR_IE_Pos)

#define	RNG_CR_CED RNG_CR_IE_Msk

#define	RNG_SR_DRDY_Pos (0U)

#define	RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos)

#define	RNG_SR_DRDY RNG_SR_DRDY_Msk

#define	RNG_SR_CECS_Pos (1U)

#define	RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos)

#define	RNG_SR_CECS RNG_SR_CECS_Msk

#define	RNG_SR_SECS_Pos (2U)

#define	RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos)

#define	RNG_SR_SECS RNG_SR_SECS_Msk

#define	RNG_SR_CEIS_Pos (5U)

#define	RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos)

#define	RNG_SR_CEIS RNG_SR_CEIS_Msk

#define	RNG_SR_SEIS_Pos (6U)

#define	RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos)

#define	RNG_SR_SEIS RNG_SR_SEIS_Msk

#define	RTC_TR_PM_Pos (22U)

#define	RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos)

#define	RTC_TR_PM RTC_TR_PM_Msk

#define	RTC_TR_HT_Pos (20U)

#define	RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos)

#define	RTC_TR_HT RTC_TR_HT_Msk

#define	RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos)

#define	RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos)

#define	RTC_TR_HU_Pos (16U)

#define	RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos)

#define	RTC_TR_HU RTC_TR_HU_Msk

#define	RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos)

#define	RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos)

#define	RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos)

#define	RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos)

#define	RTC_TR_MNT_Pos (12U)

#define	RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos)

#define	RTC_TR_MNT RTC_TR_MNT_Msk

#define	RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos)

#define	RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos)

#define	RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos)

#define	RTC_TR_MNU_Pos (8U)

#define	RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos)

#define	RTC_TR_MNU RTC_TR_MNU_Msk

#define	RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos)

#define	RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos)

#define	RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos)

#define	RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos)

#define	RTC_TR_ST_Pos (4U)

#define	RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos)

#define	RTC_TR_ST RTC_TR_ST_Msk

#define	RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos)

#define	RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos)

#define	RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos)

#define	RTC_TR_SU_Pos (0U)

#define	RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos)

#define	RTC_TR_SU RTC_TR_SU_Msk

#define	RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos)

#define	RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos)

#define	RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos)

#define	RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos)

#define	RTC_DR_YT_Pos (20U)

#define	RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos)

#define	RTC_DR_YT RTC_DR_YT_Msk

#define	RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos)

#define	RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos)

#define	RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos)

#define	RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos)

#define	RTC_DR_YU_Pos (16U)

#define	RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos)

#define	RTC_DR_YU RTC_DR_YU_Msk

#define	RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos)

#define	RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos)

#define	RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos)

#define	RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos)

#define	RTC_DR_WDU_Pos (13U)

#define	RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos)

#define	RTC_DR_WDU RTC_DR_WDU_Msk

#define	RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos)

#define	RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos)

#define	RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos)

#define	RTC_DR_MT_Pos (12U)

#define	RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos)

#define	RTC_DR_MT RTC_DR_MT_Msk

#define	RTC_DR_MU_Pos (8U)

#define	RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos)

#define	RTC_DR_MU RTC_DR_MU_Msk

#define	RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos)

#define	RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos)

#define	RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos)

#define	RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos)

#define	RTC_DR_DT_Pos (4U)

#define	RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos)

#define	RTC_DR_DT RTC_DR_DT_Msk

#define	RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos)

#define	RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos)

#define	RTC_DR_DU_Pos (0U)

#define	RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos)

#define	RTC_DR_DU RTC_DR_DU_Msk

#define	RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos)

#define	RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos)

#define	RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos)

#define	RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos)

#define	RTC_SSR_SS_Pos (0U)

#define	RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos)

#define	RTC_SSR_SS RTC_SSR_SS_Msk

#define	RTC_ICSR_RECALPF_Pos (16U)

#define	RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos)

#define	RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk

#define	RTC_ICSR_INIT_Pos (7U)

#define	RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos)

#define	RTC_ICSR_INIT RTC_ICSR_INIT_Msk

#define	RTC_ICSR_INITF_Pos (6U)

#define	RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos)

#define	RTC_ICSR_INITF RTC_ICSR_INITF_Msk

#define	RTC_ICSR_RSF_Pos (5U)

#define	RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos)

#define	RTC_ICSR_RSF RTC_ICSR_RSF_Msk

#define	RTC_ICSR_INITS_Pos (4U)

#define	RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos)

#define	RTC_ICSR_INITS RTC_ICSR_INITS_Msk

#define	RTC_ICSR_SHPF_Pos (3U)

#define	RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos)

#define	RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk

#define	RTC_ICSR_WUTWF_Pos (2U)

#define	RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos)

#define	RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk

#define	RTC_ICSR_ALRBWF_Pos (1U)

#define	RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos)

#define	RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk

#define	RTC_ICSR_ALRAWF_Pos (0U)

#define	RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos)

#define	RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk

#define	RTC_PRER_PREDIV_A_Pos (16U)

#define	RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos)

#define	RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk

#define	RTC_PRER_PREDIV_S_Pos (0U)

#define	RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)

#define	RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk

#define	RTC_WUTR_WUT_Pos (0U)

#define	RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos)

#define	RTC_WUTR_WUT RTC_WUTR_WUT_Msk

#define	RTC_CR_OUT2EN_Pos (31U)

#define	RTC_CR_OUT2EN_Msk (0x1UL << RTC_CR_OUT2EN_Pos)

#define	RTC_CR_OUT2EN RTC_CR_OUT2EN_Msk

#define	RTC_CR_TAMPALRM_TYPE_Pos (30U)

#define	RTC_CR_TAMPALRM_TYPE_Msk (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos)

#define	RTC_CR_TAMPALRM_TYPE RTC_CR_TAMPALRM_TYPE_Msk

#define	RTC_CR_TAMPALRM_PU_Pos (29U)

#define	RTC_CR_TAMPALRM_PU_Msk (0x1UL << RTC_CR_TAMPALRM_PU_Pos)

#define	RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk

#define	RTC_CR_TAMPOE_Pos (26U)

#define	RTC_CR_TAMPOE_Msk (0x1UL << RTC_CR_TAMPOE_Pos)

#define	RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk

#define	RTC_CR_TAMPTS_Pos (25U)

#define	RTC_CR_TAMPTS_Msk (0x1UL << RTC_CR_TAMPTS_Pos)

#define	RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk

#define	RTC_CR_ITSE_Pos (24U)

#define	RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos)

#define	RTC_CR_ITSE RTC_CR_ITSE_Msk

#define	RTC_CR_COE_Pos (23U)

#define	RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos)

#define	RTC_CR_COE RTC_CR_COE_Msk

#define	RTC_CR_OSEL_Pos (21U)

#define	RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos)

#define	RTC_CR_OSEL RTC_CR_OSEL_Msk

#define	RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos)

#define	RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos)

#define	RTC_CR_POL_Pos (20U)

#define	RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos)

#define	RTC_CR_POL RTC_CR_POL_Msk

#define	RTC_CR_COSEL_Pos (19U)

#define	RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos)

#define	RTC_CR_COSEL RTC_CR_COSEL_Msk

#define	RTC_CR_BKP_Pos (18U)

#define	RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos)

#define	RTC_CR_BKP RTC_CR_BKP_Msk

#define	RTC_CR_SUB1H_Pos (17U)

#define	RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos)

#define	RTC_CR_SUB1H RTC_CR_SUB1H_Msk

#define	RTC_CR_ADD1H_Pos (16U)

#define	RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos)

#define	RTC_CR_ADD1H RTC_CR_ADD1H_Msk

#define	RTC_CR_TSIE_Pos (15U)

#define	RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos)

#define	RTC_CR_TSIE RTC_CR_TSIE_Msk

#define	RTC_CR_WUTIE_Pos (14U)

#define	RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos)

#define	RTC_CR_WUTIE RTC_CR_WUTIE_Msk

#define	RTC_CR_ALRBIE_Pos (13U)

#define	RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos)

#define	RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk

#define	RTC_CR_ALRAIE_Pos (12U)

#define	RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos)

#define	RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk

#define	RTC_CR_TSE_Pos (11U)

#define	RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos)

#define	RTC_CR_TSE RTC_CR_TSE_Msk

#define	RTC_CR_WUTE_Pos (10U)

#define	RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos)

#define	RTC_CR_WUTE RTC_CR_WUTE_Msk

#define	RTC_CR_ALRBE_Pos (9U)

#define	RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos)

#define	RTC_CR_ALRBE RTC_CR_ALRBE_Msk

#define	RTC_CR_ALRAE_Pos (8U)

#define	RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos)

#define	RTC_CR_ALRAE RTC_CR_ALRAE_Msk

#define	RTC_CR_FMT_Pos (6U)

#define	RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos)

#define	RTC_CR_FMT RTC_CR_FMT_Msk

#define	RTC_CR_BYPSHAD_Pos (5U)

#define	RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos)

#define	RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk

#define	RTC_CR_REFCKON_Pos (4U)

#define	RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos)

#define	RTC_CR_REFCKON RTC_CR_REFCKON_Msk

#define	RTC_CR_TSEDGE_Pos (3U)

#define	RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos)

#define	RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk

#define	RTC_CR_WUCKSEL_Pos (0U)

#define	RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos)

#define	RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk

#define	RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos)

#define	RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos)

#define	RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos)

#define	RTC_WPR_KEY_Pos (0U)

#define	RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos)

#define	RTC_WPR_KEY RTC_WPR_KEY_Msk

#define	RTC_CALR_CALP_Pos (15U)

#define	RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos)

#define	RTC_CALR_CALP RTC_CALR_CALP_Msk

#define	RTC_CALR_CALW8_Pos (14U)

#define	RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos)

#define	RTC_CALR_CALW8 RTC_CALR_CALW8_Msk

#define	RTC_CALR_CALW16_Pos (13U)

#define	RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos)

#define	RTC_CALR_CALW16 RTC_CALR_CALW16_Msk

#define	RTC_CALR_CALM_Pos (0U)

#define	RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos)

#define	RTC_CALR_CALM RTC_CALR_CALM_Msk

#define	RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos)

#define	RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos)

#define	RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos)

#define	RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos)

#define	RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos)

#define	RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos)

#define	RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos)

#define	RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos)

#define	RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos)

#define	RTC_SHIFTR_SUBFS_Pos (0U)

#define	RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)

#define	RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk

#define	RTC_SHIFTR_ADD1S_Pos (31U)

#define	RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos)

#define	RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk

#define	RTC_TSTR_PM_Pos (22U)

#define	RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos)

#define	RTC_TSTR_PM RTC_TSTR_PM_Msk

#define	RTC_TSTR_HT_Pos (20U)

#define	RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos)

#define	RTC_TSTR_HT RTC_TSTR_HT_Msk

#define	RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos)

#define	RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos)

#define	RTC_TSTR_HU_Pos (16U)

#define	RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos)

#define	RTC_TSTR_HU RTC_TSTR_HU_Msk

#define	RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos)

#define	RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos)

#define	RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos)

#define	RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos)

#define	RTC_TSTR_MNT_Pos (12U)

#define	RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos)

#define	RTC_TSTR_MNT RTC_TSTR_MNT_Msk

#define	RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos)

#define	RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos)

#define	RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos)

#define	RTC_TSTR_MNU_Pos (8U)

#define	RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos)

#define	RTC_TSTR_MNU RTC_TSTR_MNU_Msk

#define	RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos)

#define	RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos)

#define	RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos)

#define	RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos)

#define	RTC_TSTR_ST_Pos (4U)

#define	RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos)

#define	RTC_TSTR_ST RTC_TSTR_ST_Msk

#define	RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos)

#define	RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos)

#define	RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos)

#define	RTC_TSTR_SU_Pos (0U)

#define	RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos)

#define	RTC_TSTR_SU RTC_TSTR_SU_Msk

#define	RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos)

#define	RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos)

#define	RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos)

#define	RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos)

#define	RTC_TSDR_WDU_Pos (13U)

#define	RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos)

#define	RTC_TSDR_WDU RTC_TSDR_WDU_Msk

#define	RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos)

#define	RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos)

#define	RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos)

#define	RTC_TSDR_MT_Pos (12U)

#define	RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos)

#define	RTC_TSDR_MT RTC_TSDR_MT_Msk

#define	RTC_TSDR_MU_Pos (8U)

#define	RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos)

#define	RTC_TSDR_MU RTC_TSDR_MU_Msk

#define	RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos)

#define	RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos)

#define	RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos)

#define	RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos)

#define	RTC_TSDR_DT_Pos (4U)

#define	RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos)

#define	RTC_TSDR_DT RTC_TSDR_DT_Msk

#define	RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos)

#define	RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos)

#define	RTC_TSDR_DU_Pos (0U)

#define	RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos)

#define	RTC_TSDR_DU RTC_TSDR_DU_Msk

#define	RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos)

#define	RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos)

#define	RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos)

#define	RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos)

#define	RTC_TSSSR_SS_Pos (0U)

#define	RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos)

#define	RTC_TSSSR_SS RTC_TSSSR_SS_Msk

#define	RTC_ALRMAR_MSK4_Pos (31U)

#define	RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos)

#define	RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk

#define	RTC_ALRMAR_WDSEL_Pos (30U)

#define	RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos)

#define	RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk

#define	RTC_ALRMAR_DT_Pos (28U)

#define	RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos)

#define	RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk

#define	RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos)

#define	RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos)

#define	RTC_ALRMAR_DU_Pos (24U)

#define	RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos)

#define	RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk

#define	RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos)

#define	RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos)

#define	RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos)

#define	RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos)

#define	RTC_ALRMAR_MSK3_Pos (23U)

#define	RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos)

#define	RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk

#define	RTC_ALRMAR_PM_Pos (22U)

#define	RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos)

#define	RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk

#define	RTC_ALRMAR_HT_Pos (20U)

#define	RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos)

#define	RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk

#define	RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos)

#define	RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos)

#define	RTC_ALRMAR_HU_Pos (16U)

#define	RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos)

#define	RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk

#define	RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos)

#define	RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos)

#define	RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos)

#define	RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos)

#define	RTC_ALRMAR_MSK2_Pos (15U)

#define	RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos)

#define	RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk

#define	RTC_ALRMAR_MNT_Pos (12U)

#define	RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos)

#define	RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk

#define	RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos)

#define	RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos)

#define	RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos)

#define	RTC_ALRMAR_MNU_Pos (8U)

#define	RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos)

#define	RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk

#define	RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos)

#define	RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos)

#define	RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos)

#define	RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos)

#define	RTC_ALRMAR_MSK1_Pos (7U)

#define	RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos)

#define	RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk

#define	RTC_ALRMAR_ST_Pos (4U)

#define	RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos)

#define	RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk

#define	RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos)

#define	RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos)

#define	RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos)

#define	RTC_ALRMAR_SU_Pos (0U)

#define	RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos)

#define	RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk

#define	RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos)

#define	RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos)

#define	RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos)

#define	RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos)

#define	RTC_ALRMASSR_MASKSS_Pos (24U)

#define	RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos)

#define	RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk

#define	RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos)

#define	RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos)

#define	RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos)

#define	RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos)

#define	RTC_ALRMASSR_SS_Pos (0U)

#define	RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos)

#define	RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk

#define	RTC_ALRMBR_MSK4_Pos (31U)

#define	RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos)

#define	RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk

#define	RTC_ALRMBR_WDSEL_Pos (30U)

#define	RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos)

#define	RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk

#define	RTC_ALRMBR_DT_Pos (28U)

#define	RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos)

#define	RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk

#define	RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos)

#define	RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos)

#define	RTC_ALRMBR_DU_Pos (24U)

#define	RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos)

#define	RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk

#define	RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos)

#define	RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos)

#define	RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos)

#define	RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos)

#define	RTC_ALRMBR_MSK3_Pos (23U)

#define	RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos)

#define	RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk

#define	RTC_ALRMBR_PM_Pos (22U)

#define	RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos)

#define	RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk

#define	RTC_ALRMBR_HT_Pos (20U)

#define	RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos)

#define	RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk

#define	RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos)

#define	RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos)

#define	RTC_ALRMBR_HU_Pos (16U)

#define	RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos)

#define	RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk

#define	RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos)

#define	RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos)

#define	RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos)

#define	RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos)

#define	RTC_ALRMBR_MSK2_Pos (15U)

#define	RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos)

#define	RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk

#define	RTC_ALRMBR_MNT_Pos (12U)

#define	RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos)

#define	RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk

#define	RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos)

#define	RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos)

#define	RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos)

#define	RTC_ALRMBR_MNU_Pos (8U)

#define	RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos)

#define	RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk

#define	RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos)

#define	RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos)

#define	RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos)

#define	RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos)

#define	RTC_ALRMBR_MSK1_Pos (7U)

#define	RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos)

#define	RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk

#define	RTC_ALRMBR_ST_Pos (4U)

#define	RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos)

#define	RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk

#define	RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos)

#define	RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos)

#define	RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos)

#define	RTC_ALRMBR_SU_Pos (0U)

#define	RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos)

#define	RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk

#define	RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos)

#define	RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos)

#define	RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos)

#define	RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos)

#define	RTC_ALRMBSSR_MASKSS_Pos (24U)

#define	RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)

#define	RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk

#define	RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)

#define	RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)

#define	RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)

#define	RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)

#define	RTC_ALRMBSSR_SS_Pos (0U)

#define	RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)

#define	RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk

#define	RTC_SR_ITSF_Pos (5U)

#define	RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos)

#define	RTC_SR_ITSF RTC_SR_ITSF_Msk

#define	RTC_SR_TSOVF_Pos (4U)

#define	RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos)

#define	RTC_SR_TSOVF RTC_SR_TSOVF_Msk

#define	RTC_SR_TSF_Pos (3U)

#define	RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos)

#define	RTC_SR_TSF RTC_SR_TSF_Msk

#define	RTC_SR_WUTF_Pos (2U)

#define	RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos)

#define	RTC_SR_WUTF RTC_SR_WUTF_Msk

#define	RTC_SR_ALRBF_Pos (1U)

#define	RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos)

#define	RTC_SR_ALRBF RTC_SR_ALRBF_Msk

#define	RTC_SR_ALRAF_Pos (0U)

#define	RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos)

#define	RTC_SR_ALRAF RTC_SR_ALRAF_Msk

#define	RTC_MISR_ITSMF_Pos (5U)

#define	RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos)

#define	RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk

#define	RTC_MISR_TSOVMF_Pos (4U)

#define	RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos)

#define	RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk

#define	RTC_MISR_TSMF_Pos (3U)

#define	RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos)

#define	RTC_MISR_TSMF RTC_MISR_TSMF_Msk

#define	RTC_MISR_WUTMF_Pos (2U)

#define	RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos)

#define	RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk

#define	RTC_MISR_ALRBMF_Pos (1U)

#define	RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos)

#define	RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk

#define	RTC_MISR_ALRAMF_Pos (0U)

#define	RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos)

#define	RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk

#define	RTC_SCR_CITSF_Pos (5U)

#define	RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos)

#define	RTC_SCR_CITSF RTC_SCR_CITSF_Msk

#define	RTC_SCR_CTSOVF_Pos (4U)

#define	RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos)

#define	RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk

#define	RTC_SCR_CTSF_Pos (3U)

#define	RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos)

#define	RTC_SCR_CTSF RTC_SCR_CTSF_Msk

#define	RTC_SCR_CWUTF_Pos (2U)

#define	RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos)

#define	RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk

#define	RTC_SCR_CALRBF_Pos (1U)

#define	RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos)

#define	RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk

#define	RTC_SCR_CALRAF_Pos (0U)

#define	RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos)

#define	RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk

#define	TAMP_CR1_TAMP1E_Pos (0U)

#define	TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos)

#define	TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk

#define	TAMP_CR1_TAMP2E_Pos (1U)

#define	TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos)

#define	TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk

#define	TAMP_CR1_TAMP3E_Pos (2U)

#define	TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos)

#define	TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk

#define	TAMP_CR1_ITAMP3E_Pos (18U)

#define	TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos)

#define	TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk

#define	TAMP_CR1_ITAMP4E_Pos (19U)

#define	TAMP_CR1_ITAMP4E_Msk (0x1UL << TAMP_CR1_ITAMP4E_Pos)

#define	TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk

#define	TAMP_CR1_ITAMP5E_Pos (20U)

#define	TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos)

#define	TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk

#define	TAMP_CR1_ITAMP6E_Pos (21U)

#define	TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos)

#define	TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk

#define	TAMP_CR2_TAMP1NOERASE_Pos (0U)

#define	TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos)

#define	TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk

#define	TAMP_CR2_TAMP2NOERASE_Pos (1U)

#define	TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos)

#define	TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk

#define	TAMP_CR2_TAMP3NOERASE_Pos (2U)

#define	TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos)

#define	TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk

#define	TAMP_CR2_TAMP1MF_Pos (16U)

#define	TAMP_CR2_TAMP1MF_Msk (0x1UL << TAMP_CR2_TAMP1MF_Pos)

#define	TAMP_CR2_TAMP1MF TAMP_CR2_TAMP1MF_Msk

#define	TAMP_CR2_TAMP2MF_Pos (17U)

#define	TAMP_CR2_TAMP2MF_Msk (0x1UL << TAMP_CR2_TAMP2MF_Pos)

#define	TAMP_CR2_TAMP2MF TAMP_CR2_TAMP2MF_Msk

#define	TAMP_CR2_TAMP3MF_Pos (18U)

#define	TAMP_CR2_TAMP3MF_Msk (0x1UL << TAMP_CR2_TAMP3MF_Pos)

#define	TAMP_CR2_TAMP3MF TAMP_CR2_TAMP3MF_Msk

#define	TAMP_CR2_TAMP1TRG_Pos (24U)

#define	TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos)

#define	TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk

#define	TAMP_CR2_TAMP2TRG_Pos (25U)

#define	TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos)

#define	TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk

#define	TAMP_CR2_TAMP3TRG_Pos (26U)

#define	TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos)

#define	TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk

#define	TAMP_FLTCR_TAMPFREQ_0 (0x00000001UL)

#define	TAMP_FLTCR_TAMPFREQ_1 (0x00000002UL)

#define	TAMP_FLTCR_TAMPFREQ_2 (0x00000004UL)

#define	TAMP_FLTCR_TAMPFREQ_Pos (0U)

#define	TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos)

#define	TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk

#define	TAMP_FLTCR_TAMPFLT_0 (0x00000008UL)

#define	TAMP_FLTCR_TAMPFLT_1 (0x00000010UL)

#define	TAMP_FLTCR_TAMPFLT_Pos (3U)

#define	TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos)

#define	TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk

#define	TAMP_FLTCR_TAMPPRCH_0 (0x00000020UL)

#define	TAMP_FLTCR_TAMPPRCH_1 (0x00000040UL)

#define	TAMP_FLTCR_TAMPPRCH_Pos (5U)

#define	TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos)

#define	TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk

#define	TAMP_FLTCR_TAMPPUDIS_Pos (7U)

#define	TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos)

#define	TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk

#define	TAMP_IER_TAMP1IE_Pos (0U)

#define	TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos)

#define	TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk

#define	TAMP_IER_TAMP2IE_Pos (1U)

#define	TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos)

#define	TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk

#define	TAMP_IER_TAMP3IE_Pos (2U)

#define	TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos)

#define	TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk

#define	TAMP_IER_ITAMP3IE_Pos (18U)

#define	TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos)

#define	TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk

#define	TAMP_IER_ITAMP4IE_Pos (19U)

#define	TAMP_IER_ITAMP4IE_Msk (0x1UL << TAMP_IER_ITAMP4IE_Pos)

#define	TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk

#define	TAMP_IER_ITAMP5IE_Pos (20U)

#define	TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos)

#define	TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk

#define	TAMP_IER_ITAMP6IE_Pos (21U)

#define	TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos)

#define	TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk

#define	TAMP_SR_TAMP1F_Pos (0U)

#define	TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos)

#define	TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk

#define	TAMP_SR_TAMP2F_Pos (1U)

#define	TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos)

#define	TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk

#define	TAMP_SR_TAMP3F_Pos (2U)

#define	TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos)

#define	TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk

#define	TAMP_SR_ITAMP3F_Pos (18U)

#define	TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos)

#define	TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk

#define	TAMP_SR_ITAMP4F_Pos (19U)

#define	TAMP_SR_ITAMP4F_Msk (0x1UL << TAMP_SR_ITAMP4F_Pos)

#define	TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk

#define	TAMP_SR_ITAMP5F_Pos (20U)

#define	TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos)

#define	TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk

#define	TAMP_SR_ITAMP6F_Pos (21U)

#define	TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos)

#define	TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk

#define	TAMP_MISR_TAMP1MF_Pos (0U)

#define	TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos)

#define	TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk

#define	TAMP_MISR_TAMP2MF_Pos (1U)

#define	TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos)

#define	TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk

#define	TAMP_MISR_TAMP3MF_Pos (2U)

#define	TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos)

#define	TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk

#define	TAMP_MISR_ITAMP3MF_Pos (18U)

#define	TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos)

#define	TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk

#define	TAMP_MISR_ITAMP4MF_Pos (19U)

#define	TAMP_MISR_ITAMP4MF_Msk (0x1UL << TAMP_MISR_ITAMP4MF_Pos)

#define	TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk

#define	TAMP_MISR_ITAMP5MF_Pos (20U)

#define	TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos)

#define	TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk

#define	TAMP_MISR_ITAMP6MF_Pos (21U)

#define	TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos)

#define	TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk

#define	TAMP_SCR_CTAMP1F_Pos (0U)

#define	TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos)

#define	TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk

#define	TAMP_SCR_CTAMP2F_Pos (1U)

#define	TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos)

#define	TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk

#define	TAMP_SCR_CTAMP3F_Pos (2U)

#define	TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos)

#define	TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk

#define	TAMP_SCR_CITAMP3F_Pos (18U)

#define	TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos)

#define	TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk

#define	TAMP_SCR_CITAMP4F_Pos (19U)

#define	TAMP_SCR_CITAMP4F_Msk (0x1UL << TAMP_SCR_CITAMP4F_Pos)

#define	TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk

#define	TAMP_SCR_CITAMP5F_Pos (20U)

#define	TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos)

#define	TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk

#define	TAMP_SCR_CITAMP6F_Pos (21U)

#define	TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos)

#define	TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk

#define	TAMP_BKP0R_Pos (0U)

#define	TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos)

#define	TAMP_BKP0R TAMP_BKP0R_Msk

#define	TAMP_BKP1R_Pos (0U)

#define	TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos)

#define	TAMP_BKP1R TAMP_BKP1R_Msk

#define	TAMP_BKP2R_Pos (0U)

#define	TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos)

#define	TAMP_BKP2R TAMP_BKP2R_Msk

#define	TAMP_BKP3R_Pos (0U)

#define	TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos)

#define	TAMP_BKP3R TAMP_BKP3R_Msk

#define	TAMP_BKP4R_Pos (0U)

#define	TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos)

#define	TAMP_BKP4R TAMP_BKP4R_Msk

#define	TAMP_BKP5R_Pos (0U)

#define	TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos)

#define	TAMP_BKP5R TAMP_BKP5R_Msk

#define	TAMP_BKP6R_Pos (0U)

#define	TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos)

#define	TAMP_BKP6R TAMP_BKP6R_Msk

#define	TAMP_BKP7R_Pos (0U)

#define	TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos)

#define	TAMP_BKP7R TAMP_BKP7R_Msk

#define	TAMP_BKP8R_Pos (0U)

#define	TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos)

#define	TAMP_BKP8R TAMP_BKP8R_Msk

#define	TAMP_BKP9R_Pos (0U)

#define	TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos)

#define	TAMP_BKP9R TAMP_BKP9R_Msk

#define	TAMP_BKP10R_Pos (0U)

#define	TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos)

#define	TAMP_BKP10R TAMP_BKP10R_Msk

#define	TAMP_BKP11R_Pos (0U)

#define	TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos)

#define	TAMP_BKP11R TAMP_BKP11R_Msk

#define	TAMP_BKP12R_Pos (0U)

#define	TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos)

#define	TAMP_BKP12R TAMP_BKP12R_Msk

#define	TAMP_BKP13R_Pos (0U)

#define	TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos)

#define	TAMP_BKP13R TAMP_BKP13R_Msk

#define	TAMP_BKP14R_Pos (0U)

#define	TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos)

#define	TAMP_BKP14R TAMP_BKP14R_Msk

#define	TAMP_BKP15R_Pos (0U)

#define	TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos)

#define	TAMP_BKP15R TAMP_BKP15R_Msk

#define	SAI_GCR_SYNCIN_Pos (0U)

#define	SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos)

#define	SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk

#define	SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos)

#define	SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos)

#define	SAI_GCR_SYNCOUT_Pos (4U)

#define	SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos)

#define	SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk

#define	SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos)

#define	SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos)

#define	SAI_xCR1_MODE_Pos (0U)

#define	SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos)

#define	SAI_xCR1_MODE SAI_xCR1_MODE_Msk

#define	SAI_xCR1_MODE_0 (0x1UL << SAI_xCR1_MODE_Pos)

#define	SAI_xCR1_MODE_1 (0x2UL << SAI_xCR1_MODE_Pos)

#define	SAI_xCR1_PRTCFG_Pos (2U)

#define	SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos)

#define	SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk

#define	SAI_xCR1_PRTCFG_0 (0x1UL << SAI_xCR1_PRTCFG_Pos)

#define	SAI_xCR1_PRTCFG_1 (0x2UL << SAI_xCR1_PRTCFG_Pos)

#define	SAI_xCR1_DS_Pos (5U)

#define	SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos)

#define	SAI_xCR1_DS SAI_xCR1_DS_Msk

#define	SAI_xCR1_DS_0 (0x1UL << SAI_xCR1_DS_Pos)

#define	SAI_xCR1_DS_1 (0x2UL << SAI_xCR1_DS_Pos)

#define	SAI_xCR1_DS_2 (0x4UL << SAI_xCR1_DS_Pos)

#define	SAI_xCR1_LSBFIRST_Pos (8U)

#define	SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos)

#define	SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk

#define	SAI_xCR1_CKSTR_Pos (9U)

#define	SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos)

#define	SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk

#define	SAI_xCR1_SYNCEN_Pos (10U)

#define	SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos)

#define	SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk

#define	SAI_xCR1_SYNCEN_0 (0x1UL << SAI_xCR1_SYNCEN_Pos)

#define	SAI_xCR1_SYNCEN_1 (0x2UL << SAI_xCR1_SYNCEN_Pos)

#define	SAI_xCR1_MONO_Pos (12U)

#define	SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos)

#define	SAI_xCR1_MONO SAI_xCR1_MONO_Msk

#define	SAI_xCR1_OUTDRIV_Pos (13U)

#define	SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos)

#define	SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk

#define	SAI_xCR1_SAIEN_Pos (16U)

#define	SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos)

#define	SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk

#define	SAI_xCR1_DMAEN_Pos (17U)

#define	SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos)

#define	SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk

#define	SAI_xCR1_NODIV_Pos (19U)

#define	SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos)

#define	SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk

#define	SAI_xCR1_MCKDIV_Pos (20U)

#define	SAI_xCR1_MCKDIV_Msk (0x3FUL << SAI_xCR1_MCKDIV_Pos)

#define	SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk

#define	SAI_xCR1_MCKDIV_0 (0x00100000U)

#define	SAI_xCR1_MCKDIV_1 (0x00200000U)

#define	SAI_xCR1_MCKDIV_2 (0x00400000U)

#define	SAI_xCR1_MCKDIV_3 (0x00800000U)

#define	SAI_xCR1_MCKDIV_4 (0x01000000U)

#define	SAI_xCR1_MCKDIV_5 (0x02000000U)

#define	SAI_xCR1_OSR_Pos (26U)

#define	SAI_xCR1_OSR_Msk (0x1UL << SAI_xCR1_OSR_Pos)

#define	SAI_xCR1_OSR SAI_xCR1_OSR_Msk

#define	SAI_xCR1_MCKEN_Pos (27U)

#define	SAI_xCR1_MCKEN_Msk (0x1UL << SAI_xCR1_MCKEN_Pos)

#define	SAI_xCR1_MCKEN SAI_xCR1_MCKEN_Msk

#define	SAI_xCR2_FTH_Pos (0U)

#define	SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos)

#define	SAI_xCR2_FTH SAI_xCR2_FTH_Msk

#define	SAI_xCR2_FTH_0 (0x1UL << SAI_xCR2_FTH_Pos)

#define	SAI_xCR2_FTH_1 (0x2UL << SAI_xCR2_FTH_Pos)

#define	SAI_xCR2_FTH_2 (0x4UL << SAI_xCR2_FTH_Pos)

#define	SAI_xCR2_FFLUSH_Pos (3U)

#define	SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos)

#define	SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk

#define	SAI_xCR2_TRIS_Pos (4U)

#define	SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos)

#define	SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk

#define	SAI_xCR2_MUTE_Pos (5U)

#define	SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos)

#define	SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk

#define	SAI_xCR2_MUTEVAL_Pos (6U)

#define	SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos)

#define	SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk

#define	SAI_xCR2_MUTECNT_Pos (7U)

#define	SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos)

#define	SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk

#define	SAI_xCR2_MUTECNT_0 (0x01UL << SAI_xCR2_MUTECNT_Pos)

#define	SAI_xCR2_MUTECNT_1 (0x02UL << SAI_xCR2_MUTECNT_Pos)

#define	SAI_xCR2_MUTECNT_2 (0x04UL << SAI_xCR2_MUTECNT_Pos)

#define	SAI_xCR2_MUTECNT_3 (0x08UL << SAI_xCR2_MUTECNT_Pos)

#define	SAI_xCR2_MUTECNT_4 (0x10UL << SAI_xCR2_MUTECNT_Pos)

#define	SAI_xCR2_MUTECNT_5 (0x20UL << SAI_xCR2_MUTECNT_Pos)

#define	SAI_xCR2_CPL_Pos (13U)

#define	SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos)

#define	SAI_xCR2_CPL SAI_xCR2_CPL_Msk

#define	SAI_xCR2_COMP_Pos (14U)

#define	SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos)

#define	SAI_xCR2_COMP SAI_xCR2_COMP_Msk

#define	SAI_xCR2_COMP_0 (0x1UL << SAI_xCR2_COMP_Pos)

#define	SAI_xCR2_COMP_1 (0x2UL << SAI_xCR2_COMP_Pos)

#define	SAI_xFRCR_FRL_Pos (0U)

#define	SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos)

#define	SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk

#define	SAI_xFRCR_FRL_0 (0x01UL << SAI_xFRCR_FRL_Pos)

#define	SAI_xFRCR_FRL_1 (0x02UL << SAI_xFRCR_FRL_Pos)

#define	SAI_xFRCR_FRL_2 (0x04UL << SAI_xFRCR_FRL_Pos)

#define	SAI_xFRCR_FRL_3 (0x08UL << SAI_xFRCR_FRL_Pos)

#define	SAI_xFRCR_FRL_4 (0x10UL << SAI_xFRCR_FRL_Pos)

#define	SAI_xFRCR_FRL_5 (0x20UL << SAI_xFRCR_FRL_Pos)

#define	SAI_xFRCR_FRL_6 (0x40UL << SAI_xFRCR_FRL_Pos)

#define	SAI_xFRCR_FRL_7 (0x80UL << SAI_xFRCR_FRL_Pos)

#define	SAI_xFRCR_FSALL_Pos (8U)

#define	SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos)

#define	SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk

#define	SAI_xFRCR_FSALL_0 (0x01UL << SAI_xFRCR_FSALL_Pos)

#define	SAI_xFRCR_FSALL_1 (0x02UL << SAI_xFRCR_FSALL_Pos)

#define	SAI_xFRCR_FSALL_2 (0x04UL << SAI_xFRCR_FSALL_Pos)

#define	SAI_xFRCR_FSALL_3 (0x08UL << SAI_xFRCR_FSALL_Pos)

#define	SAI_xFRCR_FSALL_4 (0x10UL << SAI_xFRCR_FSALL_Pos)

#define	SAI_xFRCR_FSALL_5 (0x20UL << SAI_xFRCR_FSALL_Pos)

#define	SAI_xFRCR_FSALL_6 (0x40UL << SAI_xFRCR_FSALL_Pos)

#define	SAI_xFRCR_FSDEF_Pos (16U)

#define	SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos)

#define	SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk

#define	SAI_xFRCR_FSPOL_Pos (17U)

#define	SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos)

#define	SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk

#define	SAI_xFRCR_FSOFF_Pos (18U)

#define	SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos)

#define	SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk

#define	SAI_xSLOTR_FBOFF_Pos (0U)

#define	SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos)

#define	SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk

#define	SAI_xSLOTR_FBOFF_0 (0x01UL << SAI_xSLOTR_FBOFF_Pos)

#define	SAI_xSLOTR_FBOFF_1 (0x02UL << SAI_xSLOTR_FBOFF_Pos)

#define	SAI_xSLOTR_FBOFF_2 (0x04UL << SAI_xSLOTR_FBOFF_Pos)

#define	SAI_xSLOTR_FBOFF_3 (0x08UL << SAI_xSLOTR_FBOFF_Pos)

#define	SAI_xSLOTR_FBOFF_4 (0x10UL << SAI_xSLOTR_FBOFF_Pos)

#define	SAI_xSLOTR_SLOTSZ_Pos (6U)

#define	SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)

#define	SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk

#define	SAI_xSLOTR_SLOTSZ_0 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)

#define	SAI_xSLOTR_SLOTSZ_1 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)

#define	SAI_xSLOTR_NBSLOT_Pos (8U)

#define	SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos)

#define	SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk

#define	SAI_xSLOTR_NBSLOT_0 (0x1UL << SAI_xSLOTR_NBSLOT_Pos)

#define	SAI_xSLOTR_NBSLOT_1 (0x2UL << SAI_xSLOTR_NBSLOT_Pos)

#define	SAI_xSLOTR_NBSLOT_2 (0x4UL << SAI_xSLOTR_NBSLOT_Pos)

#define	SAI_xSLOTR_NBSLOT_3 (0x8UL << SAI_xSLOTR_NBSLOT_Pos)

#define	SAI_xSLOTR_SLOTEN_Pos (16U)

#define	SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)

#define	SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk

#define	SAI_xIMR_OVRUDRIE_Pos (0U)

#define	SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos)

#define	SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk

#define	SAI_xIMR_MUTEDETIE_Pos (1U)

#define	SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos)

#define	SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk

#define	SAI_xIMR_WCKCFGIE_Pos (2U)

#define	SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos)

#define	SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk

#define	SAI_xIMR_FREQIE_Pos (3U)

#define	SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos)

#define	SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk

#define	SAI_xIMR_CNRDYIE_Pos (4U)

#define	SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos)

#define	SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk

#define	SAI_xIMR_AFSDETIE_Pos (5U)

#define	SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos)

#define	SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk

#define	SAI_xIMR_LFSDETIE_Pos (6U)

#define	SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos)

#define	SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk

#define	SAI_xSR_OVRUDR_Pos (0U)

#define	SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos)

#define	SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk

#define	SAI_xSR_MUTEDET_Pos (1U)

#define	SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos)

#define	SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk

#define	SAI_xSR_WCKCFG_Pos (2U)

#define	SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos)

#define	SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk

#define	SAI_xSR_FREQ_Pos (3U)

#define	SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos)

#define	SAI_xSR_FREQ SAI_xSR_FREQ_Msk

#define	SAI_xSR_CNRDY_Pos (4U)

#define	SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos)

#define	SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk

#define	SAI_xSR_AFSDET_Pos (5U)

#define	SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos)

#define	SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk

#define	SAI_xSR_LFSDET_Pos (6U)

#define	SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos)

#define	SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk

#define	SAI_xSR_FLVL_Pos (16U)

#define	SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos)

#define	SAI_xSR_FLVL SAI_xSR_FLVL_Msk

#define	SAI_xSR_FLVL_0 (0x1UL << SAI_xSR_FLVL_Pos)

#define	SAI_xSR_FLVL_1 (0x2UL << SAI_xSR_FLVL_Pos)

#define	SAI_xSR_FLVL_2 (0x4UL << SAI_xSR_FLVL_Pos)

#define	SAI_xCLRFR_COVRUDR_Pos (0U)

#define	SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos)

#define	SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk

#define	SAI_xCLRFR_CMUTEDET_Pos (1U)

#define	SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)

#define	SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk

#define	SAI_xCLRFR_CWCKCFG_Pos (2U)

#define	SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)

#define	SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk

#define	SAI_xCLRFR_CFREQ_Pos (3U)

#define	SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos)

#define	SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk

#define	SAI_xCLRFR_CCNRDY_Pos (4U)

#define	SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos)

#define	SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk

#define	SAI_xCLRFR_CAFSDET_Pos (5U)

#define	SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos)

#define	SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk

#define	SAI_xCLRFR_CLFSDET_Pos (6U)

#define	SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos)

#define	SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk

#define	SAI_xDR_DATA_Pos (0U)

#define	SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)

#define	SAI_xDR_DATA SAI_xDR_DATA_Msk

#define	SAI_PDMCR_PDMEN_Pos (0U)

#define	SAI_PDMCR_PDMEN_Msk (0x1UL << SAI_PDMCR_PDMEN_Pos)

#define	SAI_PDMCR_PDMEN SAI_PDMCR_PDMEN_Msk

#define	SAI_PDMCR_MICNBR_Pos (4U)

#define	SAI_PDMCR_MICNBR_Msk (0x3UL << SAI_PDMCR_MICNBR_Pos)

#define	SAI_PDMCR_MICNBR SAI_PDMCR_MICNBR_Msk

#define	SAI_PDMCR_MICNBR_0 (0x1UL << SAI_PDMCR_MICNBR_Pos)

#define	SAI_PDMCR_MICNBR_1 (0x2UL << SAI_PDMCR_MICNBR_Pos)

#define	SAI_PDMCR_CKEN1_Pos (8U)

#define	SAI_PDMCR_CKEN1_Msk (0x1UL << SAI_PDMCR_CKEN1_Pos)

#define	SAI_PDMCR_CKEN1 SAI_PDMCR_CKEN1_Msk

#define	SAI_PDMCR_CKEN2_Pos (9U)

#define	SAI_PDMCR_CKEN2_Msk (0x1UL << SAI_PDMCR_CKEN2_Pos)

#define	SAI_PDMCR_CKEN2 SAI_PDMCR_CKEN2_Msk

#define	SAI_PDMCR_CKEN3_Pos (10U)

#define	SAI_PDMCR_CKEN3_Msk (0x1UL << SAI_PDMCR_CKEN3_Pos)

#define	SAI_PDMCR_CKEN3 SAI_PDMCR_CKEN3_Msk

#define	SAI_PDMCR_CKEN4_Pos (11U)

#define	SAI_PDMCR_CKEN4_Msk (0x1UL << SAI_PDMCR_CKEN4_Pos)

#define	SAI_PDMCR_CKEN4 SAI_PDMCR_CKEN4_Msk

#define	SAI_PDMDLY_DLYM1L_Pos (0U)

#define	SAI_PDMDLY_DLYM1L_Msk (0x7UL << SAI_PDMDLY_DLYM1L_Pos)

#define	SAI_PDMDLY_DLYM1L SAI_PDMDLY_DLYM1L_Msk

#define	SAI_PDMDLY_DLYM1L_0 (0x1UL << SAI_PDMDLY_DLYM1L_Pos)

#define	SAI_PDMDLY_DLYM1L_1 (0x2UL << SAI_PDMDLY_DLYM1L_Pos)

#define	SAI_PDMDLY_DLYM1L_2 (0x4UL << SAI_PDMDLY_DLYM1L_Pos)

#define	SAI_PDMDLY_DLYM1R_Pos (4U)

#define	SAI_PDMDLY_DLYM1R_Msk (0x7UL << SAI_PDMDLY_DLYM1R_Pos)

#define	SAI_PDMDLY_DLYM1R SAI_PDMDLY_DLYM1R_Msk

#define	SAI_PDMDLY_DLYM1R_0 (0x1UL << SAI_PDMDLY_DLYM1R_Pos)

#define	SAI_PDMDLY_DLYM1R_1 (0x2UL << SAI_PDMDLY_DLYM1R_Pos)

#define	SAI_PDMDLY_DLYM1R_2 (0x4UL << SAI_PDMDLY_DLYM1R_Pos)

#define	SAI_PDMDLY_DLYM2L_Pos (8U)

#define	SAI_PDMDLY_DLYM2L_Msk (0x7UL << SAI_PDMDLY_DLYM2L_Pos)

#define	SAI_PDMDLY_DLYM2L SAI_PDMDLY_DLYM2L_Msk

#define	SAI_PDMDLY_DLYM2L_0 (0x1UL << SAI_PDMDLY_DLYM2L_Pos)

#define	SAI_PDMDLY_DLYM2L_1 (0x2UL << SAI_PDMDLY_DLYM2L_Pos)

#define	SAI_PDMDLY_DLYM2L_2 (0x4UL << SAI_PDMDLY_DLYM2L_Pos)

#define	SAI_PDMDLY_DLYM2R_Pos (12U)

#define	SAI_PDMDLY_DLYM2R_Msk (0x7UL << SAI_PDMDLY_DLYM2R_Pos)

#define	SAI_PDMDLY_DLYM2R SAI_PDMDLY_DLYM2R_Msk

#define	SAI_PDMDLY_DLYM2R_0 (0x1UL << SAI_PDMDLY_DLYM2R_Pos)

#define	SAI_PDMDLY_DLYM2R_1 (0x2UL << SAI_PDMDLY_DLYM2R_Pos)

#define	SAI_PDMDLY_DLYM2R_2 (0x4UL << SAI_PDMDLY_DLYM2R_Pos)

#define	SAI_PDMDLY_DLYM3L_Pos (16U)

#define	SAI_PDMDLY_DLYM3L_Msk (0x7UL << SAI_PDMDLY_DLYM3L_Pos)

#define	SAI_PDMDLY_DLYM3L SAI_PDMDLY_DLYM3L_Msk

#define	SAI_PDMDLY_DLYM3L_0 (0x1UL << SAI_PDMDLY_DLYM3L_Pos)

#define	SAI_PDMDLY_DLYM3L_1 (0x2UL << SAI_PDMDLY_DLYM3L_Pos)

#define	SAI_PDMDLY_DLYM3L_2 (0x4UL << SAI_PDMDLY_DLYM3L_Pos)

#define	SAI_PDMDLY_DLYM3R_Pos (20U)

#define	SAI_PDMDLY_DLYM3R_Msk (0x7UL << SAI_PDMDLY_DLYM3R_Pos)

#define	SAI_PDMDLY_DLYM3R SAI_PDMDLY_DLYM3R_Msk

#define	SAI_PDMDLY_DLYM3R_0 (0x1UL << SAI_PDMDLY_DLYM3R_Pos)

#define	SAI_PDMDLY_DLYM3R_1 (0x2UL << SAI_PDMDLY_DLYM3R_Pos)

#define	SAI_PDMDLY_DLYM3R_2 (0x4UL << SAI_PDMDLY_DLYM3R_Pos)

#define	SAI_PDMDLY_DLYM4L_Pos (24U)

#define	SAI_PDMDLY_DLYM4L_Msk (0x7UL << SAI_PDMDLY_DLYM4L_Pos)

#define	SAI_PDMDLY_DLYM4L SAI_PDMDLY_DLYM4L_Msk

#define	SAI_PDMDLY_DLYM4L_0 (0x1UL << SAI_PDMDLY_DLYM4L_Pos)

#define	SAI_PDMDLY_DLYM4L_1 (0x2UL << SAI_PDMDLY_DLYM4L_Pos)

#define	SAI_PDMDLY_DLYM4L_2 (0x4UL << SAI_PDMDLY_DLYM4L_Pos)

#define	SAI_PDMDLY_DLYM4R_Pos (28U)

#define	SAI_PDMDLY_DLYM4R_Msk (0x7UL << SAI_PDMDLY_DLYM4R_Pos)

#define	SAI_PDMDLY_DLYM4R SAI_PDMDLY_DLYM4R_Msk

#define	SAI_PDMDLY_DLYM4R_0 (0x1UL << SAI_PDMDLY_DLYM4R_Pos)

#define	SAI_PDMDLY_DLYM4R_1 (0x2UL << SAI_PDMDLY_DLYM4R_Pos)

#define	SAI_PDMDLY_DLYM4R_2 (0x4UL << SAI_PDMDLY_DLYM4R_Pos)

#define	SPI_I2S_SUPPORT

#define	SPI_CR1_CPHA_Pos (0U)

#define	SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos)

#define	SPI_CR1_CPHA SPI_CR1_CPHA_Msk

#define	SPI_CR1_CPOL_Pos (1U)

#define	SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos)

#define	SPI_CR1_CPOL SPI_CR1_CPOL_Msk

#define	SPI_CR1_MSTR_Pos (2U)

#define	SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos)

#define	SPI_CR1_MSTR SPI_CR1_MSTR_Msk

#define	SPI_CR1_BR_Pos (3U)

#define	SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos)

#define	SPI_CR1_BR SPI_CR1_BR_Msk

#define	SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos)

#define	SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos)

#define	SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos)

#define	SPI_CR1_SPE_Pos (6U)

#define	SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos)

#define	SPI_CR1_SPE SPI_CR1_SPE_Msk

#define	SPI_CR1_LSBFIRST_Pos (7U)

#define	SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos)

#define	SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk

#define	SPI_CR1_SSI_Pos (8U)

#define	SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos)

#define	SPI_CR1_SSI SPI_CR1_SSI_Msk

#define	SPI_CR1_SSM_Pos (9U)

#define	SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos)

#define	SPI_CR1_SSM SPI_CR1_SSM_Msk

#define	SPI_CR1_RXONLY_Pos (10U)

#define	SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos)

#define	SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk

#define	SPI_CR1_CRCL_Pos (11U)

#define	SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos)

#define	SPI_CR1_CRCL SPI_CR1_CRCL_Msk

#define	SPI_CR1_CRCNEXT_Pos (12U)

#define	SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos)

#define	SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk

#define	SPI_CR1_CRCEN_Pos (13U)

#define	SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos)

#define	SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk

#define	SPI_CR1_BIDIOE_Pos (14U)

#define	SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos)

#define	SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk

#define	SPI_CR1_BIDIMODE_Pos (15U)

#define	SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos)

#define	SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk

#define	SPI_CR2_RXDMAEN_Pos (0U)

#define	SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos)

#define	SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk

#define	SPI_CR2_TXDMAEN_Pos (1U)

#define	SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos)

#define	SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk

#define	SPI_CR2_SSOE_Pos (2U)

#define	SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos)

#define	SPI_CR2_SSOE SPI_CR2_SSOE_Msk

#define	SPI_CR2_NSSP_Pos (3U)

#define	SPI_CR2_NSSP_Msk (0x1UL << SPI_CR2_NSSP_Pos)

#define	SPI_CR2_NSSP SPI_CR2_NSSP_Msk

#define	SPI_CR2_FRF_Pos (4U)

#define	SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos)

#define	SPI_CR2_FRF SPI_CR2_FRF_Msk

#define	SPI_CR2_ERRIE_Pos (5U)

#define	SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos)

#define	SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk

#define	SPI_CR2_RXNEIE_Pos (6U)

#define	SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos)

#define	SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk

#define	SPI_CR2_TXEIE_Pos (7U)

#define	SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos)

#define	SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk

#define	SPI_CR2_DS_Pos (8U)

#define	SPI_CR2_DS_Msk (0xFUL << SPI_CR2_DS_Pos)

#define	SPI_CR2_DS SPI_CR2_DS_Msk

#define	SPI_CR2_DS_0 (0x1UL << SPI_CR2_DS_Pos)

#define	SPI_CR2_DS_1 (0x2UL << SPI_CR2_DS_Pos)

#define	SPI_CR2_DS_2 (0x4UL << SPI_CR2_DS_Pos)

#define	SPI_CR2_DS_3 (0x8UL << SPI_CR2_DS_Pos)

#define	SPI_CR2_FRXTH_Pos (12U)

#define	SPI_CR2_FRXTH_Msk (0x1UL << SPI_CR2_FRXTH_Pos)

#define	SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk

#define	SPI_CR2_LDMARX_Pos (13U)

#define	SPI_CR2_LDMARX_Msk (0x1UL << SPI_CR2_LDMARX_Pos)

#define	SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk

#define	SPI_CR2_LDMATX_Pos (14U)

#define	SPI_CR2_LDMATX_Msk (0x1UL << SPI_CR2_LDMATX_Pos)

#define	SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk

#define	SPI_SR_RXNE_Pos (0U)

#define	SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos)

#define	SPI_SR_RXNE SPI_SR_RXNE_Msk

#define	SPI_SR_TXE_Pos (1U)

#define	SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos)

#define	SPI_SR_TXE SPI_SR_TXE_Msk

#define	SPI_SR_CHSIDE_Pos (2U)

#define	SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos)

#define	SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk

#define	SPI_SR_UDR_Pos (3U)

#define	SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos)

#define	SPI_SR_UDR SPI_SR_UDR_Msk

#define	SPI_SR_CRCERR_Pos (4U)

#define	SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos)

#define	SPI_SR_CRCERR SPI_SR_CRCERR_Msk

#define	SPI_SR_MODF_Pos (5U)

#define	SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos)

#define	SPI_SR_MODF SPI_SR_MODF_Msk

#define	SPI_SR_OVR_Pos (6U)

#define	SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos)

#define	SPI_SR_OVR SPI_SR_OVR_Msk

#define	SPI_SR_BSY_Pos (7U)

#define	SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos)

#define	SPI_SR_BSY SPI_SR_BSY_Msk

#define	SPI_SR_FRE_Pos (8U)

#define	SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos)

#define	SPI_SR_FRE SPI_SR_FRE_Msk

#define	SPI_SR_FRLVL_Pos (9U)

#define	SPI_SR_FRLVL_Msk (0x3UL << SPI_SR_FRLVL_Pos)

#define	SPI_SR_FRLVL SPI_SR_FRLVL_Msk

#define	SPI_SR_FRLVL_0 (0x1UL << SPI_SR_FRLVL_Pos)

#define	SPI_SR_FRLVL_1 (0x2UL << SPI_SR_FRLVL_Pos)

#define	SPI_SR_FTLVL_Pos (11U)

#define	SPI_SR_FTLVL_Msk (0x3UL << SPI_SR_FTLVL_Pos)

#define	SPI_SR_FTLVL SPI_SR_FTLVL_Msk

#define	SPI_SR_FTLVL_0 (0x1UL << SPI_SR_FTLVL_Pos)

#define	SPI_SR_FTLVL_1 (0x2UL << SPI_SR_FTLVL_Pos)

#define	SPI_DR_DR_Pos (0U)

#define	SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos)

#define	SPI_DR_DR SPI_DR_DR_Msk

#define	SPI_CRCPR_CRCPOLY_Pos (0U)

#define	SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)

#define	SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk

#define	SPI_RXCRCR_RXCRC_Pos (0U)

#define	SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)

#define	SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk

#define	SPI_TXCRCR_TXCRC_Pos (0U)

#define	SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)

#define	SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk

#define	SPI_I2SCFGR_CHLEN_Pos (0U)

#define	SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos)

#define	SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk

#define	SPI_I2SCFGR_DATLEN_Pos (1U)

#define	SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos)

#define	SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk

#define	SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos)

#define	SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos)

#define	SPI_I2SCFGR_CKPOL_Pos (3U)

#define	SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos)

#define	SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk

#define	SPI_I2SCFGR_I2SSTD_Pos (4U)

#define	SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)

#define	SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk

#define	SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)

#define	SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)

#define	SPI_I2SCFGR_PCMSYNC_Pos (7U)

#define	SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)

#define	SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk

#define	SPI_I2SCFGR_I2SCFG_Pos (8U)

#define	SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)

#define	SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk

#define	SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)

#define	SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)

#define	SPI_I2SCFGR_I2SE_Pos (10U)

#define	SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos)

#define	SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk

#define	SPI_I2SCFGR_I2SMOD_Pos (11U)

#define	SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)

#define	SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk

#define	SPI_I2SCFGR_ASTRTEN_Pos (12U)

#define	SPI_I2SCFGR_ASTRTEN_Msk (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos)

#define	SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk

#define	SPI_I2SPR_I2SDIV_Pos (0U)

#define	SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos)

#define	SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk

#define	SPI_I2SPR_ODD_Pos (8U)

#define	SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos)

#define	SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk

#define	SPI_I2SPR_MCKOE_Pos (9U)

#define	SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos)

#define	SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk

#define	SYSCFG_MEMRMP_MEM_MODE_Pos (0U)

#define	SYSCFG_MEMRMP_MEM_MODE_Msk (0x7UL << SYSCFG_MEMRMP_MEM_MODE_Pos)

#define	SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk

#define	SYSCFG_MEMRMP_MEM_MODE_0 (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)

#define	SYSCFG_MEMRMP_MEM_MODE_1 (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)

#define	SYSCFG_MEMRMP_MEM_MODE_2 (0x4UL << SYSCFG_MEMRMP_MEM_MODE_Pos)

#define	SYSCFG_MEMRMP_FB_MODE_Pos (8U)

#define	SYSCFG_MEMRMP_FB_MODE_Msk (0x1UL << SYSCFG_MEMRMP_FB_MODE_Pos)

#define	SYSCFG_MEMRMP_FB_MODE SYSCFG_MEMRMP_FB_MODE_Msk

#define	SYSCFG_CFGR1_BOOSTEN_Pos (8U)

#define	SYSCFG_CFGR1_BOOSTEN_Msk (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos)

#define	SYSCFG_CFGR1_BOOSTEN SYSCFG_CFGR1_BOOSTEN_Msk

#define	SYSCFG_CFGR1_ANASWVDD_Pos (9U)

#define	SYSCFG_CFGR1_ANASWVDD_Msk (0x1UL << SYSCFG_CFGR1_ANASWVDD_Pos)

#define	SYSCFG_CFGR1_ANASWVDD SYSCFG_CFGR1_ANASWVDD_Msk

#define	SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U)

#define	SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos)

#define	SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk

#define	SYSCFG_CFGR1_I2C_PB7_FMP_Pos (17U)

#define	SYSCFG_CFGR1_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos)

#define	SYSCFG_CFGR1_I2C_PB7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk

#define	SYSCFG_CFGR1_I2C_PB8_FMP_Pos (18U)

#define	SYSCFG_CFGR1_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos)

#define	SYSCFG_CFGR1_I2C_PB8_FMP SYSCFG_CFGR1_I2C_PB8_FMP_Msk

#define	SYSCFG_CFGR1_I2C_PB9_FMP_Pos (19U)

#define	SYSCFG_CFGR1_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos)

#define	SYSCFG_CFGR1_I2C_PB9_FMP SYSCFG_CFGR1_I2C_PB9_FMP_Msk

#define	SYSCFG_CFGR1_I2C1_FMP_Pos (20U)

#define	SYSCFG_CFGR1_I2C1_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos)

#define	SYSCFG_CFGR1_I2C1_FMP SYSCFG_CFGR1_I2C1_FMP_Msk

#define	SYSCFG_CFGR1_I2C2_FMP_Pos (21U)

#define	SYSCFG_CFGR1_I2C2_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C2_FMP_Pos)

#define	SYSCFG_CFGR1_I2C2_FMP SYSCFG_CFGR1_I2C2_FMP_Msk

#define	SYSCFG_CFGR1_I2C3_FMP_Pos (22U)

#define	SYSCFG_CFGR1_I2C3_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C3_FMP_Pos)

#define	SYSCFG_CFGR1_I2C3_FMP SYSCFG_CFGR1_I2C3_FMP_Msk

#define	SYSCFG_CFGR1_FPU_IE_0 (0x04000000U)

#define	SYSCFG_CFGR1_FPU_IE_1 (0x08000000U)

#define	SYSCFG_CFGR1_FPU_IE_2 (0x10000000U)

#define	SYSCFG_CFGR1_FPU_IE_3 (0x20000000U)

#define	SYSCFG_CFGR1_FPU_IE_4 (0x40000000U)

#define	SYSCFG_CFGR1_FPU_IE_5 (0x80000000U)

#define	SYSCFG_EXTICR1_EXTI0_Pos (0U)

#define	SYSCFG_EXTICR1_EXTI0_Msk (0x7UL << SYSCFG_EXTICR1_EXTI0_Pos)

#define	SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk

#define	SYSCFG_EXTICR1_EXTI1_Pos (4U)

#define	SYSCFG_EXTICR1_EXTI1_Msk (0x7UL << SYSCFG_EXTICR1_EXTI1_Pos)

#define	SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk

#define	SYSCFG_EXTICR1_EXTI2_Pos (8U)

#define	SYSCFG_EXTICR1_EXTI2_Msk (0x7UL << SYSCFG_EXTICR1_EXTI2_Pos)

#define	SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk

#define	SYSCFG_EXTICR1_EXTI3_Pos (12U)

#define	SYSCFG_EXTICR1_EXTI3_Msk (0x7UL << SYSCFG_EXTICR1_EXTI3_Pos)

#define	SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk

#define	SYSCFG_EXTICR1_EXTI0_PA (0x00000000U)
	EXTI0 configuration. More...

#define	SYSCFG_EXTICR1_EXTI0_PB (0x00000001U)

#define	SYSCFG_EXTICR1_EXTI0_PC (0x00000002U)

#define	SYSCFG_EXTICR1_EXTI0_PD (0x00000003U)

#define	SYSCFG_EXTICR1_EXTI0_PE (0x00000004U)

#define	SYSCFG_EXTICR1_EXTI0_PF (0x00000005U)

#define	SYSCFG_EXTICR1_EXTI0_PG (0x00000006U)

#define	SYSCFG_EXTICR1_EXTI1_PA (0x00000000U)
	EXTI1 configuration. More...

#define	SYSCFG_EXTICR1_EXTI1_PB (0x00000010U)

#define	SYSCFG_EXTICR1_EXTI1_PC (0x00000020U)

#define	SYSCFG_EXTICR1_EXTI1_PD (0x00000030U)

#define	SYSCFG_EXTICR1_EXTI1_PE (0x00000040U)

#define	SYSCFG_EXTICR1_EXTI1_PF (0x00000050U)

#define	SYSCFG_EXTICR1_EXTI1_PG (0x00000060U)

#define	SYSCFG_EXTICR1_EXTI2_PA (0x00000000U)
	EXTI2 configuration. More...

#define	SYSCFG_EXTICR1_EXTI2_PB (0x00000100U)

#define	SYSCFG_EXTICR1_EXTI2_PC (0x00000200U)

#define	SYSCFG_EXTICR1_EXTI2_PD (0x00000300U)

#define	SYSCFG_EXTICR1_EXTI2_PE (0x00000400U)

#define	SYSCFG_EXTICR1_EXTI2_PF (0x00000500U)

#define	SYSCFG_EXTICR1_EXTI2_PG (0x00000600U)

#define	SYSCFG_EXTICR1_EXTI3_PA (0x00000000U)
	EXTI3 configuration. More...

#define	SYSCFG_EXTICR1_EXTI3_PB (0x00001000U)

#define	SYSCFG_EXTICR1_EXTI3_PC (0x00002000U)

#define	SYSCFG_EXTICR1_EXTI3_PD (0x00003000U)

#define	SYSCFG_EXTICR1_EXTI3_PE (0x00004000U)

#define	SYSCFG_EXTICR1_EXTI3_PF (0x00005000U)

#define	SYSCFG_EXTICR1_EXTI3_PG (0x00006000U)

#define	SYSCFG_EXTICR2_EXTI4_Pos (0U)

#define	SYSCFG_EXTICR2_EXTI4_Msk (0x7UL << SYSCFG_EXTICR2_EXTI4_Pos)

#define	SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk

#define	SYSCFG_EXTICR2_EXTI5_Pos (4U)

#define	SYSCFG_EXTICR2_EXTI5_Msk (0x7UL << SYSCFG_EXTICR2_EXTI5_Pos)

#define	SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk

#define	SYSCFG_EXTICR2_EXTI6_Pos (8U)

#define	SYSCFG_EXTICR2_EXTI6_Msk (0x7UL << SYSCFG_EXTICR2_EXTI6_Pos)

#define	SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk

#define	SYSCFG_EXTICR2_EXTI7_Pos (12U)

#define	SYSCFG_EXTICR2_EXTI7_Msk (0x7UL << SYSCFG_EXTICR2_EXTI7_Pos)

#define	SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk

#define	SYSCFG_EXTICR2_EXTI4_PA (0x00000000U)
	EXTI4 configuration. More...

#define	SYSCFG_EXTICR2_EXTI4_PB (0x00000001U)

#define	SYSCFG_EXTICR2_EXTI4_PC (0x00000002U)

#define	SYSCFG_EXTICR2_EXTI4_PD (0x00000003U)

#define	SYSCFG_EXTICR2_EXTI4_PE (0x00000004U)

#define	SYSCFG_EXTICR2_EXTI4_PF (0x00000005U)

#define	SYSCFG_EXTICR2_EXTI4_PG (0x00000006U)

#define	SYSCFG_EXTICR2_EXTI5_PA (0x00000000U)
	EXTI5 configuration. More...

#define	SYSCFG_EXTICR2_EXTI5_PB (0x00000010U)

#define	SYSCFG_EXTICR2_EXTI5_PC (0x00000020U)

#define	SYSCFG_EXTICR2_EXTI5_PD (0x00000030U)

#define	SYSCFG_EXTICR2_EXTI5_PE (0x00000040U)

#define	SYSCFG_EXTICR2_EXTI5_PF (0x00000050U)

#define	SYSCFG_EXTICR2_EXTI5_PG (0x00000060U)

#define	SYSCFG_EXTICR2_EXTI6_PA (0x00000000U)
	EXTI6 configuration. More...

#define	SYSCFG_EXTICR2_EXTI6_PB (0x00000100U)

#define	SYSCFG_EXTICR2_EXTI6_PC (0x00000200U)

#define	SYSCFG_EXTICR2_EXTI6_PD (0x00000300U)

#define	SYSCFG_EXTICR2_EXTI6_PE (0x00000400U)

#define	SYSCFG_EXTICR2_EXTI6_PF (0x00000500U)

#define	SYSCFG_EXTICR2_EXTI6_PG (0x00000600U)

#define	SYSCFG_EXTICR2_EXTI7_PA (0x00000000U)
	EXTI7 configuration. More...

#define	SYSCFG_EXTICR2_EXTI7_PB (0x00001000U)

#define	SYSCFG_EXTICR2_EXTI7_PC (0x00002000U)

#define	SYSCFG_EXTICR2_EXTI7_PD (0x00003000U)

#define	SYSCFG_EXTICR2_EXTI7_PE (0x00004000U)

#define	SYSCFG_EXTICR2_EXTI7_PF (0x00005000U)

#define	SYSCFG_EXTICR2_EXTI7_PG (0x00006000U)

#define	SYSCFG_EXTICR3_EXTI8_Pos (0U)

#define	SYSCFG_EXTICR3_EXTI8_Msk (0x7UL << SYSCFG_EXTICR3_EXTI8_Pos)

#define	SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk

#define	SYSCFG_EXTICR3_EXTI9_Pos (4U)

#define	SYSCFG_EXTICR3_EXTI9_Msk (0x7UL << SYSCFG_EXTICR3_EXTI9_Pos)

#define	SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk

#define	SYSCFG_EXTICR3_EXTI10_Pos (8U)

#define	SYSCFG_EXTICR3_EXTI10_Msk (0x7UL << SYSCFG_EXTICR3_EXTI10_Pos)

#define	SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk

#define	SYSCFG_EXTICR3_EXTI11_Pos (12U)

#define	SYSCFG_EXTICR3_EXTI11_Msk (0x7UL << SYSCFG_EXTICR3_EXTI11_Pos)

#define	SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk

#define	SYSCFG_EXTICR3_EXTI8_PA (0x00000000U)
	EXTI8 configuration. More...

#define	SYSCFG_EXTICR3_EXTI8_PB (0x00000001U)

#define	SYSCFG_EXTICR3_EXTI8_PC (0x00000002U)

#define	SYSCFG_EXTICR3_EXTI8_PD (0x00000003U)

#define	SYSCFG_EXTICR3_EXTI8_PE (0x00000004U)

#define	SYSCFG_EXTICR3_EXTI8_PF (0x00000005U)

#define	SYSCFG_EXTICR3_EXTI8_PG (0x00000006U)

#define	SYSCFG_EXTICR3_EXTI9_PA (0x00000000U)
	EXTI9 configuration. More...

#define	SYSCFG_EXTICR3_EXTI9_PB (0x00000010U)

#define	SYSCFG_EXTICR3_EXTI9_PC (0x00000020U)

#define	SYSCFG_EXTICR3_EXTI9_PD (0x00000030U)

#define	SYSCFG_EXTICR3_EXTI9_PE (0x00000040U)

#define	SYSCFG_EXTICR3_EXTI9_PF (0x00000050U)

#define	SYSCFG_EXTICR3_EXTI9_PG (0x00000060U)

#define	SYSCFG_EXTICR3_EXTI10_PA (0x00000000U)
	EXTI10 configuration. More...

#define	SYSCFG_EXTICR3_EXTI10_PB (0x00000100U)

#define	SYSCFG_EXTICR3_EXTI10_PC (0x00000200U)

#define	SYSCFG_EXTICR3_EXTI10_PD (0x00000300U)

#define	SYSCFG_EXTICR3_EXTI10_PE (0x00000400U)

#define	SYSCFG_EXTICR3_EXTI10_PF (0x00000500U)

#define	SYSCFG_EXTICR3_EXTI11_PA (0x00000000U)
	EXTI11 configuration. More...

#define	SYSCFG_EXTICR3_EXTI11_PB (0x00001000U)

#define	SYSCFG_EXTICR3_EXTI11_PC (0x00002000U)

#define	SYSCFG_EXTICR3_EXTI11_PD (0x00003000U)

#define	SYSCFG_EXTICR3_EXTI11_PE (0x00004000U)

#define	SYSCFG_EXTICR3_EXTI11_PF (0x00005000U)

#define	SYSCFG_EXTICR4_EXTI12_Pos (0U)

#define	SYSCFG_EXTICR4_EXTI12_Msk (0x7UL << SYSCFG_EXTICR4_EXTI12_Pos)

#define	SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk

#define	SYSCFG_EXTICR4_EXTI13_Pos (4U)

#define	SYSCFG_EXTICR4_EXTI13_Msk (0x7UL << SYSCFG_EXTICR4_EXTI13_Pos)

#define	SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk

#define	SYSCFG_EXTICR4_EXTI14_Pos (8U)

#define	SYSCFG_EXTICR4_EXTI14_Msk (0x7UL << SYSCFG_EXTICR4_EXTI14_Pos)

#define	SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk

#define	SYSCFG_EXTICR4_EXTI15_Pos (12U)

#define	SYSCFG_EXTICR4_EXTI15_Msk (0x7UL << SYSCFG_EXTICR4_EXTI15_Pos)

#define	SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk

#define	SYSCFG_EXTICR4_EXTI12_PA (0x00000000U)
	EXTI12 configuration. More...

#define	SYSCFG_EXTICR4_EXTI12_PB (0x00000001U)

#define	SYSCFG_EXTICR4_EXTI12_PC (0x00000002U)

#define	SYSCFG_EXTICR4_EXTI12_PD (0x00000003U)

#define	SYSCFG_EXTICR4_EXTI12_PE (0x00000004U)

#define	SYSCFG_EXTICR4_EXTI12_PF (0x00000005U)

#define	SYSCFG_EXTICR4_EXTI13_PA (0x00000000U)
	EXTI13 configuration. More...

#define	SYSCFG_EXTICR4_EXTI13_PB (0x00000010U)

#define	SYSCFG_EXTICR4_EXTI13_PC (0x00000020U)

#define	SYSCFG_EXTICR4_EXTI13_PD (0x00000030U)

#define	SYSCFG_EXTICR4_EXTI13_PE (0x00000040U)

#define	SYSCFG_EXTICR4_EXTI13_PF (0x00000050U)

#define	SYSCFG_EXTICR4_EXTI14_PA (0x00000000U)
	EXTI14 configuration. More...

#define	SYSCFG_EXTICR4_EXTI14_PB (0x00000100U)

#define	SYSCFG_EXTICR4_EXTI14_PC (0x00000200U)

#define	SYSCFG_EXTICR4_EXTI14_PD (0x00000300U)

#define	SYSCFG_EXTICR4_EXTI14_PE (0x00000400U)

#define	SYSCFG_EXTICR4_EXTI14_PF (0x00000500U)

#define	SYSCFG_EXTICR4_EXTI15_PA (0x00000000U)
	EXTI15 configuration. More...

#define	SYSCFG_EXTICR4_EXTI15_PB (0x00001000U)

#define	SYSCFG_EXTICR4_EXTI15_PC (0x00002000U)

#define	SYSCFG_EXTICR4_EXTI15_PD (0x00003000U)

#define	SYSCFG_EXTICR4_EXTI15_PE (0x00004000U)

#define	SYSCFG_EXTICR4_EXTI15_PF (0x00005000U)

#define	SYSCFG_SCSR_CCMER_Pos (0U)

#define	SYSCFG_SCSR_CCMER_Msk (0x1UL << SYSCFG_SCSR_CCMER_Pos)

#define	SYSCFG_SCSR_CCMER SYSCFG_SCSR_CCMER_Msk

#define	SYSCFG_SCSR_CCMBSY_Pos (1U)

#define	SYSCFG_SCSR_CCMBSY_Msk (0x1UL << SYSCFG_SCSR_CCMBSY_Pos)

#define	SYSCFG_SCSR_CCMBSY SYSCFG_SCSR_CCMBSY_Msk

#define	SYSCFG_CFGR2_CLL_Pos (0U)

#define	SYSCFG_CFGR2_CLL_Msk (0x1UL << SYSCFG_CFGR2_CLL_Pos)

#define	SYSCFG_CFGR2_CLL SYSCFG_CFGR2_CLL_Msk

#define	SYSCFG_CFGR2_SPL_Pos (1U)

#define	SYSCFG_CFGR2_SPL_Msk (0x1UL << SYSCFG_CFGR2_SPL_Pos)

#define	SYSCFG_CFGR2_SPL SYSCFG_CFGR2_SPL_Msk

#define	SYSCFG_CFGR2_PVDL_Pos (2U)

#define	SYSCFG_CFGR2_PVDL_Msk (0x1UL << SYSCFG_CFGR2_PVDL_Pos)

#define	SYSCFG_CFGR2_PVDL SYSCFG_CFGR2_PVDL_Msk

#define	SYSCFG_CFGR2_ECCL_Pos (3U)

#define	SYSCFG_CFGR2_ECCL_Msk (0x1UL << SYSCFG_CFGR2_ECCL_Pos)

#define	SYSCFG_CFGR2_ECCL SYSCFG_CFGR2_ECCL_Msk

#define	SYSCFG_CFGR2_SPF_Pos (8U)

#define	SYSCFG_CFGR2_SPF_Msk (0x1UL << SYSCFG_CFGR2_SPF_Pos)

#define	SYSCFG_CFGR2_SPF SYSCFG_CFGR2_SPF_Msk

#define	SYSCFG_SWPR_PAGE0_Pos (0U)

#define	SYSCFG_SWPR_PAGE0_Msk (0x1UL << SYSCFG_SWPR_PAGE0_Pos)

#define	SYSCFG_SWPR_PAGE0 (SYSCFG_SWPR_PAGE0_Msk)

#define	SYSCFG_SWPR_PAGE1_Pos (1U)

#define	SYSCFG_SWPR_PAGE1_Msk (0x1UL << SYSCFG_SWPR_PAGE1_Pos)

#define	SYSCFG_SWPR_PAGE1 (SYSCFG_SWPR_PAGE1_Msk)

#define	SYSCFG_SWPR_PAGE2_Pos (2U)

#define	SYSCFG_SWPR_PAGE2_Msk (0x1UL << SYSCFG_SWPR_PAGE2_Pos)

#define	SYSCFG_SWPR_PAGE2 (SYSCFG_SWPR_PAGE2_Msk)

#define	SYSCFG_SWPR_PAGE3_Pos (3U)

#define	SYSCFG_SWPR_PAGE3_Msk (0x1UL << SYSCFG_SWPR_PAGE3_Pos)

#define	SYSCFG_SWPR_PAGE3 (SYSCFG_SWPR_PAGE3_Msk)

#define	SYSCFG_SWPR_PAGE4_Pos (4U)

#define	SYSCFG_SWPR_PAGE4_Msk (0x1UL << SYSCFG_SWPR_PAGE4_Pos)

#define	SYSCFG_SWPR_PAGE4 (SYSCFG_SWPR_PAGE4_Msk)

#define	SYSCFG_SWPR_PAGE5_Pos (5U)

#define	SYSCFG_SWPR_PAGE5_Msk (0x1UL << SYSCFG_SWPR_PAGE5_Pos)

#define	SYSCFG_SWPR_PAGE5 (SYSCFG_SWPR_PAGE5_Msk)

#define	SYSCFG_SWPR_PAGE6_Pos (6U)

#define	SYSCFG_SWPR_PAGE6_Msk (0x1UL << SYSCFG_SWPR_PAGE6_Pos)

#define	SYSCFG_SWPR_PAGE6 (SYSCFG_SWPR_PAGE6_Msk)

#define	SYSCFG_SWPR_PAGE7_Pos (7U)

#define	SYSCFG_SWPR_PAGE7_Msk (0x1UL << SYSCFG_SWPR_PAGE7_Pos)

#define	SYSCFG_SWPR_PAGE7 (SYSCFG_SWPR_PAGE7_Msk)

#define	SYSCFG_SWPR_PAGE8_Pos (8U)

#define	SYSCFG_SWPR_PAGE8_Msk (0x1UL << SYSCFG_SWPR_PAGE8_Pos)

#define	SYSCFG_SWPR_PAGE8 (SYSCFG_SWPR_PAGE8_Msk)

#define	SYSCFG_SWPR_PAGE9_Pos (9U)

#define	SYSCFG_SWPR_PAGE9_Msk (0x1UL << SYSCFG_SWPR_PAGE9_Pos)

#define	SYSCFG_SWPR_PAGE9 (SYSCFG_SWPR_PAGE9_Msk)

#define	SYSCFG_SKR_KEY_Pos (0U)

#define	SYSCFG_SKR_KEY_Msk (0xFFUL << SYSCFG_SKR_KEY_Pos)

#define	SYSCFG_SKR_KEY SYSCFG_SKR_KEY_Msk

#define	TIM_CR1_CEN_Pos (0U)

#define	TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos)

#define	TIM_CR1_CEN TIM_CR1_CEN_Msk

#define	TIM_CR1_UDIS_Pos (1U)

#define	TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos)

#define	TIM_CR1_UDIS TIM_CR1_UDIS_Msk

#define	TIM_CR1_URS_Pos (2U)

#define	TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos)

#define	TIM_CR1_URS TIM_CR1_URS_Msk

#define	TIM_CR1_OPM_Pos (3U)

#define	TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos)

#define	TIM_CR1_OPM TIM_CR1_OPM_Msk

#define	TIM_CR1_DIR_Pos (4U)

#define	TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos)

#define	TIM_CR1_DIR TIM_CR1_DIR_Msk

#define	TIM_CR1_CMS_Pos (5U)

#define	TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos)

#define	TIM_CR1_CMS TIM_CR1_CMS_Msk

#define	TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos)

#define	TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos)

#define	TIM_CR1_ARPE_Pos (7U)

#define	TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos)

#define	TIM_CR1_ARPE TIM_CR1_ARPE_Msk

#define	TIM_CR1_CKD_Pos (8U)

#define	TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos)

#define	TIM_CR1_CKD TIM_CR1_CKD_Msk

#define	TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos)

#define	TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos)

#define	TIM_CR1_UIFREMAP_Pos (11U)

#define	TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos)

#define	TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk

#define	TIM_CR1_DITHEN_Pos (12U)

#define	TIM_CR1_DITHEN_Msk (0x1UL << TIM_CR1_DITHEN_Pos)

#define	TIM_CR1_DITHEN TIM_CR1_DITHEN_Msk

#define	TIM_CR2_CCPC_Pos (0U)

#define	TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos)

#define	TIM_CR2_CCPC TIM_CR2_CCPC_Msk

#define	TIM_CR2_CCUS_Pos (2U)

#define	TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos)

#define	TIM_CR2_CCUS TIM_CR2_CCUS_Msk

#define	TIM_CR2_CCDS_Pos (3U)

#define	TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos)

#define	TIM_CR2_CCDS TIM_CR2_CCDS_Msk

#define	TIM_CR2_MMS_Pos (4U)

#define	TIM_CR2_MMS_Msk (0x200007UL << TIM_CR2_MMS_Pos)

#define	TIM_CR2_MMS TIM_CR2_MMS_Msk

#define	TIM_CR2_MMS_0 (0x000001UL << TIM_CR2_MMS_Pos)

#define	TIM_CR2_MMS_1 (0x000002UL << TIM_CR2_MMS_Pos)

#define	TIM_CR2_MMS_2 (0x000004UL << TIM_CR2_MMS_Pos)

#define	TIM_CR2_MMS_3 (0x200000UL << TIM_CR2_MMS_Pos)

#define	TIM_CR2_TI1S_Pos (7U)

#define	TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos)

#define	TIM_CR2_TI1S TIM_CR2_TI1S_Msk

#define	TIM_CR2_OIS1_Pos (8U)

#define	TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos)

#define	TIM_CR2_OIS1 TIM_CR2_OIS1_Msk

#define	TIM_CR2_OIS1N_Pos (9U)

#define	TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos)

#define	TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk

#define	TIM_CR2_OIS2_Pos (10U)

#define	TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos)

#define	TIM_CR2_OIS2 TIM_CR2_OIS2_Msk

#define	TIM_CR2_OIS2N_Pos (11U)

#define	TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos)

#define	TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk

#define	TIM_CR2_OIS3_Pos (12U)

#define	TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos)

#define	TIM_CR2_OIS3 TIM_CR2_OIS3_Msk

#define	TIM_CR2_OIS3N_Pos (13U)

#define	TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos)

#define	TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk

#define	TIM_CR2_OIS4_Pos (14U)

#define	TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos)

#define	TIM_CR2_OIS4 TIM_CR2_OIS4_Msk

#define	TIM_CR2_OIS4N_Pos (15U)

#define	TIM_CR2_OIS4N_Msk (0x1UL << TIM_CR2_OIS4N_Pos)

#define	TIM_CR2_OIS4N TIM_CR2_OIS4N_Msk

#define	TIM_CR2_OIS5_Pos (16U)

#define	TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos)

#define	TIM_CR2_OIS5 TIM_CR2_OIS5_Msk

#define	TIM_CR2_OIS6_Pos (18U)

#define	TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos)

#define	TIM_CR2_OIS6 TIM_CR2_OIS6_Msk

#define	TIM_CR2_MMS2_Pos (20U)

#define	TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos)

#define	TIM_CR2_MMS2 TIM_CR2_MMS2_Msk

#define	TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos)

#define	TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos)

#define	TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos)

#define	TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos)

#define	TIM_SMCR_SMS_Pos (0U)

#define	TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos)

#define	TIM_SMCR_SMS TIM_SMCR_SMS_Msk

#define	TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos)

#define	TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos)

#define	TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos)

#define	TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos)

#define	TIM_SMCR_OCCS_Pos (3U)

#define	TIM_SMCR_OCCS_Msk (0x1UL << TIM_SMCR_OCCS_Pos)

#define	TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk

#define	TIM_SMCR_TS_Pos (4U)

#define	TIM_SMCR_TS_Msk (0x30007UL << TIM_SMCR_TS_Pos)

#define	TIM_SMCR_TS TIM_SMCR_TS_Msk

#define	TIM_SMCR_TS_0 (0x00001UL << TIM_SMCR_TS_Pos)

#define	TIM_SMCR_TS_1 (0x00002UL << TIM_SMCR_TS_Pos)

#define	TIM_SMCR_TS_2 (0x00004UL << TIM_SMCR_TS_Pos)

#define	TIM_SMCR_TS_3 (0x10000UL << TIM_SMCR_TS_Pos)

#define	TIM_SMCR_TS_4 (0x20000UL << TIM_SMCR_TS_Pos)

#define	TIM_SMCR_MSM_Pos (7U)

#define	TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos)

#define	TIM_SMCR_MSM TIM_SMCR_MSM_Msk

#define	TIM_SMCR_ETF_Pos (8U)

#define	TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos)

#define	TIM_SMCR_ETF TIM_SMCR_ETF_Msk

#define	TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos)

#define	TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos)

#define	TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos)

#define	TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos)

#define	TIM_SMCR_ETPS_Pos (12U)

#define	TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos)

#define	TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk

#define	TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos)

#define	TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos)

#define	TIM_SMCR_ECE_Pos (14U)

#define	TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos)

#define	TIM_SMCR_ECE TIM_SMCR_ECE_Msk

#define	TIM_SMCR_ETP_Pos (15U)

#define	TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos)

#define	TIM_SMCR_ETP TIM_SMCR_ETP_Msk

#define	TIM_SMCR_SMSPE_Pos (24U)

#define	TIM_SMCR_SMSPE_Msk (0x1UL << TIM_SMCR_SMSPE_Pos)

#define	TIM_SMCR_SMSPE TIM_SMCR_SMSPE_Msk

#define	TIM_SMCR_SMSPS_Pos (25U)

#define	TIM_SMCR_SMSPS_Msk (0x1UL << TIM_SMCR_SMSPS_Pos)

#define	TIM_SMCR_SMSPS TIM_SMCR_SMSPS_Msk

#define	TIM_DIER_UIE_Pos (0U)

#define	TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos)

#define	TIM_DIER_UIE TIM_DIER_UIE_Msk

#define	TIM_DIER_CC1IE_Pos (1U)

#define	TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos)

#define	TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk

#define	TIM_DIER_CC2IE_Pos (2U)

#define	TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos)

#define	TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk

#define	TIM_DIER_CC3IE_Pos (3U)

#define	TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos)

#define	TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk

#define	TIM_DIER_CC4IE_Pos (4U)

#define	TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos)

#define	TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk

#define	TIM_DIER_COMIE_Pos (5U)

#define	TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos)

#define	TIM_DIER_COMIE TIM_DIER_COMIE_Msk

#define	TIM_DIER_TIE_Pos (6U)

#define	TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos)

#define	TIM_DIER_TIE TIM_DIER_TIE_Msk

#define	TIM_DIER_BIE_Pos (7U)

#define	TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos)

#define	TIM_DIER_BIE TIM_DIER_BIE_Msk

#define	TIM_DIER_UDE_Pos (8U)

#define	TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos)

#define	TIM_DIER_UDE TIM_DIER_UDE_Msk

#define	TIM_DIER_CC1DE_Pos (9U)

#define	TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos)

#define	TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk

#define	TIM_DIER_CC2DE_Pos (10U)

#define	TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos)

#define	TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk

#define	TIM_DIER_CC3DE_Pos (11U)

#define	TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos)

#define	TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk

#define	TIM_DIER_CC4DE_Pos (12U)

#define	TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos)

#define	TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk

#define	TIM_DIER_COMDE_Pos (13U)

#define	TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos)

#define	TIM_DIER_COMDE TIM_DIER_COMDE_Msk

#define	TIM_DIER_TDE_Pos (14U)

#define	TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos)

#define	TIM_DIER_TDE TIM_DIER_TDE_Msk

#define	TIM_DIER_IDXIE_Pos (20U)

#define	TIM_DIER_IDXIE_Msk (0x1UL << TIM_DIER_IDXIE_Pos)

#define	TIM_DIER_IDXIE TIM_DIER_IDXIE_Msk

#define	TIM_DIER_DIRIE_Pos (21U)

#define	TIM_DIER_DIRIE_Msk (0x1UL << TIM_DIER_DIRIE_Pos)

#define	TIM_DIER_DIRIE TIM_DIER_DIRIE_Msk

#define	TIM_DIER_IERRIE_Pos (22U)

#define	TIM_DIER_IERRIE_Msk (0x1UL << TIM_DIER_IERRIE_Pos)

#define	TIM_DIER_IERRIE TIM_DIER_IERRIE_Msk

#define	TIM_DIER_TERRIE_Pos (23U)

#define	TIM_DIER_TERRIE_Msk (0x1UL << TIM_DIER_TERRIE_Pos)

#define	TIM_DIER_TERRIE TIM_DIER_TERRIE_Msk

#define	TIM_SR_UIF_Pos (0U)

#define	TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos)

#define	TIM_SR_UIF TIM_SR_UIF_Msk

#define	TIM_SR_CC1IF_Pos (1U)

#define	TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos)

#define	TIM_SR_CC1IF TIM_SR_CC1IF_Msk

#define	TIM_SR_CC2IF_Pos (2U)

#define	TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos)

#define	TIM_SR_CC2IF TIM_SR_CC2IF_Msk

#define	TIM_SR_CC3IF_Pos (3U)

#define	TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos)

#define	TIM_SR_CC3IF TIM_SR_CC3IF_Msk

#define	TIM_SR_CC4IF_Pos (4U)

#define	TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos)

#define	TIM_SR_CC4IF TIM_SR_CC4IF_Msk

#define	TIM_SR_COMIF_Pos (5U)

#define	TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos)

#define	TIM_SR_COMIF TIM_SR_COMIF_Msk

#define	TIM_SR_TIF_Pos (6U)

#define	TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos)

#define	TIM_SR_TIF TIM_SR_TIF_Msk

#define	TIM_SR_BIF_Pos (7U)

#define	TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos)

#define	TIM_SR_BIF TIM_SR_BIF_Msk

#define	TIM_SR_B2IF_Pos (8U)

#define	TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos)

#define	TIM_SR_B2IF TIM_SR_B2IF_Msk

#define	TIM_SR_CC1OF_Pos (9U)

#define	TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos)

#define	TIM_SR_CC1OF TIM_SR_CC1OF_Msk

#define	TIM_SR_CC2OF_Pos (10U)

#define	TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos)

#define	TIM_SR_CC2OF TIM_SR_CC2OF_Msk

#define	TIM_SR_CC3OF_Pos (11U)

#define	TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos)

#define	TIM_SR_CC3OF TIM_SR_CC3OF_Msk

#define	TIM_SR_CC4OF_Pos (12U)

#define	TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos)

#define	TIM_SR_CC4OF TIM_SR_CC4OF_Msk

#define	TIM_SR_SBIF_Pos (13U)

#define	TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos)

#define	TIM_SR_SBIF TIM_SR_SBIF_Msk

#define	TIM_SR_CC5IF_Pos (16U)

#define	TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos)

#define	TIM_SR_CC5IF TIM_SR_CC5IF_Msk

#define	TIM_SR_CC6IF_Pos (17U)

#define	TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos)

#define	TIM_SR_CC6IF TIM_SR_CC6IF_Msk

#define	TIM_SR_IDXF_Pos (20U)

#define	TIM_SR_IDXF_Msk (0x1UL << TIM_SR_IDXF_Pos)

#define	TIM_SR_IDXF TIM_SR_IDXF_Msk

#define	TIM_SR_DIRF_Pos (21U)

#define	TIM_SR_DIRF_Msk (0x1UL << TIM_SR_DIRF_Pos)

#define	TIM_SR_DIRF TIM_SR_DIRF_Msk

#define	TIM_SR_IERRF_Pos (22U)

#define	TIM_SR_IERRF_Msk (0x1UL << TIM_SR_IERRF_Pos)

#define	TIM_SR_IERRF TIM_SR_IERRF_Msk

#define	TIM_SR_TERRF_Pos (23U)

#define	TIM_SR_TERRF_Msk (0x1UL << TIM_SR_TERRF_Pos)

#define	TIM_SR_TERRF TIM_SR_TERRF_Msk

#define	TIM_EGR_UG_Pos (0U)

#define	TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos)

#define	TIM_EGR_UG TIM_EGR_UG_Msk

#define	TIM_EGR_CC1G_Pos (1U)

#define	TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos)

#define	TIM_EGR_CC1G TIM_EGR_CC1G_Msk

#define	TIM_EGR_CC2G_Pos (2U)

#define	TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos)

#define	TIM_EGR_CC2G TIM_EGR_CC2G_Msk

#define	TIM_EGR_CC3G_Pos (3U)

#define	TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos)

#define	TIM_EGR_CC3G TIM_EGR_CC3G_Msk

#define	TIM_EGR_CC4G_Pos (4U)

#define	TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos)

#define	TIM_EGR_CC4G TIM_EGR_CC4G_Msk

#define	TIM_EGR_COMG_Pos (5U)

#define	TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos)

#define	TIM_EGR_COMG TIM_EGR_COMG_Msk

#define	TIM_EGR_TG_Pos (6U)

#define	TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos)

#define	TIM_EGR_TG TIM_EGR_TG_Msk

#define	TIM_EGR_BG_Pos (7U)

#define	TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos)

#define	TIM_EGR_BG TIM_EGR_BG_Msk

#define	TIM_EGR_B2G_Pos (8U)

#define	TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos)

#define	TIM_EGR_B2G TIM_EGR_B2G_Msk

#define	TIM_CCMR1_CC1S_Pos (0U)

#define	TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos)

#define	TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk

#define	TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos)

#define	TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos)

#define	TIM_CCMR1_OC1FE_Pos (2U)

#define	TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos)

#define	TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk

#define	TIM_CCMR1_OC1PE_Pos (3U)

#define	TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos)

#define	TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk

#define	TIM_CCMR1_OC1M_Pos (4U)

#define	TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos)

#define	TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk

#define	TIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos)

#define	TIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos)

#define	TIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos)

#define	TIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos)

#define	TIM_CCMR1_OC1CE_Pos (7U)

#define	TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos)

#define	TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk

#define	TIM_CCMR1_CC2S_Pos (8U)

#define	TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos)

#define	TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk

#define	TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos)

#define	TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos)

#define	TIM_CCMR1_OC2FE_Pos (10U)

#define	TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos)

#define	TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk

#define	TIM_CCMR1_OC2PE_Pos (11U)

#define	TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos)

#define	TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk

#define	TIM_CCMR1_OC2M_Pos (12U)

#define	TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos)

#define	TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk

#define	TIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos)

#define	TIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos)

#define	TIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos)

#define	TIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos)

#define	TIM_CCMR1_OC2CE_Pos (15U)

#define	TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos)

#define	TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk

#define	TIM_CCMR1_IC1PSC_Pos (2U)

#define	TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos)

#define	TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk

#define	TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos)

#define	TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos)

#define	TIM_CCMR1_IC1F_Pos (4U)

#define	TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos)

#define	TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk

#define	TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos)

#define	TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos)

#define	TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos)

#define	TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos)

#define	TIM_CCMR1_IC2PSC_Pos (10U)

#define	TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos)

#define	TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk

#define	TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos)

#define	TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos)

#define	TIM_CCMR1_IC2F_Pos (12U)

#define	TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos)

#define	TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk

#define	TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos)

#define	TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos)

#define	TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos)

#define	TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos)

#define	TIM_CCMR2_CC3S_Pos (0U)

#define	TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos)

#define	TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk

#define	TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos)

#define	TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos)

#define	TIM_CCMR2_OC3FE_Pos (2U)

#define	TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos)

#define	TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk

#define	TIM_CCMR2_OC3PE_Pos (3U)

#define	TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos)

#define	TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk

#define	TIM_CCMR2_OC3M_Pos (4U)

#define	TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos)

#define	TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk

#define	TIM_CCMR2_OC3M_0 (0x0001UL << TIM_CCMR2_OC3M_Pos)

#define	TIM_CCMR2_OC3M_1 (0x0002UL << TIM_CCMR2_OC3M_Pos)

#define	TIM_CCMR2_OC3M_2 (0x0004UL << TIM_CCMR2_OC3M_Pos)

#define	TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos)

#define	TIM_CCMR2_OC3CE_Pos (7U)

#define	TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos)

#define	TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk

#define	TIM_CCMR2_CC4S_Pos (8U)

#define	TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos)

#define	TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk

#define	TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos)

#define	TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos)

#define	TIM_CCMR2_OC4FE_Pos (10U)

#define	TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos)

#define	TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk

#define	TIM_CCMR2_OC4PE_Pos (11U)

#define	TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos)

#define	TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk

#define	TIM_CCMR2_OC4M_Pos (12U)

#define	TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos)

#define	TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk

#define	TIM_CCMR2_OC4M_0 (0x0001UL << TIM_CCMR2_OC4M_Pos)

#define	TIM_CCMR2_OC4M_1 (0x0002UL << TIM_CCMR2_OC4M_Pos)

#define	TIM_CCMR2_OC4M_2 (0x0004UL << TIM_CCMR2_OC4M_Pos)

#define	TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos)

#define	TIM_CCMR2_OC4CE_Pos (15U)

#define	TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos)

#define	TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk

#define	TIM_CCMR2_IC3PSC_Pos (2U)

#define	TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos)

#define	TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk

#define	TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos)

#define	TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos)

#define	TIM_CCMR2_IC3F_Pos (4U)

#define	TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos)

#define	TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk

#define	TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos)

#define	TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos)

#define	TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos)

#define	TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos)

#define	TIM_CCMR2_IC4PSC_Pos (10U)

#define	TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos)

#define	TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk

#define	TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos)

#define	TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos)

#define	TIM_CCMR2_IC4F_Pos (12U)

#define	TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos)

#define	TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk

#define	TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos)

#define	TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos)

#define	TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos)

#define	TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos)

#define	TIM_CCMR3_OC5FE_Pos (2U)

#define	TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos)

#define	TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk

#define	TIM_CCMR3_OC5PE_Pos (3U)

#define	TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos)

#define	TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk

#define	TIM_CCMR3_OC5M_Pos (4U)

#define	TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos)

#define	TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk

#define	TIM_CCMR3_OC5M_0 (0x0001UL << TIM_CCMR3_OC5M_Pos)

#define	TIM_CCMR3_OC5M_1 (0x0002UL << TIM_CCMR3_OC5M_Pos)

#define	TIM_CCMR3_OC5M_2 (0x0004UL << TIM_CCMR3_OC5M_Pos)

#define	TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos)

#define	TIM_CCMR3_OC5CE_Pos (7U)

#define	TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos)

#define	TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk

#define	TIM_CCMR3_OC6FE_Pos (10U)

#define	TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos)

#define	TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk

#define	TIM_CCMR3_OC6PE_Pos (11U)

#define	TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos)

#define	TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk

#define	TIM_CCMR3_OC6M_Pos (12U)

#define	TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos)

#define	TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk

#define	TIM_CCMR3_OC6M_0 (0x0001UL << TIM_CCMR3_OC6M_Pos)

#define	TIM_CCMR3_OC6M_1 (0x0002UL << TIM_CCMR3_OC6M_Pos)

#define	TIM_CCMR3_OC6M_2 (0x0004UL << TIM_CCMR3_OC6M_Pos)

#define	TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos)

#define	TIM_CCMR3_OC6CE_Pos (15U)

#define	TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos)

#define	TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk

#define	TIM_CCER_CC1E_Pos (0U)

#define	TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos)

#define	TIM_CCER_CC1E TIM_CCER_CC1E_Msk

#define	TIM_CCER_CC1P_Pos (1U)

#define	TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos)

#define	TIM_CCER_CC1P TIM_CCER_CC1P_Msk

#define	TIM_CCER_CC1NE_Pos (2U)

#define	TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos)

#define	TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk

#define	TIM_CCER_CC1NP_Pos (3U)

#define	TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos)

#define	TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk

#define	TIM_CCER_CC2E_Pos (4U)

#define	TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos)

#define	TIM_CCER_CC2E TIM_CCER_CC2E_Msk

#define	TIM_CCER_CC2P_Pos (5U)

#define	TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos)

#define	TIM_CCER_CC2P TIM_CCER_CC2P_Msk

#define	TIM_CCER_CC2NE_Pos (6U)

#define	TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos)

#define	TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk

#define	TIM_CCER_CC2NP_Pos (7U)

#define	TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos)

#define	TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk

#define	TIM_CCER_CC3E_Pos (8U)

#define	TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos)

#define	TIM_CCER_CC3E TIM_CCER_CC3E_Msk

#define	TIM_CCER_CC3P_Pos (9U)

#define	TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos)

#define	TIM_CCER_CC3P TIM_CCER_CC3P_Msk

#define	TIM_CCER_CC3NE_Pos (10U)

#define	TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos)

#define	TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk

#define	TIM_CCER_CC3NP_Pos (11U)

#define	TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos)

#define	TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk

#define	TIM_CCER_CC4E_Pos (12U)

#define	TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos)

#define	TIM_CCER_CC4E TIM_CCER_CC4E_Msk

#define	TIM_CCER_CC4P_Pos (13U)

#define	TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos)

#define	TIM_CCER_CC4P TIM_CCER_CC4P_Msk

#define	TIM_CCER_CC4NE_Pos (14U)

#define	TIM_CCER_CC4NE_Msk (0x1UL << TIM_CCER_CC4NE_Pos)

#define	TIM_CCER_CC4NE TIM_CCER_CC4NE_Msk

#define	TIM_CCER_CC4NP_Pos (15U)

#define	TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos)

#define	TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk

#define	TIM_CCER_CC5E_Pos (16U)

#define	TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos)

#define	TIM_CCER_CC5E TIM_CCER_CC5E_Msk

#define	TIM_CCER_CC5P_Pos (17U)

#define	TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos)

#define	TIM_CCER_CC5P TIM_CCER_CC5P_Msk

#define	TIM_CCER_CC6E_Pos (20U)

#define	TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos)

#define	TIM_CCER_CC6E TIM_CCER_CC6E_Msk

#define	TIM_CCER_CC6P_Pos (21U)

#define	TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos)

#define	TIM_CCER_CC6P TIM_CCER_CC6P_Msk

#define	TIM_CNT_CNT_Pos (0U)

#define	TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)

#define	TIM_CNT_CNT TIM_CNT_CNT_Msk

#define	TIM_CNT_UIFCPY_Pos (31U)

#define	TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos)

#define	TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk

#define	TIM_PSC_PSC_Pos (0U)

#define	TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos)

#define	TIM_PSC_PSC TIM_PSC_PSC_Msk

#define	TIM_ARR_ARR_Pos (0U)

#define	TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)

#define	TIM_ARR_ARR TIM_ARR_ARR_Msk

#define	TIM_RCR_REP_Pos (0U)

#define	TIM_RCR_REP_Msk (0xFFFFUL << TIM_RCR_REP_Pos)

#define	TIM_RCR_REP TIM_RCR_REP_Msk

#define	TIM_CCR1_CCR1_Pos (0U)

#define	TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos)

#define	TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk

#define	TIM_CCR2_CCR2_Pos (0U)

#define	TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos)

#define	TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk

#define	TIM_CCR3_CCR3_Pos (0U)

#define	TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos)

#define	TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk

#define	TIM_CCR4_CCR4_Pos (0U)

#define	TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos)

#define	TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk

#define	TIM_CCR5_CCR5_Pos (0U)

#define	TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)

#define	TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk

#define	TIM_CCR5_GC5C1_Pos (29U)

#define	TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos)

#define	TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk

#define	TIM_CCR5_GC5C2_Pos (30U)

#define	TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos)

#define	TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk

#define	TIM_CCR5_GC5C3_Pos (31U)

#define	TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos)

#define	TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk

#define	TIM_CCR6_CCR6_Pos (0U)

#define	TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos)

#define	TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk

#define	TIM_BDTR_DTG_Pos (0U)

#define	TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos)

#define	TIM_BDTR_DTG TIM_BDTR_DTG_Msk

#define	TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos)

#define	TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos)

#define	TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos)

#define	TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos)

#define	TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos)

#define	TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos)

#define	TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos)

#define	TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos)

#define	TIM_BDTR_LOCK_Pos (8U)

#define	TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos)

#define	TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk

#define	TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos)

#define	TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos)

#define	TIM_BDTR_OSSI_Pos (10U)

#define	TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos)

#define	TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk

#define	TIM_BDTR_OSSR_Pos (11U)

#define	TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos)

#define	TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk

#define	TIM_BDTR_BKE_Pos (12U)

#define	TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos)

#define	TIM_BDTR_BKE TIM_BDTR_BKE_Msk

#define	TIM_BDTR_BKP_Pos (13U)

#define	TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos)

#define	TIM_BDTR_BKP TIM_BDTR_BKP_Msk

#define	TIM_BDTR_AOE_Pos (14U)

#define	TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos)

#define	TIM_BDTR_AOE TIM_BDTR_AOE_Msk

#define	TIM_BDTR_MOE_Pos (15U)

#define	TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos)

#define	TIM_BDTR_MOE TIM_BDTR_MOE_Msk

#define	TIM_BDTR_BKF_Pos (16U)

#define	TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos)

#define	TIM_BDTR_BKF TIM_BDTR_BKF_Msk

#define	TIM_BDTR_BK2F_Pos (20U)

#define	TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos)

#define	TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk

#define	TIM_BDTR_BK2E_Pos (24U)

#define	TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos)

#define	TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk

#define	TIM_BDTR_BK2P_Pos (25U)

#define	TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos)

#define	TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk

#define	TIM_BDTR_BKDSRM_Pos (26U)

#define	TIM_BDTR_BKDSRM_Msk (0x1UL << TIM_BDTR_BKDSRM_Pos)

#define	TIM_BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk

#define	TIM_BDTR_BK2DSRM_Pos (27U)

#define	TIM_BDTR_BK2DSRM_Msk (0x1UL << TIM_BDTR_BK2DSRM_Pos)

#define	TIM_BDTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk

#define	TIM_BDTR_BKBID_Pos (28U)

#define	TIM_BDTR_BKBID_Msk (0x1UL << TIM_BDTR_BKBID_Pos)

#define	TIM_BDTR_BKBID TIM_BDTR_BKBID_Msk

#define	TIM_BDTR_BK2BID_Pos (29U)

#define	TIM_BDTR_BK2BID_Msk (0x1UL << TIM_BDTR_BK2BID_Pos)

#define	TIM_BDTR_BK2BID TIM_BDTR_BK2BID_Msk

#define	TIM_DCR_DBA_Pos (0U)

#define	TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos)

#define	TIM_DCR_DBA TIM_DCR_DBA_Msk

#define	TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos)

#define	TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos)

#define	TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos)

#define	TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos)

#define	TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos)

#define	TIM_DCR_DBL_Pos (8U)

#define	TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos)

#define	TIM_DCR_DBL TIM_DCR_DBL_Msk

#define	TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos)

#define	TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos)

#define	TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos)

#define	TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos)

#define	TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos)

#define	TIM1_AF1_BKINE_Pos (0U)

#define	TIM1_AF1_BKINE_Msk (0x1UL << TIM1_AF1_BKINE_Pos)

#define	TIM1_AF1_BKINE TIM1_AF1_BKINE_Msk

#define	TIM1_AF1_BKCMP1E_Pos (1U)

#define	TIM1_AF1_BKCMP1E_Msk (0x1UL << TIM1_AF1_BKCMP1E_Pos)

#define	TIM1_AF1_BKCMP1E TIM1_AF1_BKCMP1E_Msk

#define	TIM1_AF1_BKCMP2E_Pos (2U)

#define	TIM1_AF1_BKCMP2E_Msk (0x1UL << TIM1_AF1_BKCMP2E_Pos)

#define	TIM1_AF1_BKCMP2E TIM1_AF1_BKCMP2E_Msk

#define	TIM1_AF1_BKCMP3E_Pos (3U)

#define	TIM1_AF1_BKCMP3E_Msk (0x1UL << TIM1_AF1_BKCMP3E_Pos)

#define	TIM1_AF1_BKCMP3E TIM1_AF1_BKCMP3E_Msk

#define	TIM1_AF1_BKCMP4E_Pos (4U)

#define	TIM1_AF1_BKCMP4E_Msk (0x1UL << TIM1_AF1_BKCMP4E_Pos)

#define	TIM1_AF1_BKCMP4E TIM1_AF1_BKCMP4E_Msk

#define	TIM1_AF1_BKINP_Pos (9U)

#define	TIM1_AF1_BKINP_Msk (0x1UL << TIM1_AF1_BKINP_Pos)

#define	TIM1_AF1_BKINP TIM1_AF1_BKINP_Msk

#define	TIM1_AF1_BKCMP1P_Pos (10U)

#define	TIM1_AF1_BKCMP1P_Msk (0x1UL << TIM1_AF1_BKCMP1P_Pos)

#define	TIM1_AF1_BKCMP1P TIM1_AF1_BKCMP1P_Msk

#define	TIM1_AF1_BKCMP2P_Pos (11U)

#define	TIM1_AF1_BKCMP2P_Msk (0x1UL << TIM1_AF1_BKCMP2P_Pos)

#define	TIM1_AF1_BKCMP2P TIM1_AF1_BKCMP2P_Msk

#define	TIM1_AF1_BKCMP3P_Pos (12U)

#define	TIM1_AF1_BKCMP3P_Msk (0x1UL << TIM1_AF1_BKCMP3P_Pos)

#define	TIM1_AF1_BKCMP3P TIM1_AF1_BKCMP3P_Msk

#define	TIM1_AF1_BKCMP4P_Pos (13U)

#define	TIM1_AF1_BKCMP4P_Msk (0x1UL << TIM1_AF1_BKCMP4P_Pos)

#define	TIM1_AF1_BKCMP4P TIM1_AF1_BKCMP4P_Msk

#define	TIM1_AF1_ETRSEL_Pos (14U)

#define	TIM1_AF1_ETRSEL_Msk (0xFUL << TIM1_AF1_ETRSEL_Pos)

#define	TIM1_AF1_ETRSEL TIM1_AF1_ETRSEL_Msk

#define	TIM1_AF1_ETRSEL_0 (0x1UL << TIM1_AF1_ETRSEL_Pos)

#define	TIM1_AF1_ETRSEL_1 (0x2UL << TIM1_AF1_ETRSEL_Pos)

#define	TIM1_AF1_ETRSEL_2 (0x4UL << TIM1_AF1_ETRSEL_Pos)

#define	TIM1_AF1_ETRSEL_3 (0x8UL << TIM1_AF1_ETRSEL_Pos)

#define	TIM1_AF2_BK2INE_Pos (0U)

#define	TIM1_AF2_BK2INE_Msk (0x1UL << TIM1_AF2_BK2INE_Pos)

#define	TIM1_AF2_BK2INE TIM1_AF2_BK2INE_Msk

#define	TIM1_AF2_BK2CMP1E_Pos (1U)

#define	TIM1_AF2_BK2CMP1E_Msk (0x1UL << TIM1_AF2_BK2CMP1E_Pos)

#define	TIM1_AF2_BK2CMP1E TIM1_AF2_BK2CMP1E_Msk

#define	TIM1_AF2_BK2CMP2E_Pos (2U)

#define	TIM1_AF2_BK2CMP2E_Msk (0x1UL << TIM1_AF2_BK2CMP2E_Pos)

#define	TIM1_AF2_BK2CMP2E TIM1_AF2_BK2CMP2E_Msk

#define	TIM1_AF2_BK2CMP3E_Pos (3U)

#define	TIM1_AF2_BK2CMP3E_Msk (0x1UL << TIM1_AF2_BK2CMP3E_Pos)

#define	TIM1_AF2_BK2CMP3E TIM1_AF2_BK2CMP3E_Msk

#define	TIM1_AF2_BK2CMP4E_Pos (4U)

#define	TIM1_AF2_BK2CMP4E_Msk (0x1UL << TIM1_AF2_BK2CMP4E_Pos)

#define	TIM1_AF2_BK2CMP4E TIM1_AF2_BK2CMP4E_Msk

#define	TIM1_AF2_BK2INP_Pos (9U)

#define	TIM1_AF2_BK2INP_Msk (0x1UL << TIM1_AF2_BK2INP_Pos)

#define	TIM1_AF2_BK2INP TIM1_AF2_BK2INP_Msk

#define	TIM1_AF2_BK2CMP1P_Pos (10U)

#define	TIM1_AF2_BK2CMP1P_Msk (0x1UL << TIM1_AF2_BK2CMP1P_Pos)

#define	TIM1_AF2_BK2CMP1P TIM1_AF2_BK2CMP1P_Msk

#define	TIM1_AF2_BK2CMP2P_Pos (11U)

#define	TIM1_AF2_BK2CMP2P_Msk (0x1UL << TIM1_AF2_BK2CMP2P_Pos)

#define	TIM1_AF2_BK2CMP2P TIM1_AF2_BK2CMP2P_Msk

#define	TIM1_AF2_BK2CMP3P_Pos (12U)

#define	TIM1_AF2_BK2CMP3P_Msk (0x1UL << TIM1_AF2_BK2CMP3P_Pos)

#define	TIM1_AF2_BK2CMP3P TIM1_AF2_BK2CMP3P_Msk

#define	TIM1_AF2_BK2CMP4P_Pos (13U)

#define	TIM1_AF2_BK2CMP4P_Msk (0x1UL << TIM1_AF2_BK2CMP4P_Pos)

#define	TIM1_AF2_BK2CMP4P TIM1_AF2_BK2CMP4P_Msk

#define	TIM1_AF2_OCRSEL_Pos (16U)

#define	TIM1_AF2_OCRSEL_Msk (0x7UL << TIM1_AF2_OCRSEL_Pos)

#define	TIM1_AF2_OCRSEL TIM1_AF2_OCRSEL_Msk

#define	TIM1_AF2_OCRSEL_0 (0x1UL << TIM1_AF2_OCRSEL_Pos)

#define	TIM1_AF2_OCRSEL_1 (0x2UL << TIM1_AF2_OCRSEL_Pos)

#define	TIM1_AF2_OCRSEL_2 (0x4UL << TIM1_AF2_OCRSEL_Pos)

#define	TIM_OR_HSE32EN_Pos (0U)

#define	TIM_OR_HSE32EN_Msk (0x1UL << TIM_OR_HSE32EN_Pos)

#define	TIM_OR_HSE32EN TIM_OR_HSE32EN_Msk

#define	TIM_TISEL_TI1SEL_Pos (0U)

#define	TIM_TISEL_TI1SEL_Msk (0xFUL << TIM_TISEL_TI1SEL_Pos)

#define	TIM_TISEL_TI1SEL TIM_TISEL_TI1SEL_Msk

#define	TIM_TISEL_TI1SEL_0 (0x1UL << TIM_TISEL_TI1SEL_Pos)

#define	TIM_TISEL_TI1SEL_1 (0x2UL << TIM_TISEL_TI1SEL_Pos)

#define	TIM_TISEL_TI1SEL_2 (0x4UL << TIM_TISEL_TI1SEL_Pos)

#define	TIM_TISEL_TI1SEL_3 (0x8UL << TIM_TISEL_TI1SEL_Pos)

#define	TIM_TISEL_TI2SEL_Pos (8U)

#define	TIM_TISEL_TI2SEL_Msk (0xFUL << TIM_TISEL_TI2SEL_Pos)

#define	TIM_TISEL_TI2SEL TIM_TISEL_TI2SEL_Msk

#define	TIM_TISEL_TI2SEL_0 (0x1UL << TIM_TISEL_TI2SEL_Pos)

#define	TIM_TISEL_TI2SEL_1 (0x2UL << TIM_TISEL_TI2SEL_Pos)

#define	TIM_TISEL_TI2SEL_2 (0x4UL << TIM_TISEL_TI2SEL_Pos)

#define	TIM_TISEL_TI2SEL_3 (0x8UL << TIM_TISEL_TI2SEL_Pos)

#define	TIM_TISEL_TI3SEL_Pos (16U)

#define	TIM_TISEL_TI3SEL_Msk (0xFUL << TIM_TISEL_TI3SEL_Pos)

#define	TIM_TISEL_TI3SEL TIM_TISEL_TI3SEL_Msk

#define	TIM_TISEL_TI3SEL_0 (0x1UL << TIM_TISEL_TI3SEL_Pos)

#define	TIM_TISEL_TI3SEL_1 (0x2UL << TIM_TISEL_TI3SEL_Pos)

#define	TIM_TISEL_TI3SEL_2 (0x4UL << TIM_TISEL_TI3SEL_Pos)

#define	TIM_TISEL_TI3SEL_3 (0x8UL << TIM_TISEL_TI3SEL_Pos)

#define	TIM_TISEL_TI4SEL_Pos (24U)

#define	TIM_TISEL_TI4SEL_Msk (0xFUL << TIM_TISEL_TI4SEL_Pos)

#define	TIM_TISEL_TI4SEL TIM_TISEL_TI4SEL_Msk

#define	TIM_TISEL_TI4SEL_0 (0x1UL << TIM_TISEL_TI4SEL_Pos)

#define	TIM_TISEL_TI4SEL_1 (0x2UL << TIM_TISEL_TI4SEL_Pos)

#define	TIM_TISEL_TI4SEL_2 (0x4UL << TIM_TISEL_TI4SEL_Pos)

#define	TIM_TISEL_TI4SEL_3 (0x8UL << TIM_TISEL_TI4SEL_Pos)

#define	TIM_DTR2_DTGF_Pos (0U)

#define	TIM_DTR2_DTGF_Msk (0xFFUL << TIM_DTR2_DTGF_Pos)

#define	TIM_DTR2_DTGF TIM_DTR2_DTGF_Msk

#define	TIM_DTR2_DTGF_0 (0x01UL << TIM_DTR2_DTGF_Pos)

#define	TIM_DTR2_DTGF_1 (0x02UL << TIM_DTR2_DTGF_Pos)

#define	TIM_DTR2_DTGF_2 (0x04UL << TIM_DTR2_DTGF_Pos)

#define	TIM_DTR2_DTGF_3 (0x08UL << TIM_DTR2_DTGF_Pos)

#define	TIM_DTR2_DTGF_4 (0x10UL << TIM_DTR2_DTGF_Pos)

#define	TIM_DTR2_DTGF_5 (0x20UL << TIM_DTR2_DTGF_Pos)

#define	TIM_DTR2_DTGF_6 (0x40UL << TIM_DTR2_DTGF_Pos)

#define	TIM_DTR2_DTGF_7 (0x80UL << TIM_DTR2_DTGF_Pos)

#define	TIM_DTR2_DTAE_Pos (16U)

#define	TIM_DTR2_DTAE_Msk (0x1UL << TIM_DTR2_DTAE_Pos)

#define	TIM_DTR2_DTAE TIM_DTR2_DTAE_Msk

#define	TIM_DTR2_DTPE_Pos (17U)

#define	TIM_DTR2_DTPE_Msk (0x1UL << TIM_DTR2_DTPE_Pos)

#define	TIM_DTR2_DTPE TIM_DTR2_DTPE_Msk

#define	TIM_ECR_IE_Pos (0U)

#define	TIM_ECR_IE_Msk (0x1UL << TIM_ECR_IE_Pos)

#define	TIM_ECR_IE TIM_ECR_IE_Msk

#define	TIM_ECR_IDIR_Pos (1U)

#define	TIM_ECR_IDIR_Msk (0x3UL << TIM_ECR_IDIR_Pos)

#define	TIM_ECR_IDIR TIM_ECR_IDIR_Msk

#define	TIM_ECR_IDIR_0 (0x01UL << TIM_ECR_IDIR_Pos)

#define	TIM_ECR_IDIR_1 (0x02UL << TIM_ECR_IDIR_Pos)

#define	TIM_ECR_FIDX_Pos (5U)

#define	TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos)

#define	TIM_ECR_FIDX TIM_ECR_FIDX_Msk

#define	TIM_ECR_IPOS_Pos (6U)

#define	TIM_ECR_IPOS_Msk (0x3UL << TIM_ECR_IPOS_Pos)

#define	TIM_ECR_IPOS TIM_ECR_IPOS_Msk

#define	TIM_ECR_IPOS_0 (0x01UL << TIM_ECR_IPOS_Pos)

#define	TIM_ECR_IPOS_1 (0x02UL << TIM_ECR_IPOS_Pos)

#define	TIM_ECR_PW_Pos (16U)

#define	TIM_ECR_PW_Msk (0xFFUL << TIM_ECR_PW_Pos)

#define	TIM_ECR_PW TIM_ECR_PW_Msk

#define	TIM_ECR_PW_0 (0x01UL << TIM_ECR_PW_Pos)

#define	TIM_ECR_PW_1 (0x02UL << TIM_ECR_PW_Pos)

#define	TIM_ECR_PW_2 (0x04UL << TIM_ECR_PW_Pos)

#define	TIM_ECR_PW_3 (0x08UL << TIM_ECR_PW_Pos)

#define	TIM_ECR_PW_4 (0x10UL << TIM_ECR_PW_Pos)

#define	TIM_ECR_PW_5 (0x20UL << TIM_ECR_PW_Pos)

#define	TIM_ECR_PW_6 (0x40UL << TIM_ECR_PW_Pos)

#define	TIM_ECR_PW_7 (0x80UL << TIM_ECR_PW_Pos)

#define	TIM_ECR_PWPRSC_Pos (24U)

#define	TIM_ECR_PWPRSC_Msk (0x7UL << TIM_ECR_PWPRSC_Pos)

#define	TIM_ECR_PWPRSC TIM_ECR_PWPRSC_Msk

#define	TIM_ECR_PWPRSC_0 (0x01UL << TIM_ECR_PWPRSC_Pos)

#define	TIM_ECR_PWPRSC_1 (0x02UL << TIM_ECR_PWPRSC_Pos)

#define	TIM_ECR_PWPRSC_2 (0x04UL << TIM_ECR_PWPRSC_Pos)

#define	TIM_DMAR_DMAB_Pos (0U)

#define	TIM_DMAR_DMAB_Msk (0xFFFFFFFFUL << TIM_DMAR_DMAB_Pos)

#define	TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk

#define	LPTIM_ISR_CMPM_Pos (0U)

#define	LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos)

#define	LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk

#define	LPTIM_ISR_ARRM_Pos (1U)

#define	LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos)

#define	LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk

#define	LPTIM_ISR_EXTTRIG_Pos (2U)

#define	LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos)

#define	LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk

#define	LPTIM_ISR_CMPOK_Pos (3U)

#define	LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos)

#define	LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk

#define	LPTIM_ISR_ARROK_Pos (4U)

#define	LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos)

#define	LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk

#define	LPTIM_ISR_UP_Pos (5U)

#define	LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos)

#define	LPTIM_ISR_UP LPTIM_ISR_UP_Msk

#define	LPTIM_ISR_DOWN_Pos (6U)

#define	LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos)

#define	LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk

#define	LPTIM_ICR_CMPMCF_Pos (0U)

#define	LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos)

#define	LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk

#define	LPTIM_ICR_ARRMCF_Pos (1U)

#define	LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos)

#define	LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk

#define	LPTIM_ICR_EXTTRIGCF_Pos (2U)

#define	LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)

#define	LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk

#define	LPTIM_ICR_CMPOKCF_Pos (3U)

#define	LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos)

#define	LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk

#define	LPTIM_ICR_ARROKCF_Pos (4U)

#define	LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos)

#define	LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk

#define	LPTIM_ICR_UPCF_Pos (5U)

#define	LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos)

#define	LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk

#define	LPTIM_ICR_DOWNCF_Pos (6U)

#define	LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos)

#define	LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk

#define	LPTIM_IER_CMPMIE_Pos (0U)

#define	LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos)

#define	LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk

#define	LPTIM_IER_ARRMIE_Pos (1U)

#define	LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos)

#define	LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk

#define	LPTIM_IER_EXTTRIGIE_Pos (2U)

#define	LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)

#define	LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk

#define	LPTIM_IER_CMPOKIE_Pos (3U)

#define	LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos)

#define	LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk

#define	LPTIM_IER_ARROKIE_Pos (4U)

#define	LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos)

#define	LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk

#define	LPTIM_IER_UPIE_Pos (5U)

#define	LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos)

#define	LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk

#define	LPTIM_IER_DOWNIE_Pos (6U)

#define	LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos)

#define	LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk

#define	LPTIM_CFGR_CKSEL_Pos (0U)

#define	LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos)

#define	LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk

#define	LPTIM_CFGR_CKPOL_Pos (1U)

#define	LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos)

#define	LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk

#define	LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos)

#define	LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos)

#define	LPTIM_CFGR_CKFLT_Pos (3U)

#define	LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos)

#define	LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk

#define	LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos)

#define	LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos)

#define	LPTIM_CFGR_TRGFLT_Pos (6U)

#define	LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos)

#define	LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk

#define	LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos)

#define	LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos)

#define	LPTIM_CFGR_PRESC_Pos (9U)

#define	LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos)

#define	LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk

#define	LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos)

#define	LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos)

#define	LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos)

#define	LPTIM_CFGR_TRIGSEL_Pos (13U)

#define	LPTIM_CFGR_TRIGSEL_Msk (0x10007UL << LPTIM_CFGR_TRIGSEL_Pos)

#define	LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk

#define	LPTIM_CFGR_TRIGSEL_0 (0x00001UL << LPTIM_CFGR_TRIGSEL_Pos)

#define	LPTIM_CFGR_TRIGSEL_1 (0x00002UL << LPTIM_CFGR_TRIGSEL_Pos)

#define	LPTIM_CFGR_TRIGSEL_2 (0x00004UL << LPTIM_CFGR_TRIGSEL_Pos)

#define	LPTIM_CFGR_TRIGSEL_3 (0x10000UL << LPTIM_CFGR_TRIGSEL_Pos)

#define	LPTIM_CFGR_TRIGEN_Pos (17U)

#define	LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos)

#define	LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk

#define	LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos)

#define	LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos)

#define	LPTIM_CFGR_TIMOUT_Pos (19U)

#define	LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos)

#define	LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk

#define	LPTIM_CFGR_WAVE_Pos (20U)

#define	LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos)

#define	LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk

#define	LPTIM_CFGR_WAVPOL_Pos (21U)

#define	LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos)

#define	LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk

#define	LPTIM_CFGR_PRELOAD_Pos (22U)

#define	LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos)

#define	LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk

#define	LPTIM_CFGR_COUNTMODE_Pos (23U)

#define	LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)

#define	LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk

#define	LPTIM_CFGR_ENC_Pos (24U)

#define	LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos)

#define	LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk

#define	LPTIM_CR_ENABLE_Pos (0U)

#define	LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos)

#define	LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk

#define	LPTIM_CR_SNGSTRT_Pos (1U)

#define	LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos)

#define	LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk

#define	LPTIM_CR_CNTSTRT_Pos (2U)

#define	LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos)

#define	LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk

#define	LPTIM_CR_COUNTRST_Pos (3U)

#define	LPTIM_CR_COUNTRST_Msk (0x1UL << LPTIM_CR_COUNTRST_Pos)

#define	LPTIM_CR_COUNTRST LPTIM_CR_COUNTRST_Msk

#define	LPTIM_CR_RSTARE_Pos (4U)

#define	LPTIM_CR_RSTARE_Msk (0x1UL << LPTIM_CR_RSTARE_Pos)

#define	LPTIM_CR_RSTARE LPTIM_CR_RSTARE_Msk

#define	LPTIM_CMP_CMP_Pos (0U)

#define	LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos)

#define	LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk

#define	LPTIM_ARR_ARR_Pos (0U)

#define	LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos)

#define	LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk

#define	LPTIM_CNT_CNT_Pos (0U)

#define	LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos)

#define	LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk

#define	LPTIM_OR_IN1_Pos (0U)

#define	LPTIM_OR_IN1_Msk (0xDUL << LPTIM_OR_IN1_Pos)

#define	LPTIM_OR_IN1 LPTIM_OR_IN1_Msk

#define	LPTIM_OR_IN1_0 (0x1UL << LPTIM_OR_IN1_Pos)

#define	LPTIM_OR_IN1_1 (0x4UL << LPTIM_OR_IN1_Pos)

#define	LPTIM_OR_IN1_2 (0x8UL << LPTIM_OR_IN1_Pos)

#define	LPTIM_OR_IN2_Pos (1U)

#define	LPTIM_OR_IN2_Msk (0x19UL << LPTIM_OR_IN2_Pos)

#define	LPTIM_OR_IN2 LPTIM_OR_IN2_Msk

#define	LPTIM_OR_IN2_0 (0x1UL << LPTIM_OR_IN2_Pos)

#define	LPTIM_OR_IN2_1 (0x8UL << LPTIM_OR_IN2_Pos)

#define	LPTIM_OR_IN2_2 (0x10UL << LPTIM_OR_IN2_Pos)

#define	USART_CR1_UE_Pos (0U)

#define	USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos)

#define	USART_CR1_UE USART_CR1_UE_Msk

#define	USART_CR1_UESM_Pos (1U)

#define	USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos)

#define	USART_CR1_UESM USART_CR1_UESM_Msk

#define	USART_CR1_RE_Pos (2U)

#define	USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos)

#define	USART_CR1_RE USART_CR1_RE_Msk

#define	USART_CR1_TE_Pos (3U)

#define	USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos)

#define	USART_CR1_TE USART_CR1_TE_Msk

#define	USART_CR1_IDLEIE_Pos (4U)

#define	USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos)

#define	USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk

#define	USART_CR1_RXNEIE_Pos (5U)

#define	USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos)

#define	USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk

#define	USART_CR1_RXNEIE_RXFNEIE_Pos USART_CR1_RXNEIE_Pos

#define	USART_CR1_RXNEIE_RXFNEIE_Msk USART_CR1_RXNEIE_Msk

#define	USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_Msk

#define	USART_CR1_TCIE_Pos (6U)

#define	USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos)

#define	USART_CR1_TCIE USART_CR1_TCIE_Msk

#define	USART_CR1_TXEIE_Pos (7U)

#define	USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos)

#define	USART_CR1_TXEIE USART_CR1_TXEIE_Msk

#define	USART_CR1_TXEIE_TXFNFIE_Pos USART_CR1_TXEIE_Pos

#define	USART_CR1_TXEIE_TXFNFIE_Msk USART_CR1_TXEIE_Msk

#define	USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_Msk

#define	USART_CR1_PEIE_Pos (8U)

#define	USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos)

#define	USART_CR1_PEIE USART_CR1_PEIE_Msk

#define	USART_CR1_PS_Pos (9U)

#define	USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos)

#define	USART_CR1_PS USART_CR1_PS_Msk

#define	USART_CR1_PCE_Pos (10U)

#define	USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos)

#define	USART_CR1_PCE USART_CR1_PCE_Msk

#define	USART_CR1_WAKE_Pos (11U)

#define	USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos)

#define	USART_CR1_WAKE USART_CR1_WAKE_Msk

#define	USART_CR1_M_Pos (12U)

#define	USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos)

#define	USART_CR1_M USART_CR1_M_Msk

#define	USART_CR1_M0_Pos (12U)

#define	USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos)

#define	USART_CR1_M0 USART_CR1_M0_Msk

#define	USART_CR1_MME_Pos (13U)

#define	USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos)

#define	USART_CR1_MME USART_CR1_MME_Msk

#define	USART_CR1_CMIE_Pos (14U)

#define	USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos)

#define	USART_CR1_CMIE USART_CR1_CMIE_Msk

#define	USART_CR1_OVER8_Pos (15U)

#define	USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos)

#define	USART_CR1_OVER8 USART_CR1_OVER8_Msk

#define	USART_CR1_DEDT_Pos (16U)

#define	USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos)

#define	USART_CR1_DEDT USART_CR1_DEDT_Msk

#define	USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos)

#define	USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos)

#define	USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos)

#define	USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos)

#define	USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos)

#define	USART_CR1_DEAT_Pos (21U)

#define	USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos)

#define	USART_CR1_DEAT USART_CR1_DEAT_Msk

#define	USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos)

#define	USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos)

#define	USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos)

#define	USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos)

#define	USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos)

#define	USART_CR1_RTOIE_Pos (26U)

#define	USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos)

#define	USART_CR1_RTOIE USART_CR1_RTOIE_Msk

#define	USART_CR1_EOBIE_Pos (27U)

#define	USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos)

#define	USART_CR1_EOBIE USART_CR1_EOBIE_Msk

#define	USART_CR1_M1_Pos (28U)

#define	USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos)

#define	USART_CR1_M1 USART_CR1_M1_Msk

#define	USART_CR1_FIFOEN_Pos (29U)

#define	USART_CR1_FIFOEN_Msk (0x1UL << USART_CR1_FIFOEN_Pos)

#define	USART_CR1_FIFOEN USART_CR1_FIFOEN_Msk

#define	USART_CR1_TXFEIE_Pos (30U)

#define	USART_CR1_TXFEIE_Msk (0x1UL << USART_CR1_TXFEIE_Pos)

#define	USART_CR1_TXFEIE USART_CR1_TXFEIE_Msk

#define	USART_CR1_RXFFIE_Pos (31U)

#define	USART_CR1_RXFFIE_Msk (0x1UL << USART_CR1_RXFFIE_Pos)

#define	USART_CR1_RXFFIE USART_CR1_RXFFIE_Msk

#define	USART_CR2_SLVEN_Pos (0U)

#define	USART_CR2_SLVEN_Msk (0x1UL << USART_CR2_SLVEN_Pos)

#define	USART_CR2_SLVEN USART_CR2_SLVEN_Msk

#define	USART_CR2_DIS_NSS_Pos (3U)

#define	USART_CR2_DIS_NSS_Msk (0x1UL << USART_CR2_DIS_NSS_Pos)

#define	USART_CR2_DIS_NSS USART_CR2_DIS_NSS_Msk

#define	USART_CR2_ADDM7_Pos (4U)

#define	USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos)

#define	USART_CR2_ADDM7 USART_CR2_ADDM7_Msk

#define	USART_CR2_LBDL_Pos (5U)

#define	USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos)

#define	USART_CR2_LBDL USART_CR2_LBDL_Msk

#define	USART_CR2_LBDIE_Pos (6U)

#define	USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos)

#define	USART_CR2_LBDIE USART_CR2_LBDIE_Msk

#define	USART_CR2_LBCL_Pos (8U)

#define	USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos)

#define	USART_CR2_LBCL USART_CR2_LBCL_Msk

#define	USART_CR2_CPHA_Pos (9U)

#define	USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos)

#define	USART_CR2_CPHA USART_CR2_CPHA_Msk

#define	USART_CR2_CPOL_Pos (10U)

#define	USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos)

#define	USART_CR2_CPOL USART_CR2_CPOL_Msk

#define	USART_CR2_CLKEN_Pos (11U)

#define	USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos)

#define	USART_CR2_CLKEN USART_CR2_CLKEN_Msk

#define	USART_CR2_STOP_Pos (12U)

#define	USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos)

#define	USART_CR2_STOP USART_CR2_STOP_Msk

#define	USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos)

#define	USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos)

#define	USART_CR2_LINEN_Pos (14U)

#define	USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos)

#define	USART_CR2_LINEN USART_CR2_LINEN_Msk

#define	USART_CR2_SWAP_Pos (15U)

#define	USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos)

#define	USART_CR2_SWAP USART_CR2_SWAP_Msk

#define	USART_CR2_RXINV_Pos (16U)

#define	USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos)

#define	USART_CR2_RXINV USART_CR2_RXINV_Msk

#define	USART_CR2_TXINV_Pos (17U)

#define	USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos)

#define	USART_CR2_TXINV USART_CR2_TXINV_Msk

#define	USART_CR2_DATAINV_Pos (18U)

#define	USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos)

#define	USART_CR2_DATAINV USART_CR2_DATAINV_Msk

#define	USART_CR2_MSBFIRST_Pos (19U)

#define	USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos)

#define	USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk

#define	USART_CR2_ABREN_Pos (20U)

#define	USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos)

#define	USART_CR2_ABREN USART_CR2_ABREN_Msk

#define	USART_CR2_ABRMODE_Pos (21U)

#define	USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos)

#define	USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk

#define	USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos)

#define	USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos)

#define	USART_CR2_RTOEN_Pos (23U)

#define	USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos)

#define	USART_CR2_RTOEN USART_CR2_RTOEN_Msk

#define	USART_CR2_ADD_Pos (24U)

#define	USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos)

#define	USART_CR2_ADD USART_CR2_ADD_Msk

#define	USART_CR3_EIE_Pos (0U)

#define	USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos)

#define	USART_CR3_EIE USART_CR3_EIE_Msk

#define	USART_CR3_IREN_Pos (1U)

#define	USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos)

#define	USART_CR3_IREN USART_CR3_IREN_Msk

#define	USART_CR3_IRLP_Pos (2U)

#define	USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos)

#define	USART_CR3_IRLP USART_CR3_IRLP_Msk

#define	USART_CR3_HDSEL_Pos (3U)

#define	USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos)

#define	USART_CR3_HDSEL USART_CR3_HDSEL_Msk

#define	USART_CR3_NACK_Pos (4U)

#define	USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos)

#define	USART_CR3_NACK USART_CR3_NACK_Msk

#define	USART_CR3_SCEN_Pos (5U)

#define	USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos)

#define	USART_CR3_SCEN USART_CR3_SCEN_Msk

#define	USART_CR3_DMAR_Pos (6U)

#define	USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos)

#define	USART_CR3_DMAR USART_CR3_DMAR_Msk

#define	USART_CR3_DMAT_Pos (7U)

#define	USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos)

#define	USART_CR3_DMAT USART_CR3_DMAT_Msk

#define	USART_CR3_RTSE_Pos (8U)

#define	USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos)

#define	USART_CR3_RTSE USART_CR3_RTSE_Msk

#define	USART_CR3_CTSE_Pos (9U)

#define	USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos)

#define	USART_CR3_CTSE USART_CR3_CTSE_Msk

#define	USART_CR3_CTSIE_Pos (10U)

#define	USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos)

#define	USART_CR3_CTSIE USART_CR3_CTSIE_Msk

#define	USART_CR3_ONEBIT_Pos (11U)

#define	USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos)

#define	USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk

#define	USART_CR3_OVRDIS_Pos (12U)

#define	USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos)

#define	USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk

#define	USART_CR3_DDRE_Pos (13U)

#define	USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos)

#define	USART_CR3_DDRE USART_CR3_DDRE_Msk

#define	USART_CR3_DEM_Pos (14U)

#define	USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos)

#define	USART_CR3_DEM USART_CR3_DEM_Msk

#define	USART_CR3_DEP_Pos (15U)

#define	USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos)

#define	USART_CR3_DEP USART_CR3_DEP_Msk

#define	USART_CR3_SCARCNT_Pos (17U)

#define	USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos)

#define	USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk

#define	USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos)

#define	USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos)

#define	USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos)

#define	USART_CR3_WUS_Pos (20U)

#define	USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos)

#define	USART_CR3_WUS USART_CR3_WUS_Msk

#define	USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos)

#define	USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos)

#define	USART_CR3_WUFIE_Pos (22U)

#define	USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos)

#define	USART_CR3_WUFIE USART_CR3_WUFIE_Msk

#define	USART_CR3_TXFTIE_Pos (23U)

#define	USART_CR3_TXFTIE_Msk (0x1UL << USART_CR3_TXFTIE_Pos)

#define	USART_CR3_TXFTIE USART_CR3_TXFTIE_Msk

#define	USART_CR3_TCBGTIE_Pos (24U)

#define	USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos)

#define	USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk

#define	USART_CR3_RXFTCFG_Pos (25U)

#define	USART_CR3_RXFTCFG_Msk (0x7UL << USART_CR3_RXFTCFG_Pos)

#define	USART_CR3_RXFTCFG USART_CR3_RXFTCFG_Msk

#define	USART_CR3_RXFTCFG_0 (0x1UL << USART_CR3_RXFTCFG_Pos)

#define	USART_CR3_RXFTCFG_1 (0x2UL << USART_CR3_RXFTCFG_Pos)

#define	USART_CR3_RXFTCFG_2 (0x4UL << USART_CR3_RXFTCFG_Pos)

#define	USART_CR3_RXFTIE_Pos (28U)

#define	USART_CR3_RXFTIE_Msk (0x1UL << USART_CR3_RXFTIE_Pos)

#define	USART_CR3_RXFTIE USART_CR3_RXFTIE_Msk

#define	USART_CR3_TXFTCFG_Pos (29U)

#define	USART_CR3_TXFTCFG_Msk (0x7UL << USART_CR3_TXFTCFG_Pos)

#define	USART_CR3_TXFTCFG USART_CR3_TXFTCFG_Msk

#define	USART_CR3_TXFTCFG_0 (0x1UL << USART_CR3_TXFTCFG_Pos)

#define	USART_CR3_TXFTCFG_1 (0x2UL << USART_CR3_TXFTCFG_Pos)

#define	USART_CR3_TXFTCFG_2 (0x4UL << USART_CR3_TXFTCFG_Pos)

#define	USART_BRR_LPUART_Pos (0U)

#define	USART_BRR_LPUART_Msk (0xFFFFFUL << USART_BRR_LPUART_Pos)

#define	USART_BRR_LPUART USART_BRR_LPUART_Msk

#define	USART_BRR_BRR_Pos (0U)

#define	USART_BRR_BRR_Msk (0xFFFFUL << USART_BRR_BRR_Pos)

#define	USART_BRR_BRR USART_BRR_BRR_Msk

#define	USART_GTPR_PSC_Pos (0U)

#define	USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos)

#define	USART_GTPR_PSC USART_GTPR_PSC_Msk

#define	USART_GTPR_GT_Pos (8U)

#define	USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos)

#define	USART_GTPR_GT USART_GTPR_GT_Msk

#define	USART_RTOR_RTO_Pos (0U)

#define	USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos)

#define	USART_RTOR_RTO USART_RTOR_RTO_Msk

#define	USART_RTOR_BLEN_Pos (24U)

#define	USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos)

#define	USART_RTOR_BLEN USART_RTOR_BLEN_Msk

#define	USART_RQR_ABRRQ_Pos (0U)

#define	USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos)

#define	USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk

#define	USART_RQR_SBKRQ_Pos (1U)

#define	USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos)

#define	USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk

#define	USART_RQR_MMRQ_Pos (2U)

#define	USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos)

#define	USART_RQR_MMRQ USART_RQR_MMRQ_Msk

#define	USART_RQR_RXFRQ_Pos (3U)

#define	USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos)

#define	USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk

#define	USART_RQR_TXFRQ_Pos (4U)

#define	USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos)

#define	USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk

#define	USART_ISR_PE_Pos (0U)

#define	USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos)

#define	USART_ISR_PE USART_ISR_PE_Msk

#define	USART_ISR_FE_Pos (1U)

#define	USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos)

#define	USART_ISR_FE USART_ISR_FE_Msk

#define	USART_ISR_NE_Pos (2U)

#define	USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos)

#define	USART_ISR_NE USART_ISR_NE_Msk

#define	USART_ISR_ORE_Pos (3U)

#define	USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos)

#define	USART_ISR_ORE USART_ISR_ORE_Msk

#define	USART_ISR_IDLE_Pos (4U)

#define	USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos)

#define	USART_ISR_IDLE USART_ISR_IDLE_Msk

#define	USART_ISR_RXNE_Pos (5U)

#define	USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos)

#define	USART_ISR_RXNE USART_ISR_RXNE_Msk

#define	USART_ISR_RXNE_RXFNE_Pos USART_ISR_RXNE_Pos

#define	USART_ISR_RXNE_RXFNE_Msk USART_ISR_RXNE_Msk

#define	USART_ISR_RXNE_RXFNE USART_ISR_RXNE_Msk

#define	USART_ISR_TC_Pos (6U)

#define	USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos)

#define	USART_ISR_TC USART_ISR_TC_Msk

#define	USART_ISR_TXE_Pos (7U)

#define	USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos)

#define	USART_ISR_TXE USART_ISR_TXE_Msk

#define	USART_ISR_TXE_TXFNF_Pos USART_ISR_TXE_Pos

#define	USART_ISR_TXE_TXFNF_Msk USART_ISR_TXE_Msk

#define	USART_ISR_TXE_TXFNF USART_ISR_TXE_Msk

#define	USART_ISR_LBDF_Pos (8U)

#define	USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos)

#define	USART_ISR_LBDF USART_ISR_LBDF_Msk

#define	USART_ISR_CTSIF_Pos (9U)

#define	USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos)

#define	USART_ISR_CTSIF USART_ISR_CTSIF_Msk

#define	USART_ISR_CTS_Pos (10U)

#define	USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos)

#define	USART_ISR_CTS USART_ISR_CTS_Msk

#define	USART_ISR_RTOF_Pos (11U)

#define	USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos)

#define	USART_ISR_RTOF USART_ISR_RTOF_Msk

#define	USART_ISR_EOBF_Pos (12U)

#define	USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos)

#define	USART_ISR_EOBF USART_ISR_EOBF_Msk

#define	USART_ISR_UDR_Pos (13U)

#define	USART_ISR_UDR_Msk (0x1UL << USART_ISR_UDR_Pos)

#define	USART_ISR_UDR USART_ISR_UDR_Msk

#define	USART_ISR_ABRE_Pos (14U)

#define	USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos)

#define	USART_ISR_ABRE USART_ISR_ABRE_Msk

#define	USART_ISR_ABRF_Pos (15U)

#define	USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos)

#define	USART_ISR_ABRF USART_ISR_ABRF_Msk

#define	USART_ISR_BUSY_Pos (16U)

#define	USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos)

#define	USART_ISR_BUSY USART_ISR_BUSY_Msk

#define	USART_ISR_CMF_Pos (17U)

#define	USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos)

#define	USART_ISR_CMF USART_ISR_CMF_Msk

#define	USART_ISR_SBKF_Pos (18U)

#define	USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos)

#define	USART_ISR_SBKF USART_ISR_SBKF_Msk

#define	USART_ISR_RWU_Pos (19U)

#define	USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos)

#define	USART_ISR_RWU USART_ISR_RWU_Msk

#define	USART_ISR_WUF_Pos (20U)

#define	USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos)

#define	USART_ISR_WUF USART_ISR_WUF_Msk

#define	USART_ISR_TEACK_Pos (21U)

#define	USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos)

#define	USART_ISR_TEACK USART_ISR_TEACK_Msk

#define	USART_ISR_REACK_Pos (22U)

#define	USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos)

#define	USART_ISR_REACK USART_ISR_REACK_Msk

#define	USART_ISR_TXFE_Pos (23U)

#define	USART_ISR_TXFE_Msk (0x1UL << USART_ISR_TXFE_Pos)

#define	USART_ISR_TXFE USART_ISR_TXFE_Msk

#define	USART_ISR_RXFF_Pos (24U)

#define	USART_ISR_RXFF_Msk (0x1UL << USART_ISR_RXFF_Pos)

#define	USART_ISR_RXFF USART_ISR_RXFF_Msk

#define	USART_ISR_TCBGT_Pos (25U)

#define	USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos)

#define	USART_ISR_TCBGT USART_ISR_TCBGT_Msk

#define	USART_ISR_RXFT_Pos (26U)

#define	USART_ISR_RXFT_Msk (0x1UL << USART_ISR_RXFT_Pos)

#define	USART_ISR_RXFT USART_ISR_RXFT_Msk

#define	USART_ISR_TXFT_Pos (27U)

#define	USART_ISR_TXFT_Msk (0x1UL << USART_ISR_TXFT_Pos)

#define	USART_ISR_TXFT USART_ISR_TXFT_Msk

#define	USART_ICR_PECF_Pos (0U)

#define	USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos)

#define	USART_ICR_PECF USART_ICR_PECF_Msk

#define	USART_ICR_FECF_Pos (1U)

#define	USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos)

#define	USART_ICR_FECF USART_ICR_FECF_Msk

#define	USART_ICR_NECF_Pos (2U)

#define	USART_ICR_NECF_Msk (0x1UL << USART_ICR_NECF_Pos)

#define	USART_ICR_NECF USART_ICR_NECF_Msk

#define	USART_ICR_ORECF_Pos (3U)

#define	USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos)

#define	USART_ICR_ORECF USART_ICR_ORECF_Msk

#define	USART_ICR_IDLECF_Pos (4U)

#define	USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos)

#define	USART_ICR_IDLECF USART_ICR_IDLECF_Msk

#define	USART_ICR_TXFECF_Pos (5U)

#define	USART_ICR_TXFECF_Msk (0x1UL << USART_ICR_TXFECF_Pos)

#define	USART_ICR_TXFECF USART_ICR_TXFECF_Msk

#define	USART_ICR_TCCF_Pos (6U)

#define	USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos)

#define	USART_ICR_TCCF USART_ICR_TCCF_Msk

#define	USART_ICR_TCBGTCF_Pos (7U)

#define	USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos)

#define	USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk

#define	USART_ICR_LBDCF_Pos (8U)

#define	USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos)

#define	USART_ICR_LBDCF USART_ICR_LBDCF_Msk

#define	USART_ICR_CTSCF_Pos (9U)

#define	USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos)

#define	USART_ICR_CTSCF USART_ICR_CTSCF_Msk

#define	USART_ICR_RTOCF_Pos (11U)

#define	USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos)

#define	USART_ICR_RTOCF USART_ICR_RTOCF_Msk

#define	USART_ICR_EOBCF_Pos (12U)

#define	USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos)

#define	USART_ICR_EOBCF USART_ICR_EOBCF_Msk

#define	USART_ICR_UDRCF_Pos (13U)

#define	USART_ICR_UDRCF_Msk (0x1UL << USART_ICR_UDRCF_Pos)

#define	USART_ICR_UDRCF USART_ICR_UDRCF_Msk

#define	USART_ICR_CMCF_Pos (17U)

#define	USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos)

#define	USART_ICR_CMCF USART_ICR_CMCF_Msk

#define	USART_ICR_WUCF_Pos (20U)

#define	USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos)

#define	USART_ICR_WUCF USART_ICR_WUCF_Msk

#define	USART_RDR_RDR_Pos (0U)

#define	USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos)

#define	USART_RDR_RDR USART_RDR_RDR_Msk

#define	USART_TDR_TDR_Pos (0U)

#define	USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos)

#define	USART_TDR_TDR USART_TDR_TDR_Msk

#define	USART_PRESC_PRESCALER_Pos (0U)

#define	USART_PRESC_PRESCALER_Msk (0xFUL << USART_PRESC_PRESCALER_Pos)

#define	USART_PRESC_PRESCALER USART_PRESC_PRESCALER_Msk

#define	USART_PRESC_PRESCALER_0 (0x1UL << USART_PRESC_PRESCALER_Pos)

#define	USART_PRESC_PRESCALER_1 (0x2UL << USART_PRESC_PRESCALER_Pos)

#define	USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos)

#define	USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos)

#define	VREFBUF_CSR_ENVR_Pos (0U)

#define	VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos)

#define	VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk

#define	VREFBUF_CSR_HIZ_Pos (1U)

#define	VREFBUF_CSR_HIZ_Msk (0x1UL << VREFBUF_CSR_HIZ_Pos)

#define	VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk

#define	VREFBUF_CSR_VRR_Pos (3U)

#define	VREFBUF_CSR_VRR_Msk (0x1UL << VREFBUF_CSR_VRR_Pos)

#define	VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk

#define	VREFBUF_CSR_VRS_Pos (4U)

#define	VREFBUF_CSR_VRS_Msk (0x3UL << VREFBUF_CSR_VRS_Pos)

#define	VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk

#define	VREFBUF_CSR_VRS_0 (0x1UL << VREFBUF_CSR_VRS_Pos)

#define	VREFBUF_CSR_VRS_1 (0x2UL << VREFBUF_CSR_VRS_Pos)

#define	VREFBUF_CCR_TRIM_Pos (0U)

#define	VREFBUF_CCR_TRIM_Msk (0x3FUL << VREFBUF_CCR_TRIM_Pos)

#define	VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk

#define	USB_EP0R USB_BASE

#define	USB_EP1R (USB_BASE + 0x0x00000004)

#define	USB_EP2R (USB_BASE + 0x0x00000008)

#define	USB_EP3R (USB_BASE + 0x0x0000000C)

#define	USB_EP4R (USB_BASE + 0x0x00000010)

#define	USB_EP5R (USB_BASE + 0x0x00000014)

#define	USB_EP6R (USB_BASE + 0x0x00000018)

#define	USB_EP7R (USB_BASE + 0x0x0000001C)

#define	USB_EP_CTR_RX ((uint16_t)0x8000U)

#define	USB_EP_DTOG_RX ((uint16_t)0x4000U)

#define	USB_EPRX_STAT ((uint16_t)0x3000U)

#define	USB_EP_SETUP ((uint16_t)0x0800U)

#define	USB_EP_T_FIELD ((uint16_t)0x0600U)

#define	USB_EP_KIND ((uint16_t)0x0100U)

#define	USB_EP_CTR_TX ((uint16_t)0x0080U)

#define	USB_EP_DTOG_TX ((uint16_t)0x0040U)

#define	USB_EPTX_STAT ((uint16_t)0x0030U)

#define	USB_EPADDR_FIELD ((uint16_t)0x000FU)

#define	USB_EPREG_MASK (USB_EP_CTR_RX\|USB_EP_SETUP\|USB_EP_T_FIELD\|USB_EP_KIND\|USB_EP_CTR_TX\|USB_EPADDR_FIELD)

#define	USB_EP_TYPE_MASK ((uint16_t)0x0600U)

#define	USB_EP_BULK ((uint16_t)0x0000U)

#define	USB_EP_CONTROL ((uint16_t)0x0200U)

#define	USB_EP_ISOCHRONOUS ((uint16_t)0x0400U)

#define	USB_EP_INTERRUPT ((uint16_t)0x0600U)

#define	USB_EP_T_MASK ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)

#define	USB_EPKIND_MASK ((uint16_t)~USB_EP_KIND & USB_EPREG_MASK)

#define	USB_EP_TX_DIS ((uint16_t)0x0000U)

#define	USB_EP_TX_STALL ((uint16_t)0x0010U)

#define	USB_EP_TX_NAK ((uint16_t)0x0020U)

#define	USB_EP_TX_VALID ((uint16_t)0x0030U)

#define	USB_EPTX_DTOG1 ((uint16_t)0x0010U)

#define	USB_EPTX_DTOG2 ((uint16_t)0x0020U)

#define	USB_EPTX_DTOGMASK (USB_EPTX_STAT\|USB_EPREG_MASK)

#define	USB_EP_RX_DIS ((uint16_t)0x0000U)

#define	USB_EP_RX_STALL ((uint16_t)0x1000U)

#define	USB_EP_RX_NAK ((uint16_t)0x2000U)

#define	USB_EP_RX_VALID ((uint16_t)0x3000U)

#define	USB_EPRX_DTOG1 ((uint16_t)0x1000U)

#define	USB_EPRX_DTOG2 ((uint16_t)0x2000U)

#define	USB_EPRX_DTOGMASK (USB_EPRX_STAT\|USB_EPREG_MASK)

#define	USB_CNTR (USB_BASE + 0x00000040U)

#define	USB_ISTR (USB_BASE + 0x00000044U)

#define	USB_FNR (USB_BASE + 0x00000048U)

#define	USB_DADDR (USB_BASE + 0x0000004CU)

#define	USB_BTABLE (USB_BASE + 0x00000050U)

#define	USB_LPMCSR (USB_BASE + 0x00000054U)

#define	USB_BCDR (USB_BASE + 0x00000058U)

#define	USB_CNTR_CTRM ((uint16_t)0x8000U)

#define	USB_CNTR_PMAOVRM ((uint16_t)0x4000U)

#define	USB_CNTR_ERRM ((uint16_t)0x2000U)

#define	USB_CNTR_WKUPM ((uint16_t)0x1000U)

#define	USB_CNTR_SUSPM ((uint16_t)0x0800U)

#define	USB_CNTR_RESETM ((uint16_t)0x0400U)

#define	USB_CNTR_SOFM ((uint16_t)0x0200U)

#define	USB_CNTR_ESOFM ((uint16_t)0x0100U)

#define	USB_CNTR_L1REQM ((uint16_t)0x0080U)

#define	USB_CNTR_L1RESUME ((uint16_t)0x0020U)

#define	USB_CNTR_RESUME ((uint16_t)0x0010U)

#define	USB_CNTR_FSUSP ((uint16_t)0x0008U)

#define	USB_CNTR_LPMODE ((uint16_t)0x0004U)

#define	USB_CNTR_PDWN ((uint16_t)0x0002U)

#define	USB_CNTR_FRES ((uint16_t)0x0001U)

#define	USB_ISTR_EP_ID ((uint16_t)0x000FU)

#define	USB_ISTR_DIR ((uint16_t)0x0010U)

#define	USB_ISTR_L1REQ ((uint16_t)0x0080U)

#define	USB_ISTR_ESOF ((uint16_t)0x0100U)

#define	USB_ISTR_SOF ((uint16_t)0x0200U)

#define	USB_ISTR_RESET ((uint16_t)0x0400U)

#define	USB_ISTR_SUSP ((uint16_t)0x0800U)

#define	USB_ISTR_WKUP ((uint16_t)0x1000U)

#define	USB_ISTR_ERR ((uint16_t)0x2000U)

#define	USB_ISTR_PMAOVR ((uint16_t)0x4000U)

#define	USB_ISTR_CTR ((uint16_t)0x8000U)

#define	USB_CLR_L1REQ (~USB_ISTR_L1REQ)

#define	USB_CLR_ESOF (~USB_ISTR_ESOF)

#define	USB_CLR_SOF (~USB_ISTR_SOF)

#define	USB_CLR_RESET (~USB_ISTR_RESET)

#define	USB_CLR_SUSP (~USB_ISTR_SUSP)

#define	USB_CLR_WKUP (~USB_ISTR_WKUP)

#define	USB_CLR_ERR (~USB_ISTR_ERR)

#define	USB_CLR_PMAOVR (~USB_ISTR_PMAOVR)

#define	USB_CLR_CTR (~USB_ISTR_CTR)

#define	USB_FNR_FN ((uint16_t)0x07FFU)

#define	USB_FNR_LSOF ((uint16_t)0x1800U)

#define	USB_FNR_LCK ((uint16_t)0x2000U)

#define	USB_FNR_RXDM ((uint16_t)0x4000U)

#define	USB_FNR_RXDP ((uint16_t)0x8000U)

#define	USB_DADDR_ADD ((uint8_t)0x7FU)

#define	USB_DADDR_ADD0 ((uint8_t)0x01U)

#define	USB_DADDR_ADD1 ((uint8_t)0x02U)

#define	USB_DADDR_ADD2 ((uint8_t)0x04U)

#define	USB_DADDR_ADD3 ((uint8_t)0x08U)

#define	USB_DADDR_ADD4 ((uint8_t)0x10U)

#define	USB_DADDR_ADD5 ((uint8_t)0x20U)

#define	USB_DADDR_ADD6 ((uint8_t)0x40U)

#define	USB_DADDR_EF ((uint8_t)0x80U)

#define	USB_BTABLE_BTABLE ((uint16_t)0xFFF8U)

#define	USB_BCDR_BCDEN ((uint16_t)0x0001U)

#define	USB_BCDR_DCDEN ((uint16_t)0x0002U)

#define	USB_BCDR_PDEN ((uint16_t)0x0004U)

#define	USB_BCDR_SDEN ((uint16_t)0x0008U)

#define	USB_BCDR_DCDET ((uint16_t)0x0010U)

#define	USB_BCDR_PDET ((uint16_t)0x0020U)

#define	USB_BCDR_SDET ((uint16_t)0x0040U)

#define	USB_BCDR_PS2DET ((uint16_t)0x0080U)

#define	USB_BCDR_DPPU ((uint16_t)0x8000U)

#define	USB_LPMCSR_LMPEN ((uint16_t)0x0001U)

#define	USB_LPMCSR_LPMACK ((uint16_t)0x0002U)

#define	USB_LPMCSR_REMWAKE ((uint16_t)0x0008U)

#define	USB_LPMCSR_BESL ((uint16_t)0x00F0U)

#define	USB_ADDR0_TX_ADDR0_TX_Pos (1U)

#define	USB_ADDR0_TX_ADDR0_TX_Msk (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos)

#define	USB_ADDR0_TX_ADDR0_TX USB_ADDR0_TX_ADDR0_TX_Msk

#define	USB_ADDR1_TX_ADDR1_TX_Pos (1U)

#define	USB_ADDR1_TX_ADDR1_TX_Msk (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos)

#define	USB_ADDR1_TX_ADDR1_TX USB_ADDR1_TX_ADDR1_TX_Msk

#define	USB_ADDR2_TX_ADDR2_TX_Pos (1U)

#define	USB_ADDR2_TX_ADDR2_TX_Msk (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos)

#define	USB_ADDR2_TX_ADDR2_TX USB_ADDR2_TX_ADDR2_TX_Msk

#define	USB_ADDR3_TX_ADDR3_TX_Pos (1U)

#define	USB_ADDR3_TX_ADDR3_TX_Msk (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos)

#define	USB_ADDR3_TX_ADDR3_TX USB_ADDR3_TX_ADDR3_TX_Msk

#define	USB_ADDR4_TX_ADDR4_TX_Pos (1U)

#define	USB_ADDR4_TX_ADDR4_TX_Msk (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos)

#define	USB_ADDR4_TX_ADDR4_TX USB_ADDR4_TX_ADDR4_TX_Msk

#define	USB_ADDR5_TX_ADDR5_TX_Pos (1U)

#define	USB_ADDR5_TX_ADDR5_TX_Msk (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos)

#define	USB_ADDR5_TX_ADDR5_TX USB_ADDR5_TX_ADDR5_TX_Msk

#define	USB_ADDR6_TX_ADDR6_TX_Pos (1U)

#define	USB_ADDR6_TX_ADDR6_TX_Msk (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos)

#define	USB_ADDR6_TX_ADDR6_TX USB_ADDR6_TX_ADDR6_TX_Msk

#define	USB_ADDR7_TX_ADDR7_TX_Pos (1U)

#define	USB_ADDR7_TX_ADDR7_TX_Msk (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos)

#define	USB_ADDR7_TX_ADDR7_TX USB_ADDR7_TX_ADDR7_TX_Msk

#define	USB_COUNT0_TX_COUNT0_TX_Pos (0U)

#define	USB_COUNT0_TX_COUNT0_TX_Msk (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos)

#define	USB_COUNT0_TX_COUNT0_TX USB_COUNT0_TX_COUNT0_TX_Msk

#define	USB_COUNT1_TX_COUNT1_TX_Pos (0U)

#define	USB_COUNT1_TX_COUNT1_TX_Msk (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos)

#define	USB_COUNT1_TX_COUNT1_TX USB_COUNT1_TX_COUNT1_TX_Msk

#define	USB_COUNT2_TX_COUNT2_TX_Pos (0U)

#define	USB_COUNT2_TX_COUNT2_TX_Msk (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos)

#define	USB_COUNT2_TX_COUNT2_TX USB_COUNT2_TX_COUNT2_TX_Msk

#define	USB_COUNT3_TX_COUNT3_TX_Pos (0U)

#define	USB_COUNT3_TX_COUNT3_TX_Msk (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos)

#define	USB_COUNT3_TX_COUNT3_TX USB_COUNT3_TX_COUNT3_TX_Msk

#define	USB_COUNT4_TX_COUNT4_TX_Pos (0U)

#define	USB_COUNT4_TX_COUNT4_TX_Msk (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos)

#define	USB_COUNT4_TX_COUNT4_TX USB_COUNT4_TX_COUNT4_TX_Msk

#define	USB_COUNT5_TX_COUNT5_TX_Pos (0U)

#define	USB_COUNT5_TX_COUNT5_TX_Msk (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos)

#define	USB_COUNT5_TX_COUNT5_TX USB_COUNT5_TX_COUNT5_TX_Msk

#define	USB_COUNT6_TX_COUNT6_TX_Pos (0U)

#define	USB_COUNT6_TX_COUNT6_TX_Msk (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos)

#define	USB_COUNT6_TX_COUNT6_TX USB_COUNT6_TX_COUNT6_TX_Msk

#define	USB_COUNT7_TX_COUNT7_TX_Pos (0U)

#define	USB_COUNT7_TX_COUNT7_TX_Msk (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos)

#define	USB_COUNT7_TX_COUNT7_TX USB_COUNT7_TX_COUNT7_TX_Msk

#define	USB_COUNT0_TX_0_COUNT0_TX_0 (0x000003FFU)

#define	USB_COUNT0_TX_1_COUNT0_TX_1 (0x03FF0000U)

#define	USB_COUNT1_TX_0_COUNT1_TX_0 (0x000003FFU)

#define	USB_COUNT1_TX_1_COUNT1_TX_1 (0x03FF0000U)

#define	USB_COUNT2_TX_0_COUNT2_TX_0 (0x000003FFU)

#define	USB_COUNT2_TX_1_COUNT2_TX_1 (0x03FF0000U)

#define	USB_COUNT3_TX_0_COUNT3_TX_0 (0x000003FFU)

#define	USB_COUNT3_TX_1_COUNT3_TX_1 (0x03FF0000U)

#define	USB_COUNT4_TX_0_COUNT4_TX_0 (0x000003FFU)

#define	USB_COUNT4_TX_1_COUNT4_TX_1 (0x03FF0000U)

#define	USB_COUNT5_TX_0_COUNT5_TX_0 (0x000003FFU)

#define	USB_COUNT5_TX_1_COUNT5_TX_1 (0x03FF0000U)

#define	USB_COUNT6_TX_0_COUNT6_TX_0 (0x000003FFU)

#define	USB_COUNT6_TX_1_COUNT6_TX_1 (0x03FF0000U)

#define	USB_COUNT7_TX_0_COUNT7_TX_0 (0x000003FFU)

#define	USB_COUNT7_TX_1_COUNT7_TX_1 (0x03FF0000U)

#define	USB_ADDR0_RX_ADDR0_RX_Pos (1U)

#define	USB_ADDR0_RX_ADDR0_RX_Msk (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos)

#define	USB_ADDR0_RX_ADDR0_RX USB_ADDR0_RX_ADDR0_RX_Msk

#define	USB_ADDR1_RX_ADDR1_RX_Pos (1U)

#define	USB_ADDR1_RX_ADDR1_RX_Msk (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos)

#define	USB_ADDR1_RX_ADDR1_RX USB_ADDR1_RX_ADDR1_RX_Msk

#define	USB_ADDR2_RX_ADDR2_RX_Pos (1U)

#define	USB_ADDR2_RX_ADDR2_RX_Msk (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos)

#define	USB_ADDR2_RX_ADDR2_RX USB_ADDR2_RX_ADDR2_RX_Msk

#define	USB_ADDR3_RX_ADDR3_RX_Pos (1U)

#define	USB_ADDR3_RX_ADDR3_RX_Msk (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos)

#define	USB_ADDR3_RX_ADDR3_RX USB_ADDR3_RX_ADDR3_RX_Msk

#define	USB_ADDR4_RX_ADDR4_RX_Pos (1U)

#define	USB_ADDR4_RX_ADDR4_RX_Msk (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos)

#define	USB_ADDR4_RX_ADDR4_RX USB_ADDR4_RX_ADDR4_RX_Msk

#define	USB_ADDR5_RX_ADDR5_RX_Pos (1U)

#define	USB_ADDR5_RX_ADDR5_RX_Msk (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos)

#define	USB_ADDR5_RX_ADDR5_RX USB_ADDR5_RX_ADDR5_RX_Msk

#define	USB_ADDR6_RX_ADDR6_RX_Pos (1U)

#define	USB_ADDR6_RX_ADDR6_RX_Msk (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos)

#define	USB_ADDR6_RX_ADDR6_RX USB_ADDR6_RX_ADDR6_RX_Msk

#define	USB_ADDR7_RX_ADDR7_RX_Pos (1U)

#define	USB_ADDR7_RX_ADDR7_RX_Msk (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos)

#define	USB_ADDR7_RX_ADDR7_RX USB_ADDR7_RX_ADDR7_RX_Msk

#define	USB_COUNT0_RX_COUNT0_RX_Pos (0U)

#define	USB_COUNT0_RX_COUNT0_RX_Msk (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos)

#define	USB_COUNT0_RX_COUNT0_RX USB_COUNT0_RX_COUNT0_RX_Msk

#define	USB_COUNT0_RX_NUM_BLOCK_Pos (10U)

#define	USB_COUNT0_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos)

#define	USB_COUNT0_RX_NUM_BLOCK USB_COUNT0_RX_NUM_BLOCK_Msk

#define	USB_COUNT0_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos)

#define	USB_COUNT0_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos)

#define	USB_COUNT0_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos)

#define	USB_COUNT0_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos)

#define	USB_COUNT0_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos)

#define	USB_COUNT0_RX_BLSIZE_Pos (15U)

#define	USB_COUNT0_RX_BLSIZE_Msk (0x1UL << USB_COUNT0_RX_BLSIZE_Pos)

#define	USB_COUNT0_RX_BLSIZE USB_COUNT0_RX_BLSIZE_Msk

#define	USB_COUNT1_RX_COUNT1_RX_Pos (0U)

#define	USB_COUNT1_RX_COUNT1_RX_Msk (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos)

#define	USB_COUNT1_RX_COUNT1_RX USB_COUNT1_RX_COUNT1_RX_Msk

#define	USB_COUNT1_RX_NUM_BLOCK_Pos (10U)

#define	USB_COUNT1_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos)

#define	USB_COUNT1_RX_NUM_BLOCK USB_COUNT1_RX_NUM_BLOCK_Msk

#define	USB_COUNT1_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos)

#define	USB_COUNT1_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos)

#define	USB_COUNT1_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos)

#define	USB_COUNT1_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos)

#define	USB_COUNT1_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos)

#define	USB_COUNT1_RX_BLSIZE_Pos (15U)

#define	USB_COUNT1_RX_BLSIZE_Msk (0x1UL << USB_COUNT1_RX_BLSIZE_Pos)

#define	USB_COUNT1_RX_BLSIZE USB_COUNT1_RX_BLSIZE_Msk

#define	USB_COUNT2_RX_COUNT2_RX_Pos (0U)

#define	USB_COUNT2_RX_COUNT2_RX_Msk (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos)

#define	USB_COUNT2_RX_COUNT2_RX USB_COUNT2_RX_COUNT2_RX_Msk

#define	USB_COUNT2_RX_NUM_BLOCK_Pos (10U)

#define	USB_COUNT2_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos)

#define	USB_COUNT2_RX_NUM_BLOCK USB_COUNT2_RX_NUM_BLOCK_Msk

#define	USB_COUNT2_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos)

#define	USB_COUNT2_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos)

#define	USB_COUNT2_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos)

#define	USB_COUNT2_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos)

#define	USB_COUNT2_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos)

#define	USB_COUNT2_RX_BLSIZE_Pos (15U)

#define	USB_COUNT2_RX_BLSIZE_Msk (0x1UL << USB_COUNT2_RX_BLSIZE_Pos)

#define	USB_COUNT2_RX_BLSIZE USB_COUNT2_RX_BLSIZE_Msk

#define	USB_COUNT3_RX_COUNT3_RX_Pos (0U)

#define	USB_COUNT3_RX_COUNT3_RX_Msk (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos)

#define	USB_COUNT3_RX_COUNT3_RX USB_COUNT3_RX_COUNT3_RX_Msk

#define	USB_COUNT3_RX_NUM_BLOCK_Pos (10U)

#define	USB_COUNT3_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos)

#define	USB_COUNT3_RX_NUM_BLOCK USB_COUNT3_RX_NUM_BLOCK_Msk

#define	USB_COUNT3_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos)

#define	USB_COUNT3_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos)

#define	USB_COUNT3_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos)

#define	USB_COUNT3_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos)

#define	USB_COUNT3_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos)

#define	USB_COUNT3_RX_BLSIZE_Pos (15U)

#define	USB_COUNT3_RX_BLSIZE_Msk (0x1UL << USB_COUNT3_RX_BLSIZE_Pos)

#define	USB_COUNT3_RX_BLSIZE USB_COUNT3_RX_BLSIZE_Msk

#define	USB_COUNT4_RX_COUNT4_RX_Pos (0U)

#define	USB_COUNT4_RX_COUNT4_RX_Msk (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos)

#define	USB_COUNT4_RX_COUNT4_RX USB_COUNT4_RX_COUNT4_RX_Msk

#define	USB_COUNT4_RX_NUM_BLOCK_Pos (10U)

#define	USB_COUNT4_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos)

#define	USB_COUNT4_RX_NUM_BLOCK USB_COUNT4_RX_NUM_BLOCK_Msk

#define	USB_COUNT4_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos)

#define	USB_COUNT4_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos)

#define	USB_COUNT4_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos)

#define	USB_COUNT4_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos)

#define	USB_COUNT4_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos)

#define	USB_COUNT4_RX_BLSIZE_Pos (15U)

#define	USB_COUNT4_RX_BLSIZE_Msk (0x1UL << USB_COUNT4_RX_BLSIZE_Pos)

#define	USB_COUNT4_RX_BLSIZE USB_COUNT4_RX_BLSIZE_Msk

#define	USB_COUNT5_RX_COUNT5_RX_Pos (0U)

#define	USB_COUNT5_RX_COUNT5_RX_Msk (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos)

#define	USB_COUNT5_RX_COUNT5_RX USB_COUNT5_RX_COUNT5_RX_Msk

#define	USB_COUNT5_RX_NUM_BLOCK_Pos (10U)

#define	USB_COUNT5_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos)

#define	USB_COUNT5_RX_NUM_BLOCK USB_COUNT5_RX_NUM_BLOCK_Msk

#define	USB_COUNT5_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos)

#define	USB_COUNT5_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos)

#define	USB_COUNT5_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos)

#define	USB_COUNT5_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos)

#define	USB_COUNT5_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos)

#define	USB_COUNT5_RX_BLSIZE_Pos (15U)

#define	USB_COUNT5_RX_BLSIZE_Msk (0x1UL << USB_COUNT5_RX_BLSIZE_Pos)

#define	USB_COUNT5_RX_BLSIZE USB_COUNT5_RX_BLSIZE_Msk

#define	USB_COUNT6_RX_COUNT6_RX_Pos (0U)

#define	USB_COUNT6_RX_COUNT6_RX_Msk (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos)

#define	USB_COUNT6_RX_COUNT6_RX USB_COUNT6_RX_COUNT6_RX_Msk

#define	USB_COUNT6_RX_NUM_BLOCK_Pos (10U)

#define	USB_COUNT6_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos)

#define	USB_COUNT6_RX_NUM_BLOCK USB_COUNT6_RX_NUM_BLOCK_Msk

#define	USB_COUNT6_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos)

#define	USB_COUNT6_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos)

#define	USB_COUNT6_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos)

#define	USB_COUNT6_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos)

#define	USB_COUNT6_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos)

#define	USB_COUNT6_RX_BLSIZE_Pos (15U)

#define	USB_COUNT6_RX_BLSIZE_Msk (0x1UL << USB_COUNT6_RX_BLSIZE_Pos)

#define	USB_COUNT6_RX_BLSIZE USB_COUNT6_RX_BLSIZE_Msk

#define	USB_COUNT7_RX_COUNT7_RX_Pos (0U)

#define	USB_COUNT7_RX_COUNT7_RX_Msk (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos)

#define	USB_COUNT7_RX_COUNT7_RX USB_COUNT7_RX_COUNT7_RX_Msk

#define	USB_COUNT7_RX_NUM_BLOCK_Pos (10U)

#define	USB_COUNT7_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos)

#define	USB_COUNT7_RX_NUM_BLOCK USB_COUNT7_RX_NUM_BLOCK_Msk

#define	USB_COUNT7_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos)

#define	USB_COUNT7_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos)

#define	USB_COUNT7_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos)

#define	USB_COUNT7_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos)

#define	USB_COUNT7_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos)

#define	USB_COUNT7_RX_BLSIZE_Pos (15U)

#define	USB_COUNT7_RX_BLSIZE_Msk (0x1UL << USB_COUNT7_RX_BLSIZE_Pos)

#define	USB_COUNT7_RX_BLSIZE USB_COUNT7_RX_BLSIZE_Msk

#define	USB_COUNT0_RX_0_COUNT0_RX_0 (0x000003FFU)

#define	USB_COUNT0_RX_0_NUM_BLOCK_0 (0x00007C00U)

#define	USB_COUNT0_RX_0_NUM_BLOCK_0_0 (0x00000400U)

#define	USB_COUNT0_RX_0_NUM_BLOCK_0_1 (0x00000800U)

#define	USB_COUNT0_RX_0_NUM_BLOCK_0_2 (0x00001000U)

#define	USB_COUNT0_RX_0_NUM_BLOCK_0_3 (0x00002000U)

#define	USB_COUNT0_RX_0_NUM_BLOCK_0_4 (0x00004000U)

#define	USB_COUNT0_RX_0_BLSIZE_0 (0x00008000U)

#define	USB_COUNT0_RX_1_COUNT0_RX_1 (0x03FF0000U)

#define	USB_COUNT0_RX_1_NUM_BLOCK_1 (0x7C000000U)

#define	USB_COUNT0_RX_1_NUM_BLOCK_1_0 (0x04000000U)

#define	USB_COUNT0_RX_1_NUM_BLOCK_1_1 (0x08000000U)

#define	USB_COUNT0_RX_1_NUM_BLOCK_1_2 (0x10000000U)

#define	USB_COUNT0_RX_1_NUM_BLOCK_1_3 (0x20000000U)

#define	USB_COUNT0_RX_1_NUM_BLOCK_1_4 (0x40000000U)

#define	USB_COUNT0_RX_1_BLSIZE_1 (0x80000000U)

#define	USB_COUNT1_RX_0_COUNT1_RX_0 (0x000003FFU)

#define	USB_COUNT1_RX_0_NUM_BLOCK_0 (0x00007C00U)

#define	USB_COUNT1_RX_0_NUM_BLOCK_0_0 (0x00000400U)

#define	USB_COUNT1_RX_0_NUM_BLOCK_0_1 (0x00000800U)

#define	USB_COUNT1_RX_0_NUM_BLOCK_0_2 (0x00001000U)

#define	USB_COUNT1_RX_0_NUM_BLOCK_0_3 (0x00002000U)

#define	USB_COUNT1_RX_0_NUM_BLOCK_0_4 (0x00004000U)

#define	USB_COUNT1_RX_0_BLSIZE_0 (0x00008000U)

#define	USB_COUNT1_RX_1_COUNT1_RX_1 (0x03FF0000U)

#define	USB_COUNT1_RX_1_NUM_BLOCK_1 (0x7C000000U)

#define	USB_COUNT1_RX_1_NUM_BLOCK_1_0 (0x04000000U)

#define	USB_COUNT1_RX_1_NUM_BLOCK_1_1 (0x08000000U)

#define	USB_COUNT1_RX_1_NUM_BLOCK_1_2 (0x10000000U)

#define	USB_COUNT1_RX_1_NUM_BLOCK_1_3 (0x20000000U)

#define	USB_COUNT1_RX_1_NUM_BLOCK_1_4 (0x40000000U)

#define	USB_COUNT1_RX_1_BLSIZE_1 (0x80000000U)

#define	USB_COUNT2_RX_0_COUNT2_RX_0 (0x000003FFU)

#define	USB_COUNT2_RX_0_NUM_BLOCK_0 (0x00007C00U)

#define	USB_COUNT2_RX_0_NUM_BLOCK_0_0 (0x00000400U)

#define	USB_COUNT2_RX_0_NUM_BLOCK_0_1 (0x00000800U)

#define	USB_COUNT2_RX_0_NUM_BLOCK_0_2 (0x00001000U)

#define	USB_COUNT2_RX_0_NUM_BLOCK_0_3 (0x00002000U)

#define	USB_COUNT2_RX_0_NUM_BLOCK_0_4 (0x00004000U)

#define	USB_COUNT2_RX_0_BLSIZE_0 (0x00008000U)

#define	USB_COUNT2_RX_1_COUNT2_RX_1 (0x03FF0000U)

#define	USB_COUNT2_RX_1_NUM_BLOCK_1 (0x7C000000U)

#define	USB_COUNT2_RX_1_NUM_BLOCK_1_0 (0x04000000U)

#define	USB_COUNT2_RX_1_NUM_BLOCK_1_1 (0x08000000U)

#define	USB_COUNT2_RX_1_NUM_BLOCK_1_2 (0x10000000U)

#define	USB_COUNT2_RX_1_NUM_BLOCK_1_3 (0x20000000U)

#define	USB_COUNT2_RX_1_NUM_BLOCK_1_4 (0x40000000U)

#define	USB_COUNT2_RX_1_BLSIZE_1 (0x80000000U)

#define	USB_COUNT3_RX_0_COUNT3_RX_0 (0x000003FFU)

#define	USB_COUNT3_RX_0_NUM_BLOCK_0 (0x00007C00U)

#define	USB_COUNT3_RX_0_NUM_BLOCK_0_0 (0x00000400U)

#define	USB_COUNT3_RX_0_NUM_BLOCK_0_1 (0x00000800U)

#define	USB_COUNT3_RX_0_NUM_BLOCK_0_2 (0x00001000U)

#define	USB_COUNT3_RX_0_NUM_BLOCK_0_3 (0x00002000U)

#define	USB_COUNT3_RX_0_NUM_BLOCK_0_4 (0x00004000U)

#define	USB_COUNT3_RX_0_BLSIZE_0 (0x00008000U)

#define	USB_COUNT3_RX_1_COUNT3_RX_1 (0x03FF0000U)

#define	USB_COUNT3_RX_1_NUM_BLOCK_1 (0x7C000000U)

#define	USB_COUNT3_RX_1_NUM_BLOCK_1_0 (0x04000000U)

#define	USB_COUNT3_RX_1_NUM_BLOCK_1_1 (0x08000000U)

#define	USB_COUNT3_RX_1_NUM_BLOCK_1_2 (0x10000000U)

#define	USB_COUNT3_RX_1_NUM_BLOCK_1_3 (0x20000000U)

#define	USB_COUNT3_RX_1_NUM_BLOCK_1_4 (0x40000000U)

#define	USB_COUNT3_RX_1_BLSIZE_1 (0x80000000U)

#define	USB_COUNT4_RX_0_COUNT4_RX_0 (0x000003FFU)

#define	USB_COUNT4_RX_0_NUM_BLOCK_0 (0x00007C00U)

#define	USB_COUNT4_RX_0_NUM_BLOCK_0_0 (0x00000400U)

#define	USB_COUNT4_RX_0_NUM_BLOCK_0_1 (0x00000800U)

#define	USB_COUNT4_RX_0_NUM_BLOCK_0_2 (0x00001000U)

#define	USB_COUNT4_RX_0_NUM_BLOCK_0_3 (0x00002000U)

#define	USB_COUNT4_RX_0_NUM_BLOCK_0_4 (0x00004000U)

#define	USB_COUNT4_RX_0_BLSIZE_0 (0x00008000U)

#define	USB_COUNT4_RX_1_COUNT4_RX_1 (0x03FF0000U)

#define	USB_COUNT4_RX_1_NUM_BLOCK_1 (0x7C000000U)

#define	USB_COUNT4_RX_1_NUM_BLOCK_1_0 (0x04000000U)

#define	USB_COUNT4_RX_1_NUM_BLOCK_1_1 (0x08000000U)

#define	USB_COUNT4_RX_1_NUM_BLOCK_1_2 (0x10000000U)

#define	USB_COUNT4_RX_1_NUM_BLOCK_1_3 (0x20000000U)

#define	USB_COUNT4_RX_1_NUM_BLOCK_1_4 (0x40000000U)

#define	USB_COUNT4_RX_1_BLSIZE_1 (0x80000000U)

#define	USB_COUNT5_RX_0_COUNT5_RX_0 (0x000003FFU)

#define	USB_COUNT5_RX_0_NUM_BLOCK_0 (0x00007C00U)

#define	USB_COUNT5_RX_0_NUM_BLOCK_0_0 (0x00000400U)

#define	USB_COUNT5_RX_0_NUM_BLOCK_0_1 (0x00000800U)

#define	USB_COUNT5_RX_0_NUM_BLOCK_0_2 (0x00001000U)

#define	USB_COUNT5_RX_0_NUM_BLOCK_0_3 (0x00002000U)

#define	USB_COUNT5_RX_0_NUM_BLOCK_0_4 (0x00004000U)

#define	USB_COUNT5_RX_0_BLSIZE_0 (0x00008000U)

#define	USB_COUNT5_RX_1_COUNT5_RX_1 (0x03FF0000U)

#define	USB_COUNT5_RX_1_NUM_BLOCK_1 (0x7C000000U)

#define	USB_COUNT5_RX_1_NUM_BLOCK_1_0 (0x04000000U)

#define	USB_COUNT5_RX_1_NUM_BLOCK_1_1 (0x08000000U)

#define	USB_COUNT5_RX_1_NUM_BLOCK_1_2 (0x10000000U)

#define	USB_COUNT5_RX_1_NUM_BLOCK_1_3 (0x20000000U)

#define	USB_COUNT5_RX_1_NUM_BLOCK_1_4 (0x40000000U)

#define	USB_COUNT5_RX_1_BLSIZE_1 (0x80000000U)

#define	USB_COUNT6_RX_0_COUNT6_RX_0 (0x000003FFU)

#define	USB_COUNT6_RX_0_NUM_BLOCK_0 (0x00007C00U)

#define	USB_COUNT6_RX_0_NUM_BLOCK_0_0 (0x00000400U)

#define	USB_COUNT6_RX_0_NUM_BLOCK_0_1 (0x00000800U)

#define	USB_COUNT6_RX_0_NUM_BLOCK_0_2 (0x00001000U)

#define	USB_COUNT6_RX_0_NUM_BLOCK_0_3 (0x00002000U)

#define	USB_COUNT6_RX_0_NUM_BLOCK_0_4 (0x00004000U)

#define	USB_COUNT6_RX_0_BLSIZE_0 (0x00008000U)

#define	USB_COUNT6_RX_1_COUNT6_RX_1 (0x03FF0000U)

#define	USB_COUNT6_RX_1_NUM_BLOCK_1 (0x7C000000U)

#define	USB_COUNT6_RX_1_NUM_BLOCK_1_0 (0x04000000U)

#define	USB_COUNT6_RX_1_NUM_BLOCK_1_1 (0x08000000U)

#define	USB_COUNT6_RX_1_NUM_BLOCK_1_2 (0x10000000U)

#define	USB_COUNT6_RX_1_NUM_BLOCK_1_3 (0x20000000U)

#define	USB_COUNT6_RX_1_NUM_BLOCK_1_4 (0x40000000U)

#define	USB_COUNT6_RX_1_BLSIZE_1 (0x80000000U)

#define	USB_COUNT7_RX_0_COUNT7_RX_0 (0x000003FFU)

#define	USB_COUNT7_RX_0_NUM_BLOCK_0 (0x00007C00U)

#define	USB_COUNT7_RX_0_NUM_BLOCK_0_0 (0x00000400U)

#define	USB_COUNT7_RX_0_NUM_BLOCK_0_1 (0x00000800U)

#define	USB_COUNT7_RX_0_NUM_BLOCK_0_2 (0x00001000U)

#define	USB_COUNT7_RX_0_NUM_BLOCK_0_3 (0x00002000U)

#define	USB_COUNT7_RX_0_NUM_BLOCK_0_4 (0x00004000U)

#define	USB_COUNT7_RX_0_BLSIZE_0 (0x00008000U)

#define	USB_COUNT7_RX_1_COUNT7_RX_1 (0x03FF0000U)

#define	USB_COUNT7_RX_1_NUM_BLOCK_1 (0x7C000000U)

#define	USB_COUNT7_RX_1_NUM_BLOCK_1_0 (0x04000000U)

#define	USB_COUNT7_RX_1_NUM_BLOCK_1_1 (0x08000000U)

#define	USB_COUNT7_RX_1_NUM_BLOCK_1_2 (0x10000000U)

#define	USB_COUNT7_RX_1_NUM_BLOCK_1_3 (0x20000000U)

#define	USB_COUNT7_RX_1_NUM_BLOCK_1_4 (0x40000000U)

#define	USB_COUNT7_RX_1_BLSIZE_1 (0x80000000U)

#define	UCPD_CFG1_HBITCLKDIV_Pos (0U)

#define	UCPD_CFG1_HBITCLKDIV_Msk (0x3FUL << UCPD_CFG1_HBITCLKDIV_Pos)

#define	UCPD_CFG1_HBITCLKDIV UCPD_CFG1_HBITCLKDIV_Msk

#define	UCPD_CFG1_HBITCLKDIV_0 (0x01UL << UCPD_CFG1_HBITCLKDIV_Pos)

#define	UCPD_CFG1_HBITCLKDIV_1 (0x02UL << UCPD_CFG1_HBITCLKDIV_Pos)

#define	UCPD_CFG1_HBITCLKDIV_2 (0x04UL << UCPD_CFG1_HBITCLKDIV_Pos)

#define	UCPD_CFG1_HBITCLKDIV_3 (0x08UL << UCPD_CFG1_HBITCLKDIV_Pos)

#define	UCPD_CFG1_HBITCLKDIV_4 (0x10UL << UCPD_CFG1_HBITCLKDIV_Pos)

#define	UCPD_CFG1_HBITCLKDIV_5 (0x20UL << UCPD_CFG1_HBITCLKDIV_Pos)

#define	UCPD_CFG1_IFRGAP_Pos (6U)

#define	UCPD_CFG1_IFRGAP_Msk (0x1FUL << UCPD_CFG1_IFRGAP_Pos)

#define	UCPD_CFG1_IFRGAP UCPD_CFG1_IFRGAP_Msk

#define	UCPD_CFG1_IFRGAP_0 (0x01UL << UCPD_CFG1_IFRGAP_Pos)

#define	UCPD_CFG1_IFRGAP_1 (0x02UL << UCPD_CFG1_IFRGAP_Pos)

#define	UCPD_CFG1_IFRGAP_2 (0x04UL << UCPD_CFG1_IFRGAP_Pos)

#define	UCPD_CFG1_IFRGAP_3 (0x08UL << UCPD_CFG1_IFRGAP_Pos)

#define	UCPD_CFG1_IFRGAP_4 (0x10UL << UCPD_CFG1_IFRGAP_Pos)

#define	UCPD_CFG1_TRANSWIN_Pos (11U)

#define	UCPD_CFG1_TRANSWIN_Msk (0x1FUL << UCPD_CFG1_TRANSWIN_Pos)

#define	UCPD_CFG1_TRANSWIN UCPD_CFG1_TRANSWIN_Msk

#define	UCPD_CFG1_TRANSWIN_0 (0x01UL << UCPD_CFG1_TRANSWIN_Pos)

#define	UCPD_CFG1_TRANSWIN_1 (0x02UL << UCPD_CFG1_TRANSWIN_Pos)

#define	UCPD_CFG1_TRANSWIN_2 (0x04UL << UCPD_CFG1_TRANSWIN_Pos)

#define	UCPD_CFG1_TRANSWIN_3 (0x08UL << UCPD_CFG1_TRANSWIN_Pos)

#define	UCPD_CFG1_TRANSWIN_4 (0x10UL << UCPD_CFG1_TRANSWIN_Pos)

#define	UCPD_CFG1_PSC_UCPDCLK_Pos (17U)

#define	UCPD_CFG1_PSC_UCPDCLK_Msk (0x7UL << UCPD_CFG1_PSC_UCPDCLK_Pos)

#define	UCPD_CFG1_PSC_UCPDCLK UCPD_CFG1_PSC_UCPDCLK_Msk

#define	UCPD_CFG1_PSC_UCPDCLK_0 (0x1UL << UCPD_CFG1_PSC_UCPDCLK_Pos)

#define	UCPD_CFG1_PSC_UCPDCLK_1 (0x2UL << UCPD_CFG1_PSC_UCPDCLK_Pos)

#define	UCPD_CFG1_PSC_UCPDCLK_2 (0x4UL << UCPD_CFG1_PSC_UCPDCLK_Pos)

#define	UCPD_CFG1_RXORDSETEN_Pos (20U)

#define	UCPD_CFG1_RXORDSETEN_Msk (0x1FFUL << UCPD_CFG1_RXORDSETEN_Pos)

#define	UCPD_CFG1_RXORDSETEN UCPD_CFG1_RXORDSETEN_Msk

#define	UCPD_CFG1_RXORDSETEN_0 (0x001UL << UCPD_CFG1_RXORDSETEN_Pos)

#define	UCPD_CFG1_RXORDSETEN_1 (0x002UL << UCPD_CFG1_RXORDSETEN_Pos)

#define	UCPD_CFG1_RXORDSETEN_2 (0x004UL << UCPD_CFG1_RXORDSETEN_Pos)

#define	UCPD_CFG1_RXORDSETEN_3 (0x008UL << UCPD_CFG1_RXORDSETEN_Pos)

#define	UCPD_CFG1_RXORDSETEN_4 (0x010UL << UCPD_CFG1_RXORDSETEN_Pos)

#define	UCPD_CFG1_RXORDSETEN_5 (0x020UL << UCPD_CFG1_RXORDSETEN_Pos)

#define	UCPD_CFG1_RXORDSETEN_6 (0x040UL << UCPD_CFG1_RXORDSETEN_Pos)

#define	UCPD_CFG1_RXORDSETEN_7 (0x080UL << UCPD_CFG1_RXORDSETEN_Pos)

#define	UCPD_CFG1_RXORDSETEN_8 (0x100UL << UCPD_CFG1_RXORDSETEN_Pos)

#define	UCPD_CFG1_TXDMAEN_Pos (29U)

#define	UCPD_CFG1_TXDMAEN_Msk (0x1UL << UCPD_CFG1_TXDMAEN_Pos)

#define	UCPD_CFG1_TXDMAEN UCPD_CFG1_TXDMAEN_Msk

#define	UCPD_CFG1_RXDMAEN_Pos (30U)

#define	UCPD_CFG1_RXDMAEN_Msk (0x1UL << UCPD_CFG1_RXDMAEN_Pos)

#define	UCPD_CFG1_RXDMAEN UCPD_CFG1_RXDMAEN_Msk

#define	UCPD_CFG1_UCPDEN_Pos (31U)

#define	UCPD_CFG1_UCPDEN_Msk (0x1UL << UCPD_CFG1_UCPDEN_Pos)

#define	UCPD_CFG1_UCPDEN UCPD_CFG1_UCPDEN_Msk

#define	UCPD_CFG2_RXFILTDIS_Pos (0U)

#define	UCPD_CFG2_RXFILTDIS_Msk (0x1UL << UCPD_CFG2_RXFILTDIS_Pos)

#define	UCPD_CFG2_RXFILTDIS UCPD_CFG2_RXFILTDIS_Msk

#define	UCPD_CFG2_RXFILT2N3_Pos (1U)

#define	UCPD_CFG2_RXFILT2N3_Msk (0x1UL << UCPD_CFG2_RXFILT2N3_Pos)

#define	UCPD_CFG2_RXFILT2N3 UCPD_CFG2_RXFILT2N3_Msk

#define	UCPD_CFG2_FORCECLK_Pos (2U)

#define	UCPD_CFG2_FORCECLK_Msk (0x1UL << UCPD_CFG2_FORCECLK_Pos)

#define	UCPD_CFG2_FORCECLK UCPD_CFG2_FORCECLK_Msk

#define	UCPD_CFG2_WUPEN_Pos (3U)

#define	UCPD_CFG2_WUPEN_Msk (0x1UL << UCPD_CFG2_WUPEN_Pos)

#define	UCPD_CFG2_WUPEN UCPD_CFG2_WUPEN_Msk

#define	UCPD_CR_TXMODE_Pos (0U)

#define	UCPD_CR_TXMODE_Msk (0x3UL << UCPD_CR_TXMODE_Pos)

#define	UCPD_CR_TXMODE UCPD_CR_TXMODE_Msk

#define	UCPD_CR_TXMODE_0 (0x1UL << UCPD_CR_TXMODE_Pos)

#define	UCPD_CR_TXMODE_1 (0x2UL << UCPD_CR_TXMODE_Pos)

#define	UCPD_CR_TXSEND_Pos (2U)

#define	UCPD_CR_TXSEND_Msk (0x1UL << UCPD_CR_TXSEND_Pos)

#define	UCPD_CR_TXSEND UCPD_CR_TXSEND_Msk

#define	UCPD_CR_TXHRST_Pos (3U)

#define	UCPD_CR_TXHRST_Msk (0x1UL << UCPD_CR_TXHRST_Pos)

#define	UCPD_CR_TXHRST UCPD_CR_TXHRST_Msk

#define	UCPD_CR_RXMODE_Pos (4U)

#define	UCPD_CR_RXMODE_Msk (0x1UL << UCPD_CR_RXMODE_Pos)

#define	UCPD_CR_RXMODE UCPD_CR_RXMODE_Msk

#define	UCPD_CR_PHYRXEN_Pos (5U)

#define	UCPD_CR_PHYRXEN_Msk (0x1UL << UCPD_CR_PHYRXEN_Pos)

#define	UCPD_CR_PHYRXEN UCPD_CR_PHYRXEN_Msk

#define	UCPD_CR_PHYCCSEL_Pos (6U)

#define	UCPD_CR_PHYCCSEL_Msk (0x1UL << UCPD_CR_PHYCCSEL_Pos)

#define	UCPD_CR_PHYCCSEL UCPD_CR_PHYCCSEL_Msk

#define	UCPD_CR_ANASUBMODE_Pos (7U)

#define	UCPD_CR_ANASUBMODE_Msk (0x3UL << UCPD_CR_ANASUBMODE_Pos)

#define	UCPD_CR_ANASUBMODE UCPD_CR_ANASUBMODE_Msk

#define	UCPD_CR_ANASUBMODE_0 (0x1UL << UCPD_CR_ANASUBMODE_Pos)

#define	UCPD_CR_ANASUBMODE_1 (0x2UL << UCPD_CR_ANASUBMODE_Pos)

#define	UCPD_CR_ANAMODE_Pos (9U)

#define	UCPD_CR_ANAMODE_Msk (0x1UL << UCPD_CR_ANAMODE_Pos)

#define	UCPD_CR_ANAMODE UCPD_CR_ANAMODE_Msk

#define	UCPD_CR_CCENABLE_Pos (10U)

#define	UCPD_CR_CCENABLE_Msk (0x3UL << UCPD_CR_CCENABLE_Pos)

#define	UCPD_CR_CCENABLE UCPD_CR_CCENABLE_Msk

#define	UCPD_CR_CCENABLE_0 (0x1UL << UCPD_CR_CCENABLE_Pos)

#define	UCPD_CR_CCENABLE_1 (0x2UL << UCPD_CR_CCENABLE_Pos)

#define	UCPD_CR_FRSRXEN_Pos (16U)

#define	UCPD_CR_FRSRXEN_Msk (0x1UL << UCPD_CR_FRSRXEN_Pos)

#define	UCPD_CR_FRSRXEN UCPD_CR_FRSRXEN_Msk

#define	UCPD_CR_FRSTX_Pos (17U)

#define	UCPD_CR_FRSTX_Msk (0x1UL << UCPD_CR_FRSTX_Pos)

#define	UCPD_CR_FRSTX UCPD_CR_FRSTX_Msk

#define	UCPD_CR_RDCH_Pos (18U)

#define	UCPD_CR_RDCH_Msk (0x1UL << UCPD_CR_RDCH_Pos)

#define	UCPD_CR_RDCH UCPD_CR_RDCH_Msk

#define	UCPD_CR_CC1TCDIS_Pos (20U)

#define	UCPD_CR_CC1TCDIS_Msk (0x1UL << UCPD_CR_CC1TCDIS_Pos)

#define	UCPD_CR_CC1TCDIS UCPD_CR_CC1TCDIS_Msk

#define	UCPD_CR_CC2TCDIS_Pos (21U)

#define	UCPD_CR_CC2TCDIS_Msk (0x1UL << UCPD_CR_CC2TCDIS_Pos)

#define	UCPD_CR_CC2TCDIS UCPD_CR_CC2TCDIS_Msk

#define	UCPD_IMR_TXISIE_Pos (0U)

#define	UCPD_IMR_TXISIE_Msk (0x1UL << UCPD_IMR_TXISIE_Pos)

#define	UCPD_IMR_TXISIE UCPD_IMR_TXISIE_Msk

#define	UCPD_IMR_TXMSGDISCIE_Pos (1U)

#define	UCPD_IMR_TXMSGDISCIE_Msk (0x1UL << UCPD_IMR_TXMSGDISCIE_Pos)

#define	UCPD_IMR_TXMSGDISCIE UCPD_IMR_TXMSGDISCIE_Msk

#define	UCPD_IMR_TXMSGSENTIE_Pos (2U)

#define	UCPD_IMR_TXMSGSENTIE_Msk (0x1UL << UCPD_IMR_TXMSGSENTIE_Pos)

#define	UCPD_IMR_TXMSGSENTIE UCPD_IMR_TXMSGSENTIE_Msk

#define	UCPD_IMR_TXMSGABTIE_Pos (3U)

#define	UCPD_IMR_TXMSGABTIE_Msk (0x1UL << UCPD_IMR_TXMSGABTIE_Pos)

#define	UCPD_IMR_TXMSGABTIE UCPD_IMR_TXMSGABTIE_Msk

#define	UCPD_IMR_HRSTDISCIE_Pos (4U)

#define	UCPD_IMR_HRSTDISCIE_Msk (0x1UL << UCPD_IMR_HRSTDISCIE_Pos)

#define	UCPD_IMR_HRSTDISCIE UCPD_IMR_HRSTDISCIE_Msk

#define	UCPD_IMR_HRSTSENTIE_Pos (5U)

#define	UCPD_IMR_HRSTSENTIE_Msk (0x1UL << UCPD_IMR_HRSTSENTIE_Pos)

#define	UCPD_IMR_HRSTSENTIE UCPD_IMR_HRSTSENTIE_Msk

#define	UCPD_IMR_TXUNDIE_Pos (6U)

#define	UCPD_IMR_TXUNDIE_Msk (0x1UL << UCPD_IMR_TXUNDIE_Pos)

#define	UCPD_IMR_TXUNDIE UCPD_IMR_TXUNDIE_Msk

#define	UCPD_IMR_RXNEIE_Pos (8U)

#define	UCPD_IMR_RXNEIE_Msk (0x1UL << UCPD_IMR_RXNEIE_Pos)

#define	UCPD_IMR_RXNEIE UCPD_IMR_RXNEIE_Msk

#define	UCPD_IMR_RXORDDETIE_Pos (9U)

#define	UCPD_IMR_RXORDDETIE_Msk (0x1UL << UCPD_IMR_RXORDDETIE_Pos)

#define	UCPD_IMR_RXORDDETIE UCPD_IMR_RXORDDETIE_Msk

#define	UCPD_IMR_RXHRSTDETIE_Pos (10U)

#define	UCPD_IMR_RXHRSTDETIE_Msk (0x1UL << UCPD_IMR_RXHRSTDETIE_Pos)

#define	UCPD_IMR_RXHRSTDETIE UCPD_IMR_RXHRSTDETIE_Msk

#define	UCPD_IMR_RXOVRIE_Pos (11U)

#define	UCPD_IMR_RXOVRIE_Msk (0x1UL << UCPD_IMR_RXOVRIE_Pos)

#define	UCPD_IMR_RXOVRIE UCPD_IMR_RXOVRIE_Msk

#define	UCPD_IMR_RXMSGENDIE_Pos (12U)

#define	UCPD_IMR_RXMSGENDIE_Msk (0x1UL << UCPD_IMR_RXMSGENDIE_Pos)

#define	UCPD_IMR_RXMSGENDIE UCPD_IMR_RXMSGENDIE_Msk

#define	UCPD_IMR_TYPECEVT1IE_Pos (14U)

#define	UCPD_IMR_TYPECEVT1IE_Msk (0x1UL << UCPD_IMR_TYPECEVT1IE_Pos)

#define	UCPD_IMR_TYPECEVT1IE UCPD_IMR_TYPECEVT1IE_Msk

#define	UCPD_IMR_TYPECEVT2IE_Pos (15U)

#define	UCPD_IMR_TYPECEVT2IE_Msk (0x1UL << UCPD_IMR_TYPECEVT2IE_Pos)

#define	UCPD_IMR_TYPECEVT2IE UCPD_IMR_TYPECEVT2IE_Msk

#define	UCPD_IMR_FRSEVTIE_Pos (20U)

#define	UCPD_IMR_FRSEVTIE_Msk (0x1UL << UCPD_IMR_FRSEVTIE_Pos)

#define	UCPD_IMR_FRSEVTIE UCPD_IMR_FRSEVTIE_Msk

#define	UCPD_SR_TXIS_Pos (0U)

#define	UCPD_SR_TXIS_Msk (0x1UL << UCPD_SR_TXIS_Pos)

#define	UCPD_SR_TXIS UCPD_SR_TXIS_Msk

#define	UCPD_SR_TXMSGDISC_Pos (1U)

#define	UCPD_SR_TXMSGDISC_Msk (0x1UL << UCPD_SR_TXMSGDISC_Pos)

#define	UCPD_SR_TXMSGDISC UCPD_SR_TXMSGDISC_Msk

#define	UCPD_SR_TXMSGSENT_Pos (2U)

#define	UCPD_SR_TXMSGSENT_Msk (0x1UL << UCPD_SR_TXMSGSENT_Pos)

#define	UCPD_SR_TXMSGSENT UCPD_SR_TXMSGSENT_Msk

#define	UCPD_SR_TXMSGABT_Pos (3U)

#define	UCPD_SR_TXMSGABT_Msk (0x1UL << UCPD_SR_TXMSGABT_Pos)

#define	UCPD_SR_TXMSGABT UCPD_SR_TXMSGABT_Msk

#define	UCPD_SR_HRSTDISC_Pos (4U)

#define	UCPD_SR_HRSTDISC_Msk (0x1UL << UCPD_SR_HRSTDISC_Pos)

#define	UCPD_SR_HRSTDISC UCPD_SR_HRSTDISC_Msk

#define	UCPD_SR_HRSTSENT_Pos (5U)

#define	UCPD_SR_HRSTSENT_Msk (0x1UL << UCPD_SR_HRSTSENT_Pos)

#define	UCPD_SR_HRSTSENT UCPD_SR_HRSTSENT_Msk

#define	UCPD_SR_TXUND_Pos (6U)

#define	UCPD_SR_TXUND_Msk (0x1UL << UCPD_SR_TXUND_Pos)

#define	UCPD_SR_TXUND UCPD_SR_TXUND_Msk

#define	UCPD_SR_RXNE_Pos (8U)

#define	UCPD_SR_RXNE_Msk (0x1UL << UCPD_SR_RXNE_Pos)

#define	UCPD_SR_RXNE UCPD_SR_RXNE_Msk

#define	UCPD_SR_RXORDDET_Pos (9U)

#define	UCPD_SR_RXORDDET_Msk (0x1UL << UCPD_SR_RXORDDET_Pos)

#define	UCPD_SR_RXORDDET UCPD_SR_RXORDDET_Msk

#define	UCPD_SR_RXHRSTDET_Pos (10U)

#define	UCPD_SR_RXHRSTDET_Msk (0x1UL << UCPD_SR_RXHRSTDET_Pos)

#define	UCPD_SR_RXHRSTDET UCPD_SR_RXHRSTDET_Msk

#define	UCPD_SR_RXOVR_Pos (11U)

#define	UCPD_SR_RXOVR_Msk (0x1UL << UCPD_SR_RXOVR_Pos)

#define	UCPD_SR_RXOVR UCPD_SR_RXOVR_Msk

#define	UCPD_SR_RXMSGEND_Pos (12U)

#define	UCPD_SR_RXMSGEND_Msk (0x1UL << UCPD_SR_RXMSGEND_Pos)

#define	UCPD_SR_RXMSGEND UCPD_SR_RXMSGEND_Msk

#define	UCPD_SR_RXERR_Pos (13U)

#define	UCPD_SR_RXERR_Msk (0x1UL << UCPD_SR_RXERR_Pos)

#define	UCPD_SR_RXERR UCPD_SR_RXERR_Msk

#define	UCPD_SR_TYPECEVT1_Pos (14U)

#define	UCPD_SR_TYPECEVT1_Msk (0x1UL << UCPD_SR_TYPECEVT1_Pos)

#define	UCPD_SR_TYPECEVT1 UCPD_SR_TYPECEVT1_Msk

#define	UCPD_SR_TYPECEVT2_Pos (15U)

#define	UCPD_SR_TYPECEVT2_Msk (0x1UL << UCPD_SR_TYPECEVT2_Pos)

#define	UCPD_SR_TYPECEVT2 UCPD_SR_TYPECEVT2_Msk

#define	UCPD_SR_TYPEC_VSTATE_CC1_Pos (16U)

#define	UCPD_SR_TYPEC_VSTATE_CC1_Msk (0x3UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)

#define	UCPD_SR_TYPEC_VSTATE_CC1 UCPD_SR_TYPEC_VSTATE_CC1_Msk

#define	UCPD_SR_TYPEC_VSTATE_CC1_0 (0x1UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)

#define	UCPD_SR_TYPEC_VSTATE_CC1_1 (0x2UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)

#define	UCPD_SR_TYPEC_VSTATE_CC2_Pos (18U)

#define	UCPD_SR_TYPEC_VSTATE_CC2_Msk (0x3UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)

#define	UCPD_SR_TYPEC_VSTATE_CC2 UCPD_SR_TYPEC_VSTATE_CC2_Msk

#define	UCPD_SR_TYPEC_VSTATE_CC2_0 (0x1UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)

#define	UCPD_SR_TYPEC_VSTATE_CC2_1 (0x2UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)

#define	UCPD_SR_FRSEVT_Pos (20U)

#define	UCPD_SR_FRSEVT_Msk (0x1UL << UCPD_SR_FRSEVT_Pos)

#define	UCPD_SR_FRSEVT UCPD_SR_FRSEVT_Msk

#define	UCPD_ICR_TXMSGDISCCF_Pos (1U)

#define	UCPD_ICR_TXMSGDISCCF_Msk (0x1UL << UCPD_ICR_TXMSGDISCCF_Pos)

#define	UCPD_ICR_TXMSGDISCCF UCPD_ICR_TXMSGDISCCF_Msk

#define	UCPD_ICR_TXMSGSENTCF_Pos (2U)

#define	UCPD_ICR_TXMSGSENTCF_Msk (0x1UL << UCPD_ICR_TXMSGSENTCF_Pos)

#define	UCPD_ICR_TXMSGSENTCF UCPD_ICR_TXMSGSENTCF_Msk

#define	UCPD_ICR_TXMSGABTCF_Pos (3U)

#define	UCPD_ICR_TXMSGABTCF_Msk (0x1UL << UCPD_ICR_TXMSGABTCF_Pos)

#define	UCPD_ICR_TXMSGABTCF UCPD_ICR_TXMSGABTCF_Msk

#define	UCPD_ICR_HRSTDISCCF_Pos (4U)

#define	UCPD_ICR_HRSTDISCCF_Msk (0x1UL << UCPD_ICR_HRSTDISCCF_Pos)

#define	UCPD_ICR_HRSTDISCCF UCPD_ICR_HRSTDISCCF_Msk

#define	UCPD_ICR_HRSTSENTCF_Pos (5U)

#define	UCPD_ICR_HRSTSENTCF_Msk (0x1UL << UCPD_ICR_HRSTSENTCF_Pos)

#define	UCPD_ICR_HRSTSENTCF UCPD_ICR_HRSTSENTCF_Msk

#define	UCPD_ICR_TXUNDCF_Pos (6U)

#define	UCPD_ICR_TXUNDCF_Msk (0x1UL << UCPD_ICR_TXUNDCF_Pos)

#define	UCPD_ICR_TXUNDCF UCPD_ICR_TXUNDCF_Msk

#define	UCPD_ICR_RXORDDETCF_Pos (9U)

#define	UCPD_ICR_RXORDDETCF_Msk (0x1UL << UCPD_ICR_RXORDDETCF_Pos)

#define	UCPD_ICR_RXORDDETCF UCPD_ICR_RXORDDETCF_Msk

#define	UCPD_ICR_RXHRSTDETCF_Pos (10U)

#define	UCPD_ICR_RXHRSTDETCF_Msk (0x1UL << UCPD_ICR_RXHRSTDETCF_Pos)

#define	UCPD_ICR_RXHRSTDETCF UCPD_ICR_RXHRSTDETCF_Msk

#define	UCPD_ICR_RXOVRCF_Pos (11U)

#define	UCPD_ICR_RXOVRCF_Msk (0x1UL << UCPD_ICR_RXOVRCF_Pos)

#define	UCPD_ICR_RXOVRCF UCPD_ICR_RXOVRCF_Msk

#define	UCPD_ICR_RXMSGENDCF_Pos (12U)

#define	UCPD_ICR_RXMSGENDCF_Msk (0x1UL << UCPD_ICR_RXMSGENDCF_Pos)

#define	UCPD_ICR_RXMSGENDCF UCPD_ICR_RXMSGENDCF_Msk

#define	UCPD_ICR_TYPECEVT1CF_Pos (14U)

#define	UCPD_ICR_TYPECEVT1CF_Msk (0x1UL << UCPD_ICR_TYPECEVT1CF_Pos)

#define	UCPD_ICR_TYPECEVT1CF UCPD_ICR_TYPECEVT1CF_Msk

#define	UCPD_ICR_TYPECEVT2CF_Pos (15U)

#define	UCPD_ICR_TYPECEVT2CF_Msk (0x1UL << UCPD_ICR_TYPECEVT2CF_Pos)

#define	UCPD_ICR_TYPECEVT2CF UCPD_ICR_TYPECEVT2CF_Msk

#define	UCPD_ICR_FRSEVTCF_Pos (20U)

#define	UCPD_ICR_FRSEVTCF_Msk (0x1UL << UCPD_ICR_FRSEVTCF_Pos)

#define	UCPD_ICR_FRSEVTCF UCPD_ICR_FRSEVTCF_Msk

#define	UCPD_TX_ORDSET_TXORDSET_Pos (0U)

#define	UCPD_TX_ORDSET_TXORDSET_Msk (0xFFFFFUL << UCPD_TX_ORDSET_TXORDSET_Pos)

#define	UCPD_TX_ORDSET_TXORDSET UCPD_TX_ORDSET_TXORDSET_Msk

#define	UCPD_TX_PAYSZ_TXPAYSZ_Pos (0U)

#define	UCPD_TX_PAYSZ_TXPAYSZ_Msk (0x3FFUL << UCPD_TX_PAYSZ_TXPAYSZ_Pos)

#define	UCPD_TX_PAYSZ_TXPAYSZ UCPD_TX_PAYSZ_TXPAYSZ_Msk

#define	UCPD_TXDR_TXDATA_Pos (0U)

#define	UCPD_TXDR_TXDATA_Msk (0xFFUL << UCPD_TXDR_TXDATA_Pos)

#define	UCPD_TXDR_TXDATA UCPD_TXDR_TXDATA_Msk

#define	UCPD_RX_ORDSET_RXORDSET_Pos (0U)

#define	UCPD_RX_ORDSET_RXORDSET_Msk (0x7UL << UCPD_RX_ORDSET_RXORDSET_Pos)

#define	UCPD_RX_ORDSET_RXORDSET UCPD_RX_ORDSET_RXORDSET_Msk

#define	UCPD_RX_ORDSET_RXORDSET_0 (0x1UL << UCPD_RX_ORDSET_RXORDSET_Pos)

#define	UCPD_RX_ORDSET_RXORDSET_1 (0x2UL << UCPD_RX_ORDSET_RXORDSET_Pos)

#define	UCPD_RX_ORDSET_RXORDSET_2 (0x4UL << UCPD_RX_ORDSET_RXORDSET_Pos)

#define	UCPD_RX_ORDSET_RXSOP3OF4_Pos (3U)

#define	UCPD_RX_ORDSET_RXSOP3OF4_Msk (0x1UL << UCPD_RX_ORDSET_RXSOP3OF4_Pos)

#define	UCPD_RX_ORDSET_RXSOP3OF4 UCPD_RX_ORDSET_RXSOP3OF4_Msk

#define	UCPD_RX_ORDSET_RXSOPKINVALID_Pos (4U)

#define	UCPD_RX_ORDSET_RXSOPKINVALID_Msk (0x7UL << UCPD_RX_ORDSET_RXSOPKINVALID_Pos)

#define	UCPD_RX_ORDSET_RXSOPKINVALID UCPD_RX_ORDSET_RXSOPKINVALID_Msk

#define	UCPD_RX_PAYSZ_RXPAYSZ_Pos (0U)

#define	UCPD_RX_PAYSZ_RXPAYSZ_Msk (0x3FFUL << UCPD_RX_PAYSZ_RXPAYSZ_Pos)

#define	UCPD_RX_PAYSZ_RXPAYSZ UCPD_RX_PAYSZ_RXPAYSZ_Msk

#define	UCPD_RXDR_RXDATA_Pos (0U)

#define	UCPD_RXDR_RXDATA_Msk (0xFFUL << UCPD_RXDR_RXDATA_Pos)

#define	UCPD_RXDR_RXDATA UCPD_RXDR_RXDATA_Msk

#define	UCPD_RX_ORDEXT1_RXSOPX1_Pos (0U)

#define	UCPD_RX_ORDEXT1_RXSOPX1_Msk (0xFFFFFUL << UCPD_RX_ORDEXT1_RXSOPX1_Pos)

#define	UCPD_RX_ORDEXT1_RXSOPX1 UCPD_RX_ORDEXT1_RXSOPX1_Msk

#define	UCPD_RX_ORDEXT2_RXSOPX2_Pos (0U)

#define	UCPD_RX_ORDEXT2_RXSOPX2_Msk (0xFFFFFUL << UCPD_RX_ORDEXT2_RXSOPX2_Pos)

#define	UCPD_RX_ORDEXT2_RXSOPX2 UCPD_RX_ORDEXT2_RXSOPX2_Msk

#define	WWDG_CR_T_Pos (0U)

#define	WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos)

#define	WWDG_CR_T WWDG_CR_T_Msk

#define	WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos)

#define	WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos)

#define	WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos)

#define	WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos)

#define	WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos)

#define	WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos)

#define	WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos)

#define	WWDG_CR_WDGA_Pos (7U)

#define	WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos)

#define	WWDG_CR_WDGA WWDG_CR_WDGA_Msk

#define	WWDG_CFR_W_Pos (0U)

#define	WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos)

#define	WWDG_CFR_W WWDG_CFR_W_Msk

#define	WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos)

#define	WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos)

#define	WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos)

#define	WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos)

#define	WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos)

#define	WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos)

#define	WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos)

#define	WWDG_CFR_WDGTB_Pos (11U)

#define	WWDG_CFR_WDGTB_Msk (0x7UL << WWDG_CFR_WDGTB_Pos)

#define	WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk

#define	WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos)

#define	WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos)

#define	WWDG_CFR_WDGTB_2 (0x4UL << WWDG_CFR_WDGTB_Pos)

#define	WWDG_CFR_EWI_Pos (9U)

#define	WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos)

#define	WWDG_CFR_EWI WWDG_CFR_EWI_Msk

#define	WWDG_SR_EWIF_Pos (0U)

#define	WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos)

#define	WWDG_SR_EWIF WWDG_SR_EWIF_Msk

Detailed Description

Macro Definition Documentation

◆ ADC_AWD2CR_AWD2CH

#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk

ADC analog watchdog 2 monitored channel selection

Definition at line 1968 of file stm32g431xx.h.

◆ ADC_AWD2CR_AWD2CH_0

#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)

0x00000001

Definition at line 1969 of file stm32g431xx.h.

◆ ADC_AWD2CR_AWD2CH_1

#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)

0x00000002

Definition at line 1970 of file stm32g431xx.h.

◆ ADC_AWD2CR_AWD2CH_10

#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)

0x00000400

Definition at line 1979 of file stm32g431xx.h.

◆ ADC_AWD2CR_AWD2CH_11

#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)

0x00000800

Definition at line 1980 of file stm32g431xx.h.

◆ ADC_AWD2CR_AWD2CH_12

#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)

0x00001000

Definition at line 1981 of file stm32g431xx.h.

◆ ADC_AWD2CR_AWD2CH_13

#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)

0x00002000

Definition at line 1982 of file stm32g431xx.h.

◆ ADC_AWD2CR_AWD2CH_14

#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)

0x00004000

Definition at line 1983 of file stm32g431xx.h.

◆ ADC_AWD2CR_AWD2CH_15

#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)

0x00008000

Definition at line 1984 of file stm32g431xx.h.

◆ ADC_AWD2CR_AWD2CH_16

#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)

0x00010000

Definition at line 1985 of file stm32g431xx.h.

◆ ADC_AWD2CR_AWD2CH_17

#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)

0x00020000

Definition at line 1986 of file stm32g431xx.h.

◆ ADC_AWD2CR_AWD2CH_18

#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)

0x00040000

Definition at line 1987 of file stm32g431xx.h.

◆ ADC_AWD2CR_AWD2CH_2

#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)

0x00000004

Definition at line 1971 of file stm32g431xx.h.

◆ ADC_AWD2CR_AWD2CH_3

#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)

0x00000008

Definition at line 1972 of file stm32g431xx.h.

◆ ADC_AWD2CR_AWD2CH_4

#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)

0x00000010

Definition at line 1973 of file stm32g431xx.h.

◆ ADC_AWD2CR_AWD2CH_5

#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)

0x00000020

Definition at line 1974 of file stm32g431xx.h.

◆ ADC_AWD2CR_AWD2CH_6

#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)

0x00000040

Definition at line 1975 of file stm32g431xx.h.

◆ ADC_AWD2CR_AWD2CH_7

#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)

0x00000080

Definition at line 1976 of file stm32g431xx.h.

◆ ADC_AWD2CR_AWD2CH_8

#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)

0x00000100

Definition at line 1977 of file stm32g431xx.h.

◆ ADC_AWD2CR_AWD2CH_9

#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)

0x00000200

Definition at line 1978 of file stm32g431xx.h.

◆ ADC_AWD2CR_AWD2CH_Msk

#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos)

0x0007FFFF

Definition at line 1967 of file stm32g431xx.h.

◆ ADC_AWD2CR_AWD2CH_Pos

#define ADC_AWD2CR_AWD2CH_Pos (0U)

Definition at line 1966 of file stm32g431xx.h.

◆ ADC_AWD3CR_AWD3CH

#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk

ADC analog watchdog 3 monitored channel selection

Definition at line 1992 of file stm32g431xx.h.

◆ ADC_AWD3CR_AWD3CH_0

#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)

0x00000001

Definition at line 1993 of file stm32g431xx.h.

◆ ADC_AWD3CR_AWD3CH_1

#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)

0x00000002

Definition at line 1994 of file stm32g431xx.h.

◆ ADC_AWD3CR_AWD3CH_10

#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)

0x00000400

Definition at line 2003 of file stm32g431xx.h.

◆ ADC_AWD3CR_AWD3CH_11

#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)

0x00000800

Definition at line 2004 of file stm32g431xx.h.

◆ ADC_AWD3CR_AWD3CH_12

#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)

0x00001000

Definition at line 2005 of file stm32g431xx.h.

◆ ADC_AWD3CR_AWD3CH_13

#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)

0x00002000

Definition at line 2006 of file stm32g431xx.h.

◆ ADC_AWD3CR_AWD3CH_14

#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)

0x00004000

Definition at line 2007 of file stm32g431xx.h.

◆ ADC_AWD3CR_AWD3CH_15

#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)

0x00008000

Definition at line 2008 of file stm32g431xx.h.

◆ ADC_AWD3CR_AWD3CH_16

#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)

0x00010000

Definition at line 2009 of file stm32g431xx.h.

◆ ADC_AWD3CR_AWD3CH_17

#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)

0x00020000

Definition at line 2010 of file stm32g431xx.h.

◆ ADC_AWD3CR_AWD3CH_18

#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)

0x00040000

Definition at line 2011 of file stm32g431xx.h.

◆ ADC_AWD3CR_AWD3CH_2

#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)

0x00000004

Definition at line 1995 of file stm32g431xx.h.

◆ ADC_AWD3CR_AWD3CH_3

#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)

0x00000008

Definition at line 1996 of file stm32g431xx.h.

◆ ADC_AWD3CR_AWD3CH_4

#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)

0x00000010

Definition at line 1997 of file stm32g431xx.h.

◆ ADC_AWD3CR_AWD3CH_5

#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)

0x00000020

Definition at line 1998 of file stm32g431xx.h.

◆ ADC_AWD3CR_AWD3CH_6

#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)

0x00000040

Definition at line 1999 of file stm32g431xx.h.

◆ ADC_AWD3CR_AWD3CH_7

#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)

0x00000080

Definition at line 2000 of file stm32g431xx.h.

◆ ADC_AWD3CR_AWD3CH_8

#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)

0x00000100

Definition at line 2001 of file stm32g431xx.h.

◆ ADC_AWD3CR_AWD3CH_9

#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)

0x00000200

Definition at line 2002 of file stm32g431xx.h.

◆ ADC_AWD3CR_AWD3CH_Msk

#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos)

0x0007FFFF

Definition at line 1991 of file stm32g431xx.h.

◆ ADC_AWD3CR_AWD3CH_Pos

#define ADC_AWD3CR_AWD3CH_Pos (0U)

Definition at line 1990 of file stm32g431xx.h.

◆ ADC_CALFACT_CALFACT_D

#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk

ADC calibration factor in differential mode

Definition at line 2051 of file stm32g431xx.h.

◆ ADC_CALFACT_CALFACT_D_0

#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos)

0x00010000

Definition at line 2052 of file stm32g431xx.h.

◆ ADC_CALFACT_CALFACT_D_1

#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos)

0x00020000

Definition at line 2053 of file stm32g431xx.h.

◆ ADC_CALFACT_CALFACT_D_2

#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos)

0x00040000

Definition at line 2054 of file stm32g431xx.h.

◆ ADC_CALFACT_CALFACT_D_3

#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos)

0x00080000

Definition at line 2055 of file stm32g431xx.h.

◆ ADC_CALFACT_CALFACT_D_4

#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos)

0x00100000

Definition at line 2056 of file stm32g431xx.h.

◆ ADC_CALFACT_CALFACT_D_5

#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos)

0x00200000

Definition at line 2057 of file stm32g431xx.h.

◆ ADC_CALFACT_CALFACT_D_6

#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos)

0x00300000

Definition at line 2058 of file stm32g431xx.h.

◆ ADC_CALFACT_CALFACT_D_Msk

#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos)

0x007F0000

Definition at line 2050 of file stm32g431xx.h.

◆ ADC_CALFACT_CALFACT_D_Pos

#define ADC_CALFACT_CALFACT_D_Pos (16U)

Definition at line 2049 of file stm32g431xx.h.

◆ ADC_CALFACT_CALFACT_S

#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk

ADC calibration factor in single-ended mode

Definition at line 2040 of file stm32g431xx.h.

◆ ADC_CALFACT_CALFACT_S_0

#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos)

0x00000001

Definition at line 2041 of file stm32g431xx.h.

◆ ADC_CALFACT_CALFACT_S_1

#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos)

0x00000002

Definition at line 2042 of file stm32g431xx.h.

◆ ADC_CALFACT_CALFACT_S_2

#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos)

0x00000004

Definition at line 2043 of file stm32g431xx.h.

◆ ADC_CALFACT_CALFACT_S_3

#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos)

0x00000008

Definition at line 2044 of file stm32g431xx.h.

◆ ADC_CALFACT_CALFACT_S_4

#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos)

0x00000010

Definition at line 2045 of file stm32g431xx.h.

◆ ADC_CALFACT_CALFACT_S_5

#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos)

0x00000020

Definition at line 2046 of file stm32g431xx.h.

◆ ADC_CALFACT_CALFACT_S_6

#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos)

0x00000030

Definition at line 2047 of file stm32g431xx.h.

◆ ADC_CALFACT_CALFACT_S_Msk

#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos)

0x0000007F

Definition at line 2039 of file stm32g431xx.h.

◆ ADC_CALFACT_CALFACT_S_Pos

#define ADC_CALFACT_CALFACT_S_Pos (0U)

Definition at line 2038 of file stm32g431xx.h.

◆ ADC_CCR_CKMODE

#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk

ADC common clock source and prescaler (prescaler only for clock source synchronous)

Definition at line 2165 of file stm32g431xx.h.

◆ ADC_CCR_CKMODE_0

#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos)

0x00010000

Definition at line 2166 of file stm32g431xx.h.

◆ ADC_CCR_CKMODE_1

#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos)

0x00020000

Definition at line 2167 of file stm32g431xx.h.

◆ ADC_CCR_CKMODE_Msk

#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos)

0x00030000

Definition at line 2164 of file stm32g431xx.h.

◆ ADC_CCR_CKMODE_Pos

#define ADC_CCR_CKMODE_Pos (16U)

Definition at line 2163 of file stm32g431xx.h.

◆ ADC_CCR_DELAY

#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk

ADC multimode delay between 2 sampling phases

Definition at line 2147 of file stm32g431xx.h.

◆ ADC_CCR_DELAY_0

#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos)

0x00000100

Definition at line 2148 of file stm32g431xx.h.

◆ ADC_CCR_DELAY_1

#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos)

0x00000200

Definition at line 2149 of file stm32g431xx.h.

◆ ADC_CCR_DELAY_2

#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos)

0x00000400

Definition at line 2150 of file stm32g431xx.h.

◆ ADC_CCR_DELAY_3

#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos)

0x00000800

Definition at line 2151 of file stm32g431xx.h.

◆ ADC_CCR_DELAY_Msk

#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos)

0x00000F00

Definition at line 2146 of file stm32g431xx.h.

◆ ADC_CCR_DELAY_Pos

#define ADC_CCR_DELAY_Pos (8U)

Definition at line 2145 of file stm32g431xx.h.

◆ ADC_CCR_DMACFG

#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk

ADC multimode DMA transfer configuration

Definition at line 2155 of file stm32g431xx.h.

◆ ADC_CCR_DMACFG_Msk

#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos)

0x00002000

Definition at line 2154 of file stm32g431xx.h.

◆ ADC_CCR_DMACFG_Pos

#define ADC_CCR_DMACFG_Pos (13U)

Definition at line 2153 of file stm32g431xx.h.

◆ ADC_CCR_DUAL

#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk

ADC multimode mode selection

Definition at line 2138 of file stm32g431xx.h.

◆ ADC_CCR_DUAL_0

#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos)

0x00000001

Definition at line 2139 of file stm32g431xx.h.

◆ ADC_CCR_DUAL_1

#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos)

0x00000002

Definition at line 2140 of file stm32g431xx.h.

◆ ADC_CCR_DUAL_2

#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos)

0x00000004

Definition at line 2141 of file stm32g431xx.h.

◆ ADC_CCR_DUAL_3

#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos)

0x00000008

Definition at line 2142 of file stm32g431xx.h.

◆ ADC_CCR_DUAL_4

#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos)

0x00000010

Definition at line 2143 of file stm32g431xx.h.

◆ ADC_CCR_DUAL_Msk

#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos)

0x0000001F

Definition at line 2137 of file stm32g431xx.h.

◆ ADC_CCR_DUAL_Pos

#define ADC_CCR_DUAL_Pos (0U)

Definition at line 2136 of file stm32g431xx.h.

◆ ADC_CCR_MDMA

#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk

ADC multimode DMA transfer enable

Definition at line 2159 of file stm32g431xx.h.

◆ ADC_CCR_MDMA_0

#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos)

0x00004000

Definition at line 2160 of file stm32g431xx.h.

◆ ADC_CCR_MDMA_1

#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos)

0x00008000

Definition at line 2161 of file stm32g431xx.h.

◆ ADC_CCR_MDMA_Msk

#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos)

0x0000C000

Definition at line 2158 of file stm32g431xx.h.

◆ ADC_CCR_MDMA_Pos

#define ADC_CCR_MDMA_Pos (14U)

Definition at line 2157 of file stm32g431xx.h.

◆ ADC_CCR_PRESC

#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk

ADC common clock prescaler, only for clock source asynchronous

Definition at line 2171 of file stm32g431xx.h.

◆ ADC_CCR_PRESC_0

#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos)

0x00040000

Definition at line 2172 of file stm32g431xx.h.

◆ ADC_CCR_PRESC_1

#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos)

0x00080000

Definition at line 2173 of file stm32g431xx.h.

◆ ADC_CCR_PRESC_2

#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos)

0x00100000

Definition at line 2174 of file stm32g431xx.h.

◆ ADC_CCR_PRESC_3

#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos)

0x00200000

Definition at line 2175 of file stm32g431xx.h.

◆ ADC_CCR_PRESC_Msk

#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos)

0x003C0000

Definition at line 2170 of file stm32g431xx.h.

◆ ADC_CCR_PRESC_Pos

#define ADC_CCR_PRESC_Pos (18U)

Definition at line 2169 of file stm32g431xx.h.

◆ ADC_CCR_VBATSEL

#define ADC_CCR_VBATSEL ADC_CCR_VBATSEL_Msk

ADC internal path to battery voltage enable

Definition at line 2185 of file stm32g431xx.h.

◆ ADC_CCR_VBATSEL_Msk

#define ADC_CCR_VBATSEL_Msk (0x1UL << ADC_CCR_VBATSEL_Pos)

0x01000000

Definition at line 2184 of file stm32g431xx.h.

◆ ADC_CCR_VBATSEL_Pos

#define ADC_CCR_VBATSEL_Pos (24U)

Definition at line 2183 of file stm32g431xx.h.

◆ ADC_CCR_VREFEN

#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk

ADC internal path to VrefInt enable

Definition at line 2179 of file stm32g431xx.h.

◆ ADC_CCR_VREFEN_Msk

#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos)

0x00400000

Definition at line 2178 of file stm32g431xx.h.

◆ ADC_CCR_VREFEN_Pos

#define ADC_CCR_VREFEN_Pos (22U)

Definition at line 2177 of file stm32g431xx.h.

◆ ADC_CCR_VSENSESEL

#define ADC_CCR_VSENSESEL ADC_CCR_VSENSESEL_Msk

ADC internal path to temperature sensor enable

Definition at line 2182 of file stm32g431xx.h.

◆ ADC_CCR_VSENSESEL_Msk

#define ADC_CCR_VSENSESEL_Msk (0x1UL << ADC_CCR_VSENSESEL_Pos)

0x00800000

Definition at line 2181 of file stm32g431xx.h.

◆ ADC_CCR_VSENSESEL_Pos

#define ADC_CCR_VSENSESEL_Pos (23U)

Definition at line 2180 of file stm32g431xx.h.

◆ ADC_CDR_RDATA_MST

#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk

ADC multimode master group regular conversion data

Definition at line 2190 of file stm32g431xx.h.

◆ ADC_CDR_RDATA_MST_Msk

#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)

0x0000FFFF

Definition at line 2189 of file stm32g431xx.h.

◆ ADC_CDR_RDATA_MST_Pos

#define ADC_CDR_RDATA_MST_Pos (0U)

Definition at line 2188 of file stm32g431xx.h.

◆ ADC_CDR_RDATA_SLV

#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk

ADC multimode slave group regular conversion data

Definition at line 2194 of file stm32g431xx.h.

◆ ADC_CDR_RDATA_SLV_Msk

#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)

0xFFFF0000

Definition at line 2193 of file stm32g431xx.h.

◆ ADC_CDR_RDATA_SLV_Pos

#define ADC_CDR_RDATA_SLV_Pos (16U)

Definition at line 2192 of file stm32g431xx.h.

◆ ADC_CFGR2_BULB

#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk

ADC Bulb sampling mode

Definition at line 1448 of file stm32g431xx.h.

◆ ADC_CFGR2_BULB_Msk

#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos)

0x04000000

Definition at line 1447 of file stm32g431xx.h.

◆ ADC_CFGR2_BULB_Pos

#define ADC_CFGR2_BULB_Pos (26U)

Definition at line 1446 of file stm32g431xx.h.

◆ ADC_CFGR2_GCOMP

#define ADC_CFGR2_GCOMP ADC_CFGR2_GCOMP_Msk

ADC Gain Compensation mode

Definition at line 1441 of file stm32g431xx.h.

◆ ADC_CFGR2_GCOMP_Msk

#define ADC_CFGR2_GCOMP_Msk (0x1UL << ADC_CFGR2_GCOMP_Pos)

0x00010000

Definition at line 1440 of file stm32g431xx.h.

◆ ADC_CFGR2_GCOMP_Pos

#define ADC_CFGR2_GCOMP_Pos (16U)

Definition at line 1439 of file stm32g431xx.h.

◆ ADC_CFGR2_JOVSE

#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk

ADC oversampler enable on scope ADC group injected

Definition at line 1415 of file stm32g431xx.h.

◆ ADC_CFGR2_JOVSE_Msk

#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos)

0x00000002

Definition at line 1414 of file stm32g431xx.h.

◆ ADC_CFGR2_JOVSE_Pos

#define ADC_CFGR2_JOVSE_Pos (1U)

Definition at line 1413 of file stm32g431xx.h.

◆ ADC_CFGR2_OVSR

#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk

ADC oversampling ratio

Definition at line 1419 of file stm32g431xx.h.

◆ ADC_CFGR2_OVSR_0

#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos)

0x00000004

Definition at line 1420 of file stm32g431xx.h.

◆ ADC_CFGR2_OVSR_1

#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos)

0x00000008

Definition at line 1421 of file stm32g431xx.h.

◆ ADC_CFGR2_OVSR_2

#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos)

0x00000010

Definition at line 1422 of file stm32g431xx.h.

◆ ADC_CFGR2_OVSR_Msk

#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos)

0x0000001C

Definition at line 1418 of file stm32g431xx.h.

◆ ADC_CFGR2_OVSR_Pos

#define ADC_CFGR2_OVSR_Pos (2U)

Definition at line 1417 of file stm32g431xx.h.

◆ ADC_CFGR2_OVSS

#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk

ADC oversampling shift

Definition at line 1426 of file stm32g431xx.h.

◆ ADC_CFGR2_OVSS_0

#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos)

0x00000020

Definition at line 1427 of file stm32g431xx.h.

◆ ADC_CFGR2_OVSS_1

#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos)

0x00000040

Definition at line 1428 of file stm32g431xx.h.

◆ ADC_CFGR2_OVSS_2

#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos)

0x00000080

Definition at line 1429 of file stm32g431xx.h.

◆ ADC_CFGR2_OVSS_3

#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos)

0x00000100

Definition at line 1430 of file stm32g431xx.h.

◆ ADC_CFGR2_OVSS_Msk

#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos)

0x000001E0

Definition at line 1425 of file stm32g431xx.h.

◆ ADC_CFGR2_OVSS_Pos

#define ADC_CFGR2_OVSS_Pos (5U)

Definition at line 1424 of file stm32g431xx.h.

◆ ADC_CFGR2_ROVSE

#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk

ADC oversampler enable on scope ADC group regular

Definition at line 1412 of file stm32g431xx.h.

◆ ADC_CFGR2_ROVSE_Msk

#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos)

0x00000001

Definition at line 1411 of file stm32g431xx.h.

◆ ADC_CFGR2_ROVSE_Pos

#define ADC_CFGR2_ROVSE_Pos (0U)

Definition at line 1410 of file stm32g431xx.h.

◆ ADC_CFGR2_ROVSM

#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk

ADC oversampling mode managing interlaced conversions of ADC group regular and group injected

Definition at line 1437 of file stm32g431xx.h.

◆ ADC_CFGR2_ROVSM_Msk

#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos)

0x00000400

Definition at line 1436 of file stm32g431xx.h.

◆ ADC_CFGR2_ROVSM_Pos

#define ADC_CFGR2_ROVSM_Pos (10U)

Definition at line 1435 of file stm32g431xx.h.

◆ ADC_CFGR2_SMPTRIG

#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk

ADC Sample Time Control Trigger mode

Definition at line 1451 of file stm32g431xx.h.

◆ ADC_CFGR2_SMPTRIG_Msk

#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos)

0x08000000

Definition at line 1450 of file stm32g431xx.h.

◆ ADC_CFGR2_SMPTRIG_Pos

#define ADC_CFGR2_SMPTRIG_Pos (27U)

Definition at line 1449 of file stm32g431xx.h.

◆ ADC_CFGR2_SWTRIG

#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk

ADC Software Trigger Bit for Sample time control trigger mode

Definition at line 1445 of file stm32g431xx.h.

◆ ADC_CFGR2_SWTRIG_Msk

#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos)

0x02000000

Definition at line 1444 of file stm32g431xx.h.

◆ ADC_CFGR2_SWTRIG_Pos

#define ADC_CFGR2_SWTRIG_Pos (25U)

Definition at line 1443 of file stm32g431xx.h.

◆ ADC_CFGR2_TROVS

#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk

ADC oversampling discontinuous mode (triggered mode) for ADC group regular

Definition at line 1434 of file stm32g431xx.h.

◆ ADC_CFGR2_TROVS_Msk

#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos)

0x00000200

Definition at line 1433 of file stm32g431xx.h.

◆ ADC_CFGR2_TROVS_Pos

#define ADC_CFGR2_TROVS_Pos (9U)

Definition at line 1432 of file stm32g431xx.h.

◆ ADC_CFGR_ALIGN

#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk

ADC data alignement

Definition at line 1365 of file stm32g431xx.h.

◆ ADC_CFGR_ALIGN_Msk

#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos)

0x00008000

Definition at line 1364 of file stm32g431xx.h.

◆ ADC_CFGR_ALIGN_Pos

#define ADC_CFGR_ALIGN_Pos (15U)

Definition at line 1363 of file stm32g431xx.h.

◆ ADC_CFGR_AUTDLY

#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk

ADC low power auto wait

Definition at line 1362 of file stm32g431xx.h.

◆ ADC_CFGR_AUTDLY_Msk

#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos)

0x00004000

Definition at line 1361 of file stm32g431xx.h.

◆ ADC_CFGR_AUTDLY_Pos

#define ADC_CFGR_AUTDLY_Pos (14U)

Definition at line 1360 of file stm32g431xx.h.

◆ ADC_CFGR_AWD1CH

#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk

ADC analog watchdog 1 monitored channel selection

Definition at line 1398 of file stm32g431xx.h.

◆ ADC_CFGR_AWD1CH_0

#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos)

0x04000000

Definition at line 1399 of file stm32g431xx.h.

◆ ADC_CFGR_AWD1CH_1

#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos)

0x08000000

Definition at line 1400 of file stm32g431xx.h.

◆ ADC_CFGR_AWD1CH_2

#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos)

0x10000000

Definition at line 1401 of file stm32g431xx.h.

◆ ADC_CFGR_AWD1CH_3

#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos)

0x20000000

Definition at line 1402 of file stm32g431xx.h.

◆ ADC_CFGR_AWD1CH_4

#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos)

0x40000000

Definition at line 1403 of file stm32g431xx.h.

◆ ADC_CFGR_AWD1CH_Msk

#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos)

0x7C000000

Definition at line 1397 of file stm32g431xx.h.

◆ ADC_CFGR_AWD1CH_Pos

#define ADC_CFGR_AWD1CH_Pos (26U)

Definition at line 1396 of file stm32g431xx.h.

◆ ADC_CFGR_AWD1EN

#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk

ADC analog watchdog 1 enable on scope ADC group regular

Definition at line 1388 of file stm32g431xx.h.

◆ ADC_CFGR_AWD1EN_Msk

#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos)

0x00800000

Definition at line 1387 of file stm32g431xx.h.

◆ ADC_CFGR_AWD1EN_Pos

#define ADC_CFGR_AWD1EN_Pos (23U)

Definition at line 1386 of file stm32g431xx.h.

◆ ADC_CFGR_AWD1SGL

#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk

ADC analog watchdog 1 monitoring a single channel or all channels

Definition at line 1385 of file stm32g431xx.h.

◆ ADC_CFGR_AWD1SGL_Msk

#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos)

0x00400000

Definition at line 1384 of file stm32g431xx.h.

◆ ADC_CFGR_AWD1SGL_Pos

#define ADC_CFGR_AWD1SGL_Pos (22U)

Definition at line 1383 of file stm32g431xx.h.

◆ ADC_CFGR_CONT

#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk

ADC group regular continuous conversion mode

Definition at line 1359 of file stm32g431xx.h.

◆ ADC_CFGR_CONT_Msk

#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos)

0x00002000

Definition at line 1358 of file stm32g431xx.h.

◆ ADC_CFGR_CONT_Pos

#define ADC_CFGR_CONT_Pos (13U)

Definition at line 1357 of file stm32g431xx.h.

◆ ADC_CFGR_DISCEN

#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk

ADC group regular sequencer discontinuous mode

Definition at line 1368 of file stm32g431xx.h.

◆ ADC_CFGR_DISCEN_Msk

#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos)

0x00010000

Definition at line 1367 of file stm32g431xx.h.

◆ ADC_CFGR_DISCEN_Pos

#define ADC_CFGR_DISCEN_Pos (16U)

Definition at line 1366 of file stm32g431xx.h.

◆ ADC_CFGR_DISCNUM

#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk

ADC group regular sequencer discontinuous number of ranks

Definition at line 1372 of file stm32g431xx.h.

◆ ADC_CFGR_DISCNUM_0

#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos)

0x00020000

Definition at line 1373 of file stm32g431xx.h.

◆ ADC_CFGR_DISCNUM_1

#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos)

0x00040000

Definition at line 1374 of file stm32g431xx.h.

◆ ADC_CFGR_DISCNUM_2

#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos)

0x00080000

Definition at line 1375 of file stm32g431xx.h.

◆ ADC_CFGR_DISCNUM_Msk

#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos)

0x000E0000

Definition at line 1371 of file stm32g431xx.h.

◆ ADC_CFGR_DISCNUM_Pos

#define ADC_CFGR_DISCNUM_Pos (17U)

Definition at line 1370 of file stm32g431xx.h.

◆ ADC_CFGR_DMACFG

#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk

ADC DMA transfer configuration

Definition at line 1331 of file stm32g431xx.h.

◆ ADC_CFGR_DMACFG_Msk

#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos)

0x00000002

Definition at line 1330 of file stm32g431xx.h.

◆ ADC_CFGR_DMACFG_Pos

#define ADC_CFGR_DMACFG_Pos (1U)

Definition at line 1329 of file stm32g431xx.h.

◆ ADC_CFGR_DMAEN

#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk

ADC DMA transfer enable

Definition at line 1328 of file stm32g431xx.h.

◆ ADC_CFGR_DMAEN_Msk

#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos)

0x00000001

Definition at line 1327 of file stm32g431xx.h.

◆ ADC_CFGR_DMAEN_Pos

#define ADC_CFGR_DMAEN_Pos (0U)

Definition at line 1326 of file stm32g431xx.h.

◆ ADC_CFGR_EXTEN

#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk

ADC group regular external trigger polarity

Definition at line 1350 of file stm32g431xx.h.

◆ ADC_CFGR_EXTEN_0

#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos)

0x00000400

Definition at line 1351 of file stm32g431xx.h.

◆ ADC_CFGR_EXTEN_1

#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos)

0x00000800

Definition at line 1352 of file stm32g431xx.h.

◆ ADC_CFGR_EXTEN_Msk

#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos)

0x00000C00

Definition at line 1349 of file stm32g431xx.h.

◆ ADC_CFGR_EXTEN_Pos

#define ADC_CFGR_EXTEN_Pos (10U)

Definition at line 1348 of file stm32g431xx.h.

◆ ADC_CFGR_EXTSEL

#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk

ADC group regular external trigger source

Definition at line 1341 of file stm32g431xx.h.

◆ ADC_CFGR_EXTSEL_0

#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos)

0x00000020

Definition at line 1342 of file stm32g431xx.h.

◆ ADC_CFGR_EXTSEL_1

#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos)

0x00000040

Definition at line 1343 of file stm32g431xx.h.

◆ ADC_CFGR_EXTSEL_2

#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos)

0x00000080

Definition at line 1344 of file stm32g431xx.h.

◆ ADC_CFGR_EXTSEL_3

#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos)

0x00000100

Definition at line 1345 of file stm32g431xx.h.

◆ ADC_CFGR_EXTSEL_4

#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos)

0x00000200

Definition at line 1346 of file stm32g431xx.h.

◆ ADC_CFGR_EXTSEL_Msk

#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos)

0x000003E0

Definition at line 1340 of file stm32g431xx.h.

◆ ADC_CFGR_EXTSEL_Pos

#define ADC_CFGR_EXTSEL_Pos (5U)

Definition at line 1339 of file stm32g431xx.h.

◆ ADC_CFGR_JAUTO

#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk

ADC group injected automatic trigger mode

Definition at line 1394 of file stm32g431xx.h.

◆ ADC_CFGR_JAUTO_Msk

#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos)

0x02000000

Definition at line 1393 of file stm32g431xx.h.

◆ ADC_CFGR_JAUTO_Pos

#define ADC_CFGR_JAUTO_Pos (25U)

Definition at line 1392 of file stm32g431xx.h.

◆ ADC_CFGR_JAWD1EN

#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk

ADC analog watchdog 1 enable on scope ADC group injected

Definition at line 1391 of file stm32g431xx.h.

◆ ADC_CFGR_JAWD1EN_Msk

#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos)

0x01000000

Definition at line 1390 of file stm32g431xx.h.

◆ ADC_CFGR_JAWD1EN_Pos

#define ADC_CFGR_JAWD1EN_Pos (24U)

Definition at line 1389 of file stm32g431xx.h.

◆ ADC_CFGR_JDISCEN

#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk

ADC group injected sequencer discontinuous mode

Definition at line 1379 of file stm32g431xx.h.

◆ ADC_CFGR_JDISCEN_Msk

#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos)

0x00100000

Definition at line 1378 of file stm32g431xx.h.

◆ ADC_CFGR_JDISCEN_Pos

#define ADC_CFGR_JDISCEN_Pos (20U)

Definition at line 1377 of file stm32g431xx.h.

◆ ADC_CFGR_JQDIS

#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk

ADC group injected contexts queue disable

Definition at line 1407 of file stm32g431xx.h.

◆ ADC_CFGR_JQDIS_Msk

#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos)

0x80000000

Definition at line 1406 of file stm32g431xx.h.

◆ ADC_CFGR_JQDIS_Pos

#define ADC_CFGR_JQDIS_Pos (31U)

Definition at line 1405 of file stm32g431xx.h.

◆ ADC_CFGR_JQM

#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk

ADC group injected contexts queue mode

Definition at line 1382 of file stm32g431xx.h.

◆ ADC_CFGR_JQM_Msk

#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos)

0x00200000

Definition at line 1381 of file stm32g431xx.h.

◆ ADC_CFGR_JQM_Pos

#define ADC_CFGR_JQM_Pos (21U)

Definition at line 1380 of file stm32g431xx.h.

◆ ADC_CFGR_OVRMOD

#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk

ADC group regular overrun configuration

Definition at line 1356 of file stm32g431xx.h.

◆ ADC_CFGR_OVRMOD_Msk

#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos)

0x00001000

Definition at line 1355 of file stm32g431xx.h.

◆ ADC_CFGR_OVRMOD_Pos

#define ADC_CFGR_OVRMOD_Pos (12U)

Definition at line 1354 of file stm32g431xx.h.

◆ ADC_CFGR_RES

#define ADC_CFGR_RES ADC_CFGR_RES_Msk

ADC data resolution

Definition at line 1335 of file stm32g431xx.h.

◆ ADC_CFGR_RES_0

#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos)

0x00000008

Definition at line 1336 of file stm32g431xx.h.

◆ ADC_CFGR_RES_1

#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos)

0x00000010

Definition at line 1337 of file stm32g431xx.h.

◆ ADC_CFGR_RES_Msk

#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos)

0x00000018

Definition at line 1334 of file stm32g431xx.h.

◆ ADC_CFGR_RES_Pos

#define ADC_CFGR_RES_Pos (3U)

Definition at line 1333 of file stm32g431xx.h.

◆ ADC_CR_ADCAL

#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk

ADC calibration

Definition at line 1323 of file stm32g431xx.h.

◆ ADC_CR_ADCAL_Msk

#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos)

0x80000000

Definition at line 1322 of file stm32g431xx.h.

◆ ADC_CR_ADCAL_Pos

#define ADC_CR_ADCAL_Pos (31U)

Definition at line 1321 of file stm32g431xx.h.

◆ ADC_CR_ADCALDIF

#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk

ADC differential mode for calibration

Definition at line 1320 of file stm32g431xx.h.

◆ ADC_CR_ADCALDIF_Msk

#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos)

0x40000000

Definition at line 1319 of file stm32g431xx.h.

◆ ADC_CR_ADCALDIF_Pos

#define ADC_CR_ADCALDIF_Pos (30U)

Definition at line 1318 of file stm32g431xx.h.

◆ ADC_CR_ADDIS

#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk

ADC disable

Definition at line 1299 of file stm32g431xx.h.

◆ ADC_CR_ADDIS_Msk

#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos)

0x00000002

Definition at line 1298 of file stm32g431xx.h.

◆ ADC_CR_ADDIS_Pos

#define ADC_CR_ADDIS_Pos (1U)

Definition at line 1297 of file stm32g431xx.h.

◆ ADC_CR_ADEN

#define ADC_CR_ADEN ADC_CR_ADEN_Msk

ADC enable

Definition at line 1296 of file stm32g431xx.h.

◆ ADC_CR_ADEN_Msk

#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos)

0x00000001

Definition at line 1295 of file stm32g431xx.h.

◆ ADC_CR_ADEN_Pos

#define ADC_CR_ADEN_Pos (0U)

Definition at line 1294 of file stm32g431xx.h.

◆ ADC_CR_ADSTART

#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk

ADC group regular conversion start

Definition at line 1302 of file stm32g431xx.h.

◆ ADC_CR_ADSTART_Msk

#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos)

0x00000004

Definition at line 1301 of file stm32g431xx.h.

◆ ADC_CR_ADSTART_Pos

#define ADC_CR_ADSTART_Pos (2U)

Definition at line 1300 of file stm32g431xx.h.

◆ ADC_CR_ADSTP

#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk

ADC group regular conversion stop

Definition at line 1308 of file stm32g431xx.h.

◆ ADC_CR_ADSTP_Msk

#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos)

0x00000010

Definition at line 1307 of file stm32g431xx.h.

◆ ADC_CR_ADSTP_Pos

#define ADC_CR_ADSTP_Pos (4U)

Definition at line 1306 of file stm32g431xx.h.

◆ ADC_CR_ADVREGEN

#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk

ADC voltage regulator enable

Definition at line 1314 of file stm32g431xx.h.

◆ ADC_CR_ADVREGEN_Msk

#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos)

0x10000000

Definition at line 1313 of file stm32g431xx.h.

◆ ADC_CR_ADVREGEN_Pos

#define ADC_CR_ADVREGEN_Pos (28U)

Definition at line 1312 of file stm32g431xx.h.

◆ ADC_CR_DEEPPWD

#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk

ADC deep power down enable

Definition at line 1317 of file stm32g431xx.h.

◆ ADC_CR_DEEPPWD_Msk

#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos)

0x20000000

Definition at line 1316 of file stm32g431xx.h.

◆ ADC_CR_DEEPPWD_Pos

#define ADC_CR_DEEPPWD_Pos (29U)

Definition at line 1315 of file stm32g431xx.h.

◆ ADC_CR_JADSTART

#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk

ADC group injected conversion start

Definition at line 1305 of file stm32g431xx.h.

◆ ADC_CR_JADSTART_Msk

#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos)

0x00000008

Definition at line 1304 of file stm32g431xx.h.

◆ ADC_CR_JADSTART_Pos

#define ADC_CR_JADSTART_Pos (3U)

Definition at line 1303 of file stm32g431xx.h.

◆ ADC_CR_JADSTP

#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk

ADC group injected conversion stop

Definition at line 1311 of file stm32g431xx.h.

◆ ADC_CR_JADSTP_Msk

#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos)

0x00000020

Definition at line 1310 of file stm32g431xx.h.

◆ ADC_CR_JADSTP_Pos

#define ADC_CR_JADSTP_Pos (5U)

Definition at line 1309 of file stm32g431xx.h.

◆ ADC_CSR_ADRDY_MST

#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk

ADC multimode master ready flag

Definition at line 2069 of file stm32g431xx.h.

◆ ADC_CSR_ADRDY_MST_Msk

#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos)

0x00000001

Definition at line 2068 of file stm32g431xx.h.

◆ ADC_CSR_ADRDY_MST_Pos

#define ADC_CSR_ADRDY_MST_Pos (0U)

Definition at line 2067 of file stm32g431xx.h.

◆ ADC_CSR_ADRDY_SLV

#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk

ADC multimode slave ready flag

Definition at line 2103 of file stm32g431xx.h.

◆ ADC_CSR_ADRDY_SLV_Msk

#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos)

0x00010000

Definition at line 2102 of file stm32g431xx.h.

◆ ADC_CSR_ADRDY_SLV_Pos

#define ADC_CSR_ADRDY_SLV_Pos (16U)

Definition at line 2101 of file stm32g431xx.h.

◆ ADC_CSR_AWD1_MST

#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk

ADC multimode master analog watchdog 1 flag

Definition at line 2090 of file stm32g431xx.h.

◆ ADC_CSR_AWD1_MST_Msk

#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos)

0x00000080

Definition at line 2089 of file stm32g431xx.h.

◆ ADC_CSR_AWD1_MST_Pos

#define ADC_CSR_AWD1_MST_Pos (7U)

Definition at line 2088 of file stm32g431xx.h.

◆ ADC_CSR_AWD1_SLV

#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk

ADC multimode slave analog watchdog 1 flag

Definition at line 2124 of file stm32g431xx.h.

◆ ADC_CSR_AWD1_SLV_Msk

#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos)

0x00800000

Definition at line 2123 of file stm32g431xx.h.

◆ ADC_CSR_AWD1_SLV_Pos

#define ADC_CSR_AWD1_SLV_Pos (23U)

Definition at line 2122 of file stm32g431xx.h.

◆ ADC_CSR_AWD2_MST

#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk

ADC multimode master analog watchdog 2 flag

Definition at line 2093 of file stm32g431xx.h.

◆ ADC_CSR_AWD2_MST_Msk

#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos)

0x00000100

Definition at line 2092 of file stm32g431xx.h.

◆ ADC_CSR_AWD2_MST_Pos

#define ADC_CSR_AWD2_MST_Pos (8U)

Definition at line 2091 of file stm32g431xx.h.

◆ ADC_CSR_AWD2_SLV

#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk

ADC multimode slave analog watchdog 2 flag

Definition at line 2127 of file stm32g431xx.h.

◆ ADC_CSR_AWD2_SLV_Msk

#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos)

0x01000000

Definition at line 2126 of file stm32g431xx.h.

◆ ADC_CSR_AWD2_SLV_Pos

#define ADC_CSR_AWD2_SLV_Pos (24U)

Definition at line 2125 of file stm32g431xx.h.

◆ ADC_CSR_AWD3_MST

#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk

ADC multimode master analog watchdog 3 flag

Definition at line 2096 of file stm32g431xx.h.

◆ ADC_CSR_AWD3_MST_Msk

#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos)

0x00000200

Definition at line 2095 of file stm32g431xx.h.

◆ ADC_CSR_AWD3_MST_Pos

#define ADC_CSR_AWD3_MST_Pos (9U)

Definition at line 2094 of file stm32g431xx.h.

◆ ADC_CSR_AWD3_SLV

#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk

ADC multimode slave analog watchdog 3 flag

Definition at line 2130 of file stm32g431xx.h.

◆ ADC_CSR_AWD3_SLV_Msk

#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos)

0x02000000

Definition at line 2129 of file stm32g431xx.h.

◆ ADC_CSR_AWD3_SLV_Pos

#define ADC_CSR_AWD3_SLV_Pos (25U)

Definition at line 2128 of file stm32g431xx.h.

◆ ADC_CSR_EOC_MST

#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk

ADC multimode master group regular end of unitary conversion flag

Definition at line 2075 of file stm32g431xx.h.

◆ ADC_CSR_EOC_MST_Msk

#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos)

0x00000004

Definition at line 2074 of file stm32g431xx.h.

◆ ADC_CSR_EOC_MST_Pos

#define ADC_CSR_EOC_MST_Pos (2U)

Definition at line 2073 of file stm32g431xx.h.

◆ ADC_CSR_EOC_SLV

#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk

ADC multimode slave group regular end of unitary conversion flag

Definition at line 2109 of file stm32g431xx.h.

◆ ADC_CSR_EOC_SLV_Msk

#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos)

0x00040000

Definition at line 2108 of file stm32g431xx.h.

◆ ADC_CSR_EOC_SLV_Pos

#define ADC_CSR_EOC_SLV_Pos (18U)

Definition at line 2107 of file stm32g431xx.h.

◆ ADC_CSR_EOS_MST

#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk

ADC multimode master group regular end of sequence conversions flag

Definition at line 2078 of file stm32g431xx.h.

◆ ADC_CSR_EOS_MST_Msk

#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos)

0x00000008

Definition at line 2077 of file stm32g431xx.h.

◆ ADC_CSR_EOS_MST_Pos

#define ADC_CSR_EOS_MST_Pos (3U)

Definition at line 2076 of file stm32g431xx.h.

◆ ADC_CSR_EOS_SLV

#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk

ADC multimode slave group regular end of sequence conversions flag

Definition at line 2112 of file stm32g431xx.h.

◆ ADC_CSR_EOS_SLV_Msk

#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos)

0x00080000

Definition at line 2111 of file stm32g431xx.h.

◆ ADC_CSR_EOS_SLV_Pos

#define ADC_CSR_EOS_SLV_Pos (19U)

Definition at line 2110 of file stm32g431xx.h.

◆ ADC_CSR_EOSMP_MST

#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk

ADC multimode master group regular end of sampling flag

Definition at line 2072 of file stm32g431xx.h.

◆ ADC_CSR_EOSMP_MST_Msk

#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos)

0x00000002

Definition at line 2071 of file stm32g431xx.h.

◆ ADC_CSR_EOSMP_MST_Pos

#define ADC_CSR_EOSMP_MST_Pos (1U)

Definition at line 2070 of file stm32g431xx.h.

◆ ADC_CSR_EOSMP_SLV

#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk

ADC multimode slave group regular end of sampling flag

Definition at line 2106 of file stm32g431xx.h.

◆ ADC_CSR_EOSMP_SLV_Msk

#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos)

0x00020000

Definition at line 2105 of file stm32g431xx.h.

◆ ADC_CSR_EOSMP_SLV_Pos

#define ADC_CSR_EOSMP_SLV_Pos (17U)

Definition at line 2104 of file stm32g431xx.h.

◆ ADC_CSR_JEOC_MST

#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk

ADC multimode master group injected end of unitary conversion flag

Definition at line 2084 of file stm32g431xx.h.

◆ ADC_CSR_JEOC_MST_Msk

#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos)

0x00000020

Definition at line 2083 of file stm32g431xx.h.

◆ ADC_CSR_JEOC_MST_Pos

#define ADC_CSR_JEOC_MST_Pos (5U)

Definition at line 2082 of file stm32g431xx.h.

◆ ADC_CSR_JEOC_SLV

#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk

ADC multimode slave group injected end of unitary conversion flag

Definition at line 2118 of file stm32g431xx.h.

◆ ADC_CSR_JEOC_SLV_Msk

#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos)

0x00200000

Definition at line 2117 of file stm32g431xx.h.

◆ ADC_CSR_JEOC_SLV_Pos

#define ADC_CSR_JEOC_SLV_Pos (21U)

Definition at line 2116 of file stm32g431xx.h.

◆ ADC_CSR_JEOS_MST

#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk

ADC multimode master group injected end of sequence conversions flag

Definition at line 2087 of file stm32g431xx.h.

◆ ADC_CSR_JEOS_MST_Msk

#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos)

0x00000040

Definition at line 2086 of file stm32g431xx.h.

◆ ADC_CSR_JEOS_MST_Pos

#define ADC_CSR_JEOS_MST_Pos (6U)

Definition at line 2085 of file stm32g431xx.h.

◆ ADC_CSR_JEOS_SLV

#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk

ADC multimode slave group injected end of sequence conversions flag

Definition at line 2121 of file stm32g431xx.h.

◆ ADC_CSR_JEOS_SLV_Msk

#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos)

0x00400000

Definition at line 2120 of file stm32g431xx.h.

◆ ADC_CSR_JEOS_SLV_Pos

#define ADC_CSR_JEOS_SLV_Pos (22U)

Definition at line 2119 of file stm32g431xx.h.

◆ ADC_CSR_JQOVF_MST

#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk

ADC multimode master group injected contexts queue overflow flag

Definition at line 2099 of file stm32g431xx.h.

◆ ADC_CSR_JQOVF_MST_Msk

#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos)

0x00000400

Definition at line 2098 of file stm32g431xx.h.

◆ ADC_CSR_JQOVF_MST_Pos

#define ADC_CSR_JQOVF_MST_Pos (10U)

Definition at line 2097 of file stm32g431xx.h.

◆ ADC_CSR_JQOVF_SLV

#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk

ADC multimode slave group injected contexts queue overflow flag

Definition at line 2133 of file stm32g431xx.h.

◆ ADC_CSR_JQOVF_SLV_Msk

#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos)

0x04000000

Definition at line 2132 of file stm32g431xx.h.

◆ ADC_CSR_JQOVF_SLV_Pos

#define ADC_CSR_JQOVF_SLV_Pos (26U)

Definition at line 2131 of file stm32g431xx.h.

◆ ADC_CSR_OVR_MST

#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk

ADC multimode master group regular overrun flag

Definition at line 2081 of file stm32g431xx.h.

◆ ADC_CSR_OVR_MST_Msk

#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos)

0x00000010

Definition at line 2080 of file stm32g431xx.h.

◆ ADC_CSR_OVR_MST_Pos

#define ADC_CSR_OVR_MST_Pos (4U)

Definition at line 2079 of file stm32g431xx.h.

◆ ADC_CSR_OVR_SLV

#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk

ADC multimode slave group regular overrun flag

Definition at line 2115 of file stm32g431xx.h.

◆ ADC_CSR_OVR_SLV_Msk

#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos)

0x00100000

Definition at line 2114 of file stm32g431xx.h.

◆ ADC_CSR_OVR_SLV_Pos

#define ADC_CSR_OVR_SLV_Pos (20U)

Definition at line 2113 of file stm32g431xx.h.

◆ ADC_DIFSEL_DIFSEL

#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk

ADC channel differential or single-ended mode

Definition at line 2016 of file stm32g431xx.h.

◆ ADC_DIFSEL_DIFSEL_0

#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)

0x00000001

Definition at line 2017 of file stm32g431xx.h.

◆ ADC_DIFSEL_DIFSEL_1

#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)

0x00000002

Definition at line 2018 of file stm32g431xx.h.

◆ ADC_DIFSEL_DIFSEL_10

#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)

0x00000400

Definition at line 2027 of file stm32g431xx.h.

◆ ADC_DIFSEL_DIFSEL_11

#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)

0x00000800

Definition at line 2028 of file stm32g431xx.h.

◆ ADC_DIFSEL_DIFSEL_12

#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)

0x00001000

Definition at line 2029 of file stm32g431xx.h.

◆ ADC_DIFSEL_DIFSEL_13

#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)

0x00002000

Definition at line 2030 of file stm32g431xx.h.

◆ ADC_DIFSEL_DIFSEL_14

#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)

0x00004000

Definition at line 2031 of file stm32g431xx.h.

◆ ADC_DIFSEL_DIFSEL_15

#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)

0x00008000

Definition at line 2032 of file stm32g431xx.h.

◆ ADC_DIFSEL_DIFSEL_16

#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)

0x00010000

Definition at line 2033 of file stm32g431xx.h.

◆ ADC_DIFSEL_DIFSEL_17

#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)

0x00020000

Definition at line 2034 of file stm32g431xx.h.

◆ ADC_DIFSEL_DIFSEL_18

#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)

0x00040000

Definition at line 2035 of file stm32g431xx.h.

◆ ADC_DIFSEL_DIFSEL_2

#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)

0x00000004

Definition at line 2019 of file stm32g431xx.h.

◆ ADC_DIFSEL_DIFSEL_3

#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)

0x00000008

Definition at line 2020 of file stm32g431xx.h.

◆ ADC_DIFSEL_DIFSEL_4

#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)

0x00000010

Definition at line 2021 of file stm32g431xx.h.

◆ ADC_DIFSEL_DIFSEL_5

#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)

0x00000020

Definition at line 2022 of file stm32g431xx.h.

◆ ADC_DIFSEL_DIFSEL_6

#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)

0x00000040

Definition at line 2023 of file stm32g431xx.h.

◆ ADC_DIFSEL_DIFSEL_7

#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)

0x00000080

Definition at line 2024 of file stm32g431xx.h.

◆ ADC_DIFSEL_DIFSEL_8

#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)

0x00000100

Definition at line 2025 of file stm32g431xx.h.

◆ ADC_DIFSEL_DIFSEL_9

#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)

0x00000200

Definition at line 2026 of file stm32g431xx.h.

◆ ADC_DIFSEL_DIFSEL_Msk

#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos)

0x0007FFFF

Definition at line 2015 of file stm32g431xx.h.

◆ ADC_DIFSEL_DIFSEL_Pos

#define ADC_DIFSEL_DIFSEL_Pos (0U)

Definition at line 2014 of file stm32g431xx.h.

◆ ADC_DR_RDATA

#define ADC_DR_RDATA ADC_DR_RDATA_Msk

ADC group regular conversion data

Definition at line 1785 of file stm32g431xx.h.

◆ ADC_DR_RDATA_Msk

#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos)

0x0000FFFF

Definition at line 1784 of file stm32g431xx.h.

◆ ADC_DR_RDATA_Pos

#define ADC_DR_RDATA_Pos (0U)

Definition at line 1783 of file stm32g431xx.h.

◆ ADC_GCOMP_GCOMPCOEFF

#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk

ADC Gain Compensation Coefficient

Definition at line 2063 of file stm32g431xx.h.

◆ ADC_GCOMP_GCOMPCOEFF_Msk

#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos)

0x00003FFF

Definition at line 2062 of file stm32g431xx.h.

◆ ADC_GCOMP_GCOMPCOEFF_Pos

#define ADC_GCOMP_GCOMPCOEFF_Pos (0U)

Definition at line 2061 of file stm32g431xx.h.

◆ ADC_IER_ADRDYIE

#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk

ADC ready interrupt

Definition at line 1261 of file stm32g431xx.h.

◆ ADC_IER_ADRDYIE_Msk

#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos)

0x00000001

Definition at line 1260 of file stm32g431xx.h.

◆ ADC_IER_ADRDYIE_Pos

#define ADC_IER_ADRDYIE_Pos (0U)

Definition at line 1259 of file stm32g431xx.h.

◆ ADC_IER_AWD1IE

#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk

ADC analog watchdog 1 interrupt

Definition at line 1282 of file stm32g431xx.h.

◆ ADC_IER_AWD1IE_Msk

#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos)

0x00000080

Definition at line 1281 of file stm32g431xx.h.

◆ ADC_IER_AWD1IE_Pos

#define ADC_IER_AWD1IE_Pos (7U)

Definition at line 1280 of file stm32g431xx.h.

◆ ADC_IER_AWD2IE

#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk

ADC analog watchdog 2 interrupt

Definition at line 1285 of file stm32g431xx.h.

◆ ADC_IER_AWD2IE_Msk

#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos)

0x00000100

Definition at line 1284 of file stm32g431xx.h.

◆ ADC_IER_AWD2IE_Pos

#define ADC_IER_AWD2IE_Pos (8U)

Definition at line 1283 of file stm32g431xx.h.

◆ ADC_IER_AWD3IE

#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk

ADC analog watchdog 3 interrupt

Definition at line 1288 of file stm32g431xx.h.

◆ ADC_IER_AWD3IE_Msk

#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos)

0x00000200

Definition at line 1287 of file stm32g431xx.h.

◆ ADC_IER_AWD3IE_Pos

#define ADC_IER_AWD3IE_Pos (9U)

Definition at line 1286 of file stm32g431xx.h.

◆ ADC_IER_EOCIE

#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk

ADC group regular end of unitary conversion interrupt

Definition at line 1267 of file stm32g431xx.h.

◆ ADC_IER_EOCIE_Msk

#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos)

0x00000004

Definition at line 1266 of file stm32g431xx.h.

◆ ADC_IER_EOCIE_Pos

#define ADC_IER_EOCIE_Pos (2U)

Definition at line 1265 of file stm32g431xx.h.

◆ ADC_IER_EOSIE

#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk

ADC group regular end of sequence conversions interrupt

Definition at line 1270 of file stm32g431xx.h.

◆ ADC_IER_EOSIE_Msk

#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos)

0x00000008

Definition at line 1269 of file stm32g431xx.h.

◆ ADC_IER_EOSIE_Pos

#define ADC_IER_EOSIE_Pos (3U)

Definition at line 1268 of file stm32g431xx.h.

◆ ADC_IER_EOSMPIE

#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk

ADC group regular end of sampling interrupt

Definition at line 1264 of file stm32g431xx.h.

◆ ADC_IER_EOSMPIE_Msk

#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos)

0x00000002

Definition at line 1263 of file stm32g431xx.h.

◆ ADC_IER_EOSMPIE_Pos

#define ADC_IER_EOSMPIE_Pos (1U)

Definition at line 1262 of file stm32g431xx.h.

◆ ADC_IER_JEOCIE

#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk

ADC group injected end of unitary conversion interrupt

Definition at line 1276 of file stm32g431xx.h.

◆ ADC_IER_JEOCIE_Msk

#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos)

0x00000020

Definition at line 1275 of file stm32g431xx.h.

◆ ADC_IER_JEOCIE_Pos

#define ADC_IER_JEOCIE_Pos (5U)

Definition at line 1274 of file stm32g431xx.h.

◆ ADC_IER_JEOSIE

#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk

ADC group injected end of sequence conversions interrupt

Definition at line 1279 of file stm32g431xx.h.

◆ ADC_IER_JEOSIE_Msk

#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos)

0x00000040

Definition at line 1278 of file stm32g431xx.h.

◆ ADC_IER_JEOSIE_Pos

#define ADC_IER_JEOSIE_Pos (6U)

Definition at line 1277 of file stm32g431xx.h.

◆ ADC_IER_JQOVFIE

#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk

ADC group injected contexts queue overflow interrupt

Definition at line 1291 of file stm32g431xx.h.

◆ ADC_IER_JQOVFIE_Msk

#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos)

0x00000400

Definition at line 1290 of file stm32g431xx.h.

◆ ADC_IER_JQOVFIE_Pos

#define ADC_IER_JQOVFIE_Pos (10U)

Definition at line 1289 of file stm32g431xx.h.

◆ ADC_IER_OVRIE

#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk

ADC group regular overrun interrupt

Definition at line 1273 of file stm32g431xx.h.

◆ ADC_IER_OVRIE_Msk

#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos)

0x00000010

Definition at line 1272 of file stm32g431xx.h.

◆ ADC_IER_OVRIE_Pos

#define ADC_IER_OVRIE_Pos (4U)

Definition at line 1271 of file stm32g431xx.h.

◆ ADC_ISR_ADRDY

#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk

ADC ready flag

Definition at line 1226 of file stm32g431xx.h.

◆ ADC_ISR_ADRDY_Msk

#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos)

0x00000001

Definition at line 1225 of file stm32g431xx.h.

◆ ADC_ISR_ADRDY_Pos

#define ADC_ISR_ADRDY_Pos (0U)

Definition at line 1224 of file stm32g431xx.h.

◆ ADC_ISR_AWD1

#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk

ADC analog watchdog 1 flag

Definition at line 1247 of file stm32g431xx.h.

◆ ADC_ISR_AWD1_Msk

#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos)

0x00000080

Definition at line 1246 of file stm32g431xx.h.

◆ ADC_ISR_AWD1_Pos

#define ADC_ISR_AWD1_Pos (7U)

Definition at line 1245 of file stm32g431xx.h.

◆ ADC_ISR_AWD2

#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk

ADC analog watchdog 2 flag

Definition at line 1250 of file stm32g431xx.h.

◆ ADC_ISR_AWD2_Msk

#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos)

0x00000100

Definition at line 1249 of file stm32g431xx.h.

◆ ADC_ISR_AWD2_Pos

#define ADC_ISR_AWD2_Pos (8U)

Definition at line 1248 of file stm32g431xx.h.

◆ ADC_ISR_AWD3

#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk

ADC analog watchdog 3 flag

Definition at line 1253 of file stm32g431xx.h.

◆ ADC_ISR_AWD3_Msk

#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos)

0x00000200

Definition at line 1252 of file stm32g431xx.h.

◆ ADC_ISR_AWD3_Pos

#define ADC_ISR_AWD3_Pos (9U)

Definition at line 1251 of file stm32g431xx.h.

◆ ADC_ISR_EOC

#define ADC_ISR_EOC ADC_ISR_EOC_Msk

ADC group regular end of unitary conversion flag

Definition at line 1232 of file stm32g431xx.h.

◆ ADC_ISR_EOC_Msk

#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos)

0x00000004

Definition at line 1231 of file stm32g431xx.h.

◆ ADC_ISR_EOC_Pos

#define ADC_ISR_EOC_Pos (2U)

Definition at line 1230 of file stm32g431xx.h.

◆ ADC_ISR_EOS

#define ADC_ISR_EOS ADC_ISR_EOS_Msk

ADC group regular end of sequence conversions flag

Definition at line 1235 of file stm32g431xx.h.

◆ ADC_ISR_EOS_Msk

#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos)

0x00000008

Definition at line 1234 of file stm32g431xx.h.

◆ ADC_ISR_EOS_Pos

#define ADC_ISR_EOS_Pos (3U)

Definition at line 1233 of file stm32g431xx.h.

◆ ADC_ISR_EOSMP

#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk

ADC group regular end of sampling flag

Definition at line 1229 of file stm32g431xx.h.

◆ ADC_ISR_EOSMP_Msk

#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos)

0x00000002

Definition at line 1228 of file stm32g431xx.h.

◆ ADC_ISR_EOSMP_Pos

#define ADC_ISR_EOSMP_Pos (1U)

Definition at line 1227 of file stm32g431xx.h.

◆ ADC_ISR_JEOC

#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk

ADC group injected end of unitary conversion flag

Definition at line 1241 of file stm32g431xx.h.

◆ ADC_ISR_JEOC_Msk

#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos)

0x00000020

Definition at line 1240 of file stm32g431xx.h.

◆ ADC_ISR_JEOC_Pos

#define ADC_ISR_JEOC_Pos (5U)

Definition at line 1239 of file stm32g431xx.h.

◆ ADC_ISR_JEOS

#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk

ADC group injected end of sequence conversions flag

Definition at line 1244 of file stm32g431xx.h.

◆ ADC_ISR_JEOS_Msk

#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos)

0x00000040

Definition at line 1243 of file stm32g431xx.h.

◆ ADC_ISR_JEOS_Pos

#define ADC_ISR_JEOS_Pos (6U)

Definition at line 1242 of file stm32g431xx.h.

◆ ADC_ISR_JQOVF

#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk

ADC group injected contexts queue overflow flag

Definition at line 1256 of file stm32g431xx.h.

◆ ADC_ISR_JQOVF_Msk

#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos)

0x00000400

Definition at line 1255 of file stm32g431xx.h.

◆ ADC_ISR_JQOVF_Pos

#define ADC_ISR_JQOVF_Pos (10U)

Definition at line 1254 of file stm32g431xx.h.

◆ ADC_ISR_OVR

#define ADC_ISR_OVR ADC_ISR_OVR_Msk

ADC group regular overrun flag

Definition at line 1238 of file stm32g431xx.h.

◆ ADC_ISR_OVR_Msk

#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos)

0x00000010

Definition at line 1237 of file stm32g431xx.h.

◆ ADC_ISR_OVR_Pos

#define ADC_ISR_OVR_Pos (4U)

Definition at line 1236 of file stm32g431xx.h.

◆ ADC_JDR1_JDATA

#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk

ADC group injected sequencer rank 1 conversion data

Definition at line 1948 of file stm32g431xx.h.

◆ ADC_JDR1_JDATA_Msk

#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos)

0x0000FFFF

Definition at line 1947 of file stm32g431xx.h.

◆ ADC_JDR1_JDATA_Pos

#define ADC_JDR1_JDATA_Pos (0U)

Definition at line 1946 of file stm32g431xx.h.

◆ ADC_JDR2_JDATA

#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk

ADC group injected sequencer rank 2 conversion data

Definition at line 1953 of file stm32g431xx.h.

◆ ADC_JDR2_JDATA_Msk

#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos)

0x0000FFFF

Definition at line 1952 of file stm32g431xx.h.

◆ ADC_JDR2_JDATA_Pos

#define ADC_JDR2_JDATA_Pos (0U)

Definition at line 1951 of file stm32g431xx.h.

◆ ADC_JDR3_JDATA

#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk

ADC group injected sequencer rank 3 conversion data

Definition at line 1958 of file stm32g431xx.h.

◆ ADC_JDR3_JDATA_Msk

#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos)

0x0000FFFF

Definition at line 1957 of file stm32g431xx.h.

◆ ADC_JDR3_JDATA_Pos

#define ADC_JDR3_JDATA_Pos (0U)

Definition at line 1956 of file stm32g431xx.h.

◆ ADC_JDR4_JDATA

#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk

ADC group injected sequencer rank 4 conversion data

Definition at line 1963 of file stm32g431xx.h.

◆ ADC_JDR4_JDATA_Msk

#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos)

0x0000FFFF

Definition at line 1962 of file stm32g431xx.h.

◆ ADC_JDR4_JDATA_Pos

#define ADC_JDR4_JDATA_Pos (0U)

Definition at line 1961 of file stm32g431xx.h.

◆ ADC_JSQR_JEXTEN

#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk

ADC group injected external trigger polarity

Definition at line 1805 of file stm32g431xx.h.

◆ ADC_JSQR_JEXTEN_0

#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos)

0x00000080

Definition at line 1806 of file stm32g431xx.h.

◆ ADC_JSQR_JEXTEN_1

#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos)

0x00000100

Definition at line 1807 of file stm32g431xx.h.

◆ ADC_JSQR_JEXTEN_Msk

#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos)

0x00000180

Definition at line 1804 of file stm32g431xx.h.

◆ ADC_JSQR_JEXTEN_Pos

#define ADC_JSQR_JEXTEN_Pos (7U)

Definition at line 1803 of file stm32g431xx.h.

◆ ADC_JSQR_JEXTSEL

#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk

ADC group injected external trigger source

Definition at line 1796 of file stm32g431xx.h.

◆ ADC_JSQR_JEXTSEL_0

#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos)

0x00000004

Definition at line 1797 of file stm32g431xx.h.

◆ ADC_JSQR_JEXTSEL_1

#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos)

0x00000008

Definition at line 1798 of file stm32g431xx.h.

◆ ADC_JSQR_JEXTSEL_2

#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos)

0x00000010

Definition at line 1799 of file stm32g431xx.h.

◆ ADC_JSQR_JEXTSEL_3

#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos)

0x00000020

Definition at line 1800 of file stm32g431xx.h.

◆ ADC_JSQR_JEXTSEL_4

#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos)

0x00000040

Definition at line 1801 of file stm32g431xx.h.

◆ ADC_JSQR_JEXTSEL_Msk

#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos)

0x0000007C

Definition at line 1795 of file stm32g431xx.h.

◆ ADC_JSQR_JEXTSEL_Pos

#define ADC_JSQR_JEXTSEL_Pos (2U)

Definition at line 1794 of file stm32g431xx.h.

◆ ADC_JSQR_JL

#define ADC_JSQR_JL ADC_JSQR_JL_Msk

ADC group injected sequencer scan length

Definition at line 1790 of file stm32g431xx.h.

◆ ADC_JSQR_JL_0

#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos)

0x00000001

Definition at line 1791 of file stm32g431xx.h.

◆ ADC_JSQR_JL_1

#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos)

0x00000002

Definition at line 1792 of file stm32g431xx.h.

◆ ADC_JSQR_JL_Msk

#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos)

0x00000003

Definition at line 1789 of file stm32g431xx.h.

◆ ADC_JSQR_JL_Pos

#define ADC_JSQR_JL_Pos (0U)

Definition at line 1788 of file stm32g431xx.h.

◆ ADC_JSQR_JSQ1

#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk

ADC group injected sequencer rank 1

Definition at line 1811 of file stm32g431xx.h.

◆ ADC_JSQR_JSQ1_0

#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos)

0x00000200

Definition at line 1812 of file stm32g431xx.h.

◆ ADC_JSQR_JSQ1_1

#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos)

0x00000400

Definition at line 1813 of file stm32g431xx.h.

◆ ADC_JSQR_JSQ1_2

#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos)

0x00000800

Definition at line 1814 of file stm32g431xx.h.

◆ ADC_JSQR_JSQ1_3

#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos)

0x00001000

Definition at line 1815 of file stm32g431xx.h.

◆ ADC_JSQR_JSQ1_4

#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos)

0x00002000

Definition at line 1816 of file stm32g431xx.h.

◆ ADC_JSQR_JSQ1_Msk

#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos)

0x00003E00

Definition at line 1810 of file stm32g431xx.h.

◆ ADC_JSQR_JSQ1_Pos

#define ADC_JSQR_JSQ1_Pos (9U)

Definition at line 1809 of file stm32g431xx.h.

◆ ADC_JSQR_JSQ2

#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk

ADC group injected sequencer rank 2

Definition at line 1820 of file stm32g431xx.h.

◆ ADC_JSQR_JSQ2_0

#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos)

0x00004000

Definition at line 1821 of file stm32g431xx.h.

◆ ADC_JSQR_JSQ2_1

#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos)

0x00008000

Definition at line 1822 of file stm32g431xx.h.

◆ ADC_JSQR_JSQ2_2

#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos)

0x00010000

Definition at line 1823 of file stm32g431xx.h.

◆ ADC_JSQR_JSQ2_3

#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos)

0x00020000

Definition at line 1824 of file stm32g431xx.h.

◆ ADC_JSQR_JSQ2_4

#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos)

0x00040000

Definition at line 1825 of file stm32g431xx.h.

◆ ADC_JSQR_JSQ2_Msk

#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos)

0x0007C000

Definition at line 1819 of file stm32g431xx.h.

◆ ADC_JSQR_JSQ2_Pos

#define ADC_JSQR_JSQ2_Pos (15U)

Definition at line 1818 of file stm32g431xx.h.

◆ ADC_JSQR_JSQ3

#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk

ADC group injected sequencer rank 3

Definition at line 1829 of file stm32g431xx.h.

◆ ADC_JSQR_JSQ3_0

#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos)

0x00200000

Definition at line 1830 of file stm32g431xx.h.

◆ ADC_JSQR_JSQ3_1

#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos)

0x00400000

Definition at line 1831 of file stm32g431xx.h.

◆ ADC_JSQR_JSQ3_2

#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos)

0x00800000

Definition at line 1832 of file stm32g431xx.h.

◆ ADC_JSQR_JSQ3_3

#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos)

0x01000000

Definition at line 1833 of file stm32g431xx.h.

◆ ADC_JSQR_JSQ3_4

#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos)

0x02000000

Definition at line 1834 of file stm32g431xx.h.

◆ ADC_JSQR_JSQ3_Msk

#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos)

0x03E00000

Definition at line 1828 of file stm32g431xx.h.

◆ ADC_JSQR_JSQ3_Pos

#define ADC_JSQR_JSQ3_Pos (21U)

Definition at line 1827 of file stm32g431xx.h.

◆ ADC_JSQR_JSQ4

#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk

ADC group injected sequencer rank 4

Definition at line 1838 of file stm32g431xx.h.

◆ ADC_JSQR_JSQ4_0

#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos)

0x08000000

Definition at line 1839 of file stm32g431xx.h.

◆ ADC_JSQR_JSQ4_1

#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos)

0x10000000

Definition at line 1840 of file stm32g431xx.h.

◆ ADC_JSQR_JSQ4_2

#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos)

0x20000000

Definition at line 1841 of file stm32g431xx.h.

◆ ADC_JSQR_JSQ4_3

#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos)

0x40000000

Definition at line 1842 of file stm32g431xx.h.

◆ ADC_JSQR_JSQ4_4

#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos)

0x80000000

Definition at line 1843 of file stm32g431xx.h.

◆ ADC_JSQR_JSQ4_Msk

#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos)

0xF8000000

Definition at line 1837 of file stm32g431xx.h.

◆ ADC_JSQR_JSQ4_Pos

#define ADC_JSQR_JSQ4_Pos (27U)

Definition at line 1836 of file stm32g431xx.h.

◆ ADC_MULTIMODE_SUPPORT

#define ADC_MULTIMODE_SUPPORT

ADC feature available only on specific devices: multimode available on devices with several ADC instances

Definition at line 1221 of file stm32g431xx.h.

◆ ADC_OFR1_OFFSET1

#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk

ADC offset number 1 offset level

Definition at line 1848 of file stm32g431xx.h.

◆ ADC_OFR1_OFFSET1_CH

#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk

ADC offset number 1 channel selection

Definition at line 1859 of file stm32g431xx.h.

◆ ADC_OFR1_OFFSET1_CH_0

#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)

0x04000000

Definition at line 1860 of file stm32g431xx.h.

◆ ADC_OFR1_OFFSET1_CH_1

#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)

0x08000000

Definition at line 1861 of file stm32g431xx.h.

◆ ADC_OFR1_OFFSET1_CH_2

#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)

0x10000000

Definition at line 1862 of file stm32g431xx.h.

◆ ADC_OFR1_OFFSET1_CH_3

#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)

0x20000000

Definition at line 1863 of file stm32g431xx.h.

◆ ADC_OFR1_OFFSET1_CH_4

#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)

0x40000000

Definition at line 1864 of file stm32g431xx.h.

◆ ADC_OFR1_OFFSET1_CH_Msk

#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)

0x7C000000

Definition at line 1858 of file stm32g431xx.h.

◆ ADC_OFR1_OFFSET1_CH_Pos

#define ADC_OFR1_OFFSET1_CH_Pos (26U)

Definition at line 1857 of file stm32g431xx.h.

◆ ADC_OFR1_OFFSET1_EN

#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk

ADC offset number 1 enable

Definition at line 1868 of file stm32g431xx.h.

◆ ADC_OFR1_OFFSET1_EN_Msk

#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos)

0x80000000

Definition at line 1867 of file stm32g431xx.h.

◆ ADC_OFR1_OFFSET1_EN_Pos

#define ADC_OFR1_OFFSET1_EN_Pos (31U)

Definition at line 1866 of file stm32g431xx.h.

◆ ADC_OFR1_OFFSET1_Msk

#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos)

0x00000FFF

Definition at line 1847 of file stm32g431xx.h.

◆ ADC_OFR1_OFFSET1_Pos

#define ADC_OFR1_OFFSET1_Pos (0U)

Definition at line 1846 of file stm32g431xx.h.

◆ ADC_OFR1_OFFSETPOS

#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk

ADC offset number 1 positive

Definition at line 1852 of file stm32g431xx.h.

◆ ADC_OFR1_OFFSETPOS_Msk

#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos)

0x01000000

Definition at line 1851 of file stm32g431xx.h.

◆ ADC_OFR1_OFFSETPOS_Pos

#define ADC_OFR1_OFFSETPOS_Pos (24U)

Definition at line 1850 of file stm32g431xx.h.

◆ ADC_OFR1_SATEN

#define ADC_OFR1_SATEN ADC_OFR1_SATEN_Msk

ADC offset number 1 saturation enable

Definition at line 1855 of file stm32g431xx.h.

◆ ADC_OFR1_SATEN_Msk

#define ADC_OFR1_SATEN_Msk (0x1UL << ADC_OFR1_SATEN_Pos)

0x02000000

Definition at line 1854 of file stm32g431xx.h.

◆ ADC_OFR1_SATEN_Pos

#define ADC_OFR1_SATEN_Pos (25U)

Definition at line 1853 of file stm32g431xx.h.

◆ ADC_OFR2_OFFSET2

#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk

ADC offset number 2 offset level

Definition at line 1873 of file stm32g431xx.h.

◆ ADC_OFR2_OFFSET2_CH

#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk

ADC offset number 2 channel selection

Definition at line 1884 of file stm32g431xx.h.

◆ ADC_OFR2_OFFSET2_CH_0

#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)

0x04000000

Definition at line 1885 of file stm32g431xx.h.

◆ ADC_OFR2_OFFSET2_CH_1

#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)

0x08000000

Definition at line 1886 of file stm32g431xx.h.

◆ ADC_OFR2_OFFSET2_CH_2

#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)

0x10000000

Definition at line 1887 of file stm32g431xx.h.

◆ ADC_OFR2_OFFSET2_CH_3

#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)

0x20000000

Definition at line 1888 of file stm32g431xx.h.

◆ ADC_OFR2_OFFSET2_CH_4

#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)

0x40000000

Definition at line 1889 of file stm32g431xx.h.

◆ ADC_OFR2_OFFSET2_CH_Msk

#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)

0x7C000000

Definition at line 1883 of file stm32g431xx.h.

◆ ADC_OFR2_OFFSET2_CH_Pos

#define ADC_OFR2_OFFSET2_CH_Pos (26U)

Definition at line 1882 of file stm32g431xx.h.

◆ ADC_OFR2_OFFSET2_EN

#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk

ADC offset number 2 enable

Definition at line 1893 of file stm32g431xx.h.

◆ ADC_OFR2_OFFSET2_EN_Msk

#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos)

0x80000000

Definition at line 1892 of file stm32g431xx.h.

◆ ADC_OFR2_OFFSET2_EN_Pos

#define ADC_OFR2_OFFSET2_EN_Pos (31U)

Definition at line 1891 of file stm32g431xx.h.

◆ ADC_OFR2_OFFSET2_Msk

#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos)

0x00000FFF

Definition at line 1872 of file stm32g431xx.h.

◆ ADC_OFR2_OFFSET2_Pos

#define ADC_OFR2_OFFSET2_Pos (0U)

Definition at line 1871 of file stm32g431xx.h.

◆ ADC_OFR2_OFFSETPOS

#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk

ADC offset number 2 positive

Definition at line 1877 of file stm32g431xx.h.

◆ ADC_OFR2_OFFSETPOS_Msk

#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos)

0x01000000

Definition at line 1876 of file stm32g431xx.h.

◆ ADC_OFR2_OFFSETPOS_Pos

#define ADC_OFR2_OFFSETPOS_Pos (24U)

Definition at line 1875 of file stm32g431xx.h.

◆ ADC_OFR2_SATEN

#define ADC_OFR2_SATEN ADC_OFR2_SATEN_Msk

ADC offset number 2 saturation enable

Definition at line 1880 of file stm32g431xx.h.

◆ ADC_OFR2_SATEN_Msk

#define ADC_OFR2_SATEN_Msk (0x1UL << ADC_OFR2_SATEN_Pos)

0x02000000

Definition at line 1879 of file stm32g431xx.h.

◆ ADC_OFR2_SATEN_Pos

#define ADC_OFR2_SATEN_Pos (25U)

Definition at line 1878 of file stm32g431xx.h.

◆ ADC_OFR3_OFFSET3

#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk

ADC offset number 3 offset level

Definition at line 1898 of file stm32g431xx.h.

◆ ADC_OFR3_OFFSET3_CH

#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk

ADC offset number 3 channel selection

Definition at line 1909 of file stm32g431xx.h.

◆ ADC_OFR3_OFFSET3_CH_0

#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)

0x04000000

Definition at line 1910 of file stm32g431xx.h.

◆ ADC_OFR3_OFFSET3_CH_1

#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)

0x08000000

Definition at line 1911 of file stm32g431xx.h.

◆ ADC_OFR3_OFFSET3_CH_2

#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)

0x10000000

Definition at line 1912 of file stm32g431xx.h.

◆ ADC_OFR3_OFFSET3_CH_3

#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)

0x20000000

Definition at line 1913 of file stm32g431xx.h.

◆ ADC_OFR3_OFFSET3_CH_4

#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)

0x40000000

Definition at line 1914 of file stm32g431xx.h.

◆ ADC_OFR3_OFFSET3_CH_Msk

#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)

0x7C000000

Definition at line 1908 of file stm32g431xx.h.

◆ ADC_OFR3_OFFSET3_CH_Pos

#define ADC_OFR3_OFFSET3_CH_Pos (26U)

Definition at line 1907 of file stm32g431xx.h.

◆ ADC_OFR3_OFFSET3_EN

#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk

ADC offset number 3 enable

Definition at line 1918 of file stm32g431xx.h.

◆ ADC_OFR3_OFFSET3_EN_Msk

#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos)

0x80000000

Definition at line 1917 of file stm32g431xx.h.

◆ ADC_OFR3_OFFSET3_EN_Pos

#define ADC_OFR3_OFFSET3_EN_Pos (31U)

Definition at line 1916 of file stm32g431xx.h.

◆ ADC_OFR3_OFFSET3_Msk

#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos)

0x00000FFF

Definition at line 1897 of file stm32g431xx.h.

◆ ADC_OFR3_OFFSET3_Pos

#define ADC_OFR3_OFFSET3_Pos (0U)

Definition at line 1896 of file stm32g431xx.h.

◆ ADC_OFR3_OFFSETPOS

#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk

ADC offset number 3 positive

Definition at line 1902 of file stm32g431xx.h.

◆ ADC_OFR3_OFFSETPOS_Msk

#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos)

0x01000000

Definition at line 1901 of file stm32g431xx.h.

◆ ADC_OFR3_OFFSETPOS_Pos

#define ADC_OFR3_OFFSETPOS_Pos (24U)

Definition at line 1900 of file stm32g431xx.h.

◆ ADC_OFR3_SATEN

#define ADC_OFR3_SATEN ADC_OFR3_SATEN_Msk

ADC offset number 3 saturation enable

Definition at line 1905 of file stm32g431xx.h.

◆ ADC_OFR3_SATEN_Msk

#define ADC_OFR3_SATEN_Msk (0x1UL << ADC_OFR3_SATEN_Pos)

0x02000000

Definition at line 1904 of file stm32g431xx.h.

◆ ADC_OFR3_SATEN_Pos

#define ADC_OFR3_SATEN_Pos (25U)

Definition at line 1903 of file stm32g431xx.h.

◆ ADC_OFR4_OFFSET4

#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk

ADC offset number 4 offset level

Definition at line 1923 of file stm32g431xx.h.

◆ ADC_OFR4_OFFSET4_CH

#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk

ADC offset number 4 channel selection

Definition at line 1934 of file stm32g431xx.h.

◆ ADC_OFR4_OFFSET4_CH_0

#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)

0x04000000

Definition at line 1935 of file stm32g431xx.h.

◆ ADC_OFR4_OFFSET4_CH_1

#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)

0x08000000

Definition at line 1936 of file stm32g431xx.h.

◆ ADC_OFR4_OFFSET4_CH_2

#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)

0x10000000

Definition at line 1937 of file stm32g431xx.h.

◆ ADC_OFR4_OFFSET4_CH_3

#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)

0x20000000

Definition at line 1938 of file stm32g431xx.h.

◆ ADC_OFR4_OFFSET4_CH_4

#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)

0x40000000

Definition at line 1939 of file stm32g431xx.h.

◆ ADC_OFR4_OFFSET4_CH_Msk

#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)

0x7C000000

Definition at line 1933 of file stm32g431xx.h.

◆ ADC_OFR4_OFFSET4_CH_Pos

#define ADC_OFR4_OFFSET4_CH_Pos (26U)

Definition at line 1932 of file stm32g431xx.h.

◆ ADC_OFR4_OFFSET4_EN

#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk

ADC offset number 4 enable

Definition at line 1943 of file stm32g431xx.h.

◆ ADC_OFR4_OFFSET4_EN_Msk

#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos)

0x80000000

Definition at line 1942 of file stm32g431xx.h.

◆ ADC_OFR4_OFFSET4_EN_Pos

#define ADC_OFR4_OFFSET4_EN_Pos (31U)

Definition at line 1941 of file stm32g431xx.h.

◆ ADC_OFR4_OFFSET4_Msk

#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos)

0x00000FFF

Definition at line 1922 of file stm32g431xx.h.

◆ ADC_OFR4_OFFSET4_Pos

#define ADC_OFR4_OFFSET4_Pos (0U)

Definition at line 1921 of file stm32g431xx.h.

◆ ADC_OFR4_OFFSETPOS

#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk

ADC offset number 4 positive

Definition at line 1927 of file stm32g431xx.h.

◆ ADC_OFR4_OFFSETPOS_Msk

#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos)

0x01000000

Definition at line 1926 of file stm32g431xx.h.

◆ ADC_OFR4_OFFSETPOS_Pos

#define ADC_OFR4_OFFSETPOS_Pos (24U)

Definition at line 1925 of file stm32g431xx.h.

◆ ADC_OFR4_SATEN

#define ADC_OFR4_SATEN ADC_OFR4_SATEN_Msk

ADC offset number 4 saturation enable

Definition at line 1930 of file stm32g431xx.h.

◆ ADC_OFR4_SATEN_Msk

#define ADC_OFR4_SATEN_Msk (0x1UL << ADC_OFR4_SATEN_Pos)

0x02000000

Definition at line 1929 of file stm32g431xx.h.

◆ ADC_OFR4_SATEN_Pos

#define ADC_OFR4_SATEN_Pos (25U)

Definition at line 1928 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP0

#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk

ADC channel 0 sampling time selection

Definition at line 1456 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP0_0

#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos)

0x00000001

Definition at line 1457 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP0_1

#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos)

0x00000002

Definition at line 1458 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP0_2

#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos)

0x00000004

Definition at line 1459 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP0_Msk

#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos)

0x00000007

Definition at line 1455 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP0_Pos

#define ADC_SMPR1_SMP0_Pos (0U)

Definition at line 1454 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP1

#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk

ADC channel 1 sampling time selection

Definition at line 1463 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP1_0

#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos)

0x00000008

Definition at line 1464 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP1_1

#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos)

0x00000010

Definition at line 1465 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP1_2

#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos)

0x00000020

Definition at line 1466 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP1_Msk

#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos)

0x00000038

Definition at line 1462 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP1_Pos

#define ADC_SMPR1_SMP1_Pos (3U)

Definition at line 1461 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP2

#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk

ADC channel 2 sampling time selection

Definition at line 1470 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP2_0

#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos)

0x00000040

Definition at line 1471 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP2_1

#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos)

0x00000080

Definition at line 1472 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP2_2

#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos)

0x00000100

Definition at line 1473 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP2_Msk

#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos)

0x000001C0

Definition at line 1469 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP2_Pos

#define ADC_SMPR1_SMP2_Pos (6U)

Definition at line 1468 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP3

#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk

ADC channel 3 sampling time selection

Definition at line 1477 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP3_0

#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos)

0x00000200

Definition at line 1478 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP3_1

#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos)

0x00000400

Definition at line 1479 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP3_2

#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos)

0x00000800

Definition at line 1480 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP3_Msk

#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos)

0x00000E00

Definition at line 1476 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP3_Pos

#define ADC_SMPR1_SMP3_Pos (9U)

Definition at line 1475 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP4

#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk

ADC channel 4 sampling time selection

Definition at line 1484 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP4_0

#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos)

0x00001000

Definition at line 1485 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP4_1

#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos)

0x00002000

Definition at line 1486 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP4_2

#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos)

0x00004000

Definition at line 1487 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP4_Msk

#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos)

0x00007000

Definition at line 1483 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP4_Pos

#define ADC_SMPR1_SMP4_Pos (12U)

Definition at line 1482 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP5

#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk

ADC channel 5 sampling time selection

Definition at line 1491 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP5_0

#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos)

0x00008000

Definition at line 1492 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP5_1

#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos)

0x00010000

Definition at line 1493 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP5_2

#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos)

0x00020000

Definition at line 1494 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP5_Msk

#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos)

0x00038000

Definition at line 1490 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP5_Pos

#define ADC_SMPR1_SMP5_Pos (15U)

Definition at line 1489 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP6

#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk

ADC channel 6 sampling time selection

Definition at line 1498 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP6_0

#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos)

0x00040000

Definition at line 1499 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP6_1

#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos)

0x00080000

Definition at line 1500 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP6_2

#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos)

0x00100000

Definition at line 1501 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP6_Msk

#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos)

0x001C0000

Definition at line 1497 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP6_Pos

#define ADC_SMPR1_SMP6_Pos (18U)

Definition at line 1496 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP7

#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk

ADC channel 7 sampling time selection

Definition at line 1505 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP7_0

#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos)

0x00200000

Definition at line 1506 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP7_1

#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos)

0x00400000

Definition at line 1507 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP7_2

#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos)

0x00800000

Definition at line 1508 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP7_Msk

#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos)

0x00E00000

Definition at line 1504 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP7_Pos

#define ADC_SMPR1_SMP7_Pos (21U)

Definition at line 1503 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP8

#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk

ADC channel 8 sampling time selection

Definition at line 1512 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP8_0

#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos)

0x01000000

Definition at line 1513 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP8_1

#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos)

0x02000000

Definition at line 1514 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP8_2

#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos)

0x04000000

Definition at line 1515 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP8_Msk

#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos)

0x07000000

Definition at line 1511 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP8_Pos

#define ADC_SMPR1_SMP8_Pos (24U)

Definition at line 1510 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP9

#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk

ADC channel 9 sampling time selection

Definition at line 1519 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP9_0

#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos)

0x08000000

Definition at line 1520 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP9_1

#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos)

0x10000000

Definition at line 1521 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP9_2

#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos)

0x20000000

Definition at line 1522 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP9_Msk

#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos)

0x38000000

Definition at line 1518 of file stm32g431xx.h.

◆ ADC_SMPR1_SMP9_Pos

#define ADC_SMPR1_SMP9_Pos (27U)

Definition at line 1517 of file stm32g431xx.h.

◆ ADC_SMPR1_SMPPLUS

#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk

ADC channels sampling time additional setting

Definition at line 1526 of file stm32g431xx.h.

◆ ADC_SMPR1_SMPPLUS_Msk

#define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos)

0x80000000

Definition at line 1525 of file stm32g431xx.h.

◆ ADC_SMPR1_SMPPLUS_Pos

#define ADC_SMPR1_SMPPLUS_Pos (31U)

Definition at line 1524 of file stm32g431xx.h.

◆ ADC_SMPR2_SMP10

#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk

ADC channel 10 sampling time selection

Definition at line 1531 of file stm32g431xx.h.

◆ ADC_SMPR2_SMP10_0

#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos)

0x00000001

Definition at line 1532 of file stm32g431xx.h.

◆ ADC_SMPR2_SMP10_1

#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos)

0x00000002

Definition at line 1533 of file stm32g431xx.h.

◆ ADC_SMPR2_SMP10_2

#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos)

0x00000004

Definition at line 1534 of file stm32g431xx.h.

◆ ADC_SMPR2_SMP10_Msk

#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos)

0x00000007

Definition at line 1530 of file stm32g431xx.h.

◆ ADC_SMPR2_SMP10_Pos

#define ADC_SMPR2_SMP10_Pos (0U)

Definition at line 1529 of file stm32g431xx.h.

◆ ADC_SMPR2_SMP11

#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk

ADC channel 11 sampling time selection

Definition at line 1538 of file stm32g431xx.h.

◆ ADC_SMPR2_SMP11_0

#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos)

0x00000008

Definition at line 1539 of file stm32g431xx.h.

◆ ADC_SMPR2_SMP11_1

#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos)

0x00000010

Definition at line 1540 of file stm32g431xx.h.

◆ ADC_SMPR2_SMP11_2

#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos)

0x00000020

Definition at line 1541 of file stm32g431xx.h.

◆ ADC_SMPR2_SMP11_Msk

#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos)

0x00000038

Definition at line 1537 of file stm32g431xx.h.

◆ ADC_SMPR2_SMP11_Pos

#define ADC_SMPR2_SMP11_Pos (3U)

Definition at line 1536 of file stm32g431xx.h.

◆ ADC_SMPR2_SMP12

#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk

ADC channel 12 sampling time selection

Definition at line 1545 of file stm32g431xx.h.

◆ ADC_SMPR2_SMP12_0

#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos)

0x00000040

Definition at line 1546 of file stm32g431xx.h.

◆ ADC_SMPR2_SMP12_1

#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos)

0x00000080

Definition at line 1547 of file stm32g431xx.h.

◆ ADC_SMPR2_SMP12_2

#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos)

0x00000100

Definition at line 1548 of file stm32g431xx.h.

◆ ADC_SMPR2_SMP12_Msk

#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos)

0x000001C0

Definition at line 1544 of file stm32g431xx.h.

◆ ADC_SMPR2_SMP12_Pos

#define ADC_SMPR2_SMP12_Pos (6U)

Definition at line 1543 of file stm32g431xx.h.

◆ ADC_SMPR2_SMP13

#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk

ADC channel 13 sampling time selection

Definition at line 1552 of file stm32g431xx.h.

◆ ADC_SMPR2_SMP13_0

#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos)

0x00000200

Definition at line 1553 of file stm32g431xx.h.

◆ ADC_SMPR2_SMP13_1

#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos)

0x00000400

Definition at line 1554 of file stm32g431xx.h.

◆ ADC_SMPR2_SMP13_2

#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos)

0x00000800

Definition at line 1555 of file stm32g431xx.h.

◆ ADC_SMPR2_SMP13_Msk

#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos)

0x00000E00

Definition at line 1551 of file stm32g431xx.h.

◆ ADC_SMPR2_SMP13_Pos

#define ADC_SMPR2_SMP13_Pos (9U)

Definition at line 1550 of file stm32g431xx.h.

◆ ADC_SMPR2_SMP14

#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk

ADC channel 14 sampling time selection

Definition at line 1559 of file stm32g431xx.h.

◆ ADC_SMPR2_SMP14_0

#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos)

0x00001000

Definition at line 1560 of file stm32g431xx.h.

◆ ADC_SMPR2_SMP14_1

#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos)

0x00002000

Definition at line 1561 of file stm32g431xx.h.

◆ ADC_SMPR2_SMP14_2

#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos)

0x00004000

Definition at line 1562 of file stm32g431xx.h.

◆ ADC_SMPR2_SMP14_Msk

#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos)

0x00007000

Definition at line 1558 of file stm32g431xx.h.

◆ ADC_SMPR2_SMP14_Pos

#define ADC_SMPR2_SMP14_Pos (12U)

Definition at line 1557 of file stm32g431xx.h.

◆ ADC_SMPR2_SMP15

#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk

ADC channel 15 sampling time selection

Definition at line 1566 of file stm32g431xx.h.

◆ ADC_SMPR2_SMP15_0

#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos)

0x00008000

Definition at line 1567 of file stm32g431xx.h.

◆ ADC_SMPR2_SMP15_1

#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos)

0x00010000

Definition at line 1568 of file stm32g431xx.h.

◆ ADC_SMPR2_SMP15_2

#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos)

0x00020000

Definition at line 1569 of file stm32g431xx.h.

◆ ADC_SMPR2_SMP15_Msk

#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos)

0x00038000

Definition at line 1565 of file stm32g431xx.h.

◆ ADC_SMPR2_SMP15_Pos

#define ADC_SMPR2_SMP15_Pos (15U)

Definition at line 1564 of file stm32g431xx.h.

◆ ADC_SMPR2_SMP16

#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk

ADC channel 16 sampling time selection

Definition at line 1573 of file stm32g431xx.h.

◆ ADC_SMPR2_SMP16_0

#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos)

0x00040000

Definition at line 1574 of file stm32g431xx.h.

◆ ADC_SMPR2_SMP16_1

#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos)

0x00080000

Definition at line 1575 of file stm32g431xx.h.

◆ ADC_SMPR2_SMP16_2

#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos)

0x00100000

Definition at line 1576 of file stm32g431xx.h.

◆ ADC_SMPR2_SMP16_Msk

#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos)

0x001C0000

Definition at line 1572 of file stm32g431xx.h.

◆ ADC_SMPR2_SMP16_Pos

#define ADC_SMPR2_SMP16_Pos (18U)

Definition at line 1571 of file stm32g431xx.h.

◆ ADC_SMPR2_SMP17

#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk

ADC channel 17 sampling time selection

Definition at line 1580 of file stm32g431xx.h.

◆ ADC_SMPR2_SMP17_0

#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos)

0x00200000

Definition at line 1581 of file stm32g431xx.h.

◆ ADC_SMPR2_SMP17_1

#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos)

0x00400000

Definition at line 1582 of file stm32g431xx.h.

◆ ADC_SMPR2_SMP17_2

#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos)

0x00800000

Definition at line 1583 of file stm32g431xx.h.

◆ ADC_SMPR2_SMP17_Msk

#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos)

0x00E00000

Definition at line 1579 of file stm32g431xx.h.

◆ ADC_SMPR2_SMP17_Pos

#define ADC_SMPR2_SMP17_Pos (21U)

Definition at line 1578 of file stm32g431xx.h.

◆ ADC_SMPR2_SMP18

#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk

ADC channel 18 sampling time selection

Definition at line 1587 of file stm32g431xx.h.

◆ ADC_SMPR2_SMP18_0

#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos)

0x01000000

Definition at line 1588 of file stm32g431xx.h.

◆ ADC_SMPR2_SMP18_1

#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos)

0x02000000

Definition at line 1589 of file stm32g431xx.h.

◆ ADC_SMPR2_SMP18_2

#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos)

0x04000000

Definition at line 1590 of file stm32g431xx.h.

◆ ADC_SMPR2_SMP18_Msk

#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos)

0x07000000

Definition at line 1586 of file stm32g431xx.h.

◆ ADC_SMPR2_SMP18_Pos

#define ADC_SMPR2_SMP18_Pos (24U)

Definition at line 1585 of file stm32g431xx.h.

◆ ADC_SQR1_L

#define ADC_SQR1_L ADC_SQR1_L_Msk

ADC group regular sequencer scan length

Definition at line 1629 of file stm32g431xx.h.

◆ ADC_SQR1_L_0

#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos)

0x00000001

Definition at line 1630 of file stm32g431xx.h.

◆ ADC_SQR1_L_1

#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos)

0x00000002

Definition at line 1631 of file stm32g431xx.h.

◆ ADC_SQR1_L_2

#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos)

0x00000004

Definition at line 1632 of file stm32g431xx.h.

◆ ADC_SQR1_L_3

#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos)

0x00000008

Definition at line 1633 of file stm32g431xx.h.

◆ ADC_SQR1_L_Msk

#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos)

0x0000000F

Definition at line 1628 of file stm32g431xx.h.

◆ ADC_SQR1_L_Pos

#define ADC_SQR1_L_Pos (0U)

Definition at line 1627 of file stm32g431xx.h.

◆ ADC_SQR1_SQ1

#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk

ADC group regular sequencer rank 1

Definition at line 1637 of file stm32g431xx.h.

◆ ADC_SQR1_SQ1_0

#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos)

0x00000040

Definition at line 1638 of file stm32g431xx.h.

◆ ADC_SQR1_SQ1_1

#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos)

0x00000080

Definition at line 1639 of file stm32g431xx.h.

◆ ADC_SQR1_SQ1_2

#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos)

0x00000100

Definition at line 1640 of file stm32g431xx.h.

◆ ADC_SQR1_SQ1_3

#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos)

0x00000200

Definition at line 1641 of file stm32g431xx.h.

◆ ADC_SQR1_SQ1_4

#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos)

0x00000400

Definition at line 1642 of file stm32g431xx.h.

◆ ADC_SQR1_SQ1_Msk

#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos)

0x000007C0

Definition at line 1636 of file stm32g431xx.h.

◆ ADC_SQR1_SQ1_Pos

#define ADC_SQR1_SQ1_Pos (6U)

Definition at line 1635 of file stm32g431xx.h.

◆ ADC_SQR1_SQ2

#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk

ADC group regular sequencer rank 2

Definition at line 1646 of file stm32g431xx.h.

◆ ADC_SQR1_SQ2_0

#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos)

0x00001000

Definition at line 1647 of file stm32g431xx.h.

◆ ADC_SQR1_SQ2_1

#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos)

0x00002000

Definition at line 1648 of file stm32g431xx.h.

◆ ADC_SQR1_SQ2_2

#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos)

0x00004000

Definition at line 1649 of file stm32g431xx.h.

◆ ADC_SQR1_SQ2_3

#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos)

0x00008000

Definition at line 1650 of file stm32g431xx.h.

◆ ADC_SQR1_SQ2_4

#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos)

0x00010000

Definition at line 1651 of file stm32g431xx.h.

◆ ADC_SQR1_SQ2_Msk

#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos)

0x0001F000

Definition at line 1645 of file stm32g431xx.h.

◆ ADC_SQR1_SQ2_Pos

#define ADC_SQR1_SQ2_Pos (12U)

Definition at line 1644 of file stm32g431xx.h.

◆ ADC_SQR1_SQ3

#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk

ADC group regular sequencer rank 3

Definition at line 1655 of file stm32g431xx.h.

◆ ADC_SQR1_SQ3_0

#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos)

0x00040000

Definition at line 1656 of file stm32g431xx.h.

◆ ADC_SQR1_SQ3_1

#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos)

0x00080000

Definition at line 1657 of file stm32g431xx.h.

◆ ADC_SQR1_SQ3_2

#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos)

0x00100000

Definition at line 1658 of file stm32g431xx.h.

◆ ADC_SQR1_SQ3_3

#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos)

0x00200000

Definition at line 1659 of file stm32g431xx.h.

◆ ADC_SQR1_SQ3_4

#define ADC_SQR1_SQ3_4 (0x10UL<< ADC_SQR1_SQ3_Pos)

0x00400000

Definition at line 1660 of file stm32g431xx.h.

◆ ADC_SQR1_SQ3_Msk

#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos)

0x007C0000

Definition at line 1654 of file stm32g431xx.h.

◆ ADC_SQR1_SQ3_Pos

#define ADC_SQR1_SQ3_Pos (18U)

Definition at line 1653 of file stm32g431xx.h.

◆ ADC_SQR1_SQ4

#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk

ADC group regular sequencer rank 4

Definition at line 1664 of file stm32g431xx.h.

◆ ADC_SQR1_SQ4_0

#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos)

0x01000000

Definition at line 1665 of file stm32g431xx.h.

◆ ADC_SQR1_SQ4_1

#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos)

0x02000000

Definition at line 1666 of file stm32g431xx.h.

◆ ADC_SQR1_SQ4_2

#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos)

0x04000000

Definition at line 1667 of file stm32g431xx.h.

◆ ADC_SQR1_SQ4_3

#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos)

0x08000000

Definition at line 1668 of file stm32g431xx.h.

◆ ADC_SQR1_SQ4_4

#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos)

0x10000000

Definition at line 1669 of file stm32g431xx.h.

◆ ADC_SQR1_SQ4_Msk

#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos)

0x1F000000

Definition at line 1663 of file stm32g431xx.h.

◆ ADC_SQR1_SQ4_Pos

#define ADC_SQR1_SQ4_Pos (24U)

Definition at line 1662 of file stm32g431xx.h.

◆ ADC_SQR2_SQ5

#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk

ADC group regular sequencer rank 5

Definition at line 1674 of file stm32g431xx.h.

◆ ADC_SQR2_SQ5_0

#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos)

0x00000001

Definition at line 1675 of file stm32g431xx.h.

◆ ADC_SQR2_SQ5_1

#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos)

0x00000002

Definition at line 1676 of file stm32g431xx.h.

◆ ADC_SQR2_SQ5_2

#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos)

0x00000004

Definition at line 1677 of file stm32g431xx.h.

◆ ADC_SQR2_SQ5_3

#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos)

0x00000008

Definition at line 1678 of file stm32g431xx.h.

◆ ADC_SQR2_SQ5_4

#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos)

0x00000010

Definition at line 1679 of file stm32g431xx.h.

◆ ADC_SQR2_SQ5_Msk

#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos)

0x0000001F

Definition at line 1673 of file stm32g431xx.h.

◆ ADC_SQR2_SQ5_Pos

#define ADC_SQR2_SQ5_Pos (0U)

Definition at line 1672 of file stm32g431xx.h.

◆ ADC_SQR2_SQ6

#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk

ADC group regular sequencer rank 6

Definition at line 1683 of file stm32g431xx.h.

◆ ADC_SQR2_SQ6_0

#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos)

0x00000040

Definition at line 1684 of file stm32g431xx.h.

◆ ADC_SQR2_SQ6_1

#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos)

0x00000080

Definition at line 1685 of file stm32g431xx.h.

◆ ADC_SQR2_SQ6_2

#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos)

0x00000100

Definition at line 1686 of file stm32g431xx.h.

◆ ADC_SQR2_SQ6_3

#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos)

0x00000200

Definition at line 1687 of file stm32g431xx.h.

◆ ADC_SQR2_SQ6_4

#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos)

0x00000400

Definition at line 1688 of file stm32g431xx.h.

◆ ADC_SQR2_SQ6_Msk

#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos)

0x000007C0

Definition at line 1682 of file stm32g431xx.h.

◆ ADC_SQR2_SQ6_Pos

#define ADC_SQR2_SQ6_Pos (6U)

Definition at line 1681 of file stm32g431xx.h.

◆ ADC_SQR2_SQ7

#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk

ADC group regular sequencer rank 7

Definition at line 1692 of file stm32g431xx.h.

◆ ADC_SQR2_SQ7_0

#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos)

0x00001000

Definition at line 1693 of file stm32g431xx.h.

◆ ADC_SQR2_SQ7_1

#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos)

0x00002000

Definition at line 1694 of file stm32g431xx.h.

◆ ADC_SQR2_SQ7_2

#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos)

0x00004000

Definition at line 1695 of file stm32g431xx.h.

◆ ADC_SQR2_SQ7_3

#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos)

0x00008000

Definition at line 1696 of file stm32g431xx.h.

◆ ADC_SQR2_SQ7_4

#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos)

0x00010000

Definition at line 1697 of file stm32g431xx.h.

◆ ADC_SQR2_SQ7_Msk

#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos)

0x0001F000

Definition at line 1691 of file stm32g431xx.h.

◆ ADC_SQR2_SQ7_Pos

#define ADC_SQR2_SQ7_Pos (12U)

Definition at line 1690 of file stm32g431xx.h.

◆ ADC_SQR2_SQ8

#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk

ADC group regular sequencer rank 8

Definition at line 1701 of file stm32g431xx.h.

◆ ADC_SQR2_SQ8_0

#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos)

0x00040000

Definition at line 1702 of file stm32g431xx.h.

◆ ADC_SQR2_SQ8_1

#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos)

0x00080000

Definition at line 1703 of file stm32g431xx.h.

◆ ADC_SQR2_SQ8_2

#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos)

0x00100000

Definition at line 1704 of file stm32g431xx.h.

◆ ADC_SQR2_SQ8_3

#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos)

0x00200000

Definition at line 1705 of file stm32g431xx.h.

◆ ADC_SQR2_SQ8_4

#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos)

0x00400000

Definition at line 1706 of file stm32g431xx.h.

◆ ADC_SQR2_SQ8_Msk

#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos)

0x007C0000

Definition at line 1700 of file stm32g431xx.h.

◆ ADC_SQR2_SQ8_Pos

#define ADC_SQR2_SQ8_Pos (18U)

Definition at line 1699 of file stm32g431xx.h.

◆ ADC_SQR2_SQ9

#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk

ADC group regular sequencer rank 9

Definition at line 1710 of file stm32g431xx.h.

◆ ADC_SQR2_SQ9_0

#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos)

0x01000000

Definition at line 1711 of file stm32g431xx.h.

◆ ADC_SQR2_SQ9_1

#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos)

0x02000000

Definition at line 1712 of file stm32g431xx.h.

◆ ADC_SQR2_SQ9_2

#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos)

0x04000000

Definition at line 1713 of file stm32g431xx.h.

◆ ADC_SQR2_SQ9_3

#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos)

0x08000000

Definition at line 1714 of file stm32g431xx.h.

◆ ADC_SQR2_SQ9_4

#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos)

0x10000000

Definition at line 1715 of file stm32g431xx.h.

◆ ADC_SQR2_SQ9_Msk

#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos)

0x1F000000

Definition at line 1709 of file stm32g431xx.h.

◆ ADC_SQR2_SQ9_Pos

#define ADC_SQR2_SQ9_Pos (24U)

Definition at line 1708 of file stm32g431xx.h.

◆ ADC_SQR3_SQ10

#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk

ADC group regular sequencer rank 10

Definition at line 1720 of file stm32g431xx.h.

◆ ADC_SQR3_SQ10_0

#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos)

0x00000001

Definition at line 1721 of file stm32g431xx.h.

◆ ADC_SQR3_SQ10_1

#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos)

0x00000002

Definition at line 1722 of file stm32g431xx.h.

◆ ADC_SQR3_SQ10_2

#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos)

0x00000004

Definition at line 1723 of file stm32g431xx.h.

◆ ADC_SQR3_SQ10_3

#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos)

0x00000008

Definition at line 1724 of file stm32g431xx.h.

◆ ADC_SQR3_SQ10_4

#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos)

0x00000010

Definition at line 1725 of file stm32g431xx.h.

◆ ADC_SQR3_SQ10_Msk

#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos)

0x0000001F

Definition at line 1719 of file stm32g431xx.h.

◆ ADC_SQR3_SQ10_Pos

#define ADC_SQR3_SQ10_Pos (0U)

Definition at line 1718 of file stm32g431xx.h.

◆ ADC_SQR3_SQ11

#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk

ADC group regular sequencer rank 11

Definition at line 1729 of file stm32g431xx.h.

◆ ADC_SQR3_SQ11_0

#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos)

0x00000040

Definition at line 1730 of file stm32g431xx.h.

◆ ADC_SQR3_SQ11_1

#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos)

0x00000080

Definition at line 1731 of file stm32g431xx.h.

◆ ADC_SQR3_SQ11_2

#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos)

0x00000100

Definition at line 1732 of file stm32g431xx.h.

◆ ADC_SQR3_SQ11_3

#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos)

0x00000200

Definition at line 1733 of file stm32g431xx.h.

◆ ADC_SQR3_SQ11_4

#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos)

0x00000400

Definition at line 1734 of file stm32g431xx.h.

◆ ADC_SQR3_SQ11_Msk

#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos)

0x000007C0

Definition at line 1728 of file stm32g431xx.h.

◆ ADC_SQR3_SQ11_Pos

#define ADC_SQR3_SQ11_Pos (6U)

Definition at line 1727 of file stm32g431xx.h.

◆ ADC_SQR3_SQ12

#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk

ADC group regular sequencer rank 12

Definition at line 1738 of file stm32g431xx.h.

◆ ADC_SQR3_SQ12_0

#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos)

0x00001000

Definition at line 1739 of file stm32g431xx.h.

◆ ADC_SQR3_SQ12_1

#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos)

0x00002000

Definition at line 1740 of file stm32g431xx.h.

◆ ADC_SQR3_SQ12_2

#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos)

0x00004000

Definition at line 1741 of file stm32g431xx.h.

◆ ADC_SQR3_SQ12_3

#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos)

0x00008000

Definition at line 1742 of file stm32g431xx.h.

◆ ADC_SQR3_SQ12_4

#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos)

0x00010000

Definition at line 1743 of file stm32g431xx.h.

◆ ADC_SQR3_SQ12_Msk

#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos)

0x0001F000

Definition at line 1737 of file stm32g431xx.h.

◆ ADC_SQR3_SQ12_Pos

#define ADC_SQR3_SQ12_Pos (12U)

Definition at line 1736 of file stm32g431xx.h.

◆ ADC_SQR3_SQ13

#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk

ADC group regular sequencer rank 13

Definition at line 1747 of file stm32g431xx.h.

◆ ADC_SQR3_SQ13_0

#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos)

0x00040000

Definition at line 1748 of file stm32g431xx.h.

◆ ADC_SQR3_SQ13_1

#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos)

0x00080000

Definition at line 1749 of file stm32g431xx.h.

◆ ADC_SQR3_SQ13_2

#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos)

0x00100000

Definition at line 1750 of file stm32g431xx.h.

◆ ADC_SQR3_SQ13_3

#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos)

0x00200000

Definition at line 1751 of file stm32g431xx.h.

◆ ADC_SQR3_SQ13_4

#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos)

0x00400000

Definition at line 1752 of file stm32g431xx.h.

◆ ADC_SQR3_SQ13_Msk

#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos)

0x007C0000

Definition at line 1746 of file stm32g431xx.h.

◆ ADC_SQR3_SQ13_Pos

#define ADC_SQR3_SQ13_Pos (18U)

Definition at line 1745 of file stm32g431xx.h.

◆ ADC_SQR3_SQ14

#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk

ADC group regular sequencer rank 14

Definition at line 1756 of file stm32g431xx.h.

◆ ADC_SQR3_SQ14_0

#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos)

0x01000000

Definition at line 1757 of file stm32g431xx.h.

◆ ADC_SQR3_SQ14_1

#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos)

0x02000000

Definition at line 1758 of file stm32g431xx.h.

◆ ADC_SQR3_SQ14_2

#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos)

0x04000000

Definition at line 1759 of file stm32g431xx.h.

◆ ADC_SQR3_SQ14_3

#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos)

0x08000000

Definition at line 1760 of file stm32g431xx.h.

◆ ADC_SQR3_SQ14_4

#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos)

0x10000000

Definition at line 1761 of file stm32g431xx.h.

◆ ADC_SQR3_SQ14_Msk

#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos)

0x1F000000

Definition at line 1755 of file stm32g431xx.h.

◆ ADC_SQR3_SQ14_Pos

#define ADC_SQR3_SQ14_Pos (24U)

Definition at line 1754 of file stm32g431xx.h.

◆ ADC_SQR4_SQ15

#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk

ADC group regular sequencer rank 15

Definition at line 1766 of file stm32g431xx.h.

◆ ADC_SQR4_SQ15_0

#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos)

0x00000001

Definition at line 1767 of file stm32g431xx.h.

◆ ADC_SQR4_SQ15_1

#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos)

0x00000002

Definition at line 1768 of file stm32g431xx.h.

◆ ADC_SQR4_SQ15_2

#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos)

0x00000004

Definition at line 1769 of file stm32g431xx.h.

◆ ADC_SQR4_SQ15_3

#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos)

0x00000008

Definition at line 1770 of file stm32g431xx.h.

◆ ADC_SQR4_SQ15_4

#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos)

0x00000010

Definition at line 1771 of file stm32g431xx.h.

◆ ADC_SQR4_SQ15_Msk

#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos)

0x0000001F

Definition at line 1765 of file stm32g431xx.h.

◆ ADC_SQR4_SQ15_Pos

#define ADC_SQR4_SQ15_Pos (0U)

Definition at line 1764 of file stm32g431xx.h.

◆ ADC_SQR4_SQ16

#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk

ADC group regular sequencer rank 16

Definition at line 1775 of file stm32g431xx.h.

◆ ADC_SQR4_SQ16_0

#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos)

0x00000040

Definition at line 1776 of file stm32g431xx.h.

◆ ADC_SQR4_SQ16_1

#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos)

0x00000080

Definition at line 1777 of file stm32g431xx.h.

◆ ADC_SQR4_SQ16_2

#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos)

0x00000100

Definition at line 1778 of file stm32g431xx.h.

◆ ADC_SQR4_SQ16_3

#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos)

0x00000200

Definition at line 1779 of file stm32g431xx.h.

◆ ADC_SQR4_SQ16_4

#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos)

0x00000400

Definition at line 1780 of file stm32g431xx.h.

◆ ADC_SQR4_SQ16_Msk

#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos)

0x000007C0

Definition at line 1774 of file stm32g431xx.h.

◆ ADC_SQR4_SQ16_Pos

#define ADC_SQR4_SQ16_Pos (6U)

Definition at line 1773 of file stm32g431xx.h.

◆ ADC_TR1_AWDFILT

#define ADC_TR1_AWDFILT ADC_TR1_AWDFILT_Msk

ADC analog watchdog filtering parameter

Definition at line 1599 of file stm32g431xx.h.

◆ ADC_TR1_AWDFILT_0

#define ADC_TR1_AWDFILT_0 (0x1UL << ADC_TR1_AWDFILT_Pos)

0x00001000

Definition at line 1600 of file stm32g431xx.h.

◆ ADC_TR1_AWDFILT_1

#define ADC_TR1_AWDFILT_1 (0x2UL << ADC_TR1_AWDFILT_Pos)

0x00002000

Definition at line 1601 of file stm32g431xx.h.

◆ ADC_TR1_AWDFILT_2

#define ADC_TR1_AWDFILT_2 (0x4UL << ADC_TR1_AWDFILT_Pos)

0x00004000

Definition at line 1602 of file stm32g431xx.h.

◆ ADC_TR1_AWDFILT_Msk

#define ADC_TR1_AWDFILT_Msk (0x7UL << ADC_TR1_AWDFILT_Pos)

0x00007000

Definition at line 1598 of file stm32g431xx.h.

◆ ADC_TR1_AWDFILT_Pos

#define ADC_TR1_AWDFILT_Pos (12U)

Definition at line 1597 of file stm32g431xx.h.

◆ ADC_TR1_HT1

#define ADC_TR1_HT1 ADC_TR1_HT1_Msk

ADC analog watchdog 1 threshold high

Definition at line 1606 of file stm32g431xx.h.

◆ ADC_TR1_HT1_Msk

#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos)

0x0FFF0000

Definition at line 1605 of file stm32g431xx.h.

◆ ADC_TR1_HT1_Pos

#define ADC_TR1_HT1_Pos (16U)

Definition at line 1604 of file stm32g431xx.h.

◆ ADC_TR1_LT1

#define ADC_TR1_LT1 ADC_TR1_LT1_Msk

ADC analog watchdog 1 threshold low

Definition at line 1595 of file stm32g431xx.h.

◆ ADC_TR1_LT1_Msk

#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos)

0x00000FFF

Definition at line 1594 of file stm32g431xx.h.

◆ ADC_TR1_LT1_Pos

#define ADC_TR1_LT1_Pos (0U)

Definition at line 1593 of file stm32g431xx.h.

◆ ADC_TR2_HT2

#define ADC_TR2_HT2 ADC_TR2_HT2_Msk

ADC analog watchdog 2 threshold high

Definition at line 1615 of file stm32g431xx.h.

◆ ADC_TR2_HT2_Msk

#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos)

0x00FF0000

Definition at line 1614 of file stm32g431xx.h.

◆ ADC_TR2_HT2_Pos

#define ADC_TR2_HT2_Pos (16U)

Definition at line 1613 of file stm32g431xx.h.

◆ ADC_TR2_LT2

#define ADC_TR2_LT2 ADC_TR2_LT2_Msk

ADC analog watchdog 2 threshold low

Definition at line 1611 of file stm32g431xx.h.

◆ ADC_TR2_LT2_Msk

#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos)

0x000000FF

Definition at line 1610 of file stm32g431xx.h.

◆ ADC_TR2_LT2_Pos

#define ADC_TR2_LT2_Pos (0U)

Definition at line 1609 of file stm32g431xx.h.

◆ ADC_TR3_HT3

#define ADC_TR3_HT3 ADC_TR3_HT3_Msk

ADC analog watchdog 3 threshold high

Definition at line 1624 of file stm32g431xx.h.

◆ ADC_TR3_HT3_Msk

#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos)

0x00FF0000

Definition at line 1623 of file stm32g431xx.h.

◆ ADC_TR3_HT3_Pos

#define ADC_TR3_HT3_Pos (16U)

Definition at line 1622 of file stm32g431xx.h.

◆ ADC_TR3_LT3

#define ADC_TR3_LT3 ADC_TR3_LT3_Msk

ADC analog watchdog 3 threshold low

Definition at line 1620 of file stm32g431xx.h.

◆ ADC_TR3_LT3_Msk

#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos)

0x000000FF

Definition at line 1619 of file stm32g431xx.h.

◆ ADC_TR3_LT3_Pos

#define ADC_TR3_LT3_Pos (0U)

Definition at line 1618 of file stm32g431xx.h.

◆ COMP_CSR_BLANKING

#define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk

Comparator blanking source

Definition at line 2232 of file stm32g431xx.h.

◆ COMP_CSR_BLANKING_0

#define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos)

0x00080000

Definition at line 2233 of file stm32g431xx.h.

◆ COMP_CSR_BLANKING_1

#define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos)

0x00100000

Definition at line 2234 of file stm32g431xx.h.

◆ COMP_CSR_BLANKING_2

#define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos)

0x00200000

Definition at line 2235 of file stm32g431xx.h.

◆ COMP_CSR_BLANKING_Msk

#define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos)

0x00380000

Definition at line 2231 of file stm32g431xx.h.

◆ COMP_CSR_BLANKING_Pos

#define COMP_CSR_BLANKING_Pos (19U)

Definition at line 2230 of file stm32g431xx.h.

◆ COMP_CSR_BRGEN

#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk

Comparator scaler bridge enable

Definition at line 2239 of file stm32g431xx.h.

◆ COMP_CSR_BRGEN_Msk

#define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos)

0x00400000

Definition at line 2238 of file stm32g431xx.h.

◆ COMP_CSR_BRGEN_Pos

#define COMP_CSR_BRGEN_Pos (22U)

Definition at line 2237 of file stm32g431xx.h.

◆ COMP_CSR_EN

#define COMP_CSR_EN COMP_CSR_EN_Msk

Comparator enable

Definition at line 2205 of file stm32g431xx.h.

◆ COMP_CSR_EN_Msk

#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos)

0x00000001

Definition at line 2204 of file stm32g431xx.h.

◆ COMP_CSR_EN_Pos

#define COMP_CSR_EN_Pos (0U)

Definition at line 2203 of file stm32g431xx.h.

◆ COMP_CSR_HYST

#define COMP_CSR_HYST COMP_CSR_HYST_Msk

Comparator hysteresis

Definition at line 2225 of file stm32g431xx.h.

◆ COMP_CSR_HYST_0

#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos)

0x00010000

Definition at line 2226 of file stm32g431xx.h.

◆ COMP_CSR_HYST_1

#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos)

0x00020000

Definition at line 2227 of file stm32g431xx.h.

◆ COMP_CSR_HYST_2

#define COMP_CSR_HYST_2 (0x4UL << COMP_CSR_HYST_Pos)

0x00040000

Definition at line 2228 of file stm32g431xx.h.

◆ COMP_CSR_HYST_Msk

#define COMP_CSR_HYST_Msk (0x7UL << COMP_CSR_HYST_Pos)

0x00070000

Definition at line 2224 of file stm32g431xx.h.

◆ COMP_CSR_HYST_Pos

#define COMP_CSR_HYST_Pos (16U)

Definition at line 2223 of file stm32g431xx.h.

◆ COMP_CSR_INMSEL

#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk

Comparator input minus selection

Definition at line 2209 of file stm32g431xx.h.

◆ COMP_CSR_INMSEL_0

#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos)

0x00000010

Definition at line 2210 of file stm32g431xx.h.

◆ COMP_CSR_INMSEL_1

#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos)

0x00000020

Definition at line 2211 of file stm32g431xx.h.

◆ COMP_CSR_INMSEL_2

#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos)

0x00000040

Definition at line 2212 of file stm32g431xx.h.

◆ COMP_CSR_INMSEL_3

#define COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos)

0x00000080

Definition at line 2213 of file stm32g431xx.h.

◆ COMP_CSR_INMSEL_Msk

#define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos)

0x00000070

Definition at line 2208 of file stm32g431xx.h.

◆ COMP_CSR_INMSEL_Pos

#define COMP_CSR_INMSEL_Pos (4U)

Definition at line 2207 of file stm32g431xx.h.

◆ COMP_CSR_INPSEL

#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk

Comparator input plus selection

Definition at line 2217 of file stm32g431xx.h.

◆ COMP_CSR_INPSEL_Msk

#define COMP_CSR_INPSEL_Msk (0x1UL << COMP_CSR_INPSEL_Pos)

0x00000100

Definition at line 2216 of file stm32g431xx.h.

◆ COMP_CSR_INPSEL_Pos

#define COMP_CSR_INPSEL_Pos (8U)

Definition at line 2215 of file stm32g431xx.h.

◆ COMP_CSR_LOCK

#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk

Comparator lock

Definition at line 2251 of file stm32g431xx.h.

◆ COMP_CSR_LOCK_Msk

#define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos)

0x80000000

Definition at line 2250 of file stm32g431xx.h.

◆ COMP_CSR_LOCK_Pos

#define COMP_CSR_LOCK_Pos (31U)

Definition at line 2249 of file stm32g431xx.h.

◆ COMP_CSR_POLARITY

#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk

Comparator output polarity

Definition at line 2221 of file stm32g431xx.h.

◆ COMP_CSR_POLARITY_Msk

#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos)

0x00008000

Definition at line 2220 of file stm32g431xx.h.

◆ COMP_CSR_POLARITY_Pos

#define COMP_CSR_POLARITY_Pos (15U)

Definition at line 2219 of file stm32g431xx.h.

◆ COMP_CSR_SCALEN

#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk

Comparator voltage scaler enable

Definition at line 2243 of file stm32g431xx.h.

◆ COMP_CSR_SCALEN_Msk

#define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos)

0x00800000

Definition at line 2242 of file stm32g431xx.h.

◆ COMP_CSR_SCALEN_Pos

#define COMP_CSR_SCALEN_Pos (23U)

Definition at line 2241 of file stm32g431xx.h.

◆ COMP_CSR_VALUE

#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk

Comparator output level

Definition at line 2247 of file stm32g431xx.h.

◆ COMP_CSR_VALUE_Msk

#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos)

0x40000000

Definition at line 2246 of file stm32g431xx.h.

◆ COMP_CSR_VALUE_Pos

#define COMP_CSR_VALUE_Pos (30U)

Definition at line 2245 of file stm32g431xx.h.

◆ CORDIC_CSR_ARGSIZE

#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk

Width of input data

Definition at line 2299 of file stm32g431xx.h.

◆ CORDIC_CSR_ARGSIZE_Msk

#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos)

0x00400000

Definition at line 2298 of file stm32g431xx.h.

◆ CORDIC_CSR_ARGSIZE_Pos

#define CORDIC_CSR_ARGSIZE_Pos (22U)

Definition at line 2297 of file stm32g431xx.h.

◆ CORDIC_CSR_DMAREN

#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk

DMA Read channel Enable

Definition at line 2284 of file stm32g431xx.h.

◆ CORDIC_CSR_DMAREN_Msk

#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos)

0x00020000

Definition at line 2283 of file stm32g431xx.h.

◆ CORDIC_CSR_DMAREN_Pos

#define CORDIC_CSR_DMAREN_Pos (17U)

Definition at line 2282 of file stm32g431xx.h.

◆ CORDIC_CSR_DMAWEN

#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk

DMA Write channel Enable

Definition at line 2287 of file stm32g431xx.h.

◆ CORDIC_CSR_DMAWEN_Msk

#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos)

0x00040000

Definition at line 2286 of file stm32g431xx.h.

◆ CORDIC_CSR_DMAWEN_Pos

#define CORDIC_CSR_DMAWEN_Pos (18U)

Definition at line 2285 of file stm32g431xx.h.

◆ CORDIC_CSR_FUNC

#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk

Function

Definition at line 2261 of file stm32g431xx.h.

◆ CORDIC_CSR_FUNC_0

#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos)

0x00000001

Definition at line 2262 of file stm32g431xx.h.

◆ CORDIC_CSR_FUNC_1

#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos)

0x00000002

Definition at line 2263 of file stm32g431xx.h.

◆ CORDIC_CSR_FUNC_2

#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos)

0x00000004

Definition at line 2264 of file stm32g431xx.h.

◆ CORDIC_CSR_FUNC_3

#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos)

0x00000008

Definition at line 2265 of file stm32g431xx.h.

◆ CORDIC_CSR_FUNC_Msk

#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos)

0x0000000F

Definition at line 2260 of file stm32g431xx.h.

◆ CORDIC_CSR_FUNC_Pos

#define CORDIC_CSR_FUNC_Pos (0U)

Definition at line 2259 of file stm32g431xx.h.

◆ CORDIC_CSR_IEN

#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk

Interrupt Enable

Definition at line 2281 of file stm32g431xx.h.

◆ CORDIC_CSR_IEN_Msk

#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos)

0x00010000

Definition at line 2280 of file stm32g431xx.h.

◆ CORDIC_CSR_IEN_Pos

#define CORDIC_CSR_IEN_Pos (16U)

Definition at line 2279 of file stm32g431xx.h.

◆ CORDIC_CSR_NARGS

#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk

Number of arguments in RDATA register

Definition at line 2293 of file stm32g431xx.h.

◆ CORDIC_CSR_NARGS_Msk

#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos)

0x00100000

Definition at line 2292 of file stm32g431xx.h.

◆ CORDIC_CSR_NARGS_Pos

#define CORDIC_CSR_NARGS_Pos (20U)

Definition at line 2291 of file stm32g431xx.h.

◆ CORDIC_CSR_NRES

#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk

Number of results in WDATA register

Definition at line 2290 of file stm32g431xx.h.

◆ CORDIC_CSR_NRES_Msk

#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos)

0x00080000

Definition at line 2289 of file stm32g431xx.h.

◆ CORDIC_CSR_NRES_Pos

#define CORDIC_CSR_NRES_Pos (19U)

Definition at line 2288 of file stm32g431xx.h.

◆ CORDIC_CSR_PRECISION

#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk

Precision

Definition at line 2268 of file stm32g431xx.h.

◆ CORDIC_CSR_PRECISION_0

#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos)

0x00000010

Definition at line 2269 of file stm32g431xx.h.

◆ CORDIC_CSR_PRECISION_1

#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos)

0x00000020

Definition at line 2270 of file stm32g431xx.h.

◆ CORDIC_CSR_PRECISION_2

#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos)

0x00000040

Definition at line 2271 of file stm32g431xx.h.

◆ CORDIC_CSR_PRECISION_3

#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos)

0x00000080

Definition at line 2272 of file stm32g431xx.h.

◆ CORDIC_CSR_PRECISION_Msk

#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos)

0x000000F0

Definition at line 2267 of file stm32g431xx.h.

◆ CORDIC_CSR_PRECISION_Pos

#define CORDIC_CSR_PRECISION_Pos (4U)

Definition at line 2266 of file stm32g431xx.h.

◆ CORDIC_CSR_RESSIZE

#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk

Width of output data

Definition at line 2296 of file stm32g431xx.h.

◆ CORDIC_CSR_RESSIZE_Msk

#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos)

0x00200000

Definition at line 2295 of file stm32g431xx.h.

◆ CORDIC_CSR_RESSIZE_Pos

#define CORDIC_CSR_RESSIZE_Pos (21U)

Definition at line 2294 of file stm32g431xx.h.

◆ CORDIC_CSR_RRDY

#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk

Result Ready Flag

Definition at line 2302 of file stm32g431xx.h.

◆ CORDIC_CSR_RRDY_Msk

#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos)

0x80000000

Definition at line 2301 of file stm32g431xx.h.

◆ CORDIC_CSR_RRDY_Pos

#define CORDIC_CSR_RRDY_Pos (31U)

Definition at line 2300 of file stm32g431xx.h.

◆ CORDIC_CSR_SCALE

#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk

Scaling factor

Definition at line 2275 of file stm32g431xx.h.

◆ CORDIC_CSR_SCALE_0

#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos)

0x00000100

Definition at line 2276 of file stm32g431xx.h.

◆ CORDIC_CSR_SCALE_1

#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos)

0x00000200

Definition at line 2277 of file stm32g431xx.h.

◆ CORDIC_CSR_SCALE_2

#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos)

0x00000400

Definition at line 2278 of file stm32g431xx.h.

◆ CORDIC_CSR_SCALE_Msk

#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos)

0x00000700

Definition at line 2274 of file stm32g431xx.h.

◆ CORDIC_CSR_SCALE_Pos

#define CORDIC_CSR_SCALE_Pos (8U)

Definition at line 2273 of file stm32g431xx.h.

◆ CORDIC_RDATA_RES

#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk

Output Result

Definition at line 2312 of file stm32g431xx.h.

◆ CORDIC_RDATA_RES_Msk

#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos)

0xFFFFFFFF

Definition at line 2311 of file stm32g431xx.h.

◆ CORDIC_RDATA_RES_Pos

#define CORDIC_RDATA_RES_Pos (0U)

Definition at line 2310 of file stm32g431xx.h.

◆ CORDIC_WDATA_ARG

#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk

Input Argument

Definition at line 2307 of file stm32g431xx.h.

◆ CORDIC_WDATA_ARG_Msk

#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos)

0xFFFFFFFF

Definition at line 2306 of file stm32g431xx.h.

◆ CORDIC_WDATA_ARG_Pos

#define CORDIC_WDATA_ARG_Pos (0U)

Definition at line 2305 of file stm32g431xx.h.

◆ CRC_CR_POLYSIZE

#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk

Polynomial size bits

Definition at line 2335 of file stm32g431xx.h.

◆ CRC_CR_POLYSIZE_0

#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos)

0x00000008

Definition at line 2336 of file stm32g431xx.h.

◆ CRC_CR_POLYSIZE_1

#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos)

0x00000010

Definition at line 2337 of file stm32g431xx.h.

◆ CRC_CR_POLYSIZE_Msk

#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos)

0x00000018

Definition at line 2334 of file stm32g431xx.h.

◆ CRC_CR_POLYSIZE_Pos

#define CRC_CR_POLYSIZE_Pos (3U)

Definition at line 2333 of file stm32g431xx.h.

◆ CRC_CR_RESET

#define CRC_CR_RESET CRC_CR_RESET_Msk

RESET the CRC computation unit bit

Definition at line 2332 of file stm32g431xx.h.

◆ CRC_CR_RESET_Msk

#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos)

0x00000001

Definition at line 2331 of file stm32g431xx.h.

◆ CRC_CR_RESET_Pos

#define CRC_CR_RESET_Pos (0U)

Definition at line 2330 of file stm32g431xx.h.

◆ CRC_CR_REV_IN

#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk

REV_IN Reverse Input Data bits

Definition at line 2340 of file stm32g431xx.h.

◆ CRC_CR_REV_IN_0

#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos)

0x00000020

Definition at line 2341 of file stm32g431xx.h.

◆ CRC_CR_REV_IN_1

#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos)

0x00000040

Definition at line 2342 of file stm32g431xx.h.

◆ CRC_CR_REV_IN_Msk

#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos)

0x00000060

Definition at line 2339 of file stm32g431xx.h.

◆ CRC_CR_REV_IN_Pos

#define CRC_CR_REV_IN_Pos (5U)

Definition at line 2338 of file stm32g431xx.h.

◆ CRC_CR_REV_OUT

#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk

REV_OUT Reverse Output Data bits

Definition at line 2345 of file stm32g431xx.h.

◆ CRC_CR_REV_OUT_Msk

#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos)

0x00000080

Definition at line 2344 of file stm32g431xx.h.

◆ CRC_CR_REV_OUT_Pos

#define CRC_CR_REV_OUT_Pos (7U)

Definition at line 2343 of file stm32g431xx.h.

◆ CRC_DR_DR

#define CRC_DR_DR CRC_DR_DR_Msk

Data register bits

Definition at line 2322 of file stm32g431xx.h.

◆ CRC_DR_DR_Msk

#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos)

0xFFFFFFFF

Definition at line 2321 of file stm32g431xx.h.

◆ CRC_DR_DR_Pos

#define CRC_DR_DR_Pos (0U)

Definition at line 2320 of file stm32g431xx.h.

◆ CRC_IDR_IDR

#define CRC_IDR_IDR CRC_IDR_IDR_Msk

General-purpose 32-bit data register bits

Definition at line 2327 of file stm32g431xx.h.

◆ CRC_IDR_IDR_Msk

#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)

0xFFFFFFFF

Definition at line 2326 of file stm32g431xx.h.

◆ CRC_IDR_IDR_Pos

#define CRC_IDR_IDR_Pos (0U)

Definition at line 2325 of file stm32g431xx.h.

◆ CRC_INIT_INIT

#define CRC_INIT_INIT CRC_INIT_INIT_Msk

Initial CRC value bits

Definition at line 2350 of file stm32g431xx.h.

◆ CRC_INIT_INIT_Msk

#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)

0xFFFFFFFF

Definition at line 2349 of file stm32g431xx.h.

◆ CRC_INIT_INIT_Pos

#define CRC_INIT_INIT_Pos (0U)

Definition at line 2348 of file stm32g431xx.h.

◆ CRC_POL_POL

#define CRC_POL_POL CRC_POL_POL_Msk

Coefficients of the polynomial

Definition at line 2355 of file stm32g431xx.h.

◆ CRC_POL_POL_Msk

#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos)

0xFFFFFFFF

Definition at line 2354 of file stm32g431xx.h.

◆ CRC_POL_POL_Pos

#define CRC_POL_POL_Pos (0U)

Definition at line 2353 of file stm32g431xx.h.

◆ CRS_CFGR_FELIM

#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk

Frequency error limit

Definition at line 2394 of file stm32g431xx.h.

◆ CRS_CFGR_FELIM_Msk

#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos)

0x00FF0000

Definition at line 2393 of file stm32g431xx.h.

◆ CRS_CFGR_FELIM_Pos

#define CRS_CFGR_FELIM_Pos (16U)

Definition at line 2392 of file stm32g431xx.h.

◆ CRS_CFGR_RELOAD

#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk

Counter reload value

Definition at line 2391 of file stm32g431xx.h.

◆ CRS_CFGR_RELOAD_Msk

#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos)

0x0000FFFF

Definition at line 2390 of file stm32g431xx.h.

◆ CRS_CFGR_RELOAD_Pos

#define CRS_CFGR_RELOAD_Pos (0U)

Definition at line 2389 of file stm32g431xx.h.

◆ CRS_CFGR_SYNCDIV

#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk

SYNC divider

Definition at line 2398 of file stm32g431xx.h.

◆ CRS_CFGR_SYNCDIV_0

#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos)

0x01000000

Definition at line 2399 of file stm32g431xx.h.

◆ CRS_CFGR_SYNCDIV_1

#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos)

0x02000000

Definition at line 2400 of file stm32g431xx.h.

◆ CRS_CFGR_SYNCDIV_2

#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos)

0x04000000

Definition at line 2401 of file stm32g431xx.h.

◆ CRS_CFGR_SYNCDIV_Msk

#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos)

0x07000000

Definition at line 2397 of file stm32g431xx.h.

◆ CRS_CFGR_SYNCDIV_Pos

#define CRS_CFGR_SYNCDIV_Pos (24U)

Definition at line 2396 of file stm32g431xx.h.

◆ CRS_CFGR_SYNCPOL

#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk

SYNC polarity selection

Definition at line 2411 of file stm32g431xx.h.

◆ CRS_CFGR_SYNCPOL_Msk

#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos)

0x80000000

Definition at line 2410 of file stm32g431xx.h.

◆ CRS_CFGR_SYNCPOL_Pos

#define CRS_CFGR_SYNCPOL_Pos (31U)

Definition at line 2409 of file stm32g431xx.h.

◆ CRS_CFGR_SYNCSRC

#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk

SYNC signal source selection

Definition at line 2405 of file stm32g431xx.h.

◆ CRS_CFGR_SYNCSRC_0

#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos)

0x10000000

Definition at line 2406 of file stm32g431xx.h.

◆ CRS_CFGR_SYNCSRC_1

#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos)

0x20000000

Definition at line 2407 of file stm32g431xx.h.

◆ CRS_CFGR_SYNCSRC_Msk

#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos)

0x30000000

Definition at line 2404 of file stm32g431xx.h.

◆ CRS_CFGR_SYNCSRC_Pos

#define CRS_CFGR_SYNCSRC_Pos (28U)

Definition at line 2403 of file stm32g431xx.h.

◆ CRS_CR_AUTOTRIMEN

#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk

Automatic trimming enable

Definition at line 2380 of file stm32g431xx.h.

◆ CRS_CR_AUTOTRIMEN_Msk

#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos)

0x00000040

Definition at line 2379 of file stm32g431xx.h.

◆ CRS_CR_AUTOTRIMEN_Pos

#define CRS_CR_AUTOTRIMEN_Pos (6U)

Definition at line 2378 of file stm32g431xx.h.

◆ CRS_CR_CEN

#define CRS_CR_CEN CRS_CR_CEN_Msk

Frequency error counter enable

Definition at line 2377 of file stm32g431xx.h.

◆ CRS_CR_CEN_Msk

#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos)

0x00000020

Definition at line 2376 of file stm32g431xx.h.

◆ CRS_CR_CEN_Pos

#define CRS_CR_CEN_Pos (5U)

Definition at line 2375 of file stm32g431xx.h.

◆ CRS_CR_ERRIE

#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk

SYNC error or trimming error interrupt enable

Definition at line 2371 of file stm32g431xx.h.

◆ CRS_CR_ERRIE_Msk

#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos)

0x00000004

Definition at line 2370 of file stm32g431xx.h.

◆ CRS_CR_ERRIE_Pos

#define CRS_CR_ERRIE_Pos (2U)

Definition at line 2369 of file stm32g431xx.h.

◆ CRS_CR_ESYNCIE

#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk

Expected SYNC interrupt enable

Definition at line 2374 of file stm32g431xx.h.

◆ CRS_CR_ESYNCIE_Msk

#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos)

0x00000008

Definition at line 2373 of file stm32g431xx.h.

◆ CRS_CR_ESYNCIE_Pos

#define CRS_CR_ESYNCIE_Pos (3U)

Definition at line 2372 of file stm32g431xx.h.

◆ CRS_CR_SWSYNC

#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk

Generate software SYNC event

Definition at line 2383 of file stm32g431xx.h.

◆ CRS_CR_SWSYNC_Msk

#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos)

0x00000080

Definition at line 2382 of file stm32g431xx.h.

◆ CRS_CR_SWSYNC_Pos

#define CRS_CR_SWSYNC_Pos (7U)

Definition at line 2381 of file stm32g431xx.h.

◆ CRS_CR_SYNCOKIE

#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk

SYNC event OK interrupt enable

Definition at line 2365 of file stm32g431xx.h.

◆ CRS_CR_SYNCOKIE_Msk

#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos)

0x00000001

Definition at line 2364 of file stm32g431xx.h.

◆ CRS_CR_SYNCOKIE_Pos

#define CRS_CR_SYNCOKIE_Pos (0U)

Definition at line 2363 of file stm32g431xx.h.

◆ CRS_CR_SYNCWARNIE

#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk

SYNC warning interrupt enable

Definition at line 2368 of file stm32g431xx.h.

◆ CRS_CR_SYNCWARNIE_Msk

#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos)

0x00000002

Definition at line 2367 of file stm32g431xx.h.

◆ CRS_CR_SYNCWARNIE_Pos

#define CRS_CR_SYNCWARNIE_Pos (1U)

Definition at line 2366 of file stm32g431xx.h.

◆ CRS_CR_TRIM

#define CRS_CR_TRIM CRS_CR_TRIM_Msk

HSI48 oscillator smooth trimming

Definition at line 2386 of file stm32g431xx.h.

◆ CRS_CR_TRIM_Msk

#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos)

0x00007F00

Definition at line 2385 of file stm32g431xx.h.

◆ CRS_CR_TRIM_Pos

#define CRS_CR_TRIM_Pos (8U)

Definition at line 2384 of file stm32g431xx.h.

◆ CRS_ICR_ERRC

#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk

Error clear flag

Definition at line 2451 of file stm32g431xx.h.

◆ CRS_ICR_ERRC_Msk

#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos)

0x00000004

Definition at line 2450 of file stm32g431xx.h.

◆ CRS_ICR_ERRC_Pos

#define CRS_ICR_ERRC_Pos (2U)

Definition at line 2449 of file stm32g431xx.h.

◆ CRS_ICR_ESYNCC

#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk

Expected SYNC clear flag

Definition at line 2454 of file stm32g431xx.h.

◆ CRS_ICR_ESYNCC_Msk

#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos)

0x00000008

Definition at line 2453 of file stm32g431xx.h.

◆ CRS_ICR_ESYNCC_Pos

#define CRS_ICR_ESYNCC_Pos (3U)

Definition at line 2452 of file stm32g431xx.h.

◆ CRS_ICR_SYNCOKC

#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk

SYNC event OK clear flag

Definition at line 2445 of file stm32g431xx.h.

◆ CRS_ICR_SYNCOKC_Msk

#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos)

0x00000001

Definition at line 2444 of file stm32g431xx.h.

◆ CRS_ICR_SYNCOKC_Pos

#define CRS_ICR_SYNCOKC_Pos (0U)

Definition at line 2443 of file stm32g431xx.h.

◆ CRS_ICR_SYNCWARNC

#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk

SYNC warning clear flag

Definition at line 2448 of file stm32g431xx.h.

◆ CRS_ICR_SYNCWARNC_Msk

#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos)

0x00000002

Definition at line 2447 of file stm32g431xx.h.

◆ CRS_ICR_SYNCWARNC_Pos

#define CRS_ICR_SYNCWARNC_Pos (1U)

Definition at line 2446 of file stm32g431xx.h.

◆ CRS_ISR_ERRF

#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk

Error flag

Definition at line 2422 of file stm32g431xx.h.

◆ CRS_ISR_ERRF_Msk

#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos)

0x00000004

Definition at line 2421 of file stm32g431xx.h.

◆ CRS_ISR_ERRF_Pos

#define CRS_ISR_ERRF_Pos (2U)

Definition at line 2420 of file stm32g431xx.h.

◆ CRS_ISR_ESYNCF

#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk

Expected SYNC flag

Definition at line 2425 of file stm32g431xx.h.

◆ CRS_ISR_ESYNCF_Msk

#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos)

0x00000008

Definition at line 2424 of file stm32g431xx.h.

◆ CRS_ISR_ESYNCF_Pos

#define CRS_ISR_ESYNCF_Pos (3U)

Definition at line 2423 of file stm32g431xx.h.

◆ CRS_ISR_FECAP

#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk

Frequency error capture

Definition at line 2440 of file stm32g431xx.h.

◆ CRS_ISR_FECAP_Msk

#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos)

0xFFFF0000

Definition at line 2439 of file stm32g431xx.h.

◆ CRS_ISR_FECAP_Pos

#define CRS_ISR_FECAP_Pos (16U)

Definition at line 2438 of file stm32g431xx.h.

◆ CRS_ISR_FEDIR

#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk

Frequency error direction

Definition at line 2437 of file stm32g431xx.h.

◆ CRS_ISR_FEDIR_Msk

#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos)

0x00008000

Definition at line 2436 of file stm32g431xx.h.

◆ CRS_ISR_FEDIR_Pos

#define CRS_ISR_FEDIR_Pos (15U)

Definition at line 2435 of file stm32g431xx.h.

◆ CRS_ISR_SYNCERR

#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk

SYNC error

Definition at line 2428 of file stm32g431xx.h.

◆ CRS_ISR_SYNCERR_Msk

#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos)

0x00000100

Definition at line 2427 of file stm32g431xx.h.

◆ CRS_ISR_SYNCERR_Pos

#define CRS_ISR_SYNCERR_Pos (8U)

Definition at line 2426 of file stm32g431xx.h.

◆ CRS_ISR_SYNCMISS

#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk

SYNC missed

Definition at line 2431 of file stm32g431xx.h.

◆ CRS_ISR_SYNCMISS_Msk

#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos)

0x00000200

Definition at line 2430 of file stm32g431xx.h.

◆ CRS_ISR_SYNCMISS_Pos

#define CRS_ISR_SYNCMISS_Pos (9U)

Definition at line 2429 of file stm32g431xx.h.

◆ CRS_ISR_SYNCOKF

#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk

SYNC event OK flag

Definition at line 2416 of file stm32g431xx.h.

◆ CRS_ISR_SYNCOKF_Msk

#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos)

0x00000001

Definition at line 2415 of file stm32g431xx.h.

◆ CRS_ISR_SYNCOKF_Pos

#define CRS_ISR_SYNCOKF_Pos (0U)

Definition at line 2414 of file stm32g431xx.h.

◆ CRS_ISR_SYNCWARNF

#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk

SYNC warning flag

Definition at line 2419 of file stm32g431xx.h.

◆ CRS_ISR_SYNCWARNF_Msk

#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos)

0x00000002

Definition at line 2418 of file stm32g431xx.h.

◆ CRS_ISR_SYNCWARNF_Pos

#define CRS_ISR_SYNCWARNF_Pos (1U)

Definition at line 2417 of file stm32g431xx.h.

◆ CRS_ISR_TRIMOVF

#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk

Trimming overflow or underflow

Definition at line 2434 of file stm32g431xx.h.

◆ CRS_ISR_TRIMOVF_Msk

#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos)

0x00000400

Definition at line 2433 of file stm32g431xx.h.

◆ CRS_ISR_TRIMOVF_Pos

#define CRS_ISR_TRIMOVF_Pos (10U)

Definition at line 2432 of file stm32g431xx.h.

◆ DAC_CCR_OTRIM1

#define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk

DAC channel1 offset trimming value

Definition at line 2687 of file stm32g431xx.h.

◆ DAC_CCR_OTRIM1_Msk

#define DAC_CCR_OTRIM1_Msk (0x1FUL << DAC_CCR_OTRIM1_Pos)

0x0000001F

Definition at line 2686 of file stm32g431xx.h.

◆ DAC_CCR_OTRIM1_Pos

#define DAC_CCR_OTRIM1_Pos (0U)

Definition at line 2685 of file stm32g431xx.h.

◆ DAC_CCR_OTRIM2

#define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk

DAC channel2 offset trimming value

Definition at line 2690 of file stm32g431xx.h.

◆ DAC_CCR_OTRIM2_Msk

#define DAC_CCR_OTRIM2_Msk (0x1FUL << DAC_CCR_OTRIM2_Pos)

0x001F0000

Definition at line 2689 of file stm32g431xx.h.

◆ DAC_CCR_OTRIM2_Pos

#define DAC_CCR_OTRIM2_Pos (16U)

Definition at line 2688 of file stm32g431xx.h.

◆ DAC_CHANNEL2_SUPPORT

#define DAC_CHANNEL2_SUPPORT

DAC feature available only on specific devices: DAC channel 2 available

Definition at line 2464 of file stm32g431xx.h.

◆ DAC_CR_CEN1

#define DAC_CR_CEN1 DAC_CR_CEN1_Msk

DAC channel 1 calibration enable >

Definition at line 2504 of file stm32g431xx.h.

◆ DAC_CR_CEN1_Msk

#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos)

0x00004000

Definition at line 2503 of file stm32g431xx.h.

◆ DAC_CR_CEN1_Pos

#define DAC_CR_CEN1_Pos (14U)

Definition at line 2502 of file stm32g431xx.h.

◆ DAC_CR_CEN2

#define DAC_CR_CEN2 DAC_CR_CEN2_Msk

DAC channel2 calibration enable >

Definition at line 2547 of file stm32g431xx.h.

◆ DAC_CR_CEN2_Msk

#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos)

0x40000000

Definition at line 2546 of file stm32g431xx.h.

◆ DAC_CR_CEN2_Pos

#define DAC_CR_CEN2_Pos (30U)

Definition at line 2545 of file stm32g431xx.h.

◆ DAC_CR_DMAEN1

#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk

DAC channel1 DMA enable

Definition at line 2498 of file stm32g431xx.h.

◆ DAC_CR_DMAEN1_Msk

#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos)

0x00001000

Definition at line 2497 of file stm32g431xx.h.

◆ DAC_CR_DMAEN1_Pos

#define DAC_CR_DMAEN1_Pos (12U)

Definition at line 2496 of file stm32g431xx.h.

◆ DAC_CR_DMAEN2

#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk

DAC channel2 DMA enabled

Definition at line 2541 of file stm32g431xx.h.

◆ DAC_CR_DMAEN2_Msk

#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos)

0x10000000

Definition at line 2540 of file stm32g431xx.h.

◆ DAC_CR_DMAEN2_Pos

#define DAC_CR_DMAEN2_Pos (28U)

Definition at line 2539 of file stm32g431xx.h.

◆ DAC_CR_DMAUDRIE1

#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk

DAC channel 1 DMA underrun interrupt enable >

Definition at line 2501 of file stm32g431xx.h.

◆ DAC_CR_DMAUDRIE1_Msk

#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos)

0x00002000

Definition at line 2500 of file stm32g431xx.h.

◆ DAC_CR_DMAUDRIE1_Pos

#define DAC_CR_DMAUDRIE1_Pos (13U)

Definition at line 2499 of file stm32g431xx.h.

◆ DAC_CR_DMAUDRIE2

#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk

DAC channel2 DMA underrun interrupt enable >

Definition at line 2544 of file stm32g431xx.h.

◆ DAC_CR_DMAUDRIE2_Msk

#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos)

0x20000000

Definition at line 2543 of file stm32g431xx.h.

◆ DAC_CR_DMAUDRIE2_Pos

#define DAC_CR_DMAUDRIE2_Pos (29U)

Definition at line 2542 of file stm32g431xx.h.

◆ DAC_CR_EN1

#define DAC_CR_EN1 DAC_CR_EN1_Msk

DAC channel1 enable

Definition at line 2469 of file stm32g431xx.h.

◆ DAC_CR_EN1_Msk

#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos)

0x00000001

Definition at line 2468 of file stm32g431xx.h.

◆ DAC_CR_EN1_Pos

#define DAC_CR_EN1_Pos (0U)

Definition at line 2467 of file stm32g431xx.h.

◆ DAC_CR_EN2

#define DAC_CR_EN2 DAC_CR_EN2_Msk

DAC channel2 enable

Definition at line 2512 of file stm32g431xx.h.

◆ DAC_CR_EN2_Msk

#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos)

0x00010000

Definition at line 2511 of file stm32g431xx.h.

◆ DAC_CR_EN2_Pos

#define DAC_CR_EN2_Pos (16U)

Definition at line 2510 of file stm32g431xx.h.

◆ DAC_CR_HFSEL

#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk

DAC channel 1 and 2 high frequency mode enable >

Definition at line 2508 of file stm32g431xx.h.

◆ DAC_CR_HFSEL_Msk

#define DAC_CR_HFSEL_Msk (0x1UL << DAC_CR_HFSEL_Pos)

0x00008000

Definition at line 2507 of file stm32g431xx.h.

◆ DAC_CR_HFSEL_Pos

#define DAC_CR_HFSEL_Pos (15U)

Definition at line 2506 of file stm32g431xx.h.

◆ DAC_CR_MAMP1

#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk

MAMP1[3:0] (DAC channel1 Mask/Amplitude selector)

Definition at line 2490 of file stm32g431xx.h.

◆ DAC_CR_MAMP1_0

#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos)

0x00000100

Definition at line 2491 of file stm32g431xx.h.

◆ DAC_CR_MAMP1_1

#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos)

0x00000200

Definition at line 2492 of file stm32g431xx.h.

◆ DAC_CR_MAMP1_2

#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos)

0x00000400

Definition at line 2493 of file stm32g431xx.h.

◆ DAC_CR_MAMP1_3

#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos)

0x00000800

Definition at line 2494 of file stm32g431xx.h.

◆ DAC_CR_MAMP1_Msk

#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos)

0x00000F00

Definition at line 2489 of file stm32g431xx.h.

◆ DAC_CR_MAMP1_Pos

#define DAC_CR_MAMP1_Pos (8U)

Definition at line 2488 of file stm32g431xx.h.

◆ DAC_CR_MAMP2

#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk

MAMP2[3:0] (DAC channel2 Mask/Amplitude selector)

Definition at line 2533 of file stm32g431xx.h.

◆ DAC_CR_MAMP2_0

#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos)

0x01000000

Definition at line 2534 of file stm32g431xx.h.

◆ DAC_CR_MAMP2_1

#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos)

0x02000000

Definition at line 2535 of file stm32g431xx.h.

◆ DAC_CR_MAMP2_2

#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos)

0x04000000

Definition at line 2536 of file stm32g431xx.h.

◆ DAC_CR_MAMP2_3

#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos)

0x08000000

Definition at line 2537 of file stm32g431xx.h.

◆ DAC_CR_MAMP2_Msk

#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos)

0x0F000000

Definition at line 2532 of file stm32g431xx.h.

◆ DAC_CR_MAMP2_Pos

#define DAC_CR_MAMP2_Pos (24U)

Definition at line 2531 of file stm32g431xx.h.

◆ DAC_CR_TEN1

#define DAC_CR_TEN1 DAC_CR_TEN1_Msk

DAC channel1 Trigger enable

Definition at line 2472 of file stm32g431xx.h.

◆ DAC_CR_TEN1_Msk

#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos)

0x00000002

Definition at line 2471 of file stm32g431xx.h.

◆ DAC_CR_TEN1_Pos

#define DAC_CR_TEN1_Pos (1U)

Definition at line 2470 of file stm32g431xx.h.

◆ DAC_CR_TEN2

#define DAC_CR_TEN2 DAC_CR_TEN2_Msk

DAC channel2 Trigger enable

Definition at line 2515 of file stm32g431xx.h.

◆ DAC_CR_TEN2_Msk

#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos)

0x00020000

Definition at line 2514 of file stm32g431xx.h.

◆ DAC_CR_TEN2_Pos

#define DAC_CR_TEN2_Pos (17U)

Definition at line 2513 of file stm32g431xx.h.

◆ DAC_CR_TSEL1

#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk

TSEL1[3:0] (DAC channel1 Trigger selection)

Definition at line 2476 of file stm32g431xx.h.

◆ DAC_CR_TSEL1_0

#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos)

0x00000004

Definition at line 2477 of file stm32g431xx.h.

◆ DAC_CR_TSEL1_1

#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos)

0x00000008

Definition at line 2478 of file stm32g431xx.h.

◆ DAC_CR_TSEL1_2

#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos)

0x00000010

Definition at line 2479 of file stm32g431xx.h.

◆ DAC_CR_TSEL1_3

#define DAC_CR_TSEL1_3 (0x8UL << DAC_CR_TSEL1_Pos)

0x00000020

Definition at line 2480 of file stm32g431xx.h.

◆ DAC_CR_TSEL1_Msk

#define DAC_CR_TSEL1_Msk (0xFUL << DAC_CR_TSEL1_Pos)

0x0000003C

Definition at line 2475 of file stm32g431xx.h.

◆ DAC_CR_TSEL1_Pos

#define DAC_CR_TSEL1_Pos (2U)

Definition at line 2474 of file stm32g431xx.h.

◆ DAC_CR_TSEL2

#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk

TSEL2[3:0] (DAC channel2 Trigger selection)

Definition at line 2519 of file stm32g431xx.h.

◆ DAC_CR_TSEL2_0

#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos)

0x00040000

Definition at line 2520 of file stm32g431xx.h.

◆ DAC_CR_TSEL2_1

#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos)

0x00080000

Definition at line 2521 of file stm32g431xx.h.

◆ DAC_CR_TSEL2_2

#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos)

0x00100000

Definition at line 2522 of file stm32g431xx.h.

◆ DAC_CR_TSEL2_3

#define DAC_CR_TSEL2_3 (0x8UL << DAC_CR_TSEL2_Pos)

0x00200000

Definition at line 2523 of file stm32g431xx.h.

◆ DAC_CR_TSEL2_Msk

#define DAC_CR_TSEL2_Msk (0xFUL << DAC_CR_TSEL2_Pos)

0x003C0000

Definition at line 2518 of file stm32g431xx.h.

◆ DAC_CR_TSEL2_Pos

#define DAC_CR_TSEL2_Pos (18U)

Definition at line 2517 of file stm32g431xx.h.

◆ DAC_CR_WAVE1

#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk

WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable)

Definition at line 2484 of file stm32g431xx.h.

◆ DAC_CR_WAVE1_0

#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos)

0x00000040

Definition at line 2485 of file stm32g431xx.h.

◆ DAC_CR_WAVE1_1

#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos)

0x00000080

Definition at line 2486 of file stm32g431xx.h.

◆ DAC_CR_WAVE1_Msk

#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos)

0x000000C0

Definition at line 2483 of file stm32g431xx.h.

◆ DAC_CR_WAVE1_Pos

#define DAC_CR_WAVE1_Pos (6U)

Definition at line 2482 of file stm32g431xx.h.

◆ DAC_CR_WAVE2

#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk

WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable)

Definition at line 2527 of file stm32g431xx.h.

◆ DAC_CR_WAVE2_0

#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos)

0x00400000

Definition at line 2528 of file stm32g431xx.h.

◆ DAC_CR_WAVE2_1

#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos)

0x00800000

Definition at line 2529 of file stm32g431xx.h.

◆ DAC_CR_WAVE2_Msk

#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos)

0x00C00000

Definition at line 2526 of file stm32g431xx.h.

◆ DAC_CR_WAVE2_Pos

#define DAC_CR_WAVE2_Pos (22U)

Definition at line 2525 of file stm32g431xx.h.

◆ DAC_DHR12L1_DACC1DHR

#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk

DAC channel1 12-bit Left aligned data

Definition at line 2574 of file stm32g431xx.h.

◆ DAC_DHR12L1_DACC1DHR_Msk

#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)

0x0000FFF0

Definition at line 2573 of file stm32g431xx.h.

◆ DAC_DHR12L1_DACC1DHR_Pos

#define DAC_DHR12L1_DACC1DHR_Pos (4U)

Definition at line 2572 of file stm32g431xx.h.

◆ DAC_DHR12L1_DACC1DHRB

#define DAC_DHR12L1_DACC1DHRB DAC_DHR12L1_DACC1DHRB_Msk

DAC channel1 12-bit Left aligned data B

Definition at line 2577 of file stm32g431xx.h.

◆ DAC_DHR12L1_DACC1DHRB_Msk

#define DAC_DHR12L1_DACC1DHRB_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHRB_Pos)

0xFFF00000

Definition at line 2576 of file stm32g431xx.h.

◆ DAC_DHR12L1_DACC1DHRB_Pos

#define DAC_DHR12L1_DACC1DHRB_Pos (20U)

Definition at line 2575 of file stm32g431xx.h.

◆ DAC_DHR12L2_DACC2DHR

#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk

DAC channel2 12-bit Left aligned data

Definition at line 2598 of file stm32g431xx.h.

◆ DAC_DHR12L2_DACC2DHR_Msk

#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)

0x0000FFF0

Definition at line 2597 of file stm32g431xx.h.

◆ DAC_DHR12L2_DACC2DHR_Pos

#define DAC_DHR12L2_DACC2DHR_Pos (4U)

Definition at line 2596 of file stm32g431xx.h.

◆ DAC_DHR12L2_DACC2DHRB

#define DAC_DHR12L2_DACC2DHRB DAC_DHR12L2_DACC2DHRB_Msk

DAC channel2 12-bit Left aligned data B

Definition at line 2601 of file stm32g431xx.h.

◆ DAC_DHR12L2_DACC2DHRB_Msk

#define DAC_DHR12L2_DACC2DHRB_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHRB_Pos)

0xFFF00000

Definition at line 2600 of file stm32g431xx.h.

◆ DAC_DHR12L2_DACC2DHRB_Pos

#define DAC_DHR12L2_DACC2DHRB_Pos (20U)

Definition at line 2599 of file stm32g431xx.h.

◆ DAC_DHR12LD_DACC1DHR

#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk

DAC channel1 12-bit Left aligned data

Definition at line 2622 of file stm32g431xx.h.

◆ DAC_DHR12LD_DACC1DHR_Msk

#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)

0x0000FFF0

Definition at line 2621 of file stm32g431xx.h.

◆ DAC_DHR12LD_DACC1DHR_Pos

#define DAC_DHR12LD_DACC1DHR_Pos (4U)

Definition at line 2620 of file stm32g431xx.h.

◆ DAC_DHR12LD_DACC2DHR

#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk

DAC channel2 12-bit Left aligned data

Definition at line 2625 of file stm32g431xx.h.

◆ DAC_DHR12LD_DACC2DHR_Msk

#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)

0xFFF00000

Definition at line 2624 of file stm32g431xx.h.

◆ DAC_DHR12LD_DACC2DHR_Pos

#define DAC_DHR12LD_DACC2DHR_Pos (20U)

Definition at line 2623 of file stm32g431xx.h.

◆ DAC_DHR12R1_DACC1DHR

#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk

DAC channel1 12-bit Right aligned data

Definition at line 2566 of file stm32g431xx.h.

◆ DAC_DHR12R1_DACC1DHR_Msk

#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)

0x00000FFF

Definition at line 2565 of file stm32g431xx.h.

◆ DAC_DHR12R1_DACC1DHR_Pos

#define DAC_DHR12R1_DACC1DHR_Pos (0U)

Definition at line 2564 of file stm32g431xx.h.

◆ DAC_DHR12R1_DACC1DHRB

#define DAC_DHR12R1_DACC1DHRB DAC_DHR12R1_DACC1DHRB_Msk

DAC channel1 12-bit Right-aligned data B

Definition at line 2569 of file stm32g431xx.h.

◆ DAC_DHR12R1_DACC1DHRB_Msk

#define DAC_DHR12R1_DACC1DHRB_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHRB_Pos)

0x0FFF0000

Definition at line 2568 of file stm32g431xx.h.

◆ DAC_DHR12R1_DACC1DHRB_Pos

#define DAC_DHR12R1_DACC1DHRB_Pos (16U)

Definition at line 2567 of file stm32g431xx.h.

◆ DAC_DHR12R2_DACC2DHR

#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk

DAC channel2 12-bit Right aligned data

Definition at line 2590 of file stm32g431xx.h.

◆ DAC_DHR12R2_DACC2DHR_Msk

#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)

0x00000FFF

Definition at line 2589 of file stm32g431xx.h.

◆ DAC_DHR12R2_DACC2DHR_Pos

#define DAC_DHR12R2_DACC2DHR_Pos (0U)

Definition at line 2588 of file stm32g431xx.h.

◆ DAC_DHR12R2_DACC2DHRB

#define DAC_DHR12R2_DACC2DHRB DAC_DHR12R2_DACC2DHRB_Msk

DAC channel2 12-bit Right-aligned data B

Definition at line 2593 of file stm32g431xx.h.

◆ DAC_DHR12R2_DACC2DHRB_Msk

#define DAC_DHR12R2_DACC2DHRB_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHRB_Pos)

0x0FFF0000

Definition at line 2592 of file stm32g431xx.h.

◆ DAC_DHR12R2_DACC2DHRB_Pos

#define DAC_DHR12R2_DACC2DHRB_Pos (16U)

Definition at line 2591 of file stm32g431xx.h.

◆ DAC_DHR12RD_DACC1DHR

#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk

DAC channel1 12-bit Right aligned data

Definition at line 2614 of file stm32g431xx.h.

◆ DAC_DHR12RD_DACC1DHR_Msk

#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)

0x00000FFF

Definition at line 2613 of file stm32g431xx.h.

◆ DAC_DHR12RD_DACC1DHR_Pos

#define DAC_DHR12RD_DACC1DHR_Pos (0U)

Definition at line 2612 of file stm32g431xx.h.

◆ DAC_DHR12RD_DACC2DHR

#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk

DAC channel2 12-bit Right aligned data

Definition at line 2617 of file stm32g431xx.h.

◆ DAC_DHR12RD_DACC2DHR_Msk

#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)

0x0FFF0000

Definition at line 2616 of file stm32g431xx.h.

◆ DAC_DHR12RD_DACC2DHR_Pos

#define DAC_DHR12RD_DACC2DHR_Pos (16U)

Definition at line 2615 of file stm32g431xx.h.

◆ DAC_DHR8R1_DACC1DHR

#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk

DAC channel1 8-bit Right aligned data

Definition at line 2582 of file stm32g431xx.h.

◆ DAC_DHR8R1_DACC1DHR_Msk

#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)

0x000000FF

Definition at line 2581 of file stm32g431xx.h.

◆ DAC_DHR8R1_DACC1DHR_Pos

#define DAC_DHR8R1_DACC1DHR_Pos (0U)

Definition at line 2580 of file stm32g431xx.h.

◆ DAC_DHR8R1_DACC1DHRB

#define DAC_DHR8R1_DACC1DHRB DAC_DHR8R1_DACC1DHRB_Msk

DAC channel1 8-bit Right aligned data B

Definition at line 2585 of file stm32g431xx.h.

◆ DAC_DHR8R1_DACC1DHRB_Msk

#define DAC_DHR8R1_DACC1DHRB_Msk (0xFFUL << DAC_DHR8R1_DACC1DHRB_Pos)

0x0000FF00

Definition at line 2584 of file stm32g431xx.h.

◆ DAC_DHR8R1_DACC1DHRB_Pos

#define DAC_DHR8R1_DACC1DHRB_Pos (8U)

Definition at line 2583 of file stm32g431xx.h.

◆ DAC_DHR8R2_DACC2DHR

#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk

DAC channel2 8-bit Right aligned data

Definition at line 2606 of file stm32g431xx.h.

◆ DAC_DHR8R2_DACC2DHR_Msk

#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)

0x000000FF

Definition at line 2605 of file stm32g431xx.h.

◆ DAC_DHR8R2_DACC2DHR_Pos

#define DAC_DHR8R2_DACC2DHR_Pos (0U)

Definition at line 2604 of file stm32g431xx.h.

◆ DAC_DHR8R2_DACC2DHRB

#define DAC_DHR8R2_DACC2DHRB DAC_DHR8R2_DACC2DHRB_Msk

DAC channel2 8-bit Right aligned data B

Definition at line 2609 of file stm32g431xx.h.

◆ DAC_DHR8R2_DACC2DHRB_Msk

#define DAC_DHR8R2_DACC2DHRB_Msk (0xFFUL << DAC_DHR8R2_DACC2DHRB_Pos)

0x0000FF00

Definition at line 2608 of file stm32g431xx.h.

◆ DAC_DHR8R2_DACC2DHRB_Pos

#define DAC_DHR8R2_DACC2DHRB_Pos (8U)

Definition at line 2607 of file stm32g431xx.h.

◆ DAC_DHR8RD_DACC1DHR

#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk

DAC channel1 8-bit Right aligned data

Definition at line 2630 of file stm32g431xx.h.

◆ DAC_DHR8RD_DACC1DHR_Msk

#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)

0x000000FF

Definition at line 2629 of file stm32g431xx.h.

◆ DAC_DHR8RD_DACC1DHR_Pos

#define DAC_DHR8RD_DACC1DHR_Pos (0U)

Definition at line 2628 of file stm32g431xx.h.

◆ DAC_DHR8RD_DACC2DHR

#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk

DAC channel2 8-bit Right aligned data

Definition at line 2633 of file stm32g431xx.h.

◆ DAC_DHR8RD_DACC2DHR_Msk

#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)

0x0000FF00

Definition at line 2632 of file stm32g431xx.h.

◆ DAC_DHR8RD_DACC2DHR_Pos

#define DAC_DHR8RD_DACC2DHR_Pos (8U)

Definition at line 2631 of file stm32g431xx.h.

◆ DAC_DOR1_DACC1DOR

#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk

DAC channel1 data output

Definition at line 2638 of file stm32g431xx.h.

◆ DAC_DOR1_DACC1DOR_Msk

#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)

0x00000FFF

Definition at line 2637 of file stm32g431xx.h.

◆ DAC_DOR1_DACC1DOR_Pos

#define DAC_DOR1_DACC1DOR_Pos (0U)

Definition at line 2636 of file stm32g431xx.h.

◆ DAC_DOR1_DACC1DORB

#define DAC_DOR1_DACC1DORB DAC_DOR1_DACC1DORB_Msk

DAC channel1 data output B

Definition at line 2641 of file stm32g431xx.h.

◆ DAC_DOR1_DACC1DORB_Msk

#define DAC_DOR1_DACC1DORB_Msk (0xFFFUL << DAC_DOR1_DACC1DORB_Pos)

0x0FFF0000

Definition at line 2640 of file stm32g431xx.h.

◆ DAC_DOR1_DACC1DORB_Pos

#define DAC_DOR1_DACC1DORB_Pos (16U)

Definition at line 2639 of file stm32g431xx.h.

◆ DAC_DOR2_DACC2DOR

#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk

DAC channel2 data output

Definition at line 2646 of file stm32g431xx.h.

◆ DAC_DOR2_DACC2DOR_Msk

#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)

0x00000FFF

Definition at line 2645 of file stm32g431xx.h.

◆ DAC_DOR2_DACC2DOR_Pos

#define DAC_DOR2_DACC2DOR_Pos (0U)

Definition at line 2644 of file stm32g431xx.h.

◆ DAC_DOR2_DACC2DORB

#define DAC_DOR2_DACC2DORB DAC_DOR2_DACC2DORB_Msk

DAC channel2 data output B

Definition at line 2649 of file stm32g431xx.h.

◆ DAC_DOR2_DACC2DORB_Msk

#define DAC_DOR2_DACC2DORB_Msk (0xFFFUL << DAC_DOR2_DACC2DORB_Pos)

0x0FFF0000

Definition at line 2648 of file stm32g431xx.h.

◆ DAC_DOR2_DACC2DORB_Pos

#define DAC_DOR2_DACC2DORB_Pos (16U)

Definition at line 2647 of file stm32g431xx.h.

◆ DAC_MCR_DMADOUBLE1

#define DAC_MCR_DMADOUBLE1 DAC_MCR_DMADOUBLE1_Msk

DAC Channel 1 DMA double data mode

Definition at line 2702 of file stm32g431xx.h.

◆ DAC_MCR_DMADOUBLE1_Msk

#define DAC_MCR_DMADOUBLE1_Msk (0x1UL << DAC_MCR_DMADOUBLE1_Pos)

0x00000100

Definition at line 2701 of file stm32g431xx.h.

◆ DAC_MCR_DMADOUBLE1_Pos

#define DAC_MCR_DMADOUBLE1_Pos (8U)

Definition at line 2700 of file stm32g431xx.h.

◆ DAC_MCR_DMADOUBLE2

#define DAC_MCR_DMADOUBLE2 DAC_MCR_DMADOUBLE2_Msk

DAC Channel 2 DMA double data mode

Definition at line 2723 of file stm32g431xx.h.

◆ DAC_MCR_DMADOUBLE2_Msk

#define DAC_MCR_DMADOUBLE2_Msk (0x1UL << DAC_MCR_DMADOUBLE2_Pos)

0x01000000

Definition at line 2722 of file stm32g431xx.h.

◆ DAC_MCR_DMADOUBLE2_Pos

#define DAC_MCR_DMADOUBLE2_Pos (24U)

Definition at line 2721 of file stm32g431xx.h.

◆ DAC_MCR_HFSEL

#define DAC_MCR_HFSEL DAC_MCR_HFSEL_Msk

HFSEL[1:0] (High Frequency interface mode selection)

Definition at line 2710 of file stm32g431xx.h.

◆ DAC_MCR_HFSEL_0

#define DAC_MCR_HFSEL_0 (0x1UL << DAC_MCR_HFSEL_Pos)

0x00004000

Definition at line 2711 of file stm32g431xx.h.

◆ DAC_MCR_HFSEL_1

#define DAC_MCR_HFSEL_1 (0x2UL << DAC_MCR_HFSEL_Pos)

0x00008000

Definition at line 2712 of file stm32g431xx.h.

◆ DAC_MCR_HFSEL_Msk

#define DAC_MCR_HFSEL_Msk (0x3UL << DAC_MCR_HFSEL_Pos)

0x0000C000

Definition at line 2709 of file stm32g431xx.h.

◆ DAC_MCR_HFSEL_Pos

#define DAC_MCR_HFSEL_Pos (14U)

Definition at line 2708 of file stm32g431xx.h.

◆ DAC_MCR_MODE1

#define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk

MODE1[2:0] (DAC channel1 mode)

Definition at line 2695 of file stm32g431xx.h.

◆ DAC_MCR_MODE1_0

#define DAC_MCR_MODE1_0 (0x1UL << DAC_MCR_MODE1_Pos)

0x00000001

Definition at line 2696 of file stm32g431xx.h.

◆ DAC_MCR_MODE1_1

#define DAC_MCR_MODE1_1 (0x2UL << DAC_MCR_MODE1_Pos)

0x00000002

Definition at line 2697 of file stm32g431xx.h.

◆ DAC_MCR_MODE1_2

#define DAC_MCR_MODE1_2 (0x4UL << DAC_MCR_MODE1_Pos)

0x00000004

Definition at line 2698 of file stm32g431xx.h.

◆ DAC_MCR_MODE1_Msk

#define DAC_MCR_MODE1_Msk (0x7UL << DAC_MCR_MODE1_Pos)

0x00000007

Definition at line 2694 of file stm32g431xx.h.

◆ DAC_MCR_MODE1_Pos

#define DAC_MCR_MODE1_Pos (0U)

Definition at line 2693 of file stm32g431xx.h.

◆ DAC_MCR_MODE2

#define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk

MODE2[2:0] (DAC channel2 mode)

Definition at line 2716 of file stm32g431xx.h.

◆ DAC_MCR_MODE2_0

#define DAC_MCR_MODE2_0 (0x1UL << DAC_MCR_MODE2_Pos)

0x00010000

Definition at line 2717 of file stm32g431xx.h.

◆ DAC_MCR_MODE2_1

#define DAC_MCR_MODE2_1 (0x2UL << DAC_MCR_MODE2_Pos)

0x00020000

Definition at line 2718 of file stm32g431xx.h.

◆ DAC_MCR_MODE2_2

#define DAC_MCR_MODE2_2 (0x4UL << DAC_MCR_MODE2_Pos)

0x00040000

Definition at line 2719 of file stm32g431xx.h.

◆ DAC_MCR_MODE2_Msk

#define DAC_MCR_MODE2_Msk (0x7UL << DAC_MCR_MODE2_Pos)

0x00070000

Definition at line 2715 of file stm32g431xx.h.

◆ DAC_MCR_MODE2_Pos

#define DAC_MCR_MODE2_Pos (16U)

Definition at line 2714 of file stm32g431xx.h.

◆ DAC_MCR_SINFORMAT1

#define DAC_MCR_SINFORMAT1 DAC_MCR_SINFORMAT1_Msk

DAC Channel 1 enable signed format

Definition at line 2706 of file stm32g431xx.h.

◆ DAC_MCR_SINFORMAT1_Msk

#define DAC_MCR_SINFORMAT1_Msk (0x1UL << DAC_MCR_SINFORMAT1_Pos)

0x00000200

Definition at line 2705 of file stm32g431xx.h.

◆ DAC_MCR_SINFORMAT1_Pos

#define DAC_MCR_SINFORMAT1_Pos (9U)

Definition at line 2704 of file stm32g431xx.h.

◆ DAC_MCR_SINFORMAT2

#define DAC_MCR_SINFORMAT2 DAC_MCR_SINFORMAT2_Msk

DAC Channel 2 enable signed format

Definition at line 2727 of file stm32g431xx.h.

◆ DAC_MCR_SINFORMAT2_Msk

#define DAC_MCR_SINFORMAT2_Msk (0x1UL << DAC_MCR_SINFORMAT2_Pos)

0x02000000

Definition at line 2726 of file stm32g431xx.h.

◆ DAC_MCR_SINFORMAT2_Pos

#define DAC_MCR_SINFORMAT2_Pos (25U)

Definition at line 2725 of file stm32g431xx.h.

◆ DAC_SHHR_THOLD1

#define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk

DAC channel1 hold time

Definition at line 2742 of file stm32g431xx.h.

◆ DAC_SHHR_THOLD1_Msk

#define DAC_SHHR_THOLD1_Msk (0x3FFUL << DAC_SHHR_THOLD1_Pos)

0x000003FF

Definition at line 2741 of file stm32g431xx.h.

◆ DAC_SHHR_THOLD1_Pos

#define DAC_SHHR_THOLD1_Pos (0U)

Definition at line 2740 of file stm32g431xx.h.

◆ DAC_SHHR_THOLD2

#define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk

DAC channel2 hold time

Definition at line 2745 of file stm32g431xx.h.

◆ DAC_SHHR_THOLD2_Msk

#define DAC_SHHR_THOLD2_Msk (0x3FFUL << DAC_SHHR_THOLD2_Pos)

0x03FF0000

Definition at line 2744 of file stm32g431xx.h.

◆ DAC_SHHR_THOLD2_Pos

#define DAC_SHHR_THOLD2_Pos (16U)

Definition at line 2743 of file stm32g431xx.h.

◆ DAC_SHRR_TREFRESH1

#define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk

DAC channel1 refresh time

Definition at line 2750 of file stm32g431xx.h.

◆ DAC_SHRR_TREFRESH1_Msk

#define DAC_SHRR_TREFRESH1_Msk (0xFFUL << DAC_SHRR_TREFRESH1_Pos)

0x000000FF

Definition at line 2749 of file stm32g431xx.h.

◆ DAC_SHRR_TREFRESH1_Pos

#define DAC_SHRR_TREFRESH1_Pos (0U)

Definition at line 2748 of file stm32g431xx.h.

◆ DAC_SHRR_TREFRESH2

#define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk

DAC channel2 refresh time

Definition at line 2753 of file stm32g431xx.h.

◆ DAC_SHRR_TREFRESH2_Msk

#define DAC_SHRR_TREFRESH2_Msk (0xFFUL << DAC_SHRR_TREFRESH2_Pos)

0x00FF0000

Definition at line 2752 of file stm32g431xx.h.

◆ DAC_SHRR_TREFRESH2_Pos

#define DAC_SHRR_TREFRESH2_Pos (16U)

Definition at line 2751 of file stm32g431xx.h.

◆ DAC_SHSR1_TSAMPLE1

#define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk

DAC channel1 sample time

Definition at line 2732 of file stm32g431xx.h.

◆ DAC_SHSR1_TSAMPLE1_Msk

#define DAC_SHSR1_TSAMPLE1_Msk (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)

0x000003FF

Definition at line 2731 of file stm32g431xx.h.

◆ DAC_SHSR1_TSAMPLE1_Pos

#define DAC_SHSR1_TSAMPLE1_Pos (0U)

Definition at line 2730 of file stm32g431xx.h.

◆ DAC_SHSR2_TSAMPLE2

#define DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk

DAC channel2 sample time

Definition at line 2737 of file stm32g431xx.h.

◆ DAC_SHSR2_TSAMPLE2_Msk

#define DAC_SHSR2_TSAMPLE2_Msk (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)

0x000003FF

Definition at line 2736 of file stm32g431xx.h.

◆ DAC_SHSR2_TSAMPLE2_Pos

#define DAC_SHSR2_TSAMPLE2_Pos (0U)

Definition at line 2735 of file stm32g431xx.h.

◆ DAC_SR_BWST1

#define DAC_SR_BWST1 DAC_SR_BWST1_Msk

DAC channel1 busy writing sample time flag

Definition at line 2666 of file stm32g431xx.h.

◆ DAC_SR_BWST1_Msk

#define DAC_SR_BWST1_Msk (0x1UL << DAC_SR_BWST1_Pos)

0x00008000

Definition at line 2665 of file stm32g431xx.h.

◆ DAC_SR_BWST1_Pos

#define DAC_SR_BWST1_Pos (15U)

Definition at line 2664 of file stm32g431xx.h.

◆ DAC_SR_BWST2

#define DAC_SR_BWST2 DAC_SR_BWST2_Msk

DAC channel2 busy writing sample time flag

Definition at line 2682 of file stm32g431xx.h.

◆ DAC_SR_BWST2_Msk

#define DAC_SR_BWST2_Msk (0x1UL << DAC_SR_BWST2_Pos)

0x80000000

Definition at line 2681 of file stm32g431xx.h.

◆ DAC_SR_BWST2_Pos

#define DAC_SR_BWST2_Pos (31U)

Definition at line 2680 of file stm32g431xx.h.

◆ DAC_SR_CAL_FLAG1

#define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk

DAC channel1 calibration offset status

Definition at line 2663 of file stm32g431xx.h.

◆ DAC_SR_CAL_FLAG1_Msk

#define DAC_SR_CAL_FLAG1_Msk (0x1UL << DAC_SR_CAL_FLAG1_Pos)

0x00004000

Definition at line 2662 of file stm32g431xx.h.

◆ DAC_SR_CAL_FLAG1_Pos

#define DAC_SR_CAL_FLAG1_Pos (14U)

Definition at line 2661 of file stm32g431xx.h.

◆ DAC_SR_CAL_FLAG2

#define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk

DAC channel2 calibration offset status

Definition at line 2679 of file stm32g431xx.h.

◆ DAC_SR_CAL_FLAG2_Msk

#define DAC_SR_CAL_FLAG2_Msk (0x1UL << DAC_SR_CAL_FLAG2_Pos)

0x40000000

Definition at line 2678 of file stm32g431xx.h.

◆ DAC_SR_CAL_FLAG2_Pos

#define DAC_SR_CAL_FLAG2_Pos (30U)

Definition at line 2677 of file stm32g431xx.h.

◆ DAC_SR_DAC1RDY

#define DAC_SR_DAC1RDY DAC_SR_DAC1RDY_Msk

DAC channel 1 ready status bit

Definition at line 2654 of file stm32g431xx.h.

◆ DAC_SR_DAC1RDY_Msk

#define DAC_SR_DAC1RDY_Msk (0x1UL << DAC_SR_DAC1RDY_Pos)

0x00000800

Definition at line 2653 of file stm32g431xx.h.

◆ DAC_SR_DAC1RDY_Pos

#define DAC_SR_DAC1RDY_Pos (11U)

Definition at line 2652 of file stm32g431xx.h.

◆ DAC_SR_DAC2RDY

#define DAC_SR_DAC2RDY DAC_SR_DAC2RDY_Msk

DAC channel 2 ready status bit

Definition at line 2670 of file stm32g431xx.h.

◆ DAC_SR_DAC2RDY_Msk

#define DAC_SR_DAC2RDY_Msk (0x1UL << DAC_SR_DAC2RDY_Pos)

0x08000000

Definition at line 2669 of file stm32g431xx.h.

◆ DAC_SR_DAC2RDY_Pos

#define DAC_SR_DAC2RDY_Pos (27U)

Definition at line 2668 of file stm32g431xx.h.

◆ DAC_SR_DMAUDR1

#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk

DAC channel1 DMA underrun flag

Definition at line 2660 of file stm32g431xx.h.

◆ DAC_SR_DMAUDR1_Msk

#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos)

0x00002000

Definition at line 2659 of file stm32g431xx.h.

◆ DAC_SR_DMAUDR1_Pos

#define DAC_SR_DMAUDR1_Pos (13U)

Definition at line 2658 of file stm32g431xx.h.

◆ DAC_SR_DMAUDR2

#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk

DAC channel2 DMA underrun flag

Definition at line 2676 of file stm32g431xx.h.

◆ DAC_SR_DMAUDR2_Msk

#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos)

0x20000000

Definition at line 2675 of file stm32g431xx.h.

◆ DAC_SR_DMAUDR2_Pos

#define DAC_SR_DMAUDR2_Pos (29U)

Definition at line 2674 of file stm32g431xx.h.

◆ DAC_SR_DORSTAT1

#define DAC_SR_DORSTAT1 DAC_SR_DORSTAT1_Msk

DAC channel 1 output register status bit

Definition at line 2657 of file stm32g431xx.h.

◆ DAC_SR_DORSTAT1_Msk

#define DAC_SR_DORSTAT1_Msk (0x1UL << DAC_SR_DORSTAT1_Pos)

0x00001000

Definition at line 2656 of file stm32g431xx.h.

◆ DAC_SR_DORSTAT1_Pos

#define DAC_SR_DORSTAT1_Pos (12U)

Definition at line 2655 of file stm32g431xx.h.

◆ DAC_SR_DORSTAT2

#define DAC_SR_DORSTAT2 DAC_SR_DORSTAT2_Msk

DAC channel 2 output register status bit

Definition at line 2673 of file stm32g431xx.h.

◆ DAC_SR_DORSTAT2_Msk

#define DAC_SR_DORSTAT2_Msk (0x1UL << DAC_SR_DORSTAT2_Pos)

0x10000000

Definition at line 2672 of file stm32g431xx.h.

◆ DAC_SR_DORSTAT2_Pos

#define DAC_SR_DORSTAT2_Pos (28U)

Definition at line 2671 of file stm32g431xx.h.

◆ DAC_STMODR_STINCTRIGSEL1

#define DAC_STMODR_STINCTRIGSEL1 DAC_STMODR_STINCTRIGSEL1_Msk

STINCTRIGSEL1[3:0] (DAC Channel 1 Sawtooth Increment trigger selection)

Definition at line 2790 of file stm32g431xx.h.

◆ DAC_STMODR_STINCTRIGSEL1_0

#define DAC_STMODR_STINCTRIGSEL1_0 (0x1UL << DAC_STMODR_STINCTRIGSEL1_Pos)

0x00000001

Definition at line 2791 of file stm32g431xx.h.

◆ DAC_STMODR_STINCTRIGSEL1_1

#define DAC_STMODR_STINCTRIGSEL1_1 (0x2UL << DAC_STMODR_STINCTRIGSEL1_Pos)

0x00000002

Definition at line 2792 of file stm32g431xx.h.

◆ DAC_STMODR_STINCTRIGSEL1_2

#define DAC_STMODR_STINCTRIGSEL1_2 (0x4UL << DAC_STMODR_STINCTRIGSEL1_Pos)

0x00000004

Definition at line 2793 of file stm32g431xx.h.

◆ DAC_STMODR_STINCTRIGSEL1_3

#define DAC_STMODR_STINCTRIGSEL1_3 (0x8UL << DAC_STMODR_STINCTRIGSEL1_Pos)

0x00000008

Definition at line 2794 of file stm32g431xx.h.

◆ DAC_STMODR_STINCTRIGSEL1_Msk

#define DAC_STMODR_STINCTRIGSEL1_Msk (0xFUL << DAC_STMODR_STINCTRIGSEL1_Pos)

0x0000000F

Definition at line 2789 of file stm32g431xx.h.

◆ DAC_STMODR_STINCTRIGSEL1_Pos

#define DAC_STMODR_STINCTRIGSEL1_Pos (8U)

Definition at line 2788 of file stm32g431xx.h.

◆ DAC_STMODR_STINCTRIGSEL2

#define DAC_STMODR_STINCTRIGSEL2 DAC_STMODR_STINCTRIGSEL2_Msk

STINCTRIGSEL2[3:0] (DAC Channel 2 Sawtooth Increment trigger selection)

Definition at line 2806 of file stm32g431xx.h.

◆ DAC_STMODR_STINCTRIGSEL2_0

#define DAC_STMODR_STINCTRIGSEL2_0 (0x1UL << DAC_STMODR_STINCTRIGSEL2_Pos)

0x00000001

Definition at line 2807 of file stm32g431xx.h.

◆ DAC_STMODR_STINCTRIGSEL2_1

#define DAC_STMODR_STINCTRIGSEL2_1 (0x2UL << DAC_STMODR_STINCTRIGSEL2_Pos)

0x00000002

Definition at line 2808 of file stm32g431xx.h.

◆ DAC_STMODR_STINCTRIGSEL2_2

#define DAC_STMODR_STINCTRIGSEL2_2 (0x4UL << DAC_STMODR_STINCTRIGSEL2_Pos)

0x00000004

Definition at line 2809 of file stm32g431xx.h.

◆ DAC_STMODR_STINCTRIGSEL2_3

#define DAC_STMODR_STINCTRIGSEL2_3 (0x8UL << DAC_STMODR_STINCTRIGSEL2_Pos)

0x00000008

Definition at line 2810 of file stm32g431xx.h.

◆ DAC_STMODR_STINCTRIGSEL2_Msk

#define DAC_STMODR_STINCTRIGSEL2_Msk (0xFUL << DAC_STMODR_STINCTRIGSEL2_Pos)

0x0000000F

Definition at line 2805 of file stm32g431xx.h.

◆ DAC_STMODR_STINCTRIGSEL2_Pos

#define DAC_STMODR_STINCTRIGSEL2_Pos (24U)

Definition at line 2804 of file stm32g431xx.h.

◆ DAC_STMODR_STRSTTRIGSEL1

#define DAC_STMODR_STRSTTRIGSEL1 DAC_STMODR_STRSTTRIGSEL1_Msk

STRSTTRIGSEL1[3:0] (DAC Channel 1 Sawtooth Increment trigger selection)

Definition at line 2782 of file stm32g431xx.h.

◆ DAC_STMODR_STRSTTRIGSEL1_0

#define DAC_STMODR_STRSTTRIGSEL1_0 (0x1UL << DAC_STMODR_STRSTTRIGSEL1_Pos)

0x00000001

Definition at line 2783 of file stm32g431xx.h.

◆ DAC_STMODR_STRSTTRIGSEL1_1

#define DAC_STMODR_STRSTTRIGSEL1_1 (0x2UL << DAC_STMODR_STRSTTRIGSEL1_Pos)

0x00000002

Definition at line 2784 of file stm32g431xx.h.

◆ DAC_STMODR_STRSTTRIGSEL1_2

#define DAC_STMODR_STRSTTRIGSEL1_2 (0x4UL << DAC_STMODR_STRSTTRIGSEL1_Pos)

0x00000004

Definition at line 2785 of file stm32g431xx.h.

◆ DAC_STMODR_STRSTTRIGSEL1_3

#define DAC_STMODR_STRSTTRIGSEL1_3 (0x8UL << DAC_STMODR_STRSTTRIGSEL1_Pos)

0x00000008

Definition at line 2786 of file stm32g431xx.h.

◆ DAC_STMODR_STRSTTRIGSEL1_Msk

#define DAC_STMODR_STRSTTRIGSEL1_Msk (0xFUL << DAC_STMODR_STRSTTRIGSEL1_Pos)

0x0000000F

Definition at line 2781 of file stm32g431xx.h.

◆ DAC_STMODR_STRSTTRIGSEL1_Pos

#define DAC_STMODR_STRSTTRIGSEL1_Pos (0U)

Definition at line 2780 of file stm32g431xx.h.

◆ DAC_STMODR_STRSTTRIGSEL2

#define DAC_STMODR_STRSTTRIGSEL2 DAC_STMODR_STRSTTRIGSEL2_Msk

STRSTTRIGSEL2[3:0] (DAC Channel 2 Sawtooth Increment trigger selection)

Definition at line 2798 of file stm32g431xx.h.

◆ DAC_STMODR_STRSTTRIGSEL2_0

#define DAC_STMODR_STRSTTRIGSEL2_0 (0x1UL << DAC_STMODR_STRSTTRIGSEL2_Pos)

0x00000001

Definition at line 2799 of file stm32g431xx.h.

◆ DAC_STMODR_STRSTTRIGSEL2_1

#define DAC_STMODR_STRSTTRIGSEL2_1 (0x2UL << DAC_STMODR_STRSTTRIGSEL2_Pos)

0x00000002

Definition at line 2800 of file stm32g431xx.h.

◆ DAC_STMODR_STRSTTRIGSEL2_2

#define DAC_STMODR_STRSTTRIGSEL2_2 (0x4UL << DAC_STMODR_STRSTTRIGSEL2_Pos)

0x00000004

Definition at line 2801 of file stm32g431xx.h.

◆ DAC_STMODR_STRSTTRIGSEL2_3

#define DAC_STMODR_STRSTTRIGSEL2_3 (0x8UL << DAC_STMODR_STRSTTRIGSEL2_Pos)

0x00000008

Definition at line 2802 of file stm32g431xx.h.

◆ DAC_STMODR_STRSTTRIGSEL2_Msk

#define DAC_STMODR_STRSTTRIGSEL2_Msk (0xFUL << DAC_STMODR_STRSTTRIGSEL2_Pos)

0x0000000F

Definition at line 2797 of file stm32g431xx.h.

◆ DAC_STMODR_STRSTTRIGSEL2_Pos

#define DAC_STMODR_STRSTTRIGSEL2_Pos (16U)

Definition at line 2796 of file stm32g431xx.h.

◆ DAC_STR1_STDIR1

#define DAC_STR1_STDIR1 DAC_STR1_STDIR1_Msk

DAC Channel 1 Sawtooth direction setting

Definition at line 2761 of file stm32g431xx.h.

◆ DAC_STR1_STDIR1_Msk

#define DAC_STR1_STDIR1_Msk (0x1UL << DAC_STR1_STDIR1_Pos)

0x00001000

Definition at line 2760 of file stm32g431xx.h.

◆ DAC_STR1_STDIR1_Pos

#define DAC_STR1_STDIR1_Pos (12U)

Definition at line 2759 of file stm32g431xx.h.

◆ DAC_STR1_STINCDATA1

#define DAC_STR1_STINCDATA1 DAC_STR1_STINCDATA1_Msk

DAC Channel 1 Sawtooth increment value (12.4 bit format)

Definition at line 2765 of file stm32g431xx.h.

◆ DAC_STR1_STINCDATA1_Msk

#define DAC_STR1_STINCDATA1_Msk (0xFFFFUL << DAC_STR1_STINCDATA1_Pos)

0xFFFF0000

Definition at line 2764 of file stm32g431xx.h.

◆ DAC_STR1_STINCDATA1_Pos

#define DAC_STR1_STINCDATA1_Pos (16U)

Definition at line 2763 of file stm32g431xx.h.

◆ DAC_STR1_STRSTDATA1

#define DAC_STR1_STRSTDATA1 DAC_STR1_STRSTDATA1_Msk

DAC Channel 1 Sawtooth starting value

Definition at line 2758 of file stm32g431xx.h.

◆ DAC_STR1_STRSTDATA1_Msk

#define DAC_STR1_STRSTDATA1_Msk (0xFFFUL << DAC_STR1_STRSTDATA1_Pos)

0x00000FFF

Definition at line 2757 of file stm32g431xx.h.

◆ DAC_STR1_STRSTDATA1_Pos

#define DAC_STR1_STRSTDATA1_Pos (0U)

Definition at line 2756 of file stm32g431xx.h.

◆ DAC_STR2_STDIR2

#define DAC_STR2_STDIR2 DAC_STR2_STDIR2_Msk

DAC Channel 2 Sawtooth direction setting

Definition at line 2773 of file stm32g431xx.h.

◆ DAC_STR2_STDIR2_Msk

#define DAC_STR2_STDIR2_Msk (0x1UL << DAC_STR2_STDIR2_Pos)

0x00001000

Definition at line 2772 of file stm32g431xx.h.

◆ DAC_STR2_STDIR2_Pos

#define DAC_STR2_STDIR2_Pos (12U)

Definition at line 2771 of file stm32g431xx.h.

◆ DAC_STR2_STINCDATA2

#define DAC_STR2_STINCDATA2 DAC_STR2_STINCDATA2_Msk

DAC Channel 2 Sawtooth increment value (12.4 bit format)

Definition at line 2777 of file stm32g431xx.h.

◆ DAC_STR2_STINCDATA2_Msk

#define DAC_STR2_STINCDATA2_Msk (0xFFFFUL << DAC_STR2_STINCDATA2_Pos)

0xFFFF0000

Definition at line 2776 of file stm32g431xx.h.

◆ DAC_STR2_STINCDATA2_Pos

#define DAC_STR2_STINCDATA2_Pos (16U)

Definition at line 2775 of file stm32g431xx.h.

◆ DAC_STR2_STRSTDATA2

#define DAC_STR2_STRSTDATA2 DAC_STR2_STRSTDATA2_Msk

DAC Channel 2 Sawtooth starting value

Definition at line 2770 of file stm32g431xx.h.

◆ DAC_STR2_STRSTDATA2_Msk

#define DAC_STR2_STRSTDATA2_Msk (0xFFFUL << DAC_STR2_STRSTDATA2_Pos)

0x00000FFF

Definition at line 2769 of file stm32g431xx.h.

◆ DAC_STR2_STRSTDATA2_Pos

#define DAC_STR2_STRSTDATA2_Pos (0U)

Definition at line 2768 of file stm32g431xx.h.

◆ DAC_SWTRIGR_SWTRIG1

#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk

DAC channel1 software trigger

Definition at line 2552 of file stm32g431xx.h.

◆ DAC_SWTRIGR_SWTRIG1_Msk

#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)

0x00000001

Definition at line 2551 of file stm32g431xx.h.

◆ DAC_SWTRIGR_SWTRIG1_Pos

#define DAC_SWTRIGR_SWTRIG1_Pos (0U)

Definition at line 2550 of file stm32g431xx.h.

◆ DAC_SWTRIGR_SWTRIG2

#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk

DAC channel2 software trigger

Definition at line 2555 of file stm32g431xx.h.

◆ DAC_SWTRIGR_SWTRIG2_Msk

#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)

0x00000002

Definition at line 2554 of file stm32g431xx.h.

◆ DAC_SWTRIGR_SWTRIG2_Pos

#define DAC_SWTRIGR_SWTRIG2_Pos (1U)

Definition at line 2553 of file stm32g431xx.h.

◆ DAC_SWTRIGR_SWTRIGB1

#define DAC_SWTRIGR_SWTRIGB1 DAC_SWTRIGR_SWTRIGB1_Msk

DAC channel1 software trigger B

Definition at line 2558 of file stm32g431xx.h.

◆ DAC_SWTRIGR_SWTRIGB1_Msk

#define DAC_SWTRIGR_SWTRIGB1_Msk (0x1UL << DAC_SWTRIGR_SWTRIGB1_Pos)

0x00010000

Definition at line 2557 of file stm32g431xx.h.

◆ DAC_SWTRIGR_SWTRIGB1_Pos

#define DAC_SWTRIGR_SWTRIGB1_Pos (16U)

Definition at line 2556 of file stm32g431xx.h.

◆ DAC_SWTRIGR_SWTRIGB2

#define DAC_SWTRIGR_SWTRIGB2 DAC_SWTRIGR_SWTRIGB2_Msk

DAC channel2 software trigger B

Definition at line 2561 of file stm32g431xx.h.

◆ DAC_SWTRIGR_SWTRIGB2_Msk

#define DAC_SWTRIGR_SWTRIGB2_Msk (0x1UL << DAC_SWTRIGR_SWTRIGB2_Pos)

0x00020000

Definition at line 2560 of file stm32g431xx.h.

◆ DAC_SWTRIGR_SWTRIGB2_Pos

#define DAC_SWTRIGR_SWTRIGB2_Pos (17U)

Definition at line 2559 of file stm32g431xx.h.

◆ DBGMCU_APB1FZR1_DBG_I2C1_STOP

#define DBGMCU_APB1FZR1_DBG_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk

Definition at line 2872 of file stm32g431xx.h.

◆ DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk

#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos)

0x00200000

Definition at line 2871 of file stm32g431xx.h.

◆ DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos

#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos (21U)

Definition at line 2870 of file stm32g431xx.h.

◆ DBGMCU_APB1FZR1_DBG_I2C2_STOP

#define DBGMCU_APB1FZR1_DBG_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk

Definition at line 2875 of file stm32g431xx.h.

◆ DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk

#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos)

0x00400000

Definition at line 2874 of file stm32g431xx.h.

◆ DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos

#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos (22U)

Definition at line 2873 of file stm32g431xx.h.

◆ DBGMCU_APB1FZR1_DBG_I2C3_STOP

#define DBGMCU_APB1FZR1_DBG_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk

Definition at line 2878 of file stm32g431xx.h.

◆ DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk

#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos)

0x40000000

Definition at line 2877 of file stm32g431xx.h.

◆ DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos

#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos (30U)

Definition at line 2876 of file stm32g431xx.h.

◆ DBGMCU_APB1FZR1_DBG_IWDG_STOP

#define DBGMCU_APB1FZR1_DBG_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk

Definition at line 2869 of file stm32g431xx.h.

◆ DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk

#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos)

0x00001000

Definition at line 2868 of file stm32g431xx.h.

◆ DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos

#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos (12U)

Definition at line 2867 of file stm32g431xx.h.

◆ DBGMCU_APB1FZR1_DBG_LPTIM1_STOP

#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk

Definition at line 2881 of file stm32g431xx.h.

◆ DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk

#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos)

0x80000000

Definition at line 2880 of file stm32g431xx.h.

◆ DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos

#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos (31U)

Definition at line 2879 of file stm32g431xx.h.

◆ DBGMCU_APB1FZR1_DBG_RTC_STOP

#define DBGMCU_APB1FZR1_DBG_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk

Definition at line 2863 of file stm32g431xx.h.

◆ DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk

#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos)

0x00000400

Definition at line 2862 of file stm32g431xx.h.

◆ DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos

#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos (10U)

Definition at line 2861 of file stm32g431xx.h.

◆ DBGMCU_APB1FZR1_DBG_TIM2_STOP

#define DBGMCU_APB1FZR1_DBG_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk

Definition at line 2848 of file stm32g431xx.h.

◆ DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk

#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos)

0x00000001

Definition at line 2847 of file stm32g431xx.h.

◆ DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos

#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U)

Definition at line 2846 of file stm32g431xx.h.

◆ DBGMCU_APB1FZR1_DBG_TIM3_STOP

#define DBGMCU_APB1FZR1_DBG_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk

Definition at line 2851 of file stm32g431xx.h.

◆ DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk

#define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos)

0x00000002

Definition at line 2850 of file stm32g431xx.h.

◆ DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos

#define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos (1U)

Definition at line 2849 of file stm32g431xx.h.

◆ DBGMCU_APB1FZR1_DBG_TIM4_STOP

#define DBGMCU_APB1FZR1_DBG_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk

Definition at line 2854 of file stm32g431xx.h.

◆ DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk

#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos)

0x00000004

Definition at line 2853 of file stm32g431xx.h.

◆ DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos

#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos (2U)

Definition at line 2852 of file stm32g431xx.h.

◆ DBGMCU_APB1FZR1_DBG_TIM6_STOP

#define DBGMCU_APB1FZR1_DBG_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk

Definition at line 2857 of file stm32g431xx.h.

◆ DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk

#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos)

0x00000010

Definition at line 2856 of file stm32g431xx.h.

◆ DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos

#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos (4U)

Definition at line 2855 of file stm32g431xx.h.

◆ DBGMCU_APB1FZR1_DBG_TIM7_STOP

#define DBGMCU_APB1FZR1_DBG_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk

Definition at line 2860 of file stm32g431xx.h.

◆ DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk

#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos)

0x00000020

Definition at line 2859 of file stm32g431xx.h.

◆ DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos

#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos (5U)

Definition at line 2858 of file stm32g431xx.h.

◆ DBGMCU_APB1FZR1_DBG_WWDG_STOP

#define DBGMCU_APB1FZR1_DBG_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk

Definition at line 2866 of file stm32g431xx.h.

◆ DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk

#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos)

0x00000800

Definition at line 2865 of file stm32g431xx.h.

◆ DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos

#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos (11U)

Definition at line 2864 of file stm32g431xx.h.

◆ DBGMCU_APB2FZ_DBG_TIM15_STOP

#define DBGMCU_APB2FZ_DBG_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk

Definition at line 2893 of file stm32g431xx.h.

◆ DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk

#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos)

0x00010000

Definition at line 2892 of file stm32g431xx.h.

◆ DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos

#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos (16U)

Definition at line 2891 of file stm32g431xx.h.

◆ DBGMCU_APB2FZ_DBG_TIM16_STOP

#define DBGMCU_APB2FZ_DBG_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk

Definition at line 2896 of file stm32g431xx.h.

◆ DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk

#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos)

0x00020000

Definition at line 2895 of file stm32g431xx.h.

◆ DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos

#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos (17U)

Definition at line 2894 of file stm32g431xx.h.

◆ DBGMCU_APB2FZ_DBG_TIM17_STOP

#define DBGMCU_APB2FZ_DBG_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk

Definition at line 2899 of file stm32g431xx.h.

◆ DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk

#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos)

0x00040000

Definition at line 2898 of file stm32g431xx.h.

◆ DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos

#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos (18U)

Definition at line 2897 of file stm32g431xx.h.

◆ DBGMCU_APB2FZ_DBG_TIM1_STOP

#define DBGMCU_APB2FZ_DBG_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk

Definition at line 2887 of file stm32g431xx.h.

◆ DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk

#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos)

0x00000800

Definition at line 2886 of file stm32g431xx.h.

◆ DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos

#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos (11U)

Definition at line 2885 of file stm32g431xx.h.

◆ DBGMCU_APB2FZ_DBG_TIM8_STOP

#define DBGMCU_APB2FZ_DBG_TIM8_STOP DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk

Definition at line 2890 of file stm32g431xx.h.

◆ DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk

#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos)

0x00002000

Definition at line 2889 of file stm32g431xx.h.

◆ DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos

#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos (13U)

Definition at line 2888 of file stm32g431xx.h.

◆ DBGMCU_CR_DBG_SLEEP

#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk

Definition at line 2828 of file stm32g431xx.h.

◆ DBGMCU_CR_DBG_SLEEP_Msk

#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)

0x00000001

Definition at line 2827 of file stm32g431xx.h.

◆ DBGMCU_CR_DBG_SLEEP_Pos

#define DBGMCU_CR_DBG_SLEEP_Pos (0U)

Definition at line 2826 of file stm32g431xx.h.

◆ DBGMCU_CR_DBG_STANDBY

#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk

Definition at line 2834 of file stm32g431xx.h.

◆ DBGMCU_CR_DBG_STANDBY_Msk

#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)

0x00000004

Definition at line 2833 of file stm32g431xx.h.

◆ DBGMCU_CR_DBG_STANDBY_Pos

#define DBGMCU_CR_DBG_STANDBY_Pos (2U)

Definition at line 2832 of file stm32g431xx.h.

◆ DBGMCU_CR_DBG_STOP

#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk

Definition at line 2831 of file stm32g431xx.h.

◆ DBGMCU_CR_DBG_STOP_Msk

#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos)

0x00000002

Definition at line 2830 of file stm32g431xx.h.

◆ DBGMCU_CR_DBG_STOP_Pos

#define DBGMCU_CR_DBG_STOP_Pos (1U)

Definition at line 2829 of file stm32g431xx.h.

◆ DBGMCU_CR_TRACE_IOEN

#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk

Definition at line 2837 of file stm32g431xx.h.

◆ DBGMCU_CR_TRACE_IOEN_Msk

#define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)

0x00000020

Definition at line 2836 of file stm32g431xx.h.

◆ DBGMCU_CR_TRACE_IOEN_Pos

#define DBGMCU_CR_TRACE_IOEN_Pos (5U)

Definition at line 2835 of file stm32g431xx.h.

◆ DBGMCU_CR_TRACE_MODE

#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk

Definition at line 2841 of file stm32g431xx.h.

◆ DBGMCU_CR_TRACE_MODE_0

#define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)

0x00000040

Definition at line 2842 of file stm32g431xx.h.

◆ DBGMCU_CR_TRACE_MODE_1

#define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)

0x00000080

Definition at line 2843 of file stm32g431xx.h.

◆ DBGMCU_CR_TRACE_MODE_Msk

#define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)

0x000000C0

Definition at line 2840 of file stm32g431xx.h.

◆ DBGMCU_CR_TRACE_MODE_Pos

#define DBGMCU_CR_TRACE_MODE_Pos (6U)

Definition at line 2839 of file stm32g431xx.h.

◆ DBGMCU_IDCODE_DEV_ID

#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk

Definition at line 2820 of file stm32g431xx.h.

◆ DBGMCU_IDCODE_DEV_ID_Msk

#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)

0x00000FFF

Definition at line 2819 of file stm32g431xx.h.

◆ DBGMCU_IDCODE_DEV_ID_Pos

#define DBGMCU_IDCODE_DEV_ID_Pos (0U)

Definition at line 2818 of file stm32g431xx.h.

◆ DBGMCU_IDCODE_REV_ID

#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk

Definition at line 2823 of file stm32g431xx.h.

◆ DBGMCU_IDCODE_REV_ID_Msk

#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)

0xFFFF0000

Definition at line 2822 of file stm32g431xx.h.

◆ DBGMCU_IDCODE_REV_ID_Pos

#define DBGMCU_IDCODE_REV_ID_Pos (16U)

Definition at line 2821 of file stm32g431xx.h.

◆ DMA_CCR_CIRC

#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk

Circular mode

Definition at line 3073 of file stm32g431xx.h.

◆ DMA_CCR_CIRC_Msk

#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos)

0x00000020

Definition at line 3072 of file stm32g431xx.h.

◆ DMA_CCR_CIRC_Pos

#define DMA_CCR_CIRC_Pos (5U)

Definition at line 3071 of file stm32g431xx.h.

◆ DMA_CCR_DIR

#define DMA_CCR_DIR DMA_CCR_DIR_Msk

Data transfer direction

Definition at line 3070 of file stm32g431xx.h.

◆ DMA_CCR_DIR_Msk

#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos)

0x00000010

Definition at line 3069 of file stm32g431xx.h.

◆ DMA_CCR_DIR_Pos

#define DMA_CCR_DIR_Pos (4U)

Definition at line 3068 of file stm32g431xx.h.

◆ DMA_CCR_EN

#define DMA_CCR_EN DMA_CCR_EN_Msk

Channel enable

Definition at line 3058 of file stm32g431xx.h.

◆ DMA_CCR_EN_Msk

#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos)

0x00000001

Definition at line 3057 of file stm32g431xx.h.

◆ DMA_CCR_EN_Pos

#define DMA_CCR_EN_Pos (0U)

Definition at line 3056 of file stm32g431xx.h.

◆ DMA_CCR_HTIE

#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk

Half Transfer interrupt enable

Definition at line 3064 of file stm32g431xx.h.

◆ DMA_CCR_HTIE_Msk

#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos)

0x00000004

Definition at line 3063 of file stm32g431xx.h.

◆ DMA_CCR_HTIE_Pos

#define DMA_CCR_HTIE_Pos (2U)

Definition at line 3062 of file stm32g431xx.h.

◆ DMA_CCR_MEM2MEM

#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk

Memory to memory mode

Definition at line 3101 of file stm32g431xx.h.

◆ DMA_CCR_MEM2MEM_Msk

#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos)

0x00004000

Definition at line 3100 of file stm32g431xx.h.

◆ DMA_CCR_MEM2MEM_Pos

#define DMA_CCR_MEM2MEM_Pos (14U)

Definition at line 3099 of file stm32g431xx.h.

◆ DMA_CCR_MINC

#define DMA_CCR_MINC DMA_CCR_MINC_Msk

Memory increment mode

Definition at line 3079 of file stm32g431xx.h.

◆ DMA_CCR_MINC_Msk

#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos)

0x00000080

Definition at line 3078 of file stm32g431xx.h.

◆ DMA_CCR_MINC_Pos

#define DMA_CCR_MINC_Pos (7U)

Definition at line 3077 of file stm32g431xx.h.

◆ DMA_CCR_MSIZE

#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk

MSIZE[1:0] bits (Memory size)

Definition at line 3089 of file stm32g431xx.h.

◆ DMA_CCR_MSIZE_0

#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos)

0x00000400

Definition at line 3090 of file stm32g431xx.h.

◆ DMA_CCR_MSIZE_1

#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos)

0x00000800

Definition at line 3091 of file stm32g431xx.h.

◆ DMA_CCR_MSIZE_Msk

#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos)

0x00000C00

Definition at line 3088 of file stm32g431xx.h.

◆ DMA_CCR_MSIZE_Pos

#define DMA_CCR_MSIZE_Pos (10U)

Definition at line 3087 of file stm32g431xx.h.

◆ DMA_CCR_PINC

#define DMA_CCR_PINC DMA_CCR_PINC_Msk

Peripheral increment mode

Definition at line 3076 of file stm32g431xx.h.

◆ DMA_CCR_PINC_Msk

#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos)

0x00000040

Definition at line 3075 of file stm32g431xx.h.

◆ DMA_CCR_PINC_Pos

#define DMA_CCR_PINC_Pos (6U)

Definition at line 3074 of file stm32g431xx.h.

◆ DMA_CCR_PL

#define DMA_CCR_PL DMA_CCR_PL_Msk

PL[1:0] bits(Channel Priority level)

Definition at line 3095 of file stm32g431xx.h.

◆ DMA_CCR_PL_0

#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos)

0x00001000

Definition at line 3096 of file stm32g431xx.h.

◆ DMA_CCR_PL_1

#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos)

0x00002000

Definition at line 3097 of file stm32g431xx.h.

◆ DMA_CCR_PL_Msk

#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos)

0x00003000

Definition at line 3094 of file stm32g431xx.h.

◆ DMA_CCR_PL_Pos

#define DMA_CCR_PL_Pos (12U)

Definition at line 3093 of file stm32g431xx.h.

◆ DMA_CCR_PSIZE

#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk

PSIZE[1:0] bits (Peripheral size)

Definition at line 3083 of file stm32g431xx.h.

◆ DMA_CCR_PSIZE_0

#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos)

0x00000100

Definition at line 3084 of file stm32g431xx.h.

◆ DMA_CCR_PSIZE_1

#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos)

0x00000200

Definition at line 3085 of file stm32g431xx.h.

◆ DMA_CCR_PSIZE_Msk

#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos)

0x00000300

Definition at line 3082 of file stm32g431xx.h.

◆ DMA_CCR_PSIZE_Pos

#define DMA_CCR_PSIZE_Pos (8U)

Definition at line 3081 of file stm32g431xx.h.

◆ DMA_CCR_TCIE

#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk

Transfer complete interrupt enable

Definition at line 3061 of file stm32g431xx.h.

◆ DMA_CCR_TCIE_Msk

#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos)

0x00000002

Definition at line 3060 of file stm32g431xx.h.

◆ DMA_CCR_TCIE_Pos

#define DMA_CCR_TCIE_Pos (1U)

Definition at line 3059 of file stm32g431xx.h.

◆ DMA_CCR_TEIE

#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk

Transfer error interrupt enable

Definition at line 3067 of file stm32g431xx.h.

◆ DMA_CCR_TEIE_Msk

#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos)

0x00000008

Definition at line 3066 of file stm32g431xx.h.

◆ DMA_CCR_TEIE_Pos

#define DMA_CCR_TEIE_Pos (3U)

Definition at line 3065 of file stm32g431xx.h.

◆ DMA_CMAR_MA

#define DMA_CMAR_MA DMA_CMAR_MA_Msk

Memory Address

Definition at line 3116 of file stm32g431xx.h.

◆ DMA_CMAR_MA_Msk

#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)

0xFFFFFFFF

Definition at line 3115 of file stm32g431xx.h.

◆ DMA_CMAR_MA_Pos

#define DMA_CMAR_MA_Pos (0U)

Definition at line 3114 of file stm32g431xx.h.

◆ DMA_CNDTR_NDT

#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk

Number of data to Transfer

Definition at line 3106 of file stm32g431xx.h.

◆ DMA_CNDTR_NDT_Msk

#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos)

0x0000FFFF

Definition at line 3105 of file stm32g431xx.h.

◆ DMA_CNDTR_NDT_Pos

#define DMA_CNDTR_NDT_Pos (0U)

Definition at line 3104 of file stm32g431xx.h.

◆ DMA_CPAR_PA

#define DMA_CPAR_PA DMA_CPAR_PA_Msk

Peripheral Address

Definition at line 3111 of file stm32g431xx.h.

◆ DMA_CPAR_PA_Msk

#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)

0xFFFFFFFF

Definition at line 3110 of file stm32g431xx.h.

◆ DMA_CPAR_PA_Pos

#define DMA_CPAR_PA_Pos (0U)

Definition at line 3109 of file stm32g431xx.h.

◆ DMA_IFCR_CGIF1

#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk

Channel 1 Global interrupt clearr

Definition at line 2984 of file stm32g431xx.h.

◆ DMA_IFCR_CGIF1_Msk

#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos)

0x00000001

Definition at line 2983 of file stm32g431xx.h.

◆ DMA_IFCR_CGIF1_Pos

#define DMA_IFCR_CGIF1_Pos (0U)

Definition at line 2982 of file stm32g431xx.h.

◆ DMA_IFCR_CGIF2

#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk

Channel 2 Global interrupt clear

Definition at line 2996 of file stm32g431xx.h.

◆ DMA_IFCR_CGIF2_Msk

#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos)

0x00000010

Definition at line 2995 of file stm32g431xx.h.

◆ DMA_IFCR_CGIF2_Pos

#define DMA_IFCR_CGIF2_Pos (4U)

Definition at line 2994 of file stm32g431xx.h.

◆ DMA_IFCR_CGIF3

#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk

Channel 3 Global interrupt clear

Definition at line 3008 of file stm32g431xx.h.

◆ DMA_IFCR_CGIF3_Msk

#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos)

0x00000100

Definition at line 3007 of file stm32g431xx.h.

◆ DMA_IFCR_CGIF3_Pos

#define DMA_IFCR_CGIF3_Pos (8U)

Definition at line 3006 of file stm32g431xx.h.

◆ DMA_IFCR_CGIF4

#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk

Channel 4 Global interrupt clear

Definition at line 3020 of file stm32g431xx.h.

◆ DMA_IFCR_CGIF4_Msk

#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos)

0x00001000

Definition at line 3019 of file stm32g431xx.h.

◆ DMA_IFCR_CGIF4_Pos

#define DMA_IFCR_CGIF4_Pos (12U)

Definition at line 3018 of file stm32g431xx.h.

◆ DMA_IFCR_CGIF5

#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk

Channel 5 Global interrupt clear

Definition at line 3032 of file stm32g431xx.h.

◆ DMA_IFCR_CGIF5_Msk

#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos)

0x00010000

Definition at line 3031 of file stm32g431xx.h.

◆ DMA_IFCR_CGIF5_Pos

#define DMA_IFCR_CGIF5_Pos (16U)

Definition at line 3030 of file stm32g431xx.h.

◆ DMA_IFCR_CGIF6

#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk

Channel 6 Global interrupt clear

Definition at line 3044 of file stm32g431xx.h.

◆ DMA_IFCR_CGIF6_Msk

#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos)

0x00100000

Definition at line 3043 of file stm32g431xx.h.

◆ DMA_IFCR_CGIF6_Pos

#define DMA_IFCR_CGIF6_Pos (20U)

Definition at line 3042 of file stm32g431xx.h.

◆ DMA_IFCR_CHTIF1

#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk

Channel 1 Half Transfer clear

Definition at line 2990 of file stm32g431xx.h.

◆ DMA_IFCR_CHTIF1_Msk

#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos)

0x00000004

Definition at line 2989 of file stm32g431xx.h.

◆ DMA_IFCR_CHTIF1_Pos

#define DMA_IFCR_CHTIF1_Pos (2U)

Definition at line 2988 of file stm32g431xx.h.

◆ DMA_IFCR_CHTIF2

#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk

Channel 2 Half Transfer clear

Definition at line 3002 of file stm32g431xx.h.

◆ DMA_IFCR_CHTIF2_Msk

#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos)

0x00000040

Definition at line 3001 of file stm32g431xx.h.

◆ DMA_IFCR_CHTIF2_Pos

#define DMA_IFCR_CHTIF2_Pos (6U)

Definition at line 3000 of file stm32g431xx.h.

◆ DMA_IFCR_CHTIF3

#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk

Channel 3 Half Transfer clear

Definition at line 3014 of file stm32g431xx.h.

◆ DMA_IFCR_CHTIF3_Msk

#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos)

0x00000400

Definition at line 3013 of file stm32g431xx.h.

◆ DMA_IFCR_CHTIF3_Pos

#define DMA_IFCR_CHTIF3_Pos (10U)

Definition at line 3012 of file stm32g431xx.h.

◆ DMA_IFCR_CHTIF4

#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk

Channel 4 Half Transfer clear

Definition at line 3026 of file stm32g431xx.h.

◆ DMA_IFCR_CHTIF4_Msk

#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos)

0x00004000

Definition at line 3025 of file stm32g431xx.h.

◆ DMA_IFCR_CHTIF4_Pos

#define DMA_IFCR_CHTIF4_Pos (14U)

Definition at line 3024 of file stm32g431xx.h.

◆ DMA_IFCR_CHTIF5

#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk

Channel 5 Half Transfer clear

Definition at line 3038 of file stm32g431xx.h.

◆ DMA_IFCR_CHTIF5_Msk

#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos)

0x00040000

Definition at line 3037 of file stm32g431xx.h.

◆ DMA_IFCR_CHTIF5_Pos

#define DMA_IFCR_CHTIF5_Pos (18U)

Definition at line 3036 of file stm32g431xx.h.

◆ DMA_IFCR_CHTIF6

#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk

Channel 6 Half Transfer clear

Definition at line 3050 of file stm32g431xx.h.

◆ DMA_IFCR_CHTIF6_Msk

#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos)

0x00400000

Definition at line 3049 of file stm32g431xx.h.

◆ DMA_IFCR_CHTIF6_Pos

#define DMA_IFCR_CHTIF6_Pos (22U)

Definition at line 3048 of file stm32g431xx.h.

◆ DMA_IFCR_CTCIF1

#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk

Channel 1 Transfer Complete clear

Definition at line 2987 of file stm32g431xx.h.

◆ DMA_IFCR_CTCIF1_Msk

#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos)

0x00000002

Definition at line 2986 of file stm32g431xx.h.

◆ DMA_IFCR_CTCIF1_Pos

#define DMA_IFCR_CTCIF1_Pos (1U)

Definition at line 2985 of file stm32g431xx.h.

◆ DMA_IFCR_CTCIF2

#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk

Channel 2 Transfer Complete clear

Definition at line 2999 of file stm32g431xx.h.

◆ DMA_IFCR_CTCIF2_Msk

#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos)

0x00000020

Definition at line 2998 of file stm32g431xx.h.

◆ DMA_IFCR_CTCIF2_Pos

#define DMA_IFCR_CTCIF2_Pos (5U)

Definition at line 2997 of file stm32g431xx.h.

◆ DMA_IFCR_CTCIF3

#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk

Channel 3 Transfer Complete clear

Definition at line 3011 of file stm32g431xx.h.

◆ DMA_IFCR_CTCIF3_Msk

#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos)

0x00000200

Definition at line 3010 of file stm32g431xx.h.

◆ DMA_IFCR_CTCIF3_Pos

#define DMA_IFCR_CTCIF3_Pos (9U)

Definition at line 3009 of file stm32g431xx.h.

◆ DMA_IFCR_CTCIF4

#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk

Channel 4 Transfer Complete clear

Definition at line 3023 of file stm32g431xx.h.

◆ DMA_IFCR_CTCIF4_Msk

#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos)

0x00002000

Definition at line 3022 of file stm32g431xx.h.

◆ DMA_IFCR_CTCIF4_Pos

#define DMA_IFCR_CTCIF4_Pos (13U)

Definition at line 3021 of file stm32g431xx.h.

◆ DMA_IFCR_CTCIF5

#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk

Channel 5 Transfer Complete clear

Definition at line 3035 of file stm32g431xx.h.

◆ DMA_IFCR_CTCIF5_Msk

#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos)

0x00020000

Definition at line 3034 of file stm32g431xx.h.

◆ DMA_IFCR_CTCIF5_Pos

#define DMA_IFCR_CTCIF5_Pos (17U)

Definition at line 3033 of file stm32g431xx.h.

◆ DMA_IFCR_CTCIF6

#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk

Channel 6 Transfer Complete clear

Definition at line 3047 of file stm32g431xx.h.

◆ DMA_IFCR_CTCIF6_Msk

#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos)

0x00200000

Definition at line 3046 of file stm32g431xx.h.

◆ DMA_IFCR_CTCIF6_Pos

#define DMA_IFCR_CTCIF6_Pos (21U)

Definition at line 3045 of file stm32g431xx.h.

◆ DMA_IFCR_CTEIF1

#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk

Channel 1 Transfer Error clear

Definition at line 2993 of file stm32g431xx.h.

◆ DMA_IFCR_CTEIF1_Msk

#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos)

0x00000008

Definition at line 2992 of file stm32g431xx.h.

◆ DMA_IFCR_CTEIF1_Pos

#define DMA_IFCR_CTEIF1_Pos (3U)

Definition at line 2991 of file stm32g431xx.h.

◆ DMA_IFCR_CTEIF2

#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk

Channel 2 Transfer Error clear

Definition at line 3005 of file stm32g431xx.h.

◆ DMA_IFCR_CTEIF2_Msk

#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos)

0x00000080

Definition at line 3004 of file stm32g431xx.h.

◆ DMA_IFCR_CTEIF2_Pos

#define DMA_IFCR_CTEIF2_Pos (7U)

Definition at line 3003 of file stm32g431xx.h.

◆ DMA_IFCR_CTEIF3

#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk

Channel 3 Transfer Error clear

Definition at line 3017 of file stm32g431xx.h.

◆ DMA_IFCR_CTEIF3_Msk

#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos)

0x00000800

Definition at line 3016 of file stm32g431xx.h.

◆ DMA_IFCR_CTEIF3_Pos

#define DMA_IFCR_CTEIF3_Pos (11U)

Definition at line 3015 of file stm32g431xx.h.

◆ DMA_IFCR_CTEIF4

#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk

Channel 4 Transfer Error clear

Definition at line 3029 of file stm32g431xx.h.

◆ DMA_IFCR_CTEIF4_Msk

#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos)

0x00008000

Definition at line 3028 of file stm32g431xx.h.

◆ DMA_IFCR_CTEIF4_Pos

#define DMA_IFCR_CTEIF4_Pos (15U)

Definition at line 3027 of file stm32g431xx.h.

◆ DMA_IFCR_CTEIF5

#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk

Channel 5 Transfer Error clear

Definition at line 3041 of file stm32g431xx.h.

◆ DMA_IFCR_CTEIF5_Msk

#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos)

0x00080000

Definition at line 3040 of file stm32g431xx.h.

◆ DMA_IFCR_CTEIF5_Pos

#define DMA_IFCR_CTEIF5_Pos (19U)

Definition at line 3039 of file stm32g431xx.h.

◆ DMA_IFCR_CTEIF6

#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk

Channel 6 Transfer Error clear

Definition at line 3053 of file stm32g431xx.h.

◆ DMA_IFCR_CTEIF6_Msk

#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos)

0x00800000

Definition at line 3052 of file stm32g431xx.h.

◆ DMA_IFCR_CTEIF6_Pos

#define DMA_IFCR_CTEIF6_Pos (23U)

Definition at line 3051 of file stm32g431xx.h.

◆ DMA_ISR_GIF1

#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk

Channel 1 Global interrupt flag

Definition at line 2910 of file stm32g431xx.h.

◆ DMA_ISR_GIF1_Msk

#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos)

0x00000001

Definition at line 2909 of file stm32g431xx.h.

◆ DMA_ISR_GIF1_Pos

#define DMA_ISR_GIF1_Pos (0U)

Definition at line 2908 of file stm32g431xx.h.

◆ DMA_ISR_GIF2

#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk

Channel 2 Global interrupt flag

Definition at line 2922 of file stm32g431xx.h.

◆ DMA_ISR_GIF2_Msk

#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos)

0x00000010

Definition at line 2921 of file stm32g431xx.h.

◆ DMA_ISR_GIF2_Pos

#define DMA_ISR_GIF2_Pos (4U)

Definition at line 2920 of file stm32g431xx.h.

◆ DMA_ISR_GIF3

#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk

Channel 3 Global interrupt flag

Definition at line 2934 of file stm32g431xx.h.

◆ DMA_ISR_GIF3_Msk

#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos)

0x00000100

Definition at line 2933 of file stm32g431xx.h.

◆ DMA_ISR_GIF3_Pos

#define DMA_ISR_GIF3_Pos (8U)

Definition at line 2932 of file stm32g431xx.h.

◆ DMA_ISR_GIF4

#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk

Channel 4 Global interrupt flag

Definition at line 2946 of file stm32g431xx.h.

◆ DMA_ISR_GIF4_Msk

#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos)

0x00001000

Definition at line 2945 of file stm32g431xx.h.

◆ DMA_ISR_GIF4_Pos

#define DMA_ISR_GIF4_Pos (12U)

Definition at line 2944 of file stm32g431xx.h.

◆ DMA_ISR_GIF5

#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk

Channel 5 Global interrupt flag

Definition at line 2958 of file stm32g431xx.h.

◆ DMA_ISR_GIF5_Msk

#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos)

0x00010000

Definition at line 2957 of file stm32g431xx.h.

◆ DMA_ISR_GIF5_Pos

#define DMA_ISR_GIF5_Pos (16U)

Definition at line 2956 of file stm32g431xx.h.

◆ DMA_ISR_GIF6

#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk

Channel 6 Global interrupt flag

Definition at line 2970 of file stm32g431xx.h.

◆ DMA_ISR_GIF6_Msk

#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos)

0x00100000

Definition at line 2969 of file stm32g431xx.h.

◆ DMA_ISR_GIF6_Pos

#define DMA_ISR_GIF6_Pos (20U)

Definition at line 2968 of file stm32g431xx.h.

◆ DMA_ISR_HTIF1

#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk

Channel 1 Half Transfer flag

Definition at line 2916 of file stm32g431xx.h.

◆ DMA_ISR_HTIF1_Msk

#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos)

0x00000004

Definition at line 2915 of file stm32g431xx.h.

◆ DMA_ISR_HTIF1_Pos

#define DMA_ISR_HTIF1_Pos (2U)

Definition at line 2914 of file stm32g431xx.h.

◆ DMA_ISR_HTIF2

#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk

Channel 2 Half Transfer flag

Definition at line 2928 of file stm32g431xx.h.

◆ DMA_ISR_HTIF2_Msk

#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos)

0x00000040

Definition at line 2927 of file stm32g431xx.h.

◆ DMA_ISR_HTIF2_Pos

#define DMA_ISR_HTIF2_Pos (6U)

Definition at line 2926 of file stm32g431xx.h.

◆ DMA_ISR_HTIF3

#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk

Channel 3 Half Transfer flag

Definition at line 2940 of file stm32g431xx.h.

◆ DMA_ISR_HTIF3_Msk

#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos)

0x00000400

Definition at line 2939 of file stm32g431xx.h.

◆ DMA_ISR_HTIF3_Pos

#define DMA_ISR_HTIF3_Pos (10U)

Definition at line 2938 of file stm32g431xx.h.

◆ DMA_ISR_HTIF4

#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk

Channel 4 Half Transfer flag

Definition at line 2952 of file stm32g431xx.h.

◆ DMA_ISR_HTIF4_Msk

#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos)

0x00004000

Definition at line 2951 of file stm32g431xx.h.

◆ DMA_ISR_HTIF4_Pos

#define DMA_ISR_HTIF4_Pos (14U)

Definition at line 2950 of file stm32g431xx.h.

◆ DMA_ISR_HTIF5

#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk

Channel 5 Half Transfer flag

Definition at line 2964 of file stm32g431xx.h.

◆ DMA_ISR_HTIF5_Msk

#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos)

0x00040000

Definition at line 2963 of file stm32g431xx.h.

◆ DMA_ISR_HTIF5_Pos

#define DMA_ISR_HTIF5_Pos (18U)

Definition at line 2962 of file stm32g431xx.h.

◆ DMA_ISR_HTIF6

#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk

Channel 6 Half Transfer flag

Definition at line 2976 of file stm32g431xx.h.

◆ DMA_ISR_HTIF6_Msk

#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos)

0x00400000

Definition at line 2975 of file stm32g431xx.h.

◆ DMA_ISR_HTIF6_Pos

#define DMA_ISR_HTIF6_Pos (22U)

Definition at line 2974 of file stm32g431xx.h.

◆ DMA_ISR_TCIF1

#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk

Channel 1 Transfer Complete flag

Definition at line 2913 of file stm32g431xx.h.

◆ DMA_ISR_TCIF1_Msk

#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos)

0x00000002

Definition at line 2912 of file stm32g431xx.h.

◆ DMA_ISR_TCIF1_Pos

#define DMA_ISR_TCIF1_Pos (1U)

Definition at line 2911 of file stm32g431xx.h.

◆ DMA_ISR_TCIF2

#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk

Channel 2 Transfer Complete flag

Definition at line 2925 of file stm32g431xx.h.

◆ DMA_ISR_TCIF2_Msk

#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos)

0x00000020

Definition at line 2924 of file stm32g431xx.h.

◆ DMA_ISR_TCIF2_Pos

#define DMA_ISR_TCIF2_Pos (5U)

Definition at line 2923 of file stm32g431xx.h.

◆ DMA_ISR_TCIF3

#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk

Channel 3 Transfer Complete flag

Definition at line 2937 of file stm32g431xx.h.

◆ DMA_ISR_TCIF3_Msk

#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos)

0x00000200

Definition at line 2936 of file stm32g431xx.h.

◆ DMA_ISR_TCIF3_Pos

#define DMA_ISR_TCIF3_Pos (9U)

Definition at line 2935 of file stm32g431xx.h.

◆ DMA_ISR_TCIF4

#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk

Channel 4 Transfer Complete flag

Definition at line 2949 of file stm32g431xx.h.

◆ DMA_ISR_TCIF4_Msk

#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos)

0x00002000

Definition at line 2948 of file stm32g431xx.h.

◆ DMA_ISR_TCIF4_Pos

#define DMA_ISR_TCIF4_Pos (13U)

Definition at line 2947 of file stm32g431xx.h.

◆ DMA_ISR_TCIF5

#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk

Channel 5 Transfer Complete flag

Definition at line 2961 of file stm32g431xx.h.

◆ DMA_ISR_TCIF5_Msk

#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos)

0x00020000

Definition at line 2960 of file stm32g431xx.h.

◆ DMA_ISR_TCIF5_Pos

#define DMA_ISR_TCIF5_Pos (17U)

Definition at line 2959 of file stm32g431xx.h.

◆ DMA_ISR_TCIF6

#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk

Channel 6 Transfer Complete flag

Definition at line 2973 of file stm32g431xx.h.

◆ DMA_ISR_TCIF6_Msk

#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos)

0x00200000

Definition at line 2972 of file stm32g431xx.h.

◆ DMA_ISR_TCIF6_Pos

#define DMA_ISR_TCIF6_Pos (21U)

Definition at line 2971 of file stm32g431xx.h.

◆ DMA_ISR_TEIF1

#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk

Channel 1 Transfer Error flag

Definition at line 2919 of file stm32g431xx.h.

◆ DMA_ISR_TEIF1_Msk

#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos)

0x00000008

Definition at line 2918 of file stm32g431xx.h.

◆ DMA_ISR_TEIF1_Pos

#define DMA_ISR_TEIF1_Pos (3U)

Definition at line 2917 of file stm32g431xx.h.

◆ DMA_ISR_TEIF2

#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk

Channel 2 Transfer Error flag

Definition at line 2931 of file stm32g431xx.h.

◆ DMA_ISR_TEIF2_Msk

#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos)

0x00000080

Definition at line 2930 of file stm32g431xx.h.

◆ DMA_ISR_TEIF2_Pos

#define DMA_ISR_TEIF2_Pos (7U)

Definition at line 2929 of file stm32g431xx.h.

◆ DMA_ISR_TEIF3

#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk

Channel 3 Transfer Error flag

Definition at line 2943 of file stm32g431xx.h.

◆ DMA_ISR_TEIF3_Msk

#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos)

0x00000800

Definition at line 2942 of file stm32g431xx.h.

◆ DMA_ISR_TEIF3_Pos

#define DMA_ISR_TEIF3_Pos (11U)

Definition at line 2941 of file stm32g431xx.h.

◆ DMA_ISR_TEIF4

#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk

Channel 4 Transfer Error flag

Definition at line 2955 of file stm32g431xx.h.

◆ DMA_ISR_TEIF4_Msk

#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos)

0x00008000

Definition at line 2954 of file stm32g431xx.h.

◆ DMA_ISR_TEIF4_Pos

#define DMA_ISR_TEIF4_Pos (15U)

Definition at line 2953 of file stm32g431xx.h.

◆ DMA_ISR_TEIF5

#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk

Channel 5 Transfer Error flag

Definition at line 2967 of file stm32g431xx.h.

◆ DMA_ISR_TEIF5_Msk

#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos)

0x00080000

Definition at line 2966 of file stm32g431xx.h.

◆ DMA_ISR_TEIF5_Pos

#define DMA_ISR_TEIF5_Pos (19U)

Definition at line 2965 of file stm32g431xx.h.

◆ DMA_ISR_TEIF6

#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk

Channel 6 Transfer Error flag

Definition at line 2979 of file stm32g431xx.h.

◆ DMA_ISR_TEIF6_Msk

#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos)

0x00800000

Definition at line 2978 of file stm32g431xx.h.

◆ DMA_ISR_TEIF6_Pos

#define DMA_ISR_TEIF6_Pos (23U)

Definition at line 2977 of file stm32g431xx.h.

◆ DMAMUX_CFR_CSOF0

#define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk

Definition at line 3214 of file stm32g431xx.h.

◆ DMAMUX_CFR_CSOF0_Msk

#define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos)

0x00000001

Definition at line 3213 of file stm32g431xx.h.

◆ DMAMUX_CFR_CSOF0_Pos

#define DMAMUX_CFR_CSOF0_Pos (0U)

Definition at line 3212 of file stm32g431xx.h.

◆ DMAMUX_CFR_CSOF1

#define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk

Definition at line 3217 of file stm32g431xx.h.

◆ DMAMUX_CFR_CSOF10

#define DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10_Msk

Definition at line 3244 of file stm32g431xx.h.

◆ DMAMUX_CFR_CSOF10_Msk

#define DMAMUX_CFR_CSOF10_Msk (0x1UL << DMAMUX_CFR_CSOF10_Pos)

0x00000400

Definition at line 3243 of file stm32g431xx.h.

◆ DMAMUX_CFR_CSOF10_Pos

#define DMAMUX_CFR_CSOF10_Pos (10U)

Definition at line 3242 of file stm32g431xx.h.

◆ DMAMUX_CFR_CSOF11

#define DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11_Msk

Definition at line 3247 of file stm32g431xx.h.

◆ DMAMUX_CFR_CSOF11_Msk

#define DMAMUX_CFR_CSOF11_Msk (0x1UL << DMAMUX_CFR_CSOF11_Pos)

0x00000800

Definition at line 3246 of file stm32g431xx.h.

◆ DMAMUX_CFR_CSOF11_Pos

#define DMAMUX_CFR_CSOF11_Pos (11U)

Definition at line 3245 of file stm32g431xx.h.

◆ DMAMUX_CFR_CSOF1_Msk

#define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos)

0x00000002

Definition at line 3216 of file stm32g431xx.h.

◆ DMAMUX_CFR_CSOF1_Pos

#define DMAMUX_CFR_CSOF1_Pos (1U)

Definition at line 3215 of file stm32g431xx.h.

◆ DMAMUX_CFR_CSOF2

#define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk

Definition at line 3220 of file stm32g431xx.h.

◆ DMAMUX_CFR_CSOF2_Msk

#define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos)

0x00000004

Definition at line 3219 of file stm32g431xx.h.

◆ DMAMUX_CFR_CSOF2_Pos

#define DMAMUX_CFR_CSOF2_Pos (2U)

Definition at line 3218 of file stm32g431xx.h.

◆ DMAMUX_CFR_CSOF3

#define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk

Definition at line 3223 of file stm32g431xx.h.

◆ DMAMUX_CFR_CSOF3_Msk

#define DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos)

0x00000008

Definition at line 3222 of file stm32g431xx.h.

◆ DMAMUX_CFR_CSOF3_Pos

#define DMAMUX_CFR_CSOF3_Pos (3U)

Definition at line 3221 of file stm32g431xx.h.

◆ DMAMUX_CFR_CSOF4

#define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk

Definition at line 3226 of file stm32g431xx.h.

◆ DMAMUX_CFR_CSOF4_Msk

#define DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos)

0x00000010

Definition at line 3225 of file stm32g431xx.h.

◆ DMAMUX_CFR_CSOF4_Pos

#define DMAMUX_CFR_CSOF4_Pos (4U)

Definition at line 3224 of file stm32g431xx.h.

◆ DMAMUX_CFR_CSOF5

#define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk

Definition at line 3229 of file stm32g431xx.h.

◆ DMAMUX_CFR_CSOF5_Msk

#define DMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos)

0x00000020

Definition at line 3228 of file stm32g431xx.h.

◆ DMAMUX_CFR_CSOF5_Pos

#define DMAMUX_CFR_CSOF5_Pos (5U)

Definition at line 3227 of file stm32g431xx.h.

◆ DMAMUX_CFR_CSOF6

#define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk

Definition at line 3232 of file stm32g431xx.h.

◆ DMAMUX_CFR_CSOF6_Msk

#define DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos)

0x00000040

Definition at line 3231 of file stm32g431xx.h.

◆ DMAMUX_CFR_CSOF6_Pos

#define DMAMUX_CFR_CSOF6_Pos (6U)

Definition at line 3230 of file stm32g431xx.h.

◆ DMAMUX_CFR_CSOF7

#define DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7_Msk

Definition at line 3235 of file stm32g431xx.h.

◆ DMAMUX_CFR_CSOF7_Msk

#define DMAMUX_CFR_CSOF7_Msk (0x1UL << DMAMUX_CFR_CSOF7_Pos)

0x00000080

Definition at line 3234 of file stm32g431xx.h.

◆ DMAMUX_CFR_CSOF7_Pos

#define DMAMUX_CFR_CSOF7_Pos (7U)

Definition at line 3233 of file stm32g431xx.h.

◆ DMAMUX_CFR_CSOF8

#define DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8_Msk

Definition at line 3238 of file stm32g431xx.h.

◆ DMAMUX_CFR_CSOF8_Msk

#define DMAMUX_CFR_CSOF8_Msk (0x1UL << DMAMUX_CFR_CSOF8_Pos)

0x00000100

Definition at line 3237 of file stm32g431xx.h.

◆ DMAMUX_CFR_CSOF8_Pos

#define DMAMUX_CFR_CSOF8_Pos (8U)

Definition at line 3236 of file stm32g431xx.h.

◆ DMAMUX_CFR_CSOF9

#define DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9_Msk

Definition at line 3241 of file stm32g431xx.h.

◆ DMAMUX_CFR_CSOF9_Msk

#define DMAMUX_CFR_CSOF9_Msk (0x1UL << DMAMUX_CFR_CSOF9_Pos)

0x00000200

Definition at line 3240 of file stm32g431xx.h.

◆ DMAMUX_CFR_CSOF9_Pos

#define DMAMUX_CFR_CSOF9_Pos (9U)

Definition at line 3239 of file stm32g431xx.h.

◆ DMAMUX_CSR_SOF0

#define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk

Definition at line 3176 of file stm32g431xx.h.

◆ DMAMUX_CSR_SOF0_Msk

#define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos)

0x00000001

Definition at line 3175 of file stm32g431xx.h.

◆ DMAMUX_CSR_SOF0_Pos

#define DMAMUX_CSR_SOF0_Pos (0U)

Definition at line 3174 of file stm32g431xx.h.

◆ DMAMUX_CSR_SOF1

#define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk

Definition at line 3179 of file stm32g431xx.h.

◆ DMAMUX_CSR_SOF10

#define DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10_Msk

Definition at line 3206 of file stm32g431xx.h.

◆ DMAMUX_CSR_SOF10_Msk

#define DMAMUX_CSR_SOF10_Msk (0x1UL << DMAMUX_CSR_SOF10_Pos)

0x00000400

Definition at line 3205 of file stm32g431xx.h.

◆ DMAMUX_CSR_SOF10_Pos

#define DMAMUX_CSR_SOF10_Pos (10U)

Definition at line 3204 of file stm32g431xx.h.

◆ DMAMUX_CSR_SOF11

#define DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11_Msk

Definition at line 3209 of file stm32g431xx.h.

◆ DMAMUX_CSR_SOF11_Msk

#define DMAMUX_CSR_SOF11_Msk (0x1UL << DMAMUX_CSR_SOF11_Pos)

0x00000800

Definition at line 3208 of file stm32g431xx.h.

◆ DMAMUX_CSR_SOF11_Pos

#define DMAMUX_CSR_SOF11_Pos (11U)

Definition at line 3207 of file stm32g431xx.h.

◆ DMAMUX_CSR_SOF1_Msk

#define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos)

0x00000002

Definition at line 3178 of file stm32g431xx.h.

◆ DMAMUX_CSR_SOF1_Pos

#define DMAMUX_CSR_SOF1_Pos (1U)

Definition at line 3177 of file stm32g431xx.h.

◆ DMAMUX_CSR_SOF2

#define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk

Definition at line 3182 of file stm32g431xx.h.

◆ DMAMUX_CSR_SOF2_Msk

#define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos)

0x00000004

Definition at line 3181 of file stm32g431xx.h.

◆ DMAMUX_CSR_SOF2_Pos

#define DMAMUX_CSR_SOF2_Pos (2U)

Definition at line 3180 of file stm32g431xx.h.

◆ DMAMUX_CSR_SOF3

#define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk

Definition at line 3185 of file stm32g431xx.h.

◆ DMAMUX_CSR_SOF3_Msk

#define DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos)

0x00000008

Definition at line 3184 of file stm32g431xx.h.

◆ DMAMUX_CSR_SOF3_Pos

#define DMAMUX_CSR_SOF3_Pos (3U)

Definition at line 3183 of file stm32g431xx.h.

◆ DMAMUX_CSR_SOF4

#define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk

Definition at line 3188 of file stm32g431xx.h.

◆ DMAMUX_CSR_SOF4_Msk

#define DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos)

0x00000010

Definition at line 3187 of file stm32g431xx.h.

◆ DMAMUX_CSR_SOF4_Pos

#define DMAMUX_CSR_SOF4_Pos (4U)

Definition at line 3186 of file stm32g431xx.h.

◆ DMAMUX_CSR_SOF5

#define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk

Definition at line 3191 of file stm32g431xx.h.

◆ DMAMUX_CSR_SOF5_Msk

#define DMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos)

0x00000020

Definition at line 3190 of file stm32g431xx.h.

◆ DMAMUX_CSR_SOF5_Pos

#define DMAMUX_CSR_SOF5_Pos (5U)

Definition at line 3189 of file stm32g431xx.h.

◆ DMAMUX_CSR_SOF6

#define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk

Definition at line 3194 of file stm32g431xx.h.

◆ DMAMUX_CSR_SOF6_Msk

#define DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos)

0x00000040

Definition at line 3193 of file stm32g431xx.h.

◆ DMAMUX_CSR_SOF6_Pos

#define DMAMUX_CSR_SOF6_Pos (6U)

Definition at line 3192 of file stm32g431xx.h.

◆ DMAMUX_CSR_SOF7

#define DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7_Msk

Definition at line 3197 of file stm32g431xx.h.

◆ DMAMUX_CSR_SOF7_Msk

#define DMAMUX_CSR_SOF7_Msk (0x1UL << DMAMUX_CSR_SOF7_Pos)

0x00000080

Definition at line 3196 of file stm32g431xx.h.

◆ DMAMUX_CSR_SOF7_Pos

#define DMAMUX_CSR_SOF7_Pos (7U)

Definition at line 3195 of file stm32g431xx.h.

◆ DMAMUX_CSR_SOF8

#define DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8_Msk

Definition at line 3200 of file stm32g431xx.h.

◆ DMAMUX_CSR_SOF8_Msk

#define DMAMUX_CSR_SOF8_Msk (0x1UL << DMAMUX_CSR_SOF8_Pos)

0x00000100

Definition at line 3199 of file stm32g431xx.h.

◆ DMAMUX_CSR_SOF8_Pos

#define DMAMUX_CSR_SOF8_Pos (8U)

Definition at line 3198 of file stm32g431xx.h.

◆ DMAMUX_CSR_SOF9

#define DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9_Msk

Definition at line 3203 of file stm32g431xx.h.

◆ DMAMUX_CSR_SOF9_Msk

#define DMAMUX_CSR_SOF9_Msk (0x1UL << DMAMUX_CSR_SOF9_Pos)

0x00000200

Definition at line 3202 of file stm32g431xx.h.

◆ DMAMUX_CSR_SOF9_Pos

#define DMAMUX_CSR_SOF9_Pos (9U)

Definition at line 3201 of file stm32g431xx.h.

◆ DMAMUX_CxCR_DMAREQ_ID

#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk

Definition at line 3127 of file stm32g431xx.h.

◆ DMAMUX_CxCR_DMAREQ_ID_0

#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)

0x00000001

Definition at line 3128 of file stm32g431xx.h.

◆ DMAMUX_CxCR_DMAREQ_ID_1

#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)

0x00000002

Definition at line 3129 of file stm32g431xx.h.

◆ DMAMUX_CxCR_DMAREQ_ID_2

#define DMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)

0x00000004

Definition at line 3130 of file stm32g431xx.h.

◆ DMAMUX_CxCR_DMAREQ_ID_3

#define DMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)

0x00000008

Definition at line 3131 of file stm32g431xx.h.

◆ DMAMUX_CxCR_DMAREQ_ID_4

#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)

0x00000010

Definition at line 3132 of file stm32g431xx.h.

◆ DMAMUX_CxCR_DMAREQ_ID_5

#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)

0x00000020

Definition at line 3133 of file stm32g431xx.h.

◆ DMAMUX_CxCR_DMAREQ_ID_6

#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)

0x00000040

Definition at line 3134 of file stm32g431xx.h.

◆ DMAMUX_CxCR_DMAREQ_ID_7

#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)

0x00000080

Definition at line 3135 of file stm32g431xx.h.

◆ DMAMUX_CxCR_DMAREQ_ID_Msk

#define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)

0x000000FF

Definition at line 3126 of file stm32g431xx.h.

◆ DMAMUX_CxCR_DMAREQ_ID_Pos

#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U)

Definition at line 3125 of file stm32g431xx.h.

◆ DMAMUX_CxCR_EGE

#define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk

Definition at line 3143 of file stm32g431xx.h.

◆ DMAMUX_CxCR_EGE_Msk

#define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos)

0x00000200

Definition at line 3142 of file stm32g431xx.h.

◆ DMAMUX_CxCR_EGE_Pos

#define DMAMUX_CxCR_EGE_Pos (9U)

Definition at line 3141 of file stm32g431xx.h.

◆ DMAMUX_CxCR_NBREQ

#define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk

Definition at line 3157 of file stm32g431xx.h.

◆ DMAMUX_CxCR_NBREQ_0

#define DMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos)

0x00080000

Definition at line 3158 of file stm32g431xx.h.

◆ DMAMUX_CxCR_NBREQ_1

#define DMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos)

0x00100000

Definition at line 3159 of file stm32g431xx.h.

◆ DMAMUX_CxCR_NBREQ_2

#define DMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos)

0x00200000

Definition at line 3160 of file stm32g431xx.h.

◆ DMAMUX_CxCR_NBREQ_3

#define DMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos)

0x00400000

Definition at line 3161 of file stm32g431xx.h.

◆ DMAMUX_CxCR_NBREQ_4

#define DMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos)

0x00800000

Definition at line 3162 of file stm32g431xx.h.

◆ DMAMUX_CxCR_NBREQ_Msk

#define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)

0x00F80000

Definition at line 3156 of file stm32g431xx.h.

◆ DMAMUX_CxCR_NBREQ_Pos

#define DMAMUX_CxCR_NBREQ_Pos (19U)

Definition at line 3155 of file stm32g431xx.h.

◆ DMAMUX_CxCR_SE

#define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk

Definition at line 3147 of file stm32g431xx.h.

◆ DMAMUX_CxCR_SE_Msk

#define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos)

0x00010000

Definition at line 3146 of file stm32g431xx.h.

◆ DMAMUX_CxCR_SE_Pos

#define DMAMUX_CxCR_SE_Pos (16U)

Definition at line 3145 of file stm32g431xx.h.

◆ DMAMUX_CxCR_SOIE

#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk

Definition at line 3139 of file stm32g431xx.h.

◆ DMAMUX_CxCR_SOIE_Msk

#define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos)

0x00000100

Definition at line 3138 of file stm32g431xx.h.

◆ DMAMUX_CxCR_SOIE_Pos

#define DMAMUX_CxCR_SOIE_Pos (8U)

Definition at line 3137 of file stm32g431xx.h.

◆ DMAMUX_CxCR_SPOL

#define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk

Definition at line 3151 of file stm32g431xx.h.

◆ DMAMUX_CxCR_SPOL_0

#define DMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos)

0x00020000

Definition at line 3152 of file stm32g431xx.h.

◆ DMAMUX_CxCR_SPOL_1

#define DMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos)

0x00040000

Definition at line 3153 of file stm32g431xx.h.

◆ DMAMUX_CxCR_SPOL_Msk

#define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos)

0x00060000

Definition at line 3150 of file stm32g431xx.h.

◆ DMAMUX_CxCR_SPOL_Pos

#define DMAMUX_CxCR_SPOL_Pos (17U)

Definition at line 3149 of file stm32g431xx.h.

◆ DMAMUX_CxCR_SYNC_ID

#define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk

Definition at line 3166 of file stm32g431xx.h.

◆ DMAMUX_CxCR_SYNC_ID_0

#define DMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)

0x01000000

Definition at line 3167 of file stm32g431xx.h.

◆ DMAMUX_CxCR_SYNC_ID_1

#define DMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)

0x02000000

Definition at line 3168 of file stm32g431xx.h.

◆ DMAMUX_CxCR_SYNC_ID_2

#define DMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)

0x04000000

Definition at line 3169 of file stm32g431xx.h.

◆ DMAMUX_CxCR_SYNC_ID_3

#define DMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)

0x08000000

Definition at line 3170 of file stm32g431xx.h.

◆ DMAMUX_CxCR_SYNC_ID_4

#define DMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)

0x10000000

Definition at line 3171 of file stm32g431xx.h.

◆ DMAMUX_CxCR_SYNC_ID_Msk

#define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)

0x1F000000

Definition at line 3165 of file stm32g431xx.h.

◆ DMAMUX_CxCR_SYNC_ID_Pos

#define DMAMUX_CxCR_SYNC_ID_Pos (24U)

Definition at line 3164 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0

#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Msk

Definition at line 3363 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Msk

#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Pos)

0x00000100

Definition at line 3362 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Pos

#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Pos (8U)

Definition at line 3361 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1

#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Msk

Definition at line 3366 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Msk

#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Pos)

0x00000200

Definition at line 3365 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Pos

#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Pos (9U)

Definition at line 3364 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2

#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Msk

Definition at line 3369 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Msk

#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Pos)

0x00000400

Definition at line 3368 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Pos

#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Pos (10U)

Definition at line 3367 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3

#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Msk

Definition at line 3372 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Msk

#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Pos)

0x00000800

Definition at line 3371 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Pos

#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Pos (11U)

Definition at line 3370 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4

#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Msk

Definition at line 3375 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Msk

#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Pos)

0x00001000

Definition at line 3374 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Pos

#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Pos (12U)

Definition at line 3373 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5

#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Msk

Definition at line 3378 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Msk

#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Pos)

0x00002000

Definition at line 3377 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Pos

#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Pos (13U)

Definition at line 3376 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6

#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Msk

Definition at line 3381 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Msk

#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Pos)

0x00004000

Definition at line 3380 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Pos

#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Pos (14U)

Definition at line 3379 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7

#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Msk

Definition at line 3384 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Msk

#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Pos)

0x00008000

Definition at line 3383 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Pos

#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Pos (15U)

Definition at line 3382 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0

#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Msk

Definition at line 3411 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Msk

#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Pos)

0x01000000

Definition at line 3410 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Pos

#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Pos (24U)

Definition at line 3409 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1

#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Msk

Definition at line 3414 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Msk

#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Pos)

0x02000000

Definition at line 3413 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Pos

#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Pos (25U)

Definition at line 3412 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2

#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Msk

Definition at line 3417 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Msk

#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Pos)

0x04000000

Definition at line 3416 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Pos

#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Pos (26U)

Definition at line 3415 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3

#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Msk

Definition at line 3420 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Msk

#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Pos)

0x08000000

Definition at line 3419 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Pos

#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Pos (27U)

Definition at line 3418 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4

#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Msk

Definition at line 3423 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Msk

#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Pos)

0x10000000

Definition at line 3422 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Pos

#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Pos (28U)

Definition at line 3421 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5

#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Msk

Definition at line 3426 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Msk

#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Pos)

0x20000000

Definition at line 3425 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Pos

#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Pos (29U)

Definition at line 3424 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6

#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Msk

Definition at line 3429 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Msk

#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Pos)

0x40000000

Definition at line 3428 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Pos

#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Pos (30U)

Definition at line 3427 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7

#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Msk

Definition at line 3432 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Msk

#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Pos)

0x80000000

Definition at line 3431 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Pos

#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Pos (31U)

Definition at line 3430 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0

#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Msk

Definition at line 3339 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Msk

#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Pos)

0x00000001

Definition at line 3338 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Pos

#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Pos (0U)

Definition at line 3337 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1

#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Msk

Definition at line 3342 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Msk

#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Pos)

0x00000002

Definition at line 3341 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Pos

#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Pos (1U)

Definition at line 3340 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2

#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Msk

Definition at line 3345 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Msk

#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Pos)

0x00000004

Definition at line 3344 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Pos

#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Pos (2U)

Definition at line 3343 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3

#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Msk

Definition at line 3348 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Msk

#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Pos)

0x00000008

Definition at line 3347 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Pos

#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Pos (3U)

Definition at line 3346 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4

#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Msk

Definition at line 3351 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Msk

#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Pos)

0x00000010

Definition at line 3350 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Pos

#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Pos (4U)

Definition at line 3349 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5

#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Msk

Definition at line 3354 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Msk

#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Pos)

0x00000020

Definition at line 3353 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Pos

#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Pos (5U)

Definition at line 3352 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6

#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Msk

Definition at line 3357 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Msk

#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Pos)

0x00000040

Definition at line 3356 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Pos

#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Pos (6U)

Definition at line 3355 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7

#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Msk

Definition at line 3360 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Msk

#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Pos)

0x00000080

Definition at line 3359 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Pos

#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Pos (7U)

Definition at line 3358 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0

#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Msk

Definition at line 3387 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Msk

#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Pos)

0x00010000

Definition at line 3386 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Pos

#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Pos (16U)

Definition at line 3385 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1

#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Msk

Definition at line 3390 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Msk

#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Pos)

0x00020000

Definition at line 3389 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Pos

#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Pos (17U)

Definition at line 3388 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2

#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Msk

Definition at line 3393 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Msk

#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Pos)

0x00040000

Definition at line 3392 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Pos

#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Pos (18U)

Definition at line 3391 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3

#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Msk

Definition at line 3396 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Msk

#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Pos)

0x00080000

Definition at line 3395 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Pos

#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Pos (19U)

Definition at line 3394 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4

#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Msk

Definition at line 3399 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Msk

#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Pos)

0x00100000

Definition at line 3398 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Pos

#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Pos (20U)

Definition at line 3397 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5

#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Msk

Definition at line 3402 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Msk

#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Pos)

0x00200000

Definition at line 3401 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Pos

#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Pos (21U)

Definition at line 3400 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6

#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Msk

Definition at line 3405 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Msk

#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Pos)

0x00400000

Definition at line 3404 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Pos

#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Pos (22U)

Definition at line 3403 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7

#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Msk

Definition at line 3408 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Msk

#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Pos)

0x00800000

Definition at line 3407 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Pos

#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Pos (23U)

Definition at line 3406 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0

#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Msk

Definition at line 3313 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Msk

#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Pos)

0x00000001

Definition at line 3312 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Pos

#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Pos (0U)

Definition at line 3311 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1

#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Msk

Definition at line 3316 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Msk

#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Pos)

0x00000002

Definition at line 3315 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Pos

#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Pos (1U)

Definition at line 3314 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2

#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Msk

Definition at line 3319 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Msk

#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Pos)

0x00000004

Definition at line 3318 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Pos

#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Pos (2U)

Definition at line 3317 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3

#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Msk

Definition at line 3322 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Msk

#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Pos)

0x00000008

Definition at line 3321 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Pos

#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Pos (3U)

Definition at line 3320 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4

#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Msk

Definition at line 3325 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Msk

#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Pos)

0x00000010

Definition at line 3324 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Pos

#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Pos (4U)

Definition at line 3323 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5

#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Msk

Definition at line 3328 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Msk

#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Pos)

0x00000020

Definition at line 3327 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Pos

#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Pos (5U)

Definition at line 3326 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6

#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Msk

Definition at line 3331 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Msk

#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Pos)

0x00000040

Definition at line 3330 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Pos

#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Pos (6U)

Definition at line 3329 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7

#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Msk

Definition at line 3334 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Msk

#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Pos)

0x00000080

Definition at line 3333 of file stm32g431xx.h.

◆ DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Pos

#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Pos (7U)

Definition at line 3332 of file stm32g431xx.h.

◆ DMAMUX_RGCFR_COF0

#define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk

Definition at line 3299 of file stm32g431xx.h.

◆ DMAMUX_RGCFR_COF0_Msk

#define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos)

0x00000001

Definition at line 3298 of file stm32g431xx.h.

◆ DMAMUX_RGCFR_COF0_Pos

#define DMAMUX_RGCFR_COF0_Pos (0U)

Definition at line 3297 of file stm32g431xx.h.

◆ DMAMUX_RGCFR_COF1

#define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk

Definition at line 3302 of file stm32g431xx.h.

◆ DMAMUX_RGCFR_COF1_Msk

#define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos)

0x00000002

Definition at line 3301 of file stm32g431xx.h.

◆ DMAMUX_RGCFR_COF1_Pos

#define DMAMUX_RGCFR_COF1_Pos (1U)

Definition at line 3300 of file stm32g431xx.h.

◆ DMAMUX_RGCFR_COF2

#define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk

Definition at line 3305 of file stm32g431xx.h.

◆ DMAMUX_RGCFR_COF2_Msk

#define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos)

0x00000004

Definition at line 3304 of file stm32g431xx.h.

◆ DMAMUX_RGCFR_COF2_Pos

#define DMAMUX_RGCFR_COF2_Pos (2U)

Definition at line 3303 of file stm32g431xx.h.

◆ DMAMUX_RGCFR_COF3

#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk

Definition at line 3308 of file stm32g431xx.h.

◆ DMAMUX_RGCFR_COF3_Msk

#define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos)

0x00000008

Definition at line 3307 of file stm32g431xx.h.

◆ DMAMUX_RGCFR_COF3_Pos

#define DMAMUX_RGCFR_COF3_Pos (3U)

Definition at line 3306 of file stm32g431xx.h.

◆ DMAMUX_RGSR_OF0

#define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk

Definition at line 3285 of file stm32g431xx.h.

◆ DMAMUX_RGSR_OF0_Msk

#define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos)

0x00000001

Definition at line 3284 of file stm32g431xx.h.

◆ DMAMUX_RGSR_OF0_Pos

#define DMAMUX_RGSR_OF0_Pos (0U)

Definition at line 3283 of file stm32g431xx.h.

◆ DMAMUX_RGSR_OF1

#define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk

Definition at line 3288 of file stm32g431xx.h.

◆ DMAMUX_RGSR_OF1_Msk

#define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos)

0x00000002

Definition at line 3287 of file stm32g431xx.h.

◆ DMAMUX_RGSR_OF1_Pos

#define DMAMUX_RGSR_OF1_Pos (1U)

Definition at line 3286 of file stm32g431xx.h.

◆ DMAMUX_RGSR_OF2

#define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk

Definition at line 3291 of file stm32g431xx.h.

◆ DMAMUX_RGSR_OF2_Msk

#define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos)

0x00000004

Definition at line 3290 of file stm32g431xx.h.

◆ DMAMUX_RGSR_OF2_Pos

#define DMAMUX_RGSR_OF2_Pos (2U)

Definition at line 3289 of file stm32g431xx.h.

◆ DMAMUX_RGSR_OF3

#define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk

Definition at line 3294 of file stm32g431xx.h.

◆ DMAMUX_RGSR_OF3_Msk

#define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos)

0x00000008

Definition at line 3293 of file stm32g431xx.h.

◆ DMAMUX_RGSR_OF3_Pos

#define DMAMUX_RGSR_OF3_Pos (3U)

Definition at line 3292 of file stm32g431xx.h.

◆ DMAMUX_RGxCR_GE

#define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk

Definition at line 3265 of file stm32g431xx.h.

◆ DMAMUX_RGxCR_GE_Msk

#define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos)

0x00010000

Definition at line 3264 of file stm32g431xx.h.

◆ DMAMUX_RGxCR_GE_Pos

#define DMAMUX_RGxCR_GE_Pos (16U)

Definition at line 3263 of file stm32g431xx.h.

◆ DMAMUX_RGxCR_GNBREQ

#define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk

Definition at line 3275 of file stm32g431xx.h.

◆ DMAMUX_RGxCR_GNBREQ_0

#define DMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)

0x00080000

Definition at line 3276 of file stm32g431xx.h.

◆ DMAMUX_RGxCR_GNBREQ_1

#define DMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)

0x00100000

Definition at line 3277 of file stm32g431xx.h.

◆ DMAMUX_RGxCR_GNBREQ_2

#define DMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)

0x00200000

Definition at line 3278 of file stm32g431xx.h.

◆ DMAMUX_RGxCR_GNBREQ_3

#define DMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)

0x00400000

Definition at line 3279 of file stm32g431xx.h.

◆ DMAMUX_RGxCR_GNBREQ_4

#define DMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)

0x00800000

Definition at line 3280 of file stm32g431xx.h.

◆ DMAMUX_RGxCR_GNBREQ_Msk

#define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)

0x00F80000

Definition at line 3274 of file stm32g431xx.h.

◆ DMAMUX_RGxCR_GNBREQ_Pos

#define DMAMUX_RGxCR_GNBREQ_Pos (19U)

Definition at line 3273 of file stm32g431xx.h.

◆ DMAMUX_RGxCR_GPOL

#define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk

Definition at line 3269 of file stm32g431xx.h.

◆ DMAMUX_RGxCR_GPOL_0

#define DMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos)

0x00020000

Definition at line 3270 of file stm32g431xx.h.

◆ DMAMUX_RGxCR_GPOL_1

#define DMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos)

0x00040000

Definition at line 3271 of file stm32g431xx.h.

◆ DMAMUX_RGxCR_GPOL_Msk

#define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos)

0x00060000

Definition at line 3268 of file stm32g431xx.h.

◆ DMAMUX_RGxCR_GPOL_Pos

#define DMAMUX_RGxCR_GPOL_Pos (17U)

Definition at line 3267 of file stm32g431xx.h.

◆ DMAMUX_RGxCR_OIE

#define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk

Definition at line 3261 of file stm32g431xx.h.

◆ DMAMUX_RGxCR_OIE_Msk

#define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos)

0x00000100

Definition at line 3260 of file stm32g431xx.h.

◆ DMAMUX_RGxCR_OIE_Pos

#define DMAMUX_RGxCR_OIE_Pos (8U)

Definition at line 3259 of file stm32g431xx.h.

◆ DMAMUX_RGxCR_SIG_ID

#define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk

Definition at line 3252 of file stm32g431xx.h.

◆ DMAMUX_RGxCR_SIG_ID_0

#define DMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)

0x00000001

Definition at line 3253 of file stm32g431xx.h.

◆ DMAMUX_RGxCR_SIG_ID_1

#define DMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)

0x00000002

Definition at line 3254 of file stm32g431xx.h.

◆ DMAMUX_RGxCR_SIG_ID_2

#define DMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)

0x00000004

Definition at line 3255 of file stm32g431xx.h.

◆ DMAMUX_RGxCR_SIG_ID_3

#define DMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)

0x00000008

Definition at line 3256 of file stm32g431xx.h.

◆ DMAMUX_RGxCR_SIG_ID_4

#define DMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)

0x00000010

Definition at line 3257 of file stm32g431xx.h.

◆ DMAMUX_RGxCR_SIG_ID_Msk

#define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)

0x0000001F

Definition at line 3251 of file stm32g431xx.h.

◆ DMAMUX_RGxCR_SIG_ID_Pos

#define DMAMUX_RGxCR_SIG_ID_Pos (0U)

Definition at line 3250 of file stm32g431xx.h.

◆ EXTI_EMR1_EM0

#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk

Event Mask on line 0

Definition at line 3541 of file stm32g431xx.h.

◆ EXTI_EMR1_EM0_Msk

#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos)

0x00000001

Definition at line 3540 of file stm32g431xx.h.

◆ EXTI_EMR1_EM0_Pos

#define EXTI_EMR1_EM0_Pos (0U)

Definition at line 3539 of file stm32g431xx.h.

◆ EXTI_EMR1_EM1

#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk

Event Mask on line 1

Definition at line 3544 of file stm32g431xx.h.

◆ EXTI_EMR1_EM10

#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk

Event Mask on line 10

Definition at line 3571 of file stm32g431xx.h.

◆ EXTI_EMR1_EM10_Msk

#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos)

0x00000400

Definition at line 3570 of file stm32g431xx.h.

◆ EXTI_EMR1_EM10_Pos

#define EXTI_EMR1_EM10_Pos (10U)

Definition at line 3569 of file stm32g431xx.h.

◆ EXTI_EMR1_EM11

#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk

Event Mask on line 11

Definition at line 3574 of file stm32g431xx.h.

◆ EXTI_EMR1_EM11_Msk

#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos)

0x00000800

Definition at line 3573 of file stm32g431xx.h.

◆ EXTI_EMR1_EM11_Pos

#define EXTI_EMR1_EM11_Pos (11U)

Definition at line 3572 of file stm32g431xx.h.

◆ EXTI_EMR1_EM12

#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk

Event Mask on line 12

Definition at line 3577 of file stm32g431xx.h.

◆ EXTI_EMR1_EM12_Msk

#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos)

0x00001000

Definition at line 3576 of file stm32g431xx.h.

◆ EXTI_EMR1_EM12_Pos

#define EXTI_EMR1_EM12_Pos (12U)

Definition at line 3575 of file stm32g431xx.h.

◆ EXTI_EMR1_EM13

#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk

Event Mask on line 13

Definition at line 3580 of file stm32g431xx.h.

◆ EXTI_EMR1_EM13_Msk

#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos)

0x00002000

Definition at line 3579 of file stm32g431xx.h.

◆ EXTI_EMR1_EM13_Pos

#define EXTI_EMR1_EM13_Pos (13U)

Definition at line 3578 of file stm32g431xx.h.

◆ EXTI_EMR1_EM14

#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk

Event Mask on line 14

Definition at line 3583 of file stm32g431xx.h.

◆ EXTI_EMR1_EM14_Msk

#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos)

0x00004000

Definition at line 3582 of file stm32g431xx.h.

◆ EXTI_EMR1_EM14_Pos

#define EXTI_EMR1_EM14_Pos (14U)

Definition at line 3581 of file stm32g431xx.h.

◆ EXTI_EMR1_EM15

#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk

Event Mask on line 15

Definition at line 3586 of file stm32g431xx.h.

◆ EXTI_EMR1_EM15_Msk

#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos)

0x00008000

Definition at line 3585 of file stm32g431xx.h.

◆ EXTI_EMR1_EM15_Pos

#define EXTI_EMR1_EM15_Pos (15U)

Definition at line 3584 of file stm32g431xx.h.

◆ EXTI_EMR1_EM16

#define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk

Event Mask on line 16

Definition at line 3589 of file stm32g431xx.h.

◆ EXTI_EMR1_EM16_Msk

#define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos)

0x00010000

Definition at line 3588 of file stm32g431xx.h.

◆ EXTI_EMR1_EM16_Pos

#define EXTI_EMR1_EM16_Pos (16U)

Definition at line 3587 of file stm32g431xx.h.

◆ EXTI_EMR1_EM17

#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk

Event Mask on line 17

Definition at line 3592 of file stm32g431xx.h.

◆ EXTI_EMR1_EM17_Msk

#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos)

0x00020000

Definition at line 3591 of file stm32g431xx.h.

◆ EXTI_EMR1_EM17_Pos

#define EXTI_EMR1_EM17_Pos (17U)

Definition at line 3590 of file stm32g431xx.h.

◆ EXTI_EMR1_EM18

#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk

Event Mask on line 18

Definition at line 3595 of file stm32g431xx.h.

◆ EXTI_EMR1_EM18_Msk

#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos)

0x00040000

Definition at line 3594 of file stm32g431xx.h.

◆ EXTI_EMR1_EM18_Pos

#define EXTI_EMR1_EM18_Pos (18U)

Definition at line 3593 of file stm32g431xx.h.

◆ EXTI_EMR1_EM19

#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk

Event Mask on line 19

Definition at line 3598 of file stm32g431xx.h.

◆ EXTI_EMR1_EM19_Msk

#define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos)

0x00080000

Definition at line 3597 of file stm32g431xx.h.

◆ EXTI_EMR1_EM19_Pos

#define EXTI_EMR1_EM19_Pos (19U)

Definition at line 3596 of file stm32g431xx.h.

◆ EXTI_EMR1_EM1_Msk

#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos)

0x00000002

Definition at line 3543 of file stm32g431xx.h.

◆ EXTI_EMR1_EM1_Pos

#define EXTI_EMR1_EM1_Pos (1U)

Definition at line 3542 of file stm32g431xx.h.

◆ EXTI_EMR1_EM2

#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk

Event Mask on line 2

Definition at line 3547 of file stm32g431xx.h.

◆ EXTI_EMR1_EM20

#define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk

Event Mask on line 20

Definition at line 3601 of file stm32g431xx.h.

◆ EXTI_EMR1_EM20_Msk

#define EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos)

0x00100000

Definition at line 3600 of file stm32g431xx.h.

◆ EXTI_EMR1_EM20_Pos

#define EXTI_EMR1_EM20_Pos (20U)

Definition at line 3599 of file stm32g431xx.h.

◆ EXTI_EMR1_EM21

#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk

Event Mask on line 21

Definition at line 3604 of file stm32g431xx.h.

◆ EXTI_EMR1_EM21_Msk

#define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos)

0x00200000

Definition at line 3603 of file stm32g431xx.h.

◆ EXTI_EMR1_EM21_Pos

#define EXTI_EMR1_EM21_Pos (21U)

Definition at line 3602 of file stm32g431xx.h.

◆ EXTI_EMR1_EM22

#define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk

Event Mask on line 22

Definition at line 3607 of file stm32g431xx.h.

◆ EXTI_EMR1_EM22_Msk

#define EXTI_EMR1_EM22_Msk (0x1UL << EXTI_EMR1_EM22_Pos)

0x00400000

Definition at line 3606 of file stm32g431xx.h.

◆ EXTI_EMR1_EM22_Pos

#define EXTI_EMR1_EM22_Pos (22U)

Definition at line 3605 of file stm32g431xx.h.

◆ EXTI_EMR1_EM23

#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk

Event Mask on line 23

Definition at line 3610 of file stm32g431xx.h.

◆ EXTI_EMR1_EM23_Msk

#define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos)

0x00800000

Definition at line 3609 of file stm32g431xx.h.

◆ EXTI_EMR1_EM23_Pos

#define EXTI_EMR1_EM23_Pos (23U)

Definition at line 3608 of file stm32g431xx.h.

◆ EXTI_EMR1_EM24

#define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk

Event Mask on line 24

Definition at line 3613 of file stm32g431xx.h.

◆ EXTI_EMR1_EM24_Msk

#define EXTI_EMR1_EM24_Msk (0x1UL << EXTI_EMR1_EM24_Pos)

0x01000000

Definition at line 3612 of file stm32g431xx.h.

◆ EXTI_EMR1_EM24_Pos

#define EXTI_EMR1_EM24_Pos (24U)

Definition at line 3611 of file stm32g431xx.h.

◆ EXTI_EMR1_EM25

#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk

Event Mask on line 25

Definition at line 3616 of file stm32g431xx.h.

◆ EXTI_EMR1_EM25_Msk

#define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos)

0x02000000

Definition at line 3615 of file stm32g431xx.h.

◆ EXTI_EMR1_EM25_Pos

#define EXTI_EMR1_EM25_Pos (25U)

Definition at line 3614 of file stm32g431xx.h.

◆ EXTI_EMR1_EM26

#define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk

Event Mask on line 26

Definition at line 3619 of file stm32g431xx.h.

◆ EXTI_EMR1_EM26_Msk

#define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos)

0x04000000

Definition at line 3618 of file stm32g431xx.h.

◆ EXTI_EMR1_EM26_Pos

#define EXTI_EMR1_EM26_Pos (26U)

Definition at line 3617 of file stm32g431xx.h.

◆ EXTI_EMR1_EM27

#define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk

Event Mask on line 27

Definition at line 3622 of file stm32g431xx.h.

◆ EXTI_EMR1_EM27_Msk

#define EXTI_EMR1_EM27_Msk (0x1UL << EXTI_EMR1_EM27_Pos)

0x08000000

Definition at line 3621 of file stm32g431xx.h.

◆ EXTI_EMR1_EM27_Pos

#define EXTI_EMR1_EM27_Pos (27U)

Definition at line 3620 of file stm32g431xx.h.

◆ EXTI_EMR1_EM28

#define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk

Event Mask on line 28

Definition at line 3625 of file stm32g431xx.h.

◆ EXTI_EMR1_EM28_Msk

#define EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos)

0x10000000

Definition at line 3624 of file stm32g431xx.h.

◆ EXTI_EMR1_EM28_Pos

#define EXTI_EMR1_EM28_Pos (28U)

Definition at line 3623 of file stm32g431xx.h.

◆ EXTI_EMR1_EM29

#define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk

Event Mask on line 29

Definition at line 3628 of file stm32g431xx.h.

◆ EXTI_EMR1_EM29_Msk

#define EXTI_EMR1_EM29_Msk (0x1UL << EXTI_EMR1_EM29_Pos)

0x20000000

Definition at line 3627 of file stm32g431xx.h.

◆ EXTI_EMR1_EM29_Pos

#define EXTI_EMR1_EM29_Pos (29U)

Definition at line 3626 of file stm32g431xx.h.

◆ EXTI_EMR1_EM2_Msk

#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos)

0x00000004

Definition at line 3546 of file stm32g431xx.h.

◆ EXTI_EMR1_EM2_Pos

#define EXTI_EMR1_EM2_Pos (2U)

Definition at line 3545 of file stm32g431xx.h.

◆ EXTI_EMR1_EM3

#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk

Event Mask on line 3

Definition at line 3550 of file stm32g431xx.h.

◆ EXTI_EMR1_EM30

#define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk

Event Mask on line 30

Definition at line 3631 of file stm32g431xx.h.

◆ EXTI_EMR1_EM30_Msk

#define EXTI_EMR1_EM30_Msk (0x1UL << EXTI_EMR1_EM30_Pos)

0x40000000

Definition at line 3630 of file stm32g431xx.h.

◆ EXTI_EMR1_EM30_Pos

#define EXTI_EMR1_EM30_Pos (30U)

Definition at line 3629 of file stm32g431xx.h.

◆ EXTI_EMR1_EM3_Msk

#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos)

0x00000008

Definition at line 3549 of file stm32g431xx.h.

◆ EXTI_EMR1_EM3_Pos

#define EXTI_EMR1_EM3_Pos (3U)

Definition at line 3548 of file stm32g431xx.h.

◆ EXTI_EMR1_EM4

#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk

Event Mask on line 4

Definition at line 3553 of file stm32g431xx.h.

◆ EXTI_EMR1_EM4_Msk

#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos)

0x00000010

Definition at line 3552 of file stm32g431xx.h.

◆ EXTI_EMR1_EM4_Pos

#define EXTI_EMR1_EM4_Pos (4U)

Definition at line 3551 of file stm32g431xx.h.

◆ EXTI_EMR1_EM5

#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk

Event Mask on line 5

Definition at line 3556 of file stm32g431xx.h.

◆ EXTI_EMR1_EM5_Msk

#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos)

0x00000020

Definition at line 3555 of file stm32g431xx.h.

◆ EXTI_EMR1_EM5_Pos

#define EXTI_EMR1_EM5_Pos (5U)

Definition at line 3554 of file stm32g431xx.h.

◆ EXTI_EMR1_EM6

#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk

Event Mask on line 6

Definition at line 3559 of file stm32g431xx.h.

◆ EXTI_EMR1_EM6_Msk

#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos)

0x00000040

Definition at line 3558 of file stm32g431xx.h.

◆ EXTI_EMR1_EM6_Pos

#define EXTI_EMR1_EM6_Pos (6U)

Definition at line 3557 of file stm32g431xx.h.

◆ EXTI_EMR1_EM7

#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk

Event Mask on line 7

Definition at line 3562 of file stm32g431xx.h.

◆ EXTI_EMR1_EM7_Msk

#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos)

0x00000080

Definition at line 3561 of file stm32g431xx.h.

◆ EXTI_EMR1_EM7_Pos

#define EXTI_EMR1_EM7_Pos (7U)

Definition at line 3560 of file stm32g431xx.h.

◆ EXTI_EMR1_EM8

#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk

Event Mask on line 8

Definition at line 3565 of file stm32g431xx.h.

◆ EXTI_EMR1_EM8_Msk

#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos)

0x00000100

Definition at line 3564 of file stm32g431xx.h.

◆ EXTI_EMR1_EM8_Pos

#define EXTI_EMR1_EM8_Pos (8U)

Definition at line 3563 of file stm32g431xx.h.

◆ EXTI_EMR1_EM9

#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk

Event Mask on line 9

Definition at line 3568 of file stm32g431xx.h.

◆ EXTI_EMR1_EM9_Msk

#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos)

0x00000200

Definition at line 3567 of file stm32g431xx.h.

◆ EXTI_EMR1_EM9_Pos

#define EXTI_EMR1_EM9_Pos (9U)

Definition at line 3566 of file stm32g431xx.h.

◆ EXTI_EMR2_EM

#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk

Interrupt Mask all

Definition at line 3979 of file stm32g431xx.h.

◆ EXTI_EMR2_EM34

#define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk

Event Mask on line 34

Definition at line 3958 of file stm32g431xx.h.

◆ EXTI_EMR2_EM34_Msk

#define EXTI_EMR2_EM34_Msk (0x1UL << EXTI_EMR2_EM34_Pos)

0x00000004

Definition at line 3957 of file stm32g431xx.h.

◆ EXTI_EMR2_EM34_Pos

#define EXTI_EMR2_EM34_Pos (2U)

Definition at line 3956 of file stm32g431xx.h.

◆ EXTI_EMR2_EM36

#define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk

Event Mask on line 36

Definition at line 3961 of file stm32g431xx.h.

◆ EXTI_EMR2_EM36_Msk

#define EXTI_EMR2_EM36_Msk (0x1UL << EXTI_EMR2_EM36_Pos)

0x00000010

Definition at line 3960 of file stm32g431xx.h.

◆ EXTI_EMR2_EM36_Pos

#define EXTI_EMR2_EM36_Pos (4U)

Definition at line 3959 of file stm32g431xx.h.

◆ EXTI_EMR2_EM37

#define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk

Event Mask on line 37

Definition at line 3964 of file stm32g431xx.h.

◆ EXTI_EMR2_EM37_Msk

#define EXTI_EMR2_EM37_Msk (0x1UL << EXTI_EMR2_EM37_Pos)

0x00000020

Definition at line 3963 of file stm32g431xx.h.

◆ EXTI_EMR2_EM37_Pos

#define EXTI_EMR2_EM37_Pos (5U)

Definition at line 3962 of file stm32g431xx.h.

◆ EXTI_EMR2_EM38

#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk

Event Mask on line 38

Definition at line 3967 of file stm32g431xx.h.

◆ EXTI_EMR2_EM38_Msk

#define EXTI_EMR2_EM38_Msk (0x1UL << EXTI_EMR2_EM38_Pos)

0x00000040

Definition at line 3966 of file stm32g431xx.h.

◆ EXTI_EMR2_EM38_Pos

#define EXTI_EMR2_EM38_Pos (6U)

Definition at line 3965 of file stm32g431xx.h.

◆ EXTI_EMR2_EM39

#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk

Event Mask on line 39

Definition at line 3970 of file stm32g431xx.h.

◆ EXTI_EMR2_EM39_Msk

#define EXTI_EMR2_EM39_Msk (0x1UL << EXTI_EMR2_EM39_Pos)

0x00000080

Definition at line 3969 of file stm32g431xx.h.

◆ EXTI_EMR2_EM39_Pos

#define EXTI_EMR2_EM39_Pos (7U)

Definition at line 3968 of file stm32g431xx.h.

◆ EXTI_EMR2_EM40

#define EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk

Event Mask on line 40

Definition at line 3973 of file stm32g431xx.h.

◆ EXTI_EMR2_EM40_Msk

#define EXTI_EMR2_EM40_Msk (0x1UL << EXTI_EMR2_EM40_Pos)

0x00000100

Definition at line 3972 of file stm32g431xx.h.

◆ EXTI_EMR2_EM40_Pos

#define EXTI_EMR2_EM40_Pos (8U)

Definition at line 3971 of file stm32g431xx.h.

◆ EXTI_EMR2_EM41

#define EXTI_EMR2_EM41 EXTI_EMR2_EM41_Msk

Event Mask on line 41

Definition at line 3976 of file stm32g431xx.h.

◆ EXTI_EMR2_EM41_Msk

#define EXTI_EMR2_EM41_Msk (0x1UL << EXTI_EMR2_EM41_Pos)

0x00000200

Definition at line 3975 of file stm32g431xx.h.

◆ EXTI_EMR2_EM41_Pos

#define EXTI_EMR2_EM41_Pos (9U)

Definition at line 3974 of file stm32g431xx.h.

◆ EXTI_EMR2_EM_Msk

#define EXTI_EMR2_EM_Msk (0x3F4UL << EXTI_EMR2_EM_Pos)

0x000003F4

Definition at line 3978 of file stm32g431xx.h.

◆ EXTI_EMR2_EM_Pos

#define EXTI_EMR2_EM_Pos (0U)

Definition at line 3977 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT0

#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk

Falling trigger event configuration bit of line 0

Definition at line 3710 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT0_Msk

#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos)

0x00000001

Definition at line 3709 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT0_Pos

#define EXTI_FTSR1_FT0_Pos (0U)

Definition at line 3708 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT1

#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk

Falling trigger event configuration bit of line 1

Definition at line 3713 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT10

#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk

Falling trigger event configuration bit of line 10

Definition at line 3740 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT10_Msk

#define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos)

0x00000400

Definition at line 3739 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT10_Pos

#define EXTI_FTSR1_FT10_Pos (10U)

Definition at line 3738 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT11

#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk

Falling trigger event configuration bit of line 11

Definition at line 3743 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT11_Msk

#define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos)

0x00000800

Definition at line 3742 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT11_Pos

#define EXTI_FTSR1_FT11_Pos (11U)

Definition at line 3741 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT12

#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk

Falling trigger event configuration bit of line 12

Definition at line 3746 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT12_Msk

#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos)

0x00001000

Definition at line 3745 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT12_Pos

#define EXTI_FTSR1_FT12_Pos (12U)

Definition at line 3744 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT13

#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk

Falling trigger event configuration bit of line 13

Definition at line 3749 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT13_Msk

#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos)

0x00002000

Definition at line 3748 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT13_Pos

#define EXTI_FTSR1_FT13_Pos (13U)

Definition at line 3747 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT14

#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk

Falling trigger event configuration bit of line 14

Definition at line 3752 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT14_Msk

#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos)

0x00004000

Definition at line 3751 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT14_Pos

#define EXTI_FTSR1_FT14_Pos (14U)

Definition at line 3750 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT15

#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk

Falling trigger event configuration bit of line 15

Definition at line 3755 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT15_Msk

#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos)

0x00008000

Definition at line 3754 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT15_Pos

#define EXTI_FTSR1_FT15_Pos (15U)

Definition at line 3753 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT16

#define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk

Falling trigger event configuration bit of line 16

Definition at line 3758 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT16_Msk

#define EXTI_FTSR1_FT16_Msk (0x1UL << EXTI_FTSR1_FT16_Pos)

0x00010000

Definition at line 3757 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT16_Pos

#define EXTI_FTSR1_FT16_Pos (16U)

Definition at line 3756 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT17

#define EXTI_FTSR1_FT17 EXTI_FTSR1_FT17_Msk

Falling trigger event configuration bit of line 17

Definition at line 3761 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT17_Msk

#define EXTI_FTSR1_FT17_Msk (0x1UL << EXTI_FTSR1_FT17_Pos)

0x00020000

Definition at line 3760 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT17_Pos

#define EXTI_FTSR1_FT17_Pos (17U)

Definition at line 3759 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT19

#define EXTI_FTSR1_FT19 EXTI_FTSR1_FT19_Msk

Falling trigger event configuration bit of line 19

Definition at line 3764 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT19_Msk

#define EXTI_FTSR1_FT19_Msk (0x1UL << EXTI_FTSR1_FT19_Pos)

0x00080000

Definition at line 3763 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT19_Pos

#define EXTI_FTSR1_FT19_Pos (19U)

Definition at line 3762 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT1_Msk

#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos)

0x00000002

Definition at line 3712 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT1_Pos

#define EXTI_FTSR1_FT1_Pos (1U)

Definition at line 3711 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT2

#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk

Falling trigger event configuration bit of line 2

Definition at line 3716 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT20

#define EXTI_FTSR1_FT20 EXTI_FTSR1_FT20_Msk

Falling trigger event configuration bit of line 20

Definition at line 3767 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT20_Msk

#define EXTI_FTSR1_FT20_Msk (0x1UL << EXTI_FTSR1_FT20_Pos)

0x00100000

Definition at line 3766 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT20_Pos

#define EXTI_FTSR1_FT20_Pos (20U)

Definition at line 3765 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT21

#define EXTI_FTSR1_FT21 EXTI_FTSR1_FT21_Msk

Falling trigger event configuration bit of line 21

Definition at line 3770 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT21_Msk

#define EXTI_FTSR1_FT21_Msk (0x1UL << EXTI_FTSR1_FT21_Pos)

0x00200000

Definition at line 3769 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT21_Pos

#define EXTI_FTSR1_FT21_Pos (21U)

Definition at line 3768 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT22

#define EXTI_FTSR1_FT22 EXTI_FTSR1_FT22_Msk

Falling trigger event configuration bit of line 22

Definition at line 3773 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT22_Msk

#define EXTI_FTSR1_FT22_Msk (0x1UL << EXTI_FTSR1_FT22_Pos)

0x00400000

Definition at line 3772 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT22_Pos

#define EXTI_FTSR1_FT22_Pos (22U)

Definition at line 3771 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT29

#define EXTI_FTSR1_FT29 EXTI_FTSR1_FT29_Msk

Falling trigger event configuration bit of line 29

Definition at line 3776 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT29_Msk

#define EXTI_FTSR1_FT29_Msk (0x1UL << EXTI_FTSR1_FT29_Pos)

0x20000000

Definition at line 3775 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT29_Pos

#define EXTI_FTSR1_FT29_Pos (29U)

Definition at line 3774 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT2_Msk

#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos)

0x00000004

Definition at line 3715 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT2_Pos

#define EXTI_FTSR1_FT2_Pos (2U)

Definition at line 3714 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT3

#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk

Falling trigger event configuration bit of line 3

Definition at line 3719 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT30

#define EXTI_FTSR1_FT30 EXTI_FTSR1_FT30_Msk

Falling trigger event configuration bit of line 30

Definition at line 3779 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT30_Msk

#define EXTI_FTSR1_FT30_Msk (0x1UL << EXTI_FTSR1_FT30_Pos)

0x40000000

Definition at line 3778 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT30_Pos

#define EXTI_FTSR1_FT30_Pos (30U)

Definition at line 3777 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT3_Msk

#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos)

0x00000008

Definition at line 3718 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT3_Pos

#define EXTI_FTSR1_FT3_Pos (3U)

Definition at line 3717 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT4

#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk

Falling trigger event configuration bit of line 4

Definition at line 3722 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT4_Msk

#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos)

0x00000010

Definition at line 3721 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT4_Pos

#define EXTI_FTSR1_FT4_Pos (4U)

Definition at line 3720 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT5

#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk

Falling trigger event configuration bit of line 5

Definition at line 3725 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT5_Msk

#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos)

0x00000020

Definition at line 3724 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT5_Pos

#define EXTI_FTSR1_FT5_Pos (5U)

Definition at line 3723 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT6

#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk

Falling trigger event configuration bit of line 6

Definition at line 3728 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT6_Msk

#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos)

0x00000040

Definition at line 3727 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT6_Pos

#define EXTI_FTSR1_FT6_Pos (6U)

Definition at line 3726 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT7

#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk

Falling trigger event configuration bit of line 7

Definition at line 3731 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT7_Msk

#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos)

0x00000080

Definition at line 3730 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT7_Pos

#define EXTI_FTSR1_FT7_Pos (7U)

Definition at line 3729 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT8

#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk

Falling trigger event configuration bit of line 8

Definition at line 3734 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT8_Msk

#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos)

0x00000100

Definition at line 3733 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT8_Pos

#define EXTI_FTSR1_FT8_Pos (8U)

Definition at line 3732 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT9

#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk

Falling trigger event configuration bit of line 9

Definition at line 3737 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT9_Msk

#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos)

0x00000200

Definition at line 3736 of file stm32g431xx.h.

◆ EXTI_FTSR1_FT9_Pos

#define EXTI_FTSR1_FT9_Pos (9U)

Definition at line 3735 of file stm32g431xx.h.

◆ EXTI_FTSR2_FT38

#define EXTI_FTSR2_FT38 EXTI_FTSR2_FT38_Msk

Falling trigger event configuration bit of line 37

Definition at line 3998 of file stm32g431xx.h.

◆ EXTI_FTSR2_FT38_Msk

#define EXTI_FTSR2_FT38_Msk (0x1UL << EXTI_FTSR2_FT38_Pos)

0x00000040

Definition at line 3997 of file stm32g431xx.h.

◆ EXTI_FTSR2_FT38_Pos

#define EXTI_FTSR2_FT38_Pos (6U)

Definition at line 3996 of file stm32g431xx.h.

◆ EXTI_FTSR2_FT39

#define EXTI_FTSR2_FT39 EXTI_FTSR2_FT39_Msk

Falling trigger event configuration bit of line 39

Definition at line 4001 of file stm32g431xx.h.

◆ EXTI_FTSR2_FT39_Msk

#define EXTI_FTSR2_FT39_Msk (0x1UL << EXTI_FTSR2_FT39_Pos)

0x00000080

Definition at line 4000 of file stm32g431xx.h.

◆ EXTI_FTSR2_FT39_Pos

#define EXTI_FTSR2_FT39_Pos (7U)

Definition at line 3999 of file stm32g431xx.h.

◆ EXTI_FTSR2_FT40

#define EXTI_FTSR2_FT40 EXTI_FTSR2_FT40_Msk

Falling trigger event configuration bit of line 40

Definition at line 4004 of file stm32g431xx.h.

◆ EXTI_FTSR2_FT40_Msk

#define EXTI_FTSR2_FT40_Msk (0x1UL << EXTI_FTSR2_FT40_Pos)

0x00000100

Definition at line 4003 of file stm32g431xx.h.

◆ EXTI_FTSR2_FT40_Pos

#define EXTI_FTSR2_FT40_Pos (8U)

Definition at line 4002 of file stm32g431xx.h.

◆ EXTI_FTSR2_FT41

#define EXTI_FTSR2_FT41 EXTI_FTSR2_FT41_Msk

Falling trigger event configuration bit of line 41

Definition at line 4007 of file stm32g431xx.h.

◆ EXTI_FTSR2_FT41_Msk

#define EXTI_FTSR2_FT41_Msk (0x1UL << EXTI_FTSR2_FT41_Pos)

0x00000200

Definition at line 4006 of file stm32g431xx.h.

◆ EXTI_FTSR2_FT41_Pos

#define EXTI_FTSR2_FT41_Pos (9U)

Definition at line 4005 of file stm32g431xx.h.

◆ EXTI_IMR1_IM

#define EXTI_IMR1_IM EXTI_IMR1_IM_Msk

Interrupt Mask All

Definition at line 3536 of file stm32g431xx.h.

◆ EXTI_IMR1_IM0

#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk

Interrupt Mask on line 0

Definition at line 3443 of file stm32g431xx.h.

◆ EXTI_IMR1_IM0_Msk

#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos)

0x00000001

Definition at line 3442 of file stm32g431xx.h.

◆ EXTI_IMR1_IM0_Pos

#define EXTI_IMR1_IM0_Pos (0U)

Definition at line 3441 of file stm32g431xx.h.

◆ EXTI_IMR1_IM1

#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk

Interrupt Mask on line 1

Definition at line 3446 of file stm32g431xx.h.

◆ EXTI_IMR1_IM10

#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk

Interrupt Mask on line 10

Definition at line 3473 of file stm32g431xx.h.

◆ EXTI_IMR1_IM10_Msk

#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos)

0x00000400

Definition at line 3472 of file stm32g431xx.h.

◆ EXTI_IMR1_IM10_Pos

#define EXTI_IMR1_IM10_Pos (10U)

Definition at line 3471 of file stm32g431xx.h.

◆ EXTI_IMR1_IM11

#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk

Interrupt Mask on line 11

Definition at line 3476 of file stm32g431xx.h.

◆ EXTI_IMR1_IM11_Msk

#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos)

0x00000800

Definition at line 3475 of file stm32g431xx.h.

◆ EXTI_IMR1_IM11_Pos

#define EXTI_IMR1_IM11_Pos (11U)

Definition at line 3474 of file stm32g431xx.h.

◆ EXTI_IMR1_IM12

#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk

Interrupt Mask on line 12

Definition at line 3479 of file stm32g431xx.h.

◆ EXTI_IMR1_IM12_Msk

#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos)

0x00001000

Definition at line 3478 of file stm32g431xx.h.

◆ EXTI_IMR1_IM12_Pos

#define EXTI_IMR1_IM12_Pos (12U)

Definition at line 3477 of file stm32g431xx.h.

◆ EXTI_IMR1_IM13

#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk

Interrupt Mask on line 13

Definition at line 3482 of file stm32g431xx.h.

◆ EXTI_IMR1_IM13_Msk

#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos)

0x00002000

Definition at line 3481 of file stm32g431xx.h.

◆ EXTI_IMR1_IM13_Pos

#define EXTI_IMR1_IM13_Pos (13U)

Definition at line 3480 of file stm32g431xx.h.

◆ EXTI_IMR1_IM14

#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk

Interrupt Mask on line 14

Definition at line 3485 of file stm32g431xx.h.

◆ EXTI_IMR1_IM14_Msk

#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos)

0x00004000

Definition at line 3484 of file stm32g431xx.h.

◆ EXTI_IMR1_IM14_Pos

#define EXTI_IMR1_IM14_Pos (14U)

Definition at line 3483 of file stm32g431xx.h.

◆ EXTI_IMR1_IM15

#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk

Interrupt Mask on line 15

Definition at line 3488 of file stm32g431xx.h.

◆ EXTI_IMR1_IM15_Msk

#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos)

0x00008000

Definition at line 3487 of file stm32g431xx.h.

◆ EXTI_IMR1_IM15_Pos

#define EXTI_IMR1_IM15_Pos (15U)

Definition at line 3486 of file stm32g431xx.h.

◆ EXTI_IMR1_IM16

#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk

Interrupt Mask on line 16

Definition at line 3491 of file stm32g431xx.h.

◆ EXTI_IMR1_IM16_Msk

#define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos)

0x00010000

Definition at line 3490 of file stm32g431xx.h.

◆ EXTI_IMR1_IM16_Pos

#define EXTI_IMR1_IM16_Pos (16U)

Definition at line 3489 of file stm32g431xx.h.

◆ EXTI_IMR1_IM17

#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk

Interrupt Mask on line 17

Definition at line 3494 of file stm32g431xx.h.

◆ EXTI_IMR1_IM17_Msk

#define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos)

0x00020000

Definition at line 3493 of file stm32g431xx.h.

◆ EXTI_IMR1_IM17_Pos

#define EXTI_IMR1_IM17_Pos (17U)

Definition at line 3492 of file stm32g431xx.h.

◆ EXTI_IMR1_IM18

#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk

Interrupt Mask on line 18

Definition at line 3497 of file stm32g431xx.h.

◆ EXTI_IMR1_IM18_Msk

#define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos)

0x00040000

Definition at line 3496 of file stm32g431xx.h.

◆ EXTI_IMR1_IM18_Pos

#define EXTI_IMR1_IM18_Pos (18U)

Definition at line 3495 of file stm32g431xx.h.

◆ EXTI_IMR1_IM19

#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk

Interrupt Mask on line 19

Definition at line 3500 of file stm32g431xx.h.

◆ EXTI_IMR1_IM19_Msk

#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos)

0x00080000

Definition at line 3499 of file stm32g431xx.h.

◆ EXTI_IMR1_IM19_Pos

#define EXTI_IMR1_IM19_Pos (19U)

Definition at line 3498 of file stm32g431xx.h.

◆ EXTI_IMR1_IM1_Msk

#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos)

0x00000002

Definition at line 3445 of file stm32g431xx.h.

◆ EXTI_IMR1_IM1_Pos

#define EXTI_IMR1_IM1_Pos (1U)

Definition at line 3444 of file stm32g431xx.h.

◆ EXTI_IMR1_IM2

#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk

Interrupt Mask on line 2

Definition at line 3449 of file stm32g431xx.h.

◆ EXTI_IMR1_IM20

#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk

Interrupt Mask on line 20

Definition at line 3503 of file stm32g431xx.h.

◆ EXTI_IMR1_IM20_Msk

#define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos)

0x00100000

Definition at line 3502 of file stm32g431xx.h.

◆ EXTI_IMR1_IM20_Pos

#define EXTI_IMR1_IM20_Pos (20U)

Definition at line 3501 of file stm32g431xx.h.

◆ EXTI_IMR1_IM21

#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk

Interrupt Mask on line 21

Definition at line 3506 of file stm32g431xx.h.

◆ EXTI_IMR1_IM21_Msk

#define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos)

0x00200000

Definition at line 3505 of file stm32g431xx.h.

◆ EXTI_IMR1_IM21_Pos

#define EXTI_IMR1_IM21_Pos (21U)

Definition at line 3504 of file stm32g431xx.h.

◆ EXTI_IMR1_IM22

#define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk

Interrupt Mask on line 22

Definition at line 3509 of file stm32g431xx.h.

◆ EXTI_IMR1_IM22_Msk

#define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos)

0x00400000

Definition at line 3508 of file stm32g431xx.h.

◆ EXTI_IMR1_IM22_Pos

#define EXTI_IMR1_IM22_Pos (22U)

Definition at line 3507 of file stm32g431xx.h.

◆ EXTI_IMR1_IM23

#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk

Interrupt Mask on line 23

Definition at line 3512 of file stm32g431xx.h.

◆ EXTI_IMR1_IM23_Msk

#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos)

0x00800000

Definition at line 3511 of file stm32g431xx.h.

◆ EXTI_IMR1_IM23_Pos

#define EXTI_IMR1_IM23_Pos (23U)

Definition at line 3510 of file stm32g431xx.h.

◆ EXTI_IMR1_IM24

#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk

Interrupt Mask on line 24

Definition at line 3515 of file stm32g431xx.h.

◆ EXTI_IMR1_IM24_Msk

#define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos)

0x01000000

Definition at line 3514 of file stm32g431xx.h.

◆ EXTI_IMR1_IM24_Pos

#define EXTI_IMR1_IM24_Pos (24U)

Definition at line 3513 of file stm32g431xx.h.

◆ EXTI_IMR1_IM25

#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk

Interrupt Mask on line 25

Definition at line 3518 of file stm32g431xx.h.

◆ EXTI_IMR1_IM25_Msk

#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos)

0x02000000

Definition at line 3517 of file stm32g431xx.h.

◆ EXTI_IMR1_IM25_Pos

#define EXTI_IMR1_IM25_Pos (25U)

Definition at line 3516 of file stm32g431xx.h.

◆ EXTI_IMR1_IM26

#define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk

Interrupt Mask on line 26

Definition at line 3521 of file stm32g431xx.h.

◆ EXTI_IMR1_IM26_Msk

#define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos)

0x04000000

Definition at line 3520 of file stm32g431xx.h.

◆ EXTI_IMR1_IM26_Pos

#define EXTI_IMR1_IM26_Pos (26U)

Definition at line 3519 of file stm32g431xx.h.

◆ EXTI_IMR1_IM27

#define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk

Interrupt Mask on line 27

Definition at line 3524 of file stm32g431xx.h.

◆ EXTI_IMR1_IM27_Msk

#define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos)

0x08000000

Definition at line 3523 of file stm32g431xx.h.

◆ EXTI_IMR1_IM27_Pos

#define EXTI_IMR1_IM27_Pos (27U)

Definition at line 3522 of file stm32g431xx.h.

◆ EXTI_IMR1_IM28

#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk

Interrupt Mask on line 28

Definition at line 3527 of file stm32g431xx.h.

◆ EXTI_IMR1_IM28_Msk

#define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos)

0x10000000

Definition at line 3526 of file stm32g431xx.h.

◆ EXTI_IMR1_IM28_Pos

#define EXTI_IMR1_IM28_Pos (28U)

Definition at line 3525 of file stm32g431xx.h.

◆ EXTI_IMR1_IM29

#define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk

Interrupt Mask on line 29

Definition at line 3530 of file stm32g431xx.h.

◆ EXTI_IMR1_IM29_Msk

#define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos)

0x20000000

Definition at line 3529 of file stm32g431xx.h.

◆ EXTI_IMR1_IM29_Pos

#define EXTI_IMR1_IM29_Pos (29U)

Definition at line 3528 of file stm32g431xx.h.

◆ EXTI_IMR1_IM2_Msk

#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos)

0x00000004

Definition at line 3448 of file stm32g431xx.h.

◆ EXTI_IMR1_IM2_Pos

#define EXTI_IMR1_IM2_Pos (2U)

Definition at line 3447 of file stm32g431xx.h.

◆ EXTI_IMR1_IM3

#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk

Interrupt Mask on line 3

Definition at line 3452 of file stm32g431xx.h.

◆ EXTI_IMR1_IM30

#define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk

Interrupt Mask on line 30

Definition at line 3533 of file stm32g431xx.h.

◆ EXTI_IMR1_IM30_Msk

#define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos)

0x40000000

Definition at line 3532 of file stm32g431xx.h.

◆ EXTI_IMR1_IM30_Pos

#define EXTI_IMR1_IM30_Pos (30U)

Definition at line 3531 of file stm32g431xx.h.

◆ EXTI_IMR1_IM3_Msk

#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos)

0x00000008

Definition at line 3451 of file stm32g431xx.h.

◆ EXTI_IMR1_IM3_Pos

#define EXTI_IMR1_IM3_Pos (3U)

Definition at line 3450 of file stm32g431xx.h.

◆ EXTI_IMR1_IM4

#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk

Interrupt Mask on line 4

Definition at line 3455 of file stm32g431xx.h.

◆ EXTI_IMR1_IM4_Msk

#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos)

0x00000010

Definition at line 3454 of file stm32g431xx.h.

◆ EXTI_IMR1_IM4_Pos

#define EXTI_IMR1_IM4_Pos (4U)

Definition at line 3453 of file stm32g431xx.h.

◆ EXTI_IMR1_IM5

#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk

Interrupt Mask on line 5

Definition at line 3458 of file stm32g431xx.h.

◆ EXTI_IMR1_IM5_Msk

#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos)

0x00000020

Definition at line 3457 of file stm32g431xx.h.

◆ EXTI_IMR1_IM5_Pos

#define EXTI_IMR1_IM5_Pos (5U)

Definition at line 3456 of file stm32g431xx.h.

◆ EXTI_IMR1_IM6

#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk

Interrupt Mask on line 6

Definition at line 3461 of file stm32g431xx.h.

◆ EXTI_IMR1_IM6_Msk

#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos)

0x00000040

Definition at line 3460 of file stm32g431xx.h.

◆ EXTI_IMR1_IM6_Pos

#define EXTI_IMR1_IM6_Pos (6U)

Definition at line 3459 of file stm32g431xx.h.

◆ EXTI_IMR1_IM7

#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk

Interrupt Mask on line 7

Definition at line 3464 of file stm32g431xx.h.

◆ EXTI_IMR1_IM7_Msk

#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos)

0x00000080

Definition at line 3463 of file stm32g431xx.h.

◆ EXTI_IMR1_IM7_Pos

#define EXTI_IMR1_IM7_Pos (7U)

Definition at line 3462 of file stm32g431xx.h.

◆ EXTI_IMR1_IM8

#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk

Interrupt Mask on line 8

Definition at line 3467 of file stm32g431xx.h.

◆ EXTI_IMR1_IM8_Msk

#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos)

0x00000100

Definition at line 3466 of file stm32g431xx.h.

◆ EXTI_IMR1_IM8_Pos

#define EXTI_IMR1_IM8_Pos (8U)

Definition at line 3465 of file stm32g431xx.h.

◆ EXTI_IMR1_IM9

#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk

Interrupt Mask on line 9

Definition at line 3470 of file stm32g431xx.h.

◆ EXTI_IMR1_IM9_Msk

#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos)

0x00000200

Definition at line 3469 of file stm32g431xx.h.

◆ EXTI_IMR1_IM9_Pos

#define EXTI_IMR1_IM9_Pos (9U)

Definition at line 3468 of file stm32g431xx.h.

◆ EXTI_IMR1_IM_Msk

#define EXTI_IMR1_IM_Msk (0x7FFFFFFFUL << EXTI_IMR1_IM_Pos)

0x7FFFFFFF

Definition at line 3535 of file stm32g431xx.h.

◆ EXTI_IMR1_IM_Pos

#define EXTI_IMR1_IM_Pos (0U)

Definition at line 3534 of file stm32g431xx.h.

◆ EXTI_IMR2_IM

#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk

Interrupt Mask all

Definition at line 3953 of file stm32g431xx.h.

◆ EXTI_IMR2_IM34

#define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk

Interrupt Mask on line 34

Definition at line 3932 of file stm32g431xx.h.

◆ EXTI_IMR2_IM34_Msk

#define EXTI_IMR2_IM34_Msk (0x1UL << EXTI_IMR2_IM34_Pos)

0x00000004

Definition at line 3931 of file stm32g431xx.h.

◆ EXTI_IMR2_IM34_Pos

#define EXTI_IMR2_IM34_Pos (2U)

Definition at line 3930 of file stm32g431xx.h.

◆ EXTI_IMR2_IM36

#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk

Interrupt Mask on line 36

Definition at line 3935 of file stm32g431xx.h.

◆ EXTI_IMR2_IM36_Msk

#define EXTI_IMR2_IM36_Msk (0x1UL << EXTI_IMR2_IM36_Pos)

0x00000010

Definition at line 3934 of file stm32g431xx.h.

◆ EXTI_IMR2_IM36_Pos

#define EXTI_IMR2_IM36_Pos (4U)

Definition at line 3933 of file stm32g431xx.h.

◆ EXTI_IMR2_IM37

#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk

Interrupt Mask on line 37

Definition at line 3938 of file stm32g431xx.h.

◆ EXTI_IMR2_IM37_Msk

#define EXTI_IMR2_IM37_Msk (0x1UL << EXTI_IMR2_IM37_Pos)

0x00000020

Definition at line 3937 of file stm32g431xx.h.

◆ EXTI_IMR2_IM37_Pos

#define EXTI_IMR2_IM37_Pos (5U)

Definition at line 3936 of file stm32g431xx.h.

◆ EXTI_IMR2_IM38

#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk

Interrupt Mask on line 38

Definition at line 3941 of file stm32g431xx.h.

◆ EXTI_IMR2_IM38_Msk

#define EXTI_IMR2_IM38_Msk (0x1UL << EXTI_IMR2_IM38_Pos)

0x00000040

Definition at line 3940 of file stm32g431xx.h.

◆ EXTI_IMR2_IM38_Pos

#define EXTI_IMR2_IM38_Pos (6U)

Definition at line 3939 of file stm32g431xx.h.

◆ EXTI_IMR2_IM39

#define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk

Interrupt Mask on line 39

Definition at line 3944 of file stm32g431xx.h.

◆ EXTI_IMR2_IM39_Msk

#define EXTI_IMR2_IM39_Msk (0x1UL << EXTI_IMR2_IM39_Pos)

0x00000080

Definition at line 3943 of file stm32g431xx.h.

◆ EXTI_IMR2_IM39_Pos

#define EXTI_IMR2_IM39_Pos (7U)

Definition at line 3942 of file stm32g431xx.h.

◆ EXTI_IMR2_IM40

#define EXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk

Interrupt Mask on line 40

Definition at line 3947 of file stm32g431xx.h.

◆ EXTI_IMR2_IM40_Msk

#define EXTI_IMR2_IM40_Msk (0x1UL << EXTI_IMR2_IM40_Pos)

0x00000100

Definition at line 3946 of file stm32g431xx.h.

◆ EXTI_IMR2_IM40_Pos

#define EXTI_IMR2_IM40_Pos (8U)

Definition at line 3945 of file stm32g431xx.h.

◆ EXTI_IMR2_IM41

#define EXTI_IMR2_IM41 EXTI_IMR2_IM41_Msk

Interrupt Mask on line 41

Definition at line 3950 of file stm32g431xx.h.

◆ EXTI_IMR2_IM41_Msk

#define EXTI_IMR2_IM41_Msk (0x1UL << EXTI_IMR2_IM41_Pos)

0x00000200

Definition at line 3949 of file stm32g431xx.h.

◆ EXTI_IMR2_IM41_Pos

#define EXTI_IMR2_IM41_Pos (9U)

Definition at line 3948 of file stm32g431xx.h.

◆ EXTI_IMR2_IM_Msk

#define EXTI_IMR2_IM_Msk (0x3F4UL << EXTI_IMR2_IM_Pos)

0x000003F4

Definition at line 3952 of file stm32g431xx.h.

◆ EXTI_IMR2_IM_Pos

#define EXTI_IMR2_IM_Pos (0U)

Definition at line 3951 of file stm32g431xx.h.

◆ EXTI_PR1_PIF0

#define EXTI_PR1_PIF0 EXTI_PR1_PIF0_Msk

Pending bit for line 0

Definition at line 3858 of file stm32g431xx.h.

◆ EXTI_PR1_PIF0_Msk

#define EXTI_PR1_PIF0_Msk (0x1UL << EXTI_PR1_PIF0_Pos)

0x00000001

Definition at line 3857 of file stm32g431xx.h.

◆ EXTI_PR1_PIF0_Pos

#define EXTI_PR1_PIF0_Pos (0U)

Definition at line 3856 of file stm32g431xx.h.

◆ EXTI_PR1_PIF1

#define EXTI_PR1_PIF1 EXTI_PR1_PIF1_Msk

Pending bit for line 1

Definition at line 3861 of file stm32g431xx.h.

◆ EXTI_PR1_PIF10

#define EXTI_PR1_PIF10 EXTI_PR1_PIF10_Msk

Pending bit for line 10

Definition at line 3888 of file stm32g431xx.h.

◆ EXTI_PR1_PIF10_Msk

#define EXTI_PR1_PIF10_Msk (0x1UL << EXTI_PR1_PIF10_Pos)

0x00000400

Definition at line 3887 of file stm32g431xx.h.

◆ EXTI_PR1_PIF10_Pos

#define EXTI_PR1_PIF10_Pos (10U)

Definition at line 3886 of file stm32g431xx.h.

◆ EXTI_PR1_PIF11

#define EXTI_PR1_PIF11 EXTI_PR1_PIF11_Msk

Pending bit for line 11

Definition at line 3891 of file stm32g431xx.h.

◆ EXTI_PR1_PIF11_Msk

#define EXTI_PR1_PIF11_Msk (0x1UL << EXTI_PR1_PIF11_Pos)

0x00000800

Definition at line 3890 of file stm32g431xx.h.

◆ EXTI_PR1_PIF11_Pos

#define EXTI_PR1_PIF11_Pos (11U)

Definition at line 3889 of file stm32g431xx.h.

◆ EXTI_PR1_PIF12

#define EXTI_PR1_PIF12 EXTI_PR1_PIF12_Msk

Pending bit for line 12

Definition at line 3894 of file stm32g431xx.h.

◆ EXTI_PR1_PIF12_Msk

#define EXTI_PR1_PIF12_Msk (0x1UL << EXTI_PR1_PIF12_Pos)

0x00001000

Definition at line 3893 of file stm32g431xx.h.

◆ EXTI_PR1_PIF12_Pos

#define EXTI_PR1_PIF12_Pos (12U)

Definition at line 3892 of file stm32g431xx.h.

◆ EXTI_PR1_PIF13

#define EXTI_PR1_PIF13 EXTI_PR1_PIF13_Msk

Pending bit for line 13

Definition at line 3897 of file stm32g431xx.h.

◆ EXTI_PR1_PIF13_Msk

#define EXTI_PR1_PIF13_Msk (0x1UL << EXTI_PR1_PIF13_Pos)

0x00002000

Definition at line 3896 of file stm32g431xx.h.

◆ EXTI_PR1_PIF13_Pos

#define EXTI_PR1_PIF13_Pos (13U)

Definition at line 3895 of file stm32g431xx.h.

◆ EXTI_PR1_PIF14

#define EXTI_PR1_PIF14 EXTI_PR1_PIF14_Msk

Pending bit for line 14

Definition at line 3900 of file stm32g431xx.h.

◆ EXTI_PR1_PIF14_Msk

#define EXTI_PR1_PIF14_Msk (0x1UL << EXTI_PR1_PIF14_Pos)

0x00004000

Definition at line 3899 of file stm32g431xx.h.

◆ EXTI_PR1_PIF14_Pos

#define EXTI_PR1_PIF14_Pos (14U)

Definition at line 3898 of file stm32g431xx.h.

◆ EXTI_PR1_PIF15

#define EXTI_PR1_PIF15 EXTI_PR1_PIF15_Msk

Pending bit for line 15

Definition at line 3903 of file stm32g431xx.h.

◆ EXTI_PR1_PIF15_Msk

#define EXTI_PR1_PIF15_Msk (0x1UL << EXTI_PR1_PIF15_Pos)

0x00008000

Definition at line 3902 of file stm32g431xx.h.

◆ EXTI_PR1_PIF15_Pos

#define EXTI_PR1_PIF15_Pos (15U)

Definition at line 3901 of file stm32g431xx.h.

◆ EXTI_PR1_PIF16

#define EXTI_PR1_PIF16 EXTI_PR1_PIF16_Msk

Pending bit for line 16

Definition at line 3906 of file stm32g431xx.h.

◆ EXTI_PR1_PIF16_Msk

#define EXTI_PR1_PIF16_Msk (0x1UL << EXTI_PR1_PIF16_Pos)

0x00010000

Definition at line 3905 of file stm32g431xx.h.

◆ EXTI_PR1_PIF16_Pos

#define EXTI_PR1_PIF16_Pos (16U)

Definition at line 3904 of file stm32g431xx.h.

◆ EXTI_PR1_PIF17

#define EXTI_PR1_PIF17 EXTI_PR1_PIF17_Msk

Pending bit for line 17

Definition at line 3909 of file stm32g431xx.h.

◆ EXTI_PR1_PIF17_Msk

#define EXTI_PR1_PIF17_Msk (0x1UL << EXTI_PR1_PIF17_Pos)

0x00020000

Definition at line 3908 of file stm32g431xx.h.

◆ EXTI_PR1_PIF17_Pos

#define EXTI_PR1_PIF17_Pos (17U)

Definition at line 3907 of file stm32g431xx.h.

◆ EXTI_PR1_PIF19

#define EXTI_PR1_PIF19 EXTI_PR1_PIF19_Msk

Pending bit for line 19

Definition at line 3912 of file stm32g431xx.h.

◆ EXTI_PR1_PIF19_Msk

#define EXTI_PR1_PIF19_Msk (0x1UL << EXTI_PR1_PIF19_Pos)

0x00080000

Definition at line 3911 of file stm32g431xx.h.

◆ EXTI_PR1_PIF19_Pos

#define EXTI_PR1_PIF19_Pos (19U)

Definition at line 3910 of file stm32g431xx.h.

◆ EXTI_PR1_PIF1_Msk

#define EXTI_PR1_PIF1_Msk (0x1UL << EXTI_PR1_PIF1_Pos)

0x00000002

Definition at line 3860 of file stm32g431xx.h.

◆ EXTI_PR1_PIF1_Pos

#define EXTI_PR1_PIF1_Pos (1U)

Definition at line 3859 of file stm32g431xx.h.

◆ EXTI_PR1_PIF2

#define EXTI_PR1_PIF2 EXTI_PR1_PIF2_Msk

Pending bit for line 2

Definition at line 3864 of file stm32g431xx.h.

◆ EXTI_PR1_PIF20

#define EXTI_PR1_PIF20 EXTI_PR1_PIF20_Msk

Pending bit for line 20

Definition at line 3915 of file stm32g431xx.h.

◆ EXTI_PR1_PIF20_Msk

#define EXTI_PR1_PIF20_Msk (0x1UL << EXTI_PR1_PIF20_Pos)

0x00100000

Definition at line 3914 of file stm32g431xx.h.

◆ EXTI_PR1_PIF20_Pos

#define EXTI_PR1_PIF20_Pos (20U)

Definition at line 3913 of file stm32g431xx.h.

◆ EXTI_PR1_PIF21

#define EXTI_PR1_PIF21 EXTI_PR1_PIF21_Msk

Pending bit for line 21

Definition at line 3918 of file stm32g431xx.h.

◆ EXTI_PR1_PIF21_Msk

#define EXTI_PR1_PIF21_Msk (0x1UL << EXTI_PR1_PIF21_Pos)

0x00200000

Definition at line 3917 of file stm32g431xx.h.

◆ EXTI_PR1_PIF21_Pos

#define EXTI_PR1_PIF21_Pos (21U)

Definition at line 3916 of file stm32g431xx.h.

◆ EXTI_PR1_PIF22

#define EXTI_PR1_PIF22 EXTI_PR1_PIF22_Msk

Pending bit for line 22

Definition at line 3921 of file stm32g431xx.h.

◆ EXTI_PR1_PIF22_Msk

#define EXTI_PR1_PIF22_Msk (0x1UL << EXTI_PR1_PIF22_Pos)

0x00400000

Definition at line 3920 of file stm32g431xx.h.

◆ EXTI_PR1_PIF22_Pos

#define EXTI_PR1_PIF22_Pos (22U)

Definition at line 3919 of file stm32g431xx.h.

◆ EXTI_PR1_PIF29

#define EXTI_PR1_PIF29 EXTI_PR1_PIF29_Msk

Pending bit for line 29

Definition at line 3924 of file stm32g431xx.h.

◆ EXTI_PR1_PIF29_Msk

#define EXTI_PR1_PIF29_Msk (0x1UL << EXTI_PR1_PIF29_Pos)

0x20000000

Definition at line 3923 of file stm32g431xx.h.

◆ EXTI_PR1_PIF29_Pos

#define EXTI_PR1_PIF29_Pos (29U)

Definition at line 3922 of file stm32g431xx.h.

◆ EXTI_PR1_PIF2_Msk

#define EXTI_PR1_PIF2_Msk (0x1UL << EXTI_PR1_PIF2_Pos)

0x00000004

Definition at line 3863 of file stm32g431xx.h.

◆ EXTI_PR1_PIF2_Pos

#define EXTI_PR1_PIF2_Pos (2U)

Definition at line 3862 of file stm32g431xx.h.

◆ EXTI_PR1_PIF3

#define EXTI_PR1_PIF3 EXTI_PR1_PIF3_Msk

Pending bit for line 3

Definition at line 3867 of file stm32g431xx.h.

◆ EXTI_PR1_PIF30

#define EXTI_PR1_PIF30 EXTI_PR1_PIF30_Msk

Pending bit for line 30

Definition at line 3927 of file stm32g431xx.h.

◆ EXTI_PR1_PIF30_Msk

#define EXTI_PR1_PIF30_Msk (0x1UL << EXTI_PR1_PIF30_Pos)

0x40000000

Definition at line 3926 of file stm32g431xx.h.

◆ EXTI_PR1_PIF30_Pos

#define EXTI_PR1_PIF30_Pos (30U)

Definition at line 3925 of file stm32g431xx.h.

◆ EXTI_PR1_PIF3_Msk

#define EXTI_PR1_PIF3_Msk (0x1UL << EXTI_PR1_PIF3_Pos)

0x00000008

Definition at line 3866 of file stm32g431xx.h.

◆ EXTI_PR1_PIF3_Pos

#define EXTI_PR1_PIF3_Pos (3U)

Definition at line 3865 of file stm32g431xx.h.

◆ EXTI_PR1_PIF4

#define EXTI_PR1_PIF4 EXTI_PR1_PIF4_Msk

Pending bit for line 4

Definition at line 3870 of file stm32g431xx.h.

◆ EXTI_PR1_PIF4_Msk

#define EXTI_PR1_PIF4_Msk (0x1UL << EXTI_PR1_PIF4_Pos)

0x00000010

Definition at line 3869 of file stm32g431xx.h.

◆ EXTI_PR1_PIF4_Pos

#define EXTI_PR1_PIF4_Pos (4U)

Definition at line 3868 of file stm32g431xx.h.

◆ EXTI_PR1_PIF5

#define EXTI_PR1_PIF5 EXTI_PR1_PIF5_Msk

Pending bit for line 5

Definition at line 3873 of file stm32g431xx.h.

◆ EXTI_PR1_PIF5_Msk

#define EXTI_PR1_PIF5_Msk (0x1UL << EXTI_PR1_PIF5_Pos)

0x00000020

Definition at line 3872 of file stm32g431xx.h.

◆ EXTI_PR1_PIF5_Pos

#define EXTI_PR1_PIF5_Pos (5U)

Definition at line 3871 of file stm32g431xx.h.

◆ EXTI_PR1_PIF6

#define EXTI_PR1_PIF6 EXTI_PR1_PIF6_Msk

Pending bit for line 6

Definition at line 3876 of file stm32g431xx.h.

◆ EXTI_PR1_PIF6_Msk

#define EXTI_PR1_PIF6_Msk (0x1UL << EXTI_PR1_PIF6_Pos)

0x00000040

Definition at line 3875 of file stm32g431xx.h.

◆ EXTI_PR1_PIF6_Pos

#define EXTI_PR1_PIF6_Pos (6U)

Definition at line 3874 of file stm32g431xx.h.

◆ EXTI_PR1_PIF7

#define EXTI_PR1_PIF7 EXTI_PR1_PIF7_Msk

Pending bit for line 7

Definition at line 3879 of file stm32g431xx.h.

◆ EXTI_PR1_PIF7_Msk

#define EXTI_PR1_PIF7_Msk (0x1UL << EXTI_PR1_PIF7_Pos)

0x00000080

Definition at line 3878 of file stm32g431xx.h.

◆ EXTI_PR1_PIF7_Pos

#define EXTI_PR1_PIF7_Pos (7U)

Definition at line 3877 of file stm32g431xx.h.

◆ EXTI_PR1_PIF8

#define EXTI_PR1_PIF8 EXTI_PR1_PIF8_Msk

Pending bit for line 8

Definition at line 3882 of file stm32g431xx.h.

◆ EXTI_PR1_PIF8_Msk

#define EXTI_PR1_PIF8_Msk (0x1UL << EXTI_PR1_PIF8_Pos)

0x00000100

Definition at line 3881 of file stm32g431xx.h.

◆ EXTI_PR1_PIF8_Pos

#define EXTI_PR1_PIF8_Pos (8U)

Definition at line 3880 of file stm32g431xx.h.

◆ EXTI_PR1_PIF9

#define EXTI_PR1_PIF9 EXTI_PR1_PIF9_Msk

Pending bit for line 9

Definition at line 3885 of file stm32g431xx.h.

◆ EXTI_PR1_PIF9_Msk

#define EXTI_PR1_PIF9_Msk (0x1UL << EXTI_PR1_PIF9_Pos)

0x00000200

Definition at line 3884 of file stm32g431xx.h.

◆ EXTI_PR1_PIF9_Pos

#define EXTI_PR1_PIF9_Pos (9U)

Definition at line 3883 of file stm32g431xx.h.

◆ EXTI_PR2_PIF38

#define EXTI_PR2_PIF38 EXTI_PR2_PIF38_Msk

Pending bit for line 38

Definition at line 4026 of file stm32g431xx.h.

◆ EXTI_PR2_PIF38_Msk

#define EXTI_PR2_PIF38_Msk (0x1UL << EXTI_PR2_PIF38_Pos)

0x00000040

Definition at line 4025 of file stm32g431xx.h.

◆ EXTI_PR2_PIF38_Pos

#define EXTI_PR2_PIF38_Pos (6U)

Definition at line 4024 of file stm32g431xx.h.

◆ EXTI_PR2_PIF39

#define EXTI_PR2_PIF39 EXTI_PR2_PIF39_Msk

Pending bit for line 39

Definition at line 4029 of file stm32g431xx.h.

◆ EXTI_PR2_PIF39_Msk

#define EXTI_PR2_PIF39_Msk (0x1UL << EXTI_PR2_PIF39_Pos)

0x00000080

Definition at line 4028 of file stm32g431xx.h.

◆ EXTI_PR2_PIF39_Pos

#define EXTI_PR2_PIF39_Pos (7U)

Definition at line 4027 of file stm32g431xx.h.

◆ EXTI_PR2_PIF40

#define EXTI_PR2_PIF40 EXTI_PR2_PIF40_Msk

Pending bit for line 40

Definition at line 4032 of file stm32g431xx.h.

◆ EXTI_PR2_PIF40_Msk

#define EXTI_PR2_PIF40_Msk (0x1UL << EXTI_PR2_PIF40_Pos)

0x00000100

Definition at line 4031 of file stm32g431xx.h.

◆ EXTI_PR2_PIF40_Pos

#define EXTI_PR2_PIF40_Pos (8U)

Definition at line 4030 of file stm32g431xx.h.

◆ EXTI_PR2_PIF41

#define EXTI_PR2_PIF41 EXTI_PR2_PIF41_Msk

Pending bit for line 41

Definition at line 4035 of file stm32g431xx.h.

◆ EXTI_PR2_PIF41_Msk

#define EXTI_PR2_PIF41_Msk (0x1UL << EXTI_PR2_PIF41_Pos)

0x00000200

Definition at line 4034 of file stm32g431xx.h.

◆ EXTI_PR2_PIF41_Pos

#define EXTI_PR2_PIF41_Pos (9U)

Definition at line 4033 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT0

#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk

Rising trigger event configuration bit of line 0

Definition at line 3636 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT0_Msk

#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos)

0x00000001

Definition at line 3635 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT0_Pos

#define EXTI_RTSR1_RT0_Pos (0U)

Definition at line 3634 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT1

#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk

Rising trigger event configuration bit of line 1

Definition at line 3639 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT10

#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk

Rising trigger event configuration bit of line 10

Definition at line 3666 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT10_Msk

#define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos)

0x00000400

Definition at line 3665 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT10_Pos

#define EXTI_RTSR1_RT10_Pos (10U)

Definition at line 3664 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT11

#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk

Rising trigger event configuration bit of line 11

Definition at line 3669 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT11_Msk

#define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos)

0x00000800

Definition at line 3668 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT11_Pos

#define EXTI_RTSR1_RT11_Pos (11U)

Definition at line 3667 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT12

#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk

Rising trigger event configuration bit of line 12

Definition at line 3672 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT12_Msk

#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos)

0x00001000

Definition at line 3671 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT12_Pos

#define EXTI_RTSR1_RT12_Pos (12U)

Definition at line 3670 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT13

#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk

Rising trigger event configuration bit of line 13

Definition at line 3675 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT13_Msk

#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos)

0x00002000

Definition at line 3674 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT13_Pos

#define EXTI_RTSR1_RT13_Pos (13U)

Definition at line 3673 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT14

#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk

Rising trigger event configuration bit of line 14

Definition at line 3678 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT14_Msk

#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos)

0x00004000

Definition at line 3677 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT14_Pos

#define EXTI_RTSR1_RT14_Pos (14U)

Definition at line 3676 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT15

#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk

Rising trigger event configuration bit of line 15

Definition at line 3681 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT15_Msk

#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos)

0x00008000

Definition at line 3680 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT15_Pos

#define EXTI_RTSR1_RT15_Pos (15U)

Definition at line 3679 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT16

#define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk

Rising trigger event configuration bit of line 16

Definition at line 3684 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT16_Msk

#define EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos)

0x00010000

Definition at line 3683 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT16_Pos

#define EXTI_RTSR1_RT16_Pos (16U)

Definition at line 3682 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT17

#define EXTI_RTSR1_RT17 EXTI_RTSR1_RT17_Msk

Rising trigger event configuration bit of line 17

Definition at line 3687 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT17_Msk

#define EXTI_RTSR1_RT17_Msk (0x1UL << EXTI_RTSR1_RT17_Pos)

0x00020000

Definition at line 3686 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT17_Pos

#define EXTI_RTSR1_RT17_Pos (17U)

Definition at line 3685 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT19

#define EXTI_RTSR1_RT19 EXTI_RTSR1_RT19_Msk

Rising trigger event configuration bit of line 19

Definition at line 3690 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT19_Msk

#define EXTI_RTSR1_RT19_Msk (0x1UL << EXTI_RTSR1_RT19_Pos)

0x00080000

Definition at line 3689 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT19_Pos

#define EXTI_RTSR1_RT19_Pos (19U)

Definition at line 3688 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT1_Msk

#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos)

0x00000002

Definition at line 3638 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT1_Pos

#define EXTI_RTSR1_RT1_Pos (1U)

Definition at line 3637 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT2

#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk

Rising trigger event configuration bit of line 2

Definition at line 3642 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT20

#define EXTI_RTSR1_RT20 EXTI_RTSR1_RT20_Msk

Rising trigger event configuration bit of line 20

Definition at line 3693 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT20_Msk

#define EXTI_RTSR1_RT20_Msk (0x1UL << EXTI_RTSR1_RT20_Pos)

0x00100000

Definition at line 3692 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT20_Pos

#define EXTI_RTSR1_RT20_Pos (20U)

Definition at line 3691 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT21

#define EXTI_RTSR1_RT21 EXTI_RTSR1_RT21_Msk

Rising trigger event configuration bit of line 21

Definition at line 3696 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT21_Msk

#define EXTI_RTSR1_RT21_Msk (0x1UL << EXTI_RTSR1_RT21_Pos)

0x00200000

Definition at line 3695 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT21_Pos

#define EXTI_RTSR1_RT21_Pos (21U)

Definition at line 3694 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT22

#define EXTI_RTSR1_RT22 EXTI_RTSR1_RT22_Msk

Rising trigger event configuration bit of line 22

Definition at line 3699 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT22_Msk

#define EXTI_RTSR1_RT22_Msk (0x1UL << EXTI_RTSR1_RT22_Pos)

0x00400000

Definition at line 3698 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT22_Pos

#define EXTI_RTSR1_RT22_Pos (22U)

Definition at line 3697 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT29

#define EXTI_RTSR1_RT29 EXTI_RTSR1_RT29_Msk

Rising trigger event configuration bit of line 29

Definition at line 3702 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT29_Msk

#define EXTI_RTSR1_RT29_Msk (0x1UL << EXTI_RTSR1_RT29_Pos)

0x20000000

Definition at line 3701 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT29_Pos

#define EXTI_RTSR1_RT29_Pos (29U)

Definition at line 3700 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT2_Msk

#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos)

0x00000004

Definition at line 3641 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT2_Pos

#define EXTI_RTSR1_RT2_Pos (2U)

Definition at line 3640 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT3

#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk

Rising trigger event configuration bit of line 3

Definition at line 3645 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT30

#define EXTI_RTSR1_RT30 EXTI_RTSR1_RT30_Msk

Rising trigger event configuration bit of line 30

Definition at line 3705 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT30_Msk

#define EXTI_RTSR1_RT30_Msk (0x1UL << EXTI_RTSR1_RT30_Pos)

0x40000000

Definition at line 3704 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT30_Pos

#define EXTI_RTSR1_RT30_Pos (30U)

Definition at line 3703 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT3_Msk

#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos)

0x00000008

Definition at line 3644 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT3_Pos

#define EXTI_RTSR1_RT3_Pos (3U)

Definition at line 3643 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT4

#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk

Rising trigger event configuration bit of line 4

Definition at line 3648 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT4_Msk

#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos)

0x00000010

Definition at line 3647 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT4_Pos

#define EXTI_RTSR1_RT4_Pos (4U)

Definition at line 3646 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT5

#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk

Rising trigger event configuration bit of line 5

Definition at line 3651 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT5_Msk

#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos)

0x00000020

Definition at line 3650 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT5_Pos

#define EXTI_RTSR1_RT5_Pos (5U)

Definition at line 3649 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT6

#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk

Rising trigger event configuration bit of line 6

Definition at line 3654 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT6_Msk

#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos)

0x00000040

Definition at line 3653 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT6_Pos

#define EXTI_RTSR1_RT6_Pos (6U)

Definition at line 3652 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT7

#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk

Rising trigger event configuration bit of line 7

Definition at line 3657 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT7_Msk

#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos)

0x00000080

Definition at line 3656 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT7_Pos

#define EXTI_RTSR1_RT7_Pos (7U)

Definition at line 3655 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT8

#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk

Rising trigger event configuration bit of line 8

Definition at line 3660 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT8_Msk

#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos)

0x00000100

Definition at line 3659 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT8_Pos

#define EXTI_RTSR1_RT8_Pos (8U)

Definition at line 3658 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT9

#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk

Rising trigger event configuration bit of line 9

Definition at line 3663 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT9_Msk

#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos)

0x00000200

Definition at line 3662 of file stm32g431xx.h.

◆ EXTI_RTSR1_RT9_Pos

#define EXTI_RTSR1_RT9_Pos (9U)

Definition at line 3661 of file stm32g431xx.h.

◆ EXTI_RTSR2_RT38

#define EXTI_RTSR2_RT38 EXTI_RTSR2_RT38_Msk

Rising trigger event configuration bit of line 38

Definition at line 3984 of file stm32g431xx.h.

◆ EXTI_RTSR2_RT38_Msk

#define EXTI_RTSR2_RT38_Msk (0x1UL << EXTI_RTSR2_RT38_Pos)

0x00000040

Definition at line 3983 of file stm32g431xx.h.

◆ EXTI_RTSR2_RT38_Pos

#define EXTI_RTSR2_RT38_Pos (6U)

Definition at line 3982 of file stm32g431xx.h.

◆ EXTI_RTSR2_RT39

#define EXTI_RTSR2_RT39 EXTI_RTSR2_RT39_Msk

Rising trigger event configuration bit of line 39

Definition at line 3987 of file stm32g431xx.h.

◆ EXTI_RTSR2_RT39_Msk

#define EXTI_RTSR2_RT39_Msk (0x1UL << EXTI_RTSR2_RT39_Pos)

0x00000080

Definition at line 3986 of file stm32g431xx.h.

◆ EXTI_RTSR2_RT39_Pos

#define EXTI_RTSR2_RT39_Pos (7U)

Definition at line 3985 of file stm32g431xx.h.

◆ EXTI_RTSR2_RT40

#define EXTI_RTSR2_RT40 EXTI_RTSR2_RT40_Msk

Rising trigger event configuration bit of line 40

Definition at line 3990 of file stm32g431xx.h.

◆ EXTI_RTSR2_RT40_Msk

#define EXTI_RTSR2_RT40_Msk (0x1UL << EXTI_RTSR2_RT40_Pos)

0x00000100

Definition at line 3989 of file stm32g431xx.h.

◆ EXTI_RTSR2_RT40_Pos

#define EXTI_RTSR2_RT40_Pos (8U)

Definition at line 3988 of file stm32g431xx.h.

◆ EXTI_RTSR2_RT41

#define EXTI_RTSR2_RT41 EXTI_RTSR2_RT41_Msk

Rising trigger event configuration bit of line 41

Definition at line 3993 of file stm32g431xx.h.

◆ EXTI_RTSR2_RT41_Msk

#define EXTI_RTSR2_RT41_Msk (0x1UL << EXTI_RTSR2_RT41_Pos)

0x00000200

Definition at line 3992 of file stm32g431xx.h.

◆ EXTI_RTSR2_RT41_Pos

#define EXTI_RTSR2_RT41_Pos (9U)

Definition at line 3991 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI0

#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk

Software Interrupt on line 0

Definition at line 3784 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI0_Msk

#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos)

0x00000001

Definition at line 3783 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI0_Pos

#define EXTI_SWIER1_SWI0_Pos (0U)

Definition at line 3782 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI1

#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk

Software Interrupt on line 1

Definition at line 3787 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI10

#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk

Software Interrupt on line 10

Definition at line 3814 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI10_Msk

#define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos)

0x00000400

Definition at line 3813 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI10_Pos

#define EXTI_SWIER1_SWI10_Pos (10U)

Definition at line 3812 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI11

#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk

Software Interrupt on line 11

Definition at line 3817 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI11_Msk

#define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos)

0x00000800

Definition at line 3816 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI11_Pos

#define EXTI_SWIER1_SWI11_Pos (11U)

Definition at line 3815 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI12

#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk

Software Interrupt on line 12

Definition at line 3820 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI12_Msk

#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos)

0x00001000

Definition at line 3819 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI12_Pos

#define EXTI_SWIER1_SWI12_Pos (12U)

Definition at line 3818 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI13

#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk

Software Interrupt on line 13

Definition at line 3823 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI13_Msk

#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos)

0x00002000

Definition at line 3822 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI13_Pos

#define EXTI_SWIER1_SWI13_Pos (13U)

Definition at line 3821 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI14

#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk

Software Interrupt on line 14

Definition at line 3826 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI14_Msk

#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos)

0x00004000

Definition at line 3825 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI14_Pos

#define EXTI_SWIER1_SWI14_Pos (14U)

Definition at line 3824 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI15

#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk

Software Interrupt on line 15

Definition at line 3829 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI15_Msk

#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos)

0x00008000

Definition at line 3828 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI15_Pos

#define EXTI_SWIER1_SWI15_Pos (15U)

Definition at line 3827 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI16

#define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk

Software Interrupt on line 16

Definition at line 3832 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI16_Msk

#define EXTI_SWIER1_SWI16_Msk (0x1UL << EXTI_SWIER1_SWI16_Pos)

0x00010000

Definition at line 3831 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI16_Pos

#define EXTI_SWIER1_SWI16_Pos (16U)

Definition at line 3830 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI17

#define EXTI_SWIER1_SWI17 EXTI_SWIER1_SWI17_Msk

Software Interrupt on line 17

Definition at line 3835 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI17_Msk

#define EXTI_SWIER1_SWI17_Msk (0x1UL << EXTI_SWIER1_SWI17_Pos)

0x00020000

Definition at line 3834 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI17_Pos

#define EXTI_SWIER1_SWI17_Pos (17U)

Definition at line 3833 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI19

#define EXTI_SWIER1_SWI19 EXTI_SWIER1_SWI19_Msk

Software Interrupt on line 19

Definition at line 3838 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI19_Msk

#define EXTI_SWIER1_SWI19_Msk (0x1UL << EXTI_SWIER1_SWI19_Pos)

0x00080000

Definition at line 3837 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI19_Pos

#define EXTI_SWIER1_SWI19_Pos (19U)

Definition at line 3836 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI1_Msk

#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos)

0x00000002

Definition at line 3786 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI1_Pos

#define EXTI_SWIER1_SWI1_Pos (1U)

Definition at line 3785 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI2

#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk

Software Interrupt on line 2

Definition at line 3790 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI20

#define EXTI_SWIER1_SWI20 EXTI_SWIER1_SWI20_Msk

Software Interrupt on line 20

Definition at line 3841 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI20_Msk

#define EXTI_SWIER1_SWI20_Msk (0x1UL << EXTI_SWIER1_SWI20_Pos)

0x00100000

Definition at line 3840 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI20_Pos

#define EXTI_SWIER1_SWI20_Pos (20U)

Definition at line 3839 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI21

#define EXTI_SWIER1_SWI21 EXTI_SWIER1_SWI21_Msk

Software Interrupt on line 21

Definition at line 3844 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI21_Msk

#define EXTI_SWIER1_SWI21_Msk (0x1UL << EXTI_SWIER1_SWI21_Pos)

0x00200000

Definition at line 3843 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI21_Pos

#define EXTI_SWIER1_SWI21_Pos (21U)

Definition at line 3842 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI22

#define EXTI_SWIER1_SWI22 EXTI_SWIER1_SWI22_Msk

Software Interrupt on line 22

Definition at line 3847 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI22_Msk

#define EXTI_SWIER1_SWI22_Msk (0x1UL << EXTI_SWIER1_SWI22_Pos)

0x00400000

Definition at line 3846 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI22_Pos

#define EXTI_SWIER1_SWI22_Pos (22U)

Definition at line 3845 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI29

#define EXTI_SWIER1_SWI29 EXTI_SWIER1_SWI29_Msk

Software Interrupt on line 29

Definition at line 3850 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI29_Msk

#define EXTI_SWIER1_SWI29_Msk (0x1UL << EXTI_SWIER1_SWI29_Pos)

0x20000000

Definition at line 3849 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI29_Pos

#define EXTI_SWIER1_SWI29_Pos (29U)

Definition at line 3848 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI2_Msk

#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos)

0x00000004

Definition at line 3789 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI2_Pos

#define EXTI_SWIER1_SWI2_Pos (2U)

Definition at line 3788 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI3

#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk

Software Interrupt on line 3

Definition at line 3793 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI30

#define EXTI_SWIER1_SWI30 EXTI_SWIER1_SWI30_Msk

Software Interrupt on line 30

Definition at line 3853 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI30_Msk

#define EXTI_SWIER1_SWI30_Msk (0x1UL << EXTI_SWIER1_SWI30_Pos)

0x40000000

Definition at line 3852 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI30_Pos

#define EXTI_SWIER1_SWI30_Pos (30U)

Definition at line 3851 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI3_Msk

#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos)

0x00000008

Definition at line 3792 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI3_Pos

#define EXTI_SWIER1_SWI3_Pos (3U)

Definition at line 3791 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI4

#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk

Software Interrupt on line 4

Definition at line 3796 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI4_Msk

#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos)

0x00000010

Definition at line 3795 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI4_Pos

#define EXTI_SWIER1_SWI4_Pos (4U)

Definition at line 3794 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI5

#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk

Software Interrupt on line 5

Definition at line 3799 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI5_Msk

#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos)

0x00000020

Definition at line 3798 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI5_Pos

#define EXTI_SWIER1_SWI5_Pos (5U)

Definition at line 3797 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI6

#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk

Software Interrupt on line 6

Definition at line 3802 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI6_Msk

#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos)

0x00000040

Definition at line 3801 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI6_Pos

#define EXTI_SWIER1_SWI6_Pos (6U)

Definition at line 3800 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI7

#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk

Software Interrupt on line 7

Definition at line 3805 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI7_Msk

#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos)

0x00000080

Definition at line 3804 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI7_Pos

#define EXTI_SWIER1_SWI7_Pos (7U)

Definition at line 3803 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI8

#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk

Software Interrupt on line 8

Definition at line 3808 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI8_Msk

#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos)

0x00000100

Definition at line 3807 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI8_Pos

#define EXTI_SWIER1_SWI8_Pos (8U)

Definition at line 3806 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI9

#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk

Software Interrupt on line 9

Definition at line 3811 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI9_Msk

#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos)

0x00000200

Definition at line 3810 of file stm32g431xx.h.

◆ EXTI_SWIER1_SWI9_Pos

#define EXTI_SWIER1_SWI9_Pos (9U)

Definition at line 3809 of file stm32g431xx.h.

◆ EXTI_SWIER2_SWI38

#define EXTI_SWIER2_SWI38 EXTI_SWIER2_SWI38_Msk

Software Interrupt on line 38

Definition at line 4012 of file stm32g431xx.h.

◆ EXTI_SWIER2_SWI38_Msk

#define EXTI_SWIER2_SWI38_Msk (0x1UL << EXTI_SWIER2_SWI38_Pos)

0x00000040

Definition at line 4011 of file stm32g431xx.h.

◆ EXTI_SWIER2_SWI38_Pos

#define EXTI_SWIER2_SWI38_Pos (6U)

Definition at line 4010 of file stm32g431xx.h.

◆ EXTI_SWIER2_SWI39

#define EXTI_SWIER2_SWI39 EXTI_SWIER2_SWI39_Msk

Software Interrupt on line 39

Definition at line 4015 of file stm32g431xx.h.

◆ EXTI_SWIER2_SWI39_Msk

#define EXTI_SWIER2_SWI39_Msk (0x1UL << EXTI_SWIER2_SWI39_Pos)

0x00000080

Definition at line 4014 of file stm32g431xx.h.

◆ EXTI_SWIER2_SWI39_Pos

#define EXTI_SWIER2_SWI39_Pos (7U)

Definition at line 4013 of file stm32g431xx.h.

◆ EXTI_SWIER2_SWI40

#define EXTI_SWIER2_SWI40 EXTI_SWIER2_SWI40_Msk

Software Interrupt on line 40

Definition at line 4018 of file stm32g431xx.h.

◆ EXTI_SWIER2_SWI40_Msk

#define EXTI_SWIER2_SWI40_Msk (0x1UL << EXTI_SWIER2_SWI40_Pos)

0x00000100

Definition at line 4017 of file stm32g431xx.h.

◆ EXTI_SWIER2_SWI40_Pos

#define EXTI_SWIER2_SWI40_Pos (8U)

Definition at line 4016 of file stm32g431xx.h.

◆ EXTI_SWIER2_SWI41

#define EXTI_SWIER2_SWI41 EXTI_SWIER2_SWI41_Msk

Software Interrupt on line 41

Definition at line 4021 of file stm32g431xx.h.

◆ EXTI_SWIER2_SWI41_Msk

#define EXTI_SWIER2_SWI41_Msk (0x1UL << EXTI_SWIER2_SWI41_Pos)

0x00000200

Definition at line 4020 of file stm32g431xx.h.

◆ EXTI_SWIER2_SWI41_Pos

#define EXTI_SWIER2_SWI41_Pos (9U)

Definition at line 4019 of file stm32g431xx.h.

◆ FDCAN_CCCR_ASM

#define FDCAN_CCCR_ASM FDCAN_CCCR_ASM_Msk

ASM Restricted Operation Mode

Definition at line 4113 of file stm32g431xx.h.

◆ FDCAN_CCCR_ASM_Msk

#define FDCAN_CCCR_ASM_Msk (0x1UL << FDCAN_CCCR_ASM_Pos)

0x00000004

Definition at line 4112 of file stm32g431xx.h.

◆ FDCAN_CCCR_ASM_Pos

#define FDCAN_CCCR_ASM_Pos (2U)

Definition at line 4111 of file stm32g431xx.h.

◆ FDCAN_CCCR_BRSE

#define FDCAN_CCCR_BRSE FDCAN_CCCR_BRSE_Msk

FDCAN Bit Rate Switching

Definition at line 4134 of file stm32g431xx.h.

◆ FDCAN_CCCR_BRSE_Msk

#define FDCAN_CCCR_BRSE_Msk (0x1UL << FDCAN_CCCR_BRSE_Pos)

0x00000200

Definition at line 4133 of file stm32g431xx.h.

◆ FDCAN_CCCR_BRSE_Pos

#define FDCAN_CCCR_BRSE_Pos (9U)

Definition at line 4132 of file stm32g431xx.h.

◆ FDCAN_CCCR_CCE

#define FDCAN_CCCR_CCE FDCAN_CCCR_CCE_Msk

Configuration Change Enable

Definition at line 4110 of file stm32g431xx.h.

◆ FDCAN_CCCR_CCE_Msk

#define FDCAN_CCCR_CCE_Msk (0x1UL << FDCAN_CCCR_CCE_Pos)

0x00000002

Definition at line 4109 of file stm32g431xx.h.

◆ FDCAN_CCCR_CCE_Pos

#define FDCAN_CCCR_CCE_Pos (1U)

Definition at line 4108 of file stm32g431xx.h.

◆ FDCAN_CCCR_CSA

#define FDCAN_CCCR_CSA FDCAN_CCCR_CSA_Msk

Clock Stop Acknowledge

Definition at line 4116 of file stm32g431xx.h.

◆ FDCAN_CCCR_CSA_Msk

#define FDCAN_CCCR_CSA_Msk (0x1UL << FDCAN_CCCR_CSA_Pos)

0x00000008

Definition at line 4115 of file stm32g431xx.h.

◆ FDCAN_CCCR_CSA_Pos

#define FDCAN_CCCR_CSA_Pos (3U)

Definition at line 4114 of file stm32g431xx.h.

◆ FDCAN_CCCR_CSR

#define FDCAN_CCCR_CSR FDCAN_CCCR_CSR_Msk

Clock Stop Request

Definition at line 4119 of file stm32g431xx.h.

◆ FDCAN_CCCR_CSR_Msk

#define FDCAN_CCCR_CSR_Msk (0x1UL << FDCAN_CCCR_CSR_Pos)

0x00000010

Definition at line 4118 of file stm32g431xx.h.

◆ FDCAN_CCCR_CSR_Pos

#define FDCAN_CCCR_CSR_Pos (4U)

Definition at line 4117 of file stm32g431xx.h.

◆ FDCAN_CCCR_DAR

#define FDCAN_CCCR_DAR FDCAN_CCCR_DAR_Msk

Disable Automatic Retransmission

Definition at line 4125 of file stm32g431xx.h.

◆ FDCAN_CCCR_DAR_Msk

#define FDCAN_CCCR_DAR_Msk (0x1UL << FDCAN_CCCR_DAR_Pos)

0x00000040

Definition at line 4124 of file stm32g431xx.h.

◆ FDCAN_CCCR_DAR_Pos

#define FDCAN_CCCR_DAR_Pos (6U)

Definition at line 4123 of file stm32g431xx.h.

◆ FDCAN_CCCR_EFBI

#define FDCAN_CCCR_EFBI FDCAN_CCCR_EFBI_Msk

Edge Filtering during Bus Integration

Definition at line 4140 of file stm32g431xx.h.

◆ FDCAN_CCCR_EFBI_Msk

#define FDCAN_CCCR_EFBI_Msk (0x1UL << FDCAN_CCCR_EFBI_Pos)

0x00002000

Definition at line 4139 of file stm32g431xx.h.

◆ FDCAN_CCCR_EFBI_Pos

#define FDCAN_CCCR_EFBI_Pos (13U)

Definition at line 4138 of file stm32g431xx.h.

◆ FDCAN_CCCR_FDOE

#define FDCAN_CCCR_FDOE FDCAN_CCCR_FDOE_Msk

FD Operation Enable

Definition at line 4131 of file stm32g431xx.h.

◆ FDCAN_CCCR_FDOE_Msk

#define FDCAN_CCCR_FDOE_Msk (0x1UL << FDCAN_CCCR_FDOE_Pos)

0x00000100

Definition at line 4130 of file stm32g431xx.h.

◆ FDCAN_CCCR_FDOE_Pos

#define FDCAN_CCCR_FDOE_Pos (8U)

Definition at line 4129 of file stm32g431xx.h.

◆ FDCAN_CCCR_INIT

#define FDCAN_CCCR_INIT FDCAN_CCCR_INIT_Msk

Initialization

Definition at line 4107 of file stm32g431xx.h.

◆ FDCAN_CCCR_INIT_Msk

#define FDCAN_CCCR_INIT_Msk (0x1UL << FDCAN_CCCR_INIT_Pos)

0x00000001

Definition at line 4106 of file stm32g431xx.h.

◆ FDCAN_CCCR_INIT_Pos

#define FDCAN_CCCR_INIT_Pos (0U)

Definition at line 4105 of file stm32g431xx.h.

◆ FDCAN_CCCR_MON

#define FDCAN_CCCR_MON FDCAN_CCCR_MON_Msk

Bus Monitoring Mode

Definition at line 4122 of file stm32g431xx.h.

◆ FDCAN_CCCR_MON_Msk

#define FDCAN_CCCR_MON_Msk (0x1UL << FDCAN_CCCR_MON_Pos)

0x00000020

Definition at line 4121 of file stm32g431xx.h.

◆ FDCAN_CCCR_MON_Pos

#define FDCAN_CCCR_MON_Pos (5U)

Definition at line 4120 of file stm32g431xx.h.

◆ FDCAN_CCCR_NISO

#define FDCAN_CCCR_NISO FDCAN_CCCR_NISO_Msk

Non ISO Operation

Definition at line 4146 of file stm32g431xx.h.

◆ FDCAN_CCCR_NISO_Msk

#define FDCAN_CCCR_NISO_Msk (0x1UL << FDCAN_CCCR_NISO_Pos)

0x00008000

Definition at line 4145 of file stm32g431xx.h.

◆ FDCAN_CCCR_NISO_Pos

#define FDCAN_CCCR_NISO_Pos (15U)

Definition at line 4144 of file stm32g431xx.h.

◆ FDCAN_CCCR_PXHD

#define FDCAN_CCCR_PXHD FDCAN_CCCR_PXHD_Msk

Protocol Exception Handling Disable

Definition at line 4137 of file stm32g431xx.h.

◆ FDCAN_CCCR_PXHD_Msk

#define FDCAN_CCCR_PXHD_Msk (0x1UL << FDCAN_CCCR_PXHD_Pos)

0x00001000

Definition at line 4136 of file stm32g431xx.h.

◆ FDCAN_CCCR_PXHD_Pos

#define FDCAN_CCCR_PXHD_Pos (12U)

Definition at line 4135 of file stm32g431xx.h.

◆ FDCAN_CCCR_TEST

#define FDCAN_CCCR_TEST FDCAN_CCCR_TEST_Msk

Test Mode Enable

Definition at line 4128 of file stm32g431xx.h.

◆ FDCAN_CCCR_TEST_Msk

#define FDCAN_CCCR_TEST_Msk (0x1UL << FDCAN_CCCR_TEST_Pos)

0x00000080

Definition at line 4127 of file stm32g431xx.h.

◆ FDCAN_CCCR_TEST_Pos

#define FDCAN_CCCR_TEST_Pos (7U)

Definition at line 4126 of file stm32g431xx.h.

◆ FDCAN_CCCR_TXP

#define FDCAN_CCCR_TXP FDCAN_CCCR_TXP_Msk

Two CAN bit times Pause

Definition at line 4143 of file stm32g431xx.h.

◆ FDCAN_CCCR_TXP_Msk

#define FDCAN_CCCR_TXP_Msk (0x1UL << FDCAN_CCCR_TXP_Pos)

0x00004000

Definition at line 4142 of file stm32g431xx.h.

◆ FDCAN_CCCR_TXP_Pos

#define FDCAN_CCCR_TXP_Pos (14U)

Definition at line 4141 of file stm32g431xx.h.

◆ FDCAN_CKDIV_PDIV

#define FDCAN_CKDIV_PDIV FDCAN_CKDIV_PDIV_Msk

Input Clock Divider

Definition at line 4614 of file stm32g431xx.h.

◆ FDCAN_CKDIV_PDIV_Msk

#define FDCAN_CKDIV_PDIV_Msk (0xFUL << FDCAN_CKDIV_PDIV_Pos)

0x0000000F

Definition at line 4613 of file stm32g431xx.h.

◆ FDCAN_CKDIV_PDIV_Pos

#define FDCAN_CKDIV_PDIV_Pos (0U)

Definition at line 4612 of file stm32g431xx.h.

◆ FDCAN_CREL_DAY

#define FDCAN_CREL_DAY FDCAN_CREL_DAY_Msk

Timestamp Day

Definition at line 4046 of file stm32g431xx.h.

◆ FDCAN_CREL_DAY_Msk

#define FDCAN_CREL_DAY_Msk (0xFFUL << FDCAN_CREL_DAY_Pos)

0x000000FF

Definition at line 4045 of file stm32g431xx.h.

◆ FDCAN_CREL_DAY_Pos

#define FDCAN_CREL_DAY_Pos (0U)

<FDCAN control and status registers

Definition at line 4044 of file stm32g431xx.h.

◆ FDCAN_CREL_MON

#define FDCAN_CREL_MON FDCAN_CREL_MON_Msk

Timestamp Month

Definition at line 4049 of file stm32g431xx.h.

◆ FDCAN_CREL_MON_Msk

#define FDCAN_CREL_MON_Msk (0xFFUL << FDCAN_CREL_MON_Pos)

0x0000FF00

Definition at line 4048 of file stm32g431xx.h.

◆ FDCAN_CREL_MON_Pos

#define FDCAN_CREL_MON_Pos (8U)

Definition at line 4047 of file stm32g431xx.h.

◆ FDCAN_CREL_REL

#define FDCAN_CREL_REL FDCAN_CREL_REL_Msk

Core release

Definition at line 4061 of file stm32g431xx.h.

◆ FDCAN_CREL_REL_Msk

#define FDCAN_CREL_REL_Msk (0xFUL << FDCAN_CREL_REL_Pos)

0xF0000000

Definition at line 4060 of file stm32g431xx.h.

◆ FDCAN_CREL_REL_Pos

#define FDCAN_CREL_REL_Pos (28U)

Definition at line 4059 of file stm32g431xx.h.

◆ FDCAN_CREL_STEP

#define FDCAN_CREL_STEP FDCAN_CREL_STEP_Msk

Step of Core release

Definition at line 4058 of file stm32g431xx.h.

◆ FDCAN_CREL_STEP_Msk

#define FDCAN_CREL_STEP_Msk (0xFUL << FDCAN_CREL_STEP_Pos)

0x0F000000

Definition at line 4057 of file stm32g431xx.h.

◆ FDCAN_CREL_STEP_Pos

#define FDCAN_CREL_STEP_Pos (24U)

Definition at line 4056 of file stm32g431xx.h.

◆ FDCAN_CREL_SUBSTEP

#define FDCAN_CREL_SUBSTEP FDCAN_CREL_SUBSTEP_Msk

Sub-step of Core release

Definition at line 4055 of file stm32g431xx.h.

◆ FDCAN_CREL_SUBSTEP_Msk

#define FDCAN_CREL_SUBSTEP_Msk (0xFUL << FDCAN_CREL_SUBSTEP_Pos)

0x00F00000

Definition at line 4054 of file stm32g431xx.h.

◆ FDCAN_CREL_SUBSTEP_Pos

#define FDCAN_CREL_SUBSTEP_Pos (20U)

Definition at line 4053 of file stm32g431xx.h.

◆ FDCAN_CREL_YEAR

#define FDCAN_CREL_YEAR FDCAN_CREL_YEAR_Msk

Timestamp Year

Definition at line 4052 of file stm32g431xx.h.

◆ FDCAN_CREL_YEAR_Msk

#define FDCAN_CREL_YEAR_Msk (0xFUL << FDCAN_CREL_YEAR_Pos)

0x000F0000

Definition at line 4051 of file stm32g431xx.h.

◆ FDCAN_CREL_YEAR_Pos

#define FDCAN_CREL_YEAR_Pos (16U)

Definition at line 4050 of file stm32g431xx.h.

◆ FDCAN_DBTP_DBRP

#define FDCAN_DBTP_DBRP FDCAN_DBTP_DBRP_Msk

Data BIt Rate Prescaler

Definition at line 4080 of file stm32g431xx.h.

◆ FDCAN_DBTP_DBRP_Msk

#define FDCAN_DBTP_DBRP_Msk (0x1FUL << FDCAN_DBTP_DBRP_Pos)

0x001F0000

Definition at line 4079 of file stm32g431xx.h.

◆ FDCAN_DBTP_DBRP_Pos

#define FDCAN_DBTP_DBRP_Pos (16U)

Definition at line 4078 of file stm32g431xx.h.

◆ FDCAN_DBTP_DSJW

#define FDCAN_DBTP_DSJW FDCAN_DBTP_DSJW_Msk

Synchronization Jump Width

Definition at line 4071 of file stm32g431xx.h.

◆ FDCAN_DBTP_DSJW_Msk

#define FDCAN_DBTP_DSJW_Msk (0xFUL << FDCAN_DBTP_DSJW_Pos)

0x0000000F

Definition at line 4070 of file stm32g431xx.h.

◆ FDCAN_DBTP_DSJW_Pos

#define FDCAN_DBTP_DSJW_Pos (0U)

Definition at line 4069 of file stm32g431xx.h.

◆ FDCAN_DBTP_DTSEG1

#define FDCAN_DBTP_DTSEG1 FDCAN_DBTP_DTSEG1_Msk

Data time segment before sample point

Definition at line 4077 of file stm32g431xx.h.

◆ FDCAN_DBTP_DTSEG1_Msk

#define FDCAN_DBTP_DTSEG1_Msk (0x1FUL << FDCAN_DBTP_DTSEG1_Pos)

0x00001F00

Definition at line 4076 of file stm32g431xx.h.

◆ FDCAN_DBTP_DTSEG1_Pos

#define FDCAN_DBTP_DTSEG1_Pos (8U)

Definition at line 4075 of file stm32g431xx.h.

◆ FDCAN_DBTP_DTSEG2

#define FDCAN_DBTP_DTSEG2 FDCAN_DBTP_DTSEG2_Msk

Data time segment after sample point

Definition at line 4074 of file stm32g431xx.h.

◆ FDCAN_DBTP_DTSEG2_Msk

#define FDCAN_DBTP_DTSEG2_Msk (0xFUL << FDCAN_DBTP_DTSEG2_Pos)

0x000000F0

Definition at line 4073 of file stm32g431xx.h.

◆ FDCAN_DBTP_DTSEG2_Pos

#define FDCAN_DBTP_DTSEG2_Pos (4U)

Definition at line 4072 of file stm32g431xx.h.

◆ FDCAN_DBTP_TDC

#define FDCAN_DBTP_TDC FDCAN_DBTP_TDC_Msk

Transceiver Delay Compensation

Definition at line 4083 of file stm32g431xx.h.

◆ FDCAN_DBTP_TDC_Msk

#define FDCAN_DBTP_TDC_Msk (0x1UL << FDCAN_DBTP_TDC_Pos)

0x00800000

Definition at line 4082 of file stm32g431xx.h.

◆ FDCAN_DBTP_TDC_Pos

#define FDCAN_DBTP_TDC_Pos (23U)

Definition at line 4081 of file stm32g431xx.h.

◆ FDCAN_ECR_CEL

#define FDCAN_ECR_CEL FDCAN_ECR_CEL_Msk

CAN Error Logging

Definition at line 4203 of file stm32g431xx.h.

◆ FDCAN_ECR_CEL_Msk

#define FDCAN_ECR_CEL_Msk (0xFFUL << FDCAN_ECR_CEL_Pos)

0x00FF0000

Definition at line 4202 of file stm32g431xx.h.

◆ FDCAN_ECR_CEL_Pos

#define FDCAN_ECR_CEL_Pos (16U)

Definition at line 4201 of file stm32g431xx.h.

◆ FDCAN_ECR_REC

#define FDCAN_ECR_REC FDCAN_ECR_REC_Msk

Receive Error Counter

Definition at line 4197 of file stm32g431xx.h.

◆ FDCAN_ECR_REC_Msk

#define FDCAN_ECR_REC_Msk (0x7FUL << FDCAN_ECR_REC_Pos)

0x00007F00

Definition at line 4196 of file stm32g431xx.h.

◆ FDCAN_ECR_REC_Pos

#define FDCAN_ECR_REC_Pos (8U)

Definition at line 4195 of file stm32g431xx.h.

◆ FDCAN_ECR_RP

#define FDCAN_ECR_RP FDCAN_ECR_RP_Msk

Receive Error Passive

Definition at line 4200 of file stm32g431xx.h.

◆ FDCAN_ECR_RP_Msk

#define FDCAN_ECR_RP_Msk (0x1UL << FDCAN_ECR_RP_Pos)

0x00008000

Definition at line 4199 of file stm32g431xx.h.

◆ FDCAN_ECR_RP_Pos

#define FDCAN_ECR_RP_Pos (15U)

Definition at line 4198 of file stm32g431xx.h.

◆ FDCAN_ECR_TEC

#define FDCAN_ECR_TEC FDCAN_ECR_TEC_Msk

Transmit Error Counter

Definition at line 4194 of file stm32g431xx.h.

◆ FDCAN_ECR_TEC_Msk

#define FDCAN_ECR_TEC_Msk (0xFFUL << FDCAN_ECR_TEC_Pos)

0x000000FF

Definition at line 4193 of file stm32g431xx.h.

◆ FDCAN_ECR_TEC_Pos

#define FDCAN_ECR_TEC_Pos (0U)

Definition at line 4192 of file stm32g431xx.h.

◆ FDCAN_ENDN_ETV

#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk

Endiannes Test Value

Definition at line 4066 of file stm32g431xx.h.

◆ FDCAN_ENDN_ETV_Msk

#define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos)

0xFFFFFFFF

Definition at line 4065 of file stm32g431xx.h.

◆ FDCAN_ENDN_ETV_Pos

#define FDCAN_ENDN_ETV_Pos (0U)

Definition at line 4064 of file stm32g431xx.h.

◆ FDCAN_HPMS_BIDX

#define FDCAN_HPMS_BIDX FDCAN_HPMS_BIDX_Msk

Buffer Index

Definition at line 4478 of file stm32g431xx.h.

◆ FDCAN_HPMS_BIDX_Msk

#define FDCAN_HPMS_BIDX_Msk (0x7UL << FDCAN_HPMS_BIDX_Pos)

0x00000007

Definition at line 4477 of file stm32g431xx.h.

◆ FDCAN_HPMS_BIDX_Pos

#define FDCAN_HPMS_BIDX_Pos (0U)

Definition at line 4476 of file stm32g431xx.h.

◆ FDCAN_HPMS_FIDX

#define FDCAN_HPMS_FIDX FDCAN_HPMS_FIDX_Msk

Filter Index

Definition at line 4484 of file stm32g431xx.h.

◆ FDCAN_HPMS_FIDX_Msk

#define FDCAN_HPMS_FIDX_Msk (0x1FUL << FDCAN_HPMS_FIDX_Pos)

0x00001F00

Definition at line 4483 of file stm32g431xx.h.

◆ FDCAN_HPMS_FIDX_Pos

#define FDCAN_HPMS_FIDX_Pos (8U)

Definition at line 4482 of file stm32g431xx.h.

◆ FDCAN_HPMS_FLST

#define FDCAN_HPMS_FLST FDCAN_HPMS_FLST_Msk

Filter List

Definition at line 4487 of file stm32g431xx.h.

◆ FDCAN_HPMS_FLST_Msk

#define FDCAN_HPMS_FLST_Msk (0x1UL << FDCAN_HPMS_FLST_Pos)

0x00008000

Definition at line 4486 of file stm32g431xx.h.

◆ FDCAN_HPMS_FLST_Pos

#define FDCAN_HPMS_FLST_Pos (15U)

Definition at line 4485 of file stm32g431xx.h.

◆ FDCAN_HPMS_MSI

#define FDCAN_HPMS_MSI FDCAN_HPMS_MSI_Msk

Message Storage Indicator

Definition at line 4481 of file stm32g431xx.h.

◆ FDCAN_HPMS_MSI_Msk

#define FDCAN_HPMS_MSI_Msk (0x3UL << FDCAN_HPMS_MSI_Pos)

0x000000C0

Definition at line 4480 of file stm32g431xx.h.

◆ FDCAN_HPMS_MSI_Pos

#define FDCAN_HPMS_MSI_Pos (6U)

Definition at line 4479 of file stm32g431xx.h.

◆ FDCAN_IE_ARAE

#define FDCAN_IE_ARAE FDCAN_IE_ARAE_Msk

Access to Reserved Address Enable

Definition at line 4394 of file stm32g431xx.h.

◆ FDCAN_IE_ARAE_Msk

#define FDCAN_IE_ARAE_Msk (0x1UL << FDCAN_IE_ARAE_Pos)

0x00800000

Definition at line 4393 of file stm32g431xx.h.

◆ FDCAN_IE_ARAE_Pos

#define FDCAN_IE_ARAE_Pos (23U)

Definition at line 4392 of file stm32g431xx.h.

◆ FDCAN_IE_BOE

#define FDCAN_IE_BOE FDCAN_IE_BOE_Msk

Bus_Off Status Enable

Definition at line 4382 of file stm32g431xx.h.

◆ FDCAN_IE_BOE_Msk

#define FDCAN_IE_BOE_Msk (0x1UL << FDCAN_IE_BOE_Pos)

0x00080000

Definition at line 4381 of file stm32g431xx.h.

◆ FDCAN_IE_BOE_Pos

#define FDCAN_IE_BOE_Pos (19U)

Definition at line 4380 of file stm32g431xx.h.

◆ FDCAN_IE_ELOE

#define FDCAN_IE_ELOE FDCAN_IE_ELOE_Msk

Error Logging Overflow Enable

Definition at line 4373 of file stm32g431xx.h.

◆ FDCAN_IE_ELOE_Msk

#define FDCAN_IE_ELOE_Msk (0x1UL << FDCAN_IE_ELOE_Pos)

0x00010000

Definition at line 4372 of file stm32g431xx.h.

◆ FDCAN_IE_ELOE_Pos

#define FDCAN_IE_ELOE_Pos (16U)

Definition at line 4371 of file stm32g431xx.h.

◆ FDCAN_IE_EPE

#define FDCAN_IE_EPE FDCAN_IE_EPE_Msk

Error Passive Enable

Definition at line 4376 of file stm32g431xx.h.

◆ FDCAN_IE_EPE_Msk

#define FDCAN_IE_EPE_Msk (0x1UL << FDCAN_IE_EPE_Pos)

0x00020000

Definition at line 4375 of file stm32g431xx.h.

◆ FDCAN_IE_EPE_Pos

#define FDCAN_IE_EPE_Pos (17U)

Definition at line 4374 of file stm32g431xx.h.

◆ FDCAN_IE_EWE

#define FDCAN_IE_EWE FDCAN_IE_EWE_Msk

Warning Status Enable

Definition at line 4379 of file stm32g431xx.h.

◆ FDCAN_IE_EWE_Msk

#define FDCAN_IE_EWE_Msk (0x1UL << FDCAN_IE_EWE_Pos)

0x00040000

Definition at line 4378 of file stm32g431xx.h.

◆ FDCAN_IE_EWE_Pos

#define FDCAN_IE_EWE_Pos (18U)

Definition at line 4377 of file stm32g431xx.h.

◆ FDCAN_IE_HPME

#define FDCAN_IE_HPME FDCAN_IE_HPME_Msk

High Priority Message Enable

Definition at line 4343 of file stm32g431xx.h.

◆ FDCAN_IE_HPME_Msk

#define FDCAN_IE_HPME_Msk (0x1UL << FDCAN_IE_HPME_Pos)

0x00000040

Definition at line 4342 of file stm32g431xx.h.

◆ FDCAN_IE_HPME_Pos

#define FDCAN_IE_HPME_Pos (6U)

Definition at line 4341 of file stm32g431xx.h.

◆ FDCAN_IE_MRAFE

#define FDCAN_IE_MRAFE FDCAN_IE_MRAFE_Msk

Message RAM Access Failure Enable

Definition at line 4367 of file stm32g431xx.h.

◆ FDCAN_IE_MRAFE_Msk

#define FDCAN_IE_MRAFE_Msk (0x1UL << FDCAN_IE_MRAFE_Pos)

0x00004000

Definition at line 4366 of file stm32g431xx.h.

◆ FDCAN_IE_MRAFE_Pos

#define FDCAN_IE_MRAFE_Pos (14U)

Definition at line 4365 of file stm32g431xx.h.

◆ FDCAN_IE_PEAE

#define FDCAN_IE_PEAE FDCAN_IE_PEAE_Msk

Protocol Error in Arbitration Phase Enable

Definition at line 4388 of file stm32g431xx.h.

◆ FDCAN_IE_PEAE_Msk

#define FDCAN_IE_PEAE_Msk (0x1UL << FDCAN_IE_PEAE_Pos)

0x00200000

Definition at line 4387 of file stm32g431xx.h.

◆ FDCAN_IE_PEAE_Pos

#define FDCAN_IE_PEAE_Pos (21U)

Definition at line 4386 of file stm32g431xx.h.

◆ FDCAN_IE_PEDE

#define FDCAN_IE_PEDE FDCAN_IE_PEDE_Msk

Protocol Error in Data Phase Enable

Definition at line 4391 of file stm32g431xx.h.

◆ FDCAN_IE_PEDE_Msk

#define FDCAN_IE_PEDE_Msk (0x1UL << FDCAN_IE_PEDE_Pos)

0x00400000

Definition at line 4390 of file stm32g431xx.h.

◆ FDCAN_IE_PEDE_Pos

#define FDCAN_IE_PEDE_Pos (22U)

Definition at line 4389 of file stm32g431xx.h.

◆ FDCAN_IE_RF0FE

#define FDCAN_IE_RF0FE FDCAN_IE_RF0FE_Msk

Rx FIFO 0 Full Enable

Definition at line 4328 of file stm32g431xx.h.

◆ FDCAN_IE_RF0FE_Msk

#define FDCAN_IE_RF0FE_Msk (0x1UL << FDCAN_IE_RF0FE_Pos)

0x00000002

Definition at line 4327 of file stm32g431xx.h.

◆ FDCAN_IE_RF0FE_Pos

#define FDCAN_IE_RF0FE_Pos (1U)

Definition at line 4326 of file stm32g431xx.h.

◆ FDCAN_IE_RF0LE

#define FDCAN_IE_RF0LE FDCAN_IE_RF0LE_Msk

Rx FIFO 0 Message Lost Enable

Definition at line 4331 of file stm32g431xx.h.

◆ FDCAN_IE_RF0LE_Msk

#define FDCAN_IE_RF0LE_Msk (0x1UL << FDCAN_IE_RF0LE_Pos)

0x00000004

Definition at line 4330 of file stm32g431xx.h.

◆ FDCAN_IE_RF0LE_Pos

#define FDCAN_IE_RF0LE_Pos (2U)

Definition at line 4329 of file stm32g431xx.h.

◆ FDCAN_IE_RF0NE

#define FDCAN_IE_RF0NE FDCAN_IE_RF0NE_Msk

Rx FIFO 0 New Message Enable

Definition at line 4325 of file stm32g431xx.h.

◆ FDCAN_IE_RF0NE_Msk

#define FDCAN_IE_RF0NE_Msk (0x1UL << FDCAN_IE_RF0NE_Pos)

0x00000001

Definition at line 4324 of file stm32g431xx.h.

◆ FDCAN_IE_RF0NE_Pos

#define FDCAN_IE_RF0NE_Pos (0U)

Definition at line 4323 of file stm32g431xx.h.

◆ FDCAN_IE_RF1FE

#define FDCAN_IE_RF1FE FDCAN_IE_RF1FE_Msk

Rx FIFO 1 Full Enable

Definition at line 4337 of file stm32g431xx.h.

◆ FDCAN_IE_RF1FE_Msk

#define FDCAN_IE_RF1FE_Msk (0x1UL << FDCAN_IE_RF1FE_Pos)

0x00000010

Definition at line 4336 of file stm32g431xx.h.

◆ FDCAN_IE_RF1FE_Pos

#define FDCAN_IE_RF1FE_Pos (4U)

Definition at line 4335 of file stm32g431xx.h.

◆ FDCAN_IE_RF1LE

#define FDCAN_IE_RF1LE FDCAN_IE_RF1LE_Msk

Rx FIFO 1 Message Lost Enable

Definition at line 4340 of file stm32g431xx.h.

◆ FDCAN_IE_RF1LE_Msk

#define FDCAN_IE_RF1LE_Msk (0x1UL << FDCAN_IE_RF1LE_Pos)

0x00000020

Definition at line 4339 of file stm32g431xx.h.

◆ FDCAN_IE_RF1LE_Pos

#define FDCAN_IE_RF1LE_Pos (5U)

Definition at line 4338 of file stm32g431xx.h.

◆ FDCAN_IE_RF1NE

#define FDCAN_IE_RF1NE FDCAN_IE_RF1NE_Msk

Rx FIFO 1 New Message Enable

Definition at line 4334 of file stm32g431xx.h.

◆ FDCAN_IE_RF1NE_Msk

#define FDCAN_IE_RF1NE_Msk (0x1UL << FDCAN_IE_RF1NE_Pos)

0x00000008

Definition at line 4333 of file stm32g431xx.h.

◆ FDCAN_IE_RF1NE_Pos

#define FDCAN_IE_RF1NE_Pos (3U)

Definition at line 4332 of file stm32g431xx.h.

◆ FDCAN_IE_TCE

#define FDCAN_IE_TCE FDCAN_IE_TCE_Msk

Transmission Completed Enable

Definition at line 4346 of file stm32g431xx.h.

◆ FDCAN_IE_TCE_Msk

#define FDCAN_IE_TCE_Msk (0x1UL << FDCAN_IE_TCE_Pos)

0x00000080

Definition at line 4345 of file stm32g431xx.h.

◆ FDCAN_IE_TCE_Pos

#define FDCAN_IE_TCE_Pos (7U)

Definition at line 4344 of file stm32g431xx.h.

◆ FDCAN_IE_TCFE

#define FDCAN_IE_TCFE FDCAN_IE_TCFE_Msk

Transmission Cancellation Finished Enable

Definition at line 4349 of file stm32g431xx.h.

◆ FDCAN_IE_TCFE_Msk

#define FDCAN_IE_TCFE_Msk (0x1UL << FDCAN_IE_TCFE_Pos)

0x00000100

Definition at line 4348 of file stm32g431xx.h.

◆ FDCAN_IE_TCFE_Pos

#define FDCAN_IE_TCFE_Pos (8U)

Definition at line 4347 of file stm32g431xx.h.

◆ FDCAN_IE_TEFFE

#define FDCAN_IE_TEFFE FDCAN_IE_TEFFE_Msk

Tx Event FIFO Full Enable

Definition at line 4358 of file stm32g431xx.h.

◆ FDCAN_IE_TEFFE_Msk

#define FDCAN_IE_TEFFE_Msk (0x1UL << FDCAN_IE_TEFFE_Pos)

0x00000800

Definition at line 4357 of file stm32g431xx.h.

◆ FDCAN_IE_TEFFE_Pos

#define FDCAN_IE_TEFFE_Pos (11U)

Definition at line 4356 of file stm32g431xx.h.

◆ FDCAN_IE_TEFLE

#define FDCAN_IE_TEFLE FDCAN_IE_TEFLE_Msk

Tx Event FIFO Element Lost Enable

Definition at line 4361 of file stm32g431xx.h.

◆ FDCAN_IE_TEFLE_Msk

#define FDCAN_IE_TEFLE_Msk (0x1UL << FDCAN_IE_TEFLE_Pos)

0x00001000

Definition at line 4360 of file stm32g431xx.h.

◆ FDCAN_IE_TEFLE_Pos

#define FDCAN_IE_TEFLE_Pos (12U)

Definition at line 4359 of file stm32g431xx.h.

◆ FDCAN_IE_TEFNE

#define FDCAN_IE_TEFNE FDCAN_IE_TEFNE_Msk

Tx Event FIFO New Entry Enable

Definition at line 4355 of file stm32g431xx.h.

◆ FDCAN_IE_TEFNE_Msk

#define FDCAN_IE_TEFNE_Msk (0x1UL << FDCAN_IE_TEFNE_Pos)

0x00000400

Definition at line 4354 of file stm32g431xx.h.

◆ FDCAN_IE_TEFNE_Pos

#define FDCAN_IE_TEFNE_Pos (10U)

Definition at line 4353 of file stm32g431xx.h.

◆ FDCAN_IE_TFEE

#define FDCAN_IE_TFEE FDCAN_IE_TFEE_Msk

Tx FIFO Empty Enable

Definition at line 4352 of file stm32g431xx.h.

◆ FDCAN_IE_TFEE_Msk

#define FDCAN_IE_TFEE_Msk (0x1UL << FDCAN_IE_TFEE_Pos)

0x00000200

Definition at line 4351 of file stm32g431xx.h.

◆ FDCAN_IE_TFEE_Pos

#define FDCAN_IE_TFEE_Pos (9U)

Definition at line 4350 of file stm32g431xx.h.

◆ FDCAN_IE_TOOE

#define FDCAN_IE_TOOE FDCAN_IE_TOOE_Msk

Timeout Occurred Enable

Definition at line 4370 of file stm32g431xx.h.

◆ FDCAN_IE_TOOE_Msk

#define FDCAN_IE_TOOE_Msk (0x1UL << FDCAN_IE_TOOE_Pos)

0x00008000

Definition at line 4369 of file stm32g431xx.h.

◆ FDCAN_IE_TOOE_Pos

#define FDCAN_IE_TOOE_Pos (15U)

Definition at line 4368 of file stm32g431xx.h.

◆ FDCAN_IE_TSWE

#define FDCAN_IE_TSWE FDCAN_IE_TSWE_Msk

Timestamp Wraparound Enable

Definition at line 4364 of file stm32g431xx.h.

◆ FDCAN_IE_TSWE_Msk

#define FDCAN_IE_TSWE_Msk (0x1UL << FDCAN_IE_TSWE_Pos)

0x00002000

Definition at line 4363 of file stm32g431xx.h.

◆ FDCAN_IE_TSWE_Pos

#define FDCAN_IE_TSWE_Pos (13U)

Definition at line 4362 of file stm32g431xx.h.

◆ FDCAN_IE_WDIE

#define FDCAN_IE_WDIE FDCAN_IE_WDIE_Msk

Watchdog Interrupt Enable

Definition at line 4385 of file stm32g431xx.h.

◆ FDCAN_IE_WDIE_Msk

#define FDCAN_IE_WDIE_Msk (0x1UL << FDCAN_IE_WDIE_Pos)

0x00100000

Definition at line 4384 of file stm32g431xx.h.

◆ FDCAN_IE_WDIE_Pos

#define FDCAN_IE_WDIE_Pos (20U)

Definition at line 4383 of file stm32g431xx.h.

◆ FDCAN_ILE_EINT0

#define FDCAN_ILE_EINT0 FDCAN_ILE_EINT0_Msk

Enable Interrupt Line 0

Definition at line 4439 of file stm32g431xx.h.

◆ FDCAN_ILE_EINT0_Msk

#define FDCAN_ILE_EINT0_Msk (0x1UL << FDCAN_ILE_EINT0_Pos)

0x00000001

Definition at line 4438 of file stm32g431xx.h.

◆ FDCAN_ILE_EINT0_Pos

#define FDCAN_ILE_EINT0_Pos (0U)

Definition at line 4437 of file stm32g431xx.h.

◆ FDCAN_ILE_EINT1

#define FDCAN_ILE_EINT1 FDCAN_ILE_EINT1_Msk

Enable Interrupt Line 1

Definition at line 4442 of file stm32g431xx.h.

◆ FDCAN_ILE_EINT1_Msk

#define FDCAN_ILE_EINT1_Msk (0x1UL << FDCAN_ILE_EINT1_Pos)

0x00000002

Definition at line 4441 of file stm32g431xx.h.

◆ FDCAN_ILE_EINT1_Pos

#define FDCAN_ILE_EINT1_Pos (1U)

Definition at line 4440 of file stm32g431xx.h.

◆ FDCAN_ILS_BERR

#define FDCAN_ILS_BERR FDCAN_ILS_BERR_Msk

Error Passive Error Logging Overflow

Definition at line 4426 of file stm32g431xx.h.

◆ FDCAN_ILS_BERR_Msk

#define FDCAN_ILS_BERR_Msk (0x1UL << FDCAN_ILS_BERR_Pos)

0x00000020

Definition at line 4424 of file stm32g431xx.h.

◆ FDCAN_ILS_BERR_Pos

#define FDCAN_ILS_BERR_Pos (5U)

Definition at line 4423 of file stm32g431xx.h.

◆ FDCAN_ILS_MISC

#define FDCAN_ILS_MISC FDCAN_ILS_MISC_Msk

Timeout Occurred Message RAM Access Failure Timestamp Wraparound

Definition at line 4422 of file stm32g431xx.h.

◆ FDCAN_ILS_MISC_Msk

#define FDCAN_ILS_MISC_Msk (0x1UL << FDCAN_ILS_MISC_Pos)

0x00000010

Definition at line 4419 of file stm32g431xx.h.

◆ FDCAN_ILS_MISC_Pos

#define FDCAN_ILS_MISC_Pos (4U)

Definition at line 4418 of file stm32g431xx.h.

◆ FDCAN_ILS_PERR

#define FDCAN_ILS_PERR FDCAN_ILS_PERR_Msk

Access to Reserved Address Line Protocol Error in Data Phase Line Protocol Error in Arbitration Phase Line Watchdog Interrupt Line Bus_Off Status Warning Status

Definition at line 4434 of file stm32g431xx.h.

◆ FDCAN_ILS_PERR_Msk

#define FDCAN_ILS_PERR_Msk (0x1UL << FDCAN_ILS_PERR_Pos)

0x00000040

Definition at line 4428 of file stm32g431xx.h.

◆ FDCAN_ILS_PERR_Pos

#define FDCAN_ILS_PERR_Pos (6U)

Definition at line 4427 of file stm32g431xx.h.

◆ FDCAN_ILS_RXFIFO0

#define FDCAN_ILS_RXFIFO0 FDCAN_ILS_RXFIFO0_Msk

Rx FIFO 0 Message Lost Rx FIFO 0 is Full Rx FIFO 0 Has New Message

Definition at line 4401 of file stm32g431xx.h.

◆ FDCAN_ILS_RXFIFO0_Msk

#define FDCAN_ILS_RXFIFO0_Msk (0x1UL << FDCAN_ILS_RXFIFO0_Pos)

0x00000001

Definition at line 4398 of file stm32g431xx.h.

◆ FDCAN_ILS_RXFIFO0_Pos

#define FDCAN_ILS_RXFIFO0_Pos (0U)

Definition at line 4397 of file stm32g431xx.h.

◆ FDCAN_ILS_RXFIFO1

#define FDCAN_ILS_RXFIFO1 FDCAN_ILS_RXFIFO1_Msk

Rx FIFO 1 Message Lost Rx FIFO 1 is Full Rx FIFO 1 Has New Message

Definition at line 4406 of file stm32g431xx.h.

◆ FDCAN_ILS_RXFIFO1_Msk

#define FDCAN_ILS_RXFIFO1_Msk (0x1UL << FDCAN_ILS_RXFIFO1_Pos)

0x00000002

Definition at line 4403 of file stm32g431xx.h.

◆ FDCAN_ILS_RXFIFO1_Pos

#define FDCAN_ILS_RXFIFO1_Pos (1U)

Definition at line 4402 of file stm32g431xx.h.

◆ FDCAN_ILS_SMSG

#define FDCAN_ILS_SMSG FDCAN_ILS_SMSG_Msk

Transmission Cancellation Finished Transmission Completed High Priority Message

Definition at line 4411 of file stm32g431xx.h.

◆ FDCAN_ILS_SMSG_Msk

#define FDCAN_ILS_SMSG_Msk (0x1UL << FDCAN_ILS_SMSG_Pos)

0x00000004

Definition at line 4408 of file stm32g431xx.h.

◆ FDCAN_ILS_SMSG_Pos

#define FDCAN_ILS_SMSG_Pos (2U)

Definition at line 4407 of file stm32g431xx.h.

◆ FDCAN_ILS_TFERR

#define FDCAN_ILS_TFERR FDCAN_ILS_TFERR_Msk

Tx Event FIFO Element Lost Tx Event FIFO Full Tx Event FIFO New Entry Tx FIFO Empty Interrupt Line

Definition at line 4417 of file stm32g431xx.h.

◆ FDCAN_ILS_TFERR_Msk

#define FDCAN_ILS_TFERR_Msk (0x1UL << FDCAN_ILS_TFERR_Pos)

0x00000008

Definition at line 4413 of file stm32g431xx.h.

◆ FDCAN_ILS_TFERR_Pos

#define FDCAN_ILS_TFERR_Pos (3U)

Definition at line 4412 of file stm32g431xx.h.

◆ FDCAN_IR_ARA

#define FDCAN_IR_ARA FDCAN_IR_ARA_Msk

Access to Reserved Address

Definition at line 4320 of file stm32g431xx.h.

◆ FDCAN_IR_ARA_Msk

#define FDCAN_IR_ARA_Msk (0x1UL << FDCAN_IR_ARA_Pos)

0x00800000

Definition at line 4319 of file stm32g431xx.h.

◆ FDCAN_IR_ARA_Pos

#define FDCAN_IR_ARA_Pos (23U)

Definition at line 4318 of file stm32g431xx.h.

◆ FDCAN_IR_BO

#define FDCAN_IR_BO FDCAN_IR_BO_Msk

Bus_Off Status

Definition at line 4308 of file stm32g431xx.h.

◆ FDCAN_IR_BO_Msk

#define FDCAN_IR_BO_Msk (0x1UL << FDCAN_IR_BO_Pos)

0x00080000

Definition at line 4307 of file stm32g431xx.h.

◆ FDCAN_IR_BO_Pos

#define FDCAN_IR_BO_Pos (19U)

Definition at line 4306 of file stm32g431xx.h.

◆ FDCAN_IR_ELO

#define FDCAN_IR_ELO FDCAN_IR_ELO_Msk

Error Logging Overflow

Definition at line 4299 of file stm32g431xx.h.

◆ FDCAN_IR_ELO_Msk

#define FDCAN_IR_ELO_Msk (0x1UL << FDCAN_IR_ELO_Pos)

0x00010000

Definition at line 4298 of file stm32g431xx.h.

◆ FDCAN_IR_ELO_Pos

#define FDCAN_IR_ELO_Pos (16U)

Definition at line 4297 of file stm32g431xx.h.

◆ FDCAN_IR_EP

#define FDCAN_IR_EP FDCAN_IR_EP_Msk

Error Passive

Definition at line 4302 of file stm32g431xx.h.

◆ FDCAN_IR_EP_Msk

#define FDCAN_IR_EP_Msk (0x1UL << FDCAN_IR_EP_Pos)

0x00020000

Definition at line 4301 of file stm32g431xx.h.

◆ FDCAN_IR_EP_Pos

#define FDCAN_IR_EP_Pos (17U)

Definition at line 4300 of file stm32g431xx.h.

◆ FDCAN_IR_EW

#define FDCAN_IR_EW FDCAN_IR_EW_Msk

Warning Status

Definition at line 4305 of file stm32g431xx.h.

◆ FDCAN_IR_EW_Msk

#define FDCAN_IR_EW_Msk (0x1UL << FDCAN_IR_EW_Pos)

0x00040000

Definition at line 4304 of file stm32g431xx.h.

◆ FDCAN_IR_EW_Pos

#define FDCAN_IR_EW_Pos (18U)

Definition at line 4303 of file stm32g431xx.h.

◆ FDCAN_IR_HPM

#define FDCAN_IR_HPM FDCAN_IR_HPM_Msk

High Priority Message

Definition at line 4269 of file stm32g431xx.h.

◆ FDCAN_IR_HPM_Msk

#define FDCAN_IR_HPM_Msk (0x1UL << FDCAN_IR_HPM_Pos)

0x00000040

Definition at line 4268 of file stm32g431xx.h.

◆ FDCAN_IR_HPM_Pos

#define FDCAN_IR_HPM_Pos (6U)

Definition at line 4267 of file stm32g431xx.h.

◆ FDCAN_IR_MRAF

#define FDCAN_IR_MRAF FDCAN_IR_MRAF_Msk

Message RAM Access Failure

Definition at line 4293 of file stm32g431xx.h.

◆ FDCAN_IR_MRAF_Msk

#define FDCAN_IR_MRAF_Msk (0x1UL << FDCAN_IR_MRAF_Pos)

0x00004000

Definition at line 4292 of file stm32g431xx.h.

◆ FDCAN_IR_MRAF_Pos

#define FDCAN_IR_MRAF_Pos (14U)

Definition at line 4291 of file stm32g431xx.h.

◆ FDCAN_IR_PEA

#define FDCAN_IR_PEA FDCAN_IR_PEA_Msk

Protocol Error in Arbitration Phase

Definition at line 4314 of file stm32g431xx.h.

◆ FDCAN_IR_PEA_Msk

#define FDCAN_IR_PEA_Msk (0x1UL << FDCAN_IR_PEA_Pos)

0x00200000

Definition at line 4313 of file stm32g431xx.h.

◆ FDCAN_IR_PEA_Pos

#define FDCAN_IR_PEA_Pos (21U)

Definition at line 4312 of file stm32g431xx.h.

◆ FDCAN_IR_PED

#define FDCAN_IR_PED FDCAN_IR_PED_Msk

Protocol Error in Data Phase

Definition at line 4317 of file stm32g431xx.h.

◆ FDCAN_IR_PED_Msk

#define FDCAN_IR_PED_Msk (0x1UL << FDCAN_IR_PED_Pos)

0x00400000

Definition at line 4316 of file stm32g431xx.h.

◆ FDCAN_IR_PED_Pos

#define FDCAN_IR_PED_Pos (22U)

Definition at line 4315 of file stm32g431xx.h.

◆ FDCAN_IR_RF0F

#define FDCAN_IR_RF0F FDCAN_IR_RF0F_Msk

Rx FIFO 0 Full

Definition at line 4254 of file stm32g431xx.h.

◆ FDCAN_IR_RF0F_Msk

#define FDCAN_IR_RF0F_Msk (0x1UL << FDCAN_IR_RF0F_Pos)

0x00000002

Definition at line 4253 of file stm32g431xx.h.

◆ FDCAN_IR_RF0F_Pos

#define FDCAN_IR_RF0F_Pos (1U)

Definition at line 4252 of file stm32g431xx.h.

◆ FDCAN_IR_RF0L

#define FDCAN_IR_RF0L FDCAN_IR_RF0L_Msk

Rx FIFO 0 Message Lost

Definition at line 4257 of file stm32g431xx.h.

◆ FDCAN_IR_RF0L_Msk

#define FDCAN_IR_RF0L_Msk (0x1UL << FDCAN_IR_RF0L_Pos)

0x00000004

Definition at line 4256 of file stm32g431xx.h.

◆ FDCAN_IR_RF0L_Pos

#define FDCAN_IR_RF0L_Pos (2U)

Definition at line 4255 of file stm32g431xx.h.

◆ FDCAN_IR_RF0N

#define FDCAN_IR_RF0N FDCAN_IR_RF0N_Msk

Rx FIFO 0 New Message

Definition at line 4251 of file stm32g431xx.h.

◆ FDCAN_IR_RF0N_Msk

#define FDCAN_IR_RF0N_Msk (0x1UL << FDCAN_IR_RF0N_Pos)

0x00000001

Definition at line 4250 of file stm32g431xx.h.

◆ FDCAN_IR_RF0N_Pos

#define FDCAN_IR_RF0N_Pos (0U)

Definition at line 4249 of file stm32g431xx.h.

◆ FDCAN_IR_RF1F

#define FDCAN_IR_RF1F FDCAN_IR_RF1F_Msk

Rx FIFO 1 Full

Definition at line 4263 of file stm32g431xx.h.

◆ FDCAN_IR_RF1F_Msk

#define FDCAN_IR_RF1F_Msk (0x1UL << FDCAN_IR_RF1F_Pos)

0x00000010

Definition at line 4262 of file stm32g431xx.h.

◆ FDCAN_IR_RF1F_Pos

#define FDCAN_IR_RF1F_Pos (4U)

Definition at line 4261 of file stm32g431xx.h.

◆ FDCAN_IR_RF1L

#define FDCAN_IR_RF1L FDCAN_IR_RF1L_Msk

Rx FIFO 1 Message Lost

Definition at line 4266 of file stm32g431xx.h.

◆ FDCAN_IR_RF1L_Msk

#define FDCAN_IR_RF1L_Msk (0x1UL << FDCAN_IR_RF1L_Pos)

0x00000020

Definition at line 4265 of file stm32g431xx.h.

◆ FDCAN_IR_RF1L_Pos

#define FDCAN_IR_RF1L_Pos (5U)

Definition at line 4264 of file stm32g431xx.h.

◆ FDCAN_IR_RF1N

#define FDCAN_IR_RF1N FDCAN_IR_RF1N_Msk

Rx FIFO 1 New Message

Definition at line 4260 of file stm32g431xx.h.

◆ FDCAN_IR_RF1N_Msk

#define FDCAN_IR_RF1N_Msk (0x1UL << FDCAN_IR_RF1N_Pos)

0x00000008

Definition at line 4259 of file stm32g431xx.h.

◆ FDCAN_IR_RF1N_Pos

#define FDCAN_IR_RF1N_Pos (3U)

Definition at line 4258 of file stm32g431xx.h.

◆ FDCAN_IR_TC

#define FDCAN_IR_TC FDCAN_IR_TC_Msk

Transmission Completed

Definition at line 4272 of file stm32g431xx.h.

◆ FDCAN_IR_TC_Msk

#define FDCAN_IR_TC_Msk (0x1UL << FDCAN_IR_TC_Pos)

0x00000080

Definition at line 4271 of file stm32g431xx.h.

◆ FDCAN_IR_TC_Pos

#define FDCAN_IR_TC_Pos (7U)

Definition at line 4270 of file stm32g431xx.h.

◆ FDCAN_IR_TCF

#define FDCAN_IR_TCF FDCAN_IR_TCF_Msk

Transmission Cancellation Finished

Definition at line 4275 of file stm32g431xx.h.

◆ FDCAN_IR_TCF_Msk

#define FDCAN_IR_TCF_Msk (0x1UL << FDCAN_IR_TCF_Pos)

0x00000100

Definition at line 4274 of file stm32g431xx.h.

◆ FDCAN_IR_TCF_Pos

#define FDCAN_IR_TCF_Pos (8U)

Definition at line 4273 of file stm32g431xx.h.

◆ FDCAN_IR_TEFF

#define FDCAN_IR_TEFF FDCAN_IR_TEFF_Msk

Tx Event FIFO Full

Definition at line 4284 of file stm32g431xx.h.

◆ FDCAN_IR_TEFF_Msk

#define FDCAN_IR_TEFF_Msk (0x1UL << FDCAN_IR_TEFF_Pos)

0x00000800

Definition at line 4283 of file stm32g431xx.h.

◆ FDCAN_IR_TEFF_Pos

#define FDCAN_IR_TEFF_Pos (11U)

Definition at line 4282 of file stm32g431xx.h.

◆ FDCAN_IR_TEFL

#define FDCAN_IR_TEFL FDCAN_IR_TEFL_Msk

Tx Event FIFO Element Lost

Definition at line 4287 of file stm32g431xx.h.

◆ FDCAN_IR_TEFL_Msk

#define FDCAN_IR_TEFL_Msk (0x1UL << FDCAN_IR_TEFL_Pos)

0x00001000

Definition at line 4286 of file stm32g431xx.h.

◆ FDCAN_IR_TEFL_Pos

#define FDCAN_IR_TEFL_Pos (12U)

Definition at line 4285 of file stm32g431xx.h.

◆ FDCAN_IR_TEFN

#define FDCAN_IR_TEFN FDCAN_IR_TEFN_Msk

Tx Event FIFO New Entry

Definition at line 4281 of file stm32g431xx.h.

◆ FDCAN_IR_TEFN_Msk

#define FDCAN_IR_TEFN_Msk (0x1UL << FDCAN_IR_TEFN_Pos)

0x00000400

Definition at line 4280 of file stm32g431xx.h.

◆ FDCAN_IR_TEFN_Pos

#define FDCAN_IR_TEFN_Pos (10U)

Definition at line 4279 of file stm32g431xx.h.

◆ FDCAN_IR_TFE

#define FDCAN_IR_TFE FDCAN_IR_TFE_Msk

Tx FIFO Empty

Definition at line 4278 of file stm32g431xx.h.

◆ FDCAN_IR_TFE_Msk

#define FDCAN_IR_TFE_Msk (0x1UL << FDCAN_IR_TFE_Pos)

0x00000200

Definition at line 4277 of file stm32g431xx.h.

◆ FDCAN_IR_TFE_Pos

#define FDCAN_IR_TFE_Pos (9U)

Definition at line 4276 of file stm32g431xx.h.

◆ FDCAN_IR_TOO

#define FDCAN_IR_TOO FDCAN_IR_TOO_Msk

Timeout Occurred

Definition at line 4296 of file stm32g431xx.h.

◆ FDCAN_IR_TOO_Msk

#define FDCAN_IR_TOO_Msk (0x1UL << FDCAN_IR_TOO_Pos)

0x00008000

Definition at line 4295 of file stm32g431xx.h.

◆ FDCAN_IR_TOO_Pos

#define FDCAN_IR_TOO_Pos (15U)

Definition at line 4294 of file stm32g431xx.h.

◆ FDCAN_IR_TSW

#define FDCAN_IR_TSW FDCAN_IR_TSW_Msk

Timestamp Wraparound

Definition at line 4290 of file stm32g431xx.h.

◆ FDCAN_IR_TSW_Msk

#define FDCAN_IR_TSW_Msk (0x1UL << FDCAN_IR_TSW_Pos)

0x00002000

Definition at line 4289 of file stm32g431xx.h.

◆ FDCAN_IR_TSW_Pos

#define FDCAN_IR_TSW_Pos (13U)

Definition at line 4288 of file stm32g431xx.h.

◆ FDCAN_IR_WDI

#define FDCAN_IR_WDI FDCAN_IR_WDI_Msk

Watchdog Interrupt

Definition at line 4311 of file stm32g431xx.h.

◆ FDCAN_IR_WDI_Msk

#define FDCAN_IR_WDI_Msk (0x1UL << FDCAN_IR_WDI_Pos)

0x00100000

Definition at line 4310 of file stm32g431xx.h.

◆ FDCAN_IR_WDI_Pos

#define FDCAN_IR_WDI_Pos (20U)

Definition at line 4309 of file stm32g431xx.h.

◆ FDCAN_NBTP_NBRP

#define FDCAN_NBTP_NBRP FDCAN_NBTP_NBRP_Msk

Bit Rate Prescaler

Definition at line 4157 of file stm32g431xx.h.

◆ FDCAN_NBTP_NBRP_Msk

#define FDCAN_NBTP_NBRP_Msk (0x1FFUL << FDCAN_NBTP_NBRP_Pos)

0x01FF0000

Definition at line 4156 of file stm32g431xx.h.

◆ FDCAN_NBTP_NBRP_Pos

#define FDCAN_NBTP_NBRP_Pos (16U)

Definition at line 4155 of file stm32g431xx.h.

◆ FDCAN_NBTP_NSJW

#define FDCAN_NBTP_NSJW FDCAN_NBTP_NSJW_Msk

Nominal (Re)Synchronization Jump Width

Definition at line 4160 of file stm32g431xx.h.

◆ FDCAN_NBTP_NSJW_Msk

#define FDCAN_NBTP_NSJW_Msk (0x7FUL << FDCAN_NBTP_NSJW_Pos)

0xFE000000

Definition at line 4159 of file stm32g431xx.h.

◆ FDCAN_NBTP_NSJW_Pos

#define FDCAN_NBTP_NSJW_Pos (25U)

Definition at line 4158 of file stm32g431xx.h.

◆ FDCAN_NBTP_NTSEG1

#define FDCAN_NBTP_NTSEG1 FDCAN_NBTP_NTSEG1_Msk

Nominal Time segment before sample point

Definition at line 4154 of file stm32g431xx.h.

◆ FDCAN_NBTP_NTSEG1_Msk

#define FDCAN_NBTP_NTSEG1_Msk (0xFFUL << FDCAN_NBTP_NTSEG1_Pos)

0x0000FF00

Definition at line 4153 of file stm32g431xx.h.

◆ FDCAN_NBTP_NTSEG1_Pos

#define FDCAN_NBTP_NTSEG1_Pos (8U)

Definition at line 4152 of file stm32g431xx.h.

◆ FDCAN_NBTP_NTSEG2

#define FDCAN_NBTP_NTSEG2 FDCAN_NBTP_NTSEG2_Msk

Nominal Time segment after sample point

Definition at line 4151 of file stm32g431xx.h.

◆ FDCAN_NBTP_NTSEG2_Msk

#define FDCAN_NBTP_NTSEG2_Msk (0x7FUL << FDCAN_NBTP_NTSEG2_Pos)

0x0000007F

Definition at line 4150 of file stm32g431xx.h.

◆ FDCAN_NBTP_NTSEG2_Pos

#define FDCAN_NBTP_NTSEG2_Pos (0U)

Definition at line 4149 of file stm32g431xx.h.

◆ FDCAN_PSR_ACT

#define FDCAN_PSR_ACT FDCAN_PSR_ACT_Msk

Activity

Definition at line 4211 of file stm32g431xx.h.

◆ FDCAN_PSR_ACT_Msk

#define FDCAN_PSR_ACT_Msk (0x3UL << FDCAN_PSR_ACT_Pos)

0x00000018

Definition at line 4210 of file stm32g431xx.h.

◆ FDCAN_PSR_ACT_Pos

#define FDCAN_PSR_ACT_Pos (3U)

Definition at line 4209 of file stm32g431xx.h.

◆ FDCAN_PSR_BO

#define FDCAN_PSR_BO FDCAN_PSR_BO_Msk

Bus_Off Status

Definition at line 4220 of file stm32g431xx.h.

◆ FDCAN_PSR_BO_Msk

#define FDCAN_PSR_BO_Msk (0x1UL << FDCAN_PSR_BO_Pos)

0x00000080

Definition at line 4219 of file stm32g431xx.h.

◆ FDCAN_PSR_BO_Pos

#define FDCAN_PSR_BO_Pos (7U)

Definition at line 4218 of file stm32g431xx.h.

◆ FDCAN_PSR_DLEC

#define FDCAN_PSR_DLEC FDCAN_PSR_DLEC_Msk

Data Last Error Code

Definition at line 4223 of file stm32g431xx.h.

◆ FDCAN_PSR_DLEC_Msk

#define FDCAN_PSR_DLEC_Msk (0x7UL << FDCAN_PSR_DLEC_Pos)

0x00000700

Definition at line 4222 of file stm32g431xx.h.

◆ FDCAN_PSR_DLEC_Pos

#define FDCAN_PSR_DLEC_Pos (8U)

Definition at line 4221 of file stm32g431xx.h.

◆ FDCAN_PSR_EP

#define FDCAN_PSR_EP FDCAN_PSR_EP_Msk

Error Passive

Definition at line 4214 of file stm32g431xx.h.

◆ FDCAN_PSR_EP_Msk

#define FDCAN_PSR_EP_Msk (0x1UL << FDCAN_PSR_EP_Pos)

0x00000020

Definition at line 4213 of file stm32g431xx.h.

◆ FDCAN_PSR_EP_Pos

#define FDCAN_PSR_EP_Pos (5U)

Definition at line 4212 of file stm32g431xx.h.

◆ FDCAN_PSR_EW

#define FDCAN_PSR_EW FDCAN_PSR_EW_Msk

Warning Status

Definition at line 4217 of file stm32g431xx.h.

◆ FDCAN_PSR_EW_Msk

#define FDCAN_PSR_EW_Msk (0x1UL << FDCAN_PSR_EW_Pos)

0x00000040

Definition at line 4216 of file stm32g431xx.h.

◆ FDCAN_PSR_EW_Pos

#define FDCAN_PSR_EW_Pos (6U)

Definition at line 4215 of file stm32g431xx.h.

◆ FDCAN_PSR_LEC

#define FDCAN_PSR_LEC FDCAN_PSR_LEC_Msk

Last Error Code

Definition at line 4208 of file stm32g431xx.h.

◆ FDCAN_PSR_LEC_Msk

#define FDCAN_PSR_LEC_Msk (0x7UL << FDCAN_PSR_LEC_Pos)

0x00000007

Definition at line 4207 of file stm32g431xx.h.

◆ FDCAN_PSR_LEC_Pos

#define FDCAN_PSR_LEC_Pos (0U)

Definition at line 4206 of file stm32g431xx.h.

◆ FDCAN_PSR_PXE

#define FDCAN_PSR_PXE FDCAN_PSR_PXE_Msk

Protocol Exception Event

Definition at line 4235 of file stm32g431xx.h.

◆ FDCAN_PSR_PXE_Msk

#define FDCAN_PSR_PXE_Msk (0x1UL << FDCAN_PSR_PXE_Pos)

0x00004000

Definition at line 4234 of file stm32g431xx.h.

◆ FDCAN_PSR_PXE_Pos

#define FDCAN_PSR_PXE_Pos (14U)

Definition at line 4233 of file stm32g431xx.h.

◆ FDCAN_PSR_RBRS

#define FDCAN_PSR_RBRS FDCAN_PSR_RBRS_Msk

BRS flag of last received FDCAN Message

Definition at line 4229 of file stm32g431xx.h.

◆ FDCAN_PSR_RBRS_Msk

#define FDCAN_PSR_RBRS_Msk (0x1UL << FDCAN_PSR_RBRS_Pos)

0x00001000

Definition at line 4228 of file stm32g431xx.h.

◆ FDCAN_PSR_RBRS_Pos

#define FDCAN_PSR_RBRS_Pos (12U)

Definition at line 4227 of file stm32g431xx.h.

◆ FDCAN_PSR_REDL

#define FDCAN_PSR_REDL FDCAN_PSR_REDL_Msk

Received FDCAN Message

Definition at line 4232 of file stm32g431xx.h.

◆ FDCAN_PSR_REDL_Msk

#define FDCAN_PSR_REDL_Msk (0x1UL << FDCAN_PSR_REDL_Pos)

0x00002000

Definition at line 4231 of file stm32g431xx.h.

◆ FDCAN_PSR_REDL_Pos

#define FDCAN_PSR_REDL_Pos (13U)

Definition at line 4230 of file stm32g431xx.h.

◆ FDCAN_PSR_RESI

#define FDCAN_PSR_RESI FDCAN_PSR_RESI_Msk

ESI flag of last received FDCAN Message

Definition at line 4226 of file stm32g431xx.h.

◆ FDCAN_PSR_RESI_Msk

#define FDCAN_PSR_RESI_Msk (0x1UL << FDCAN_PSR_RESI_Pos)

0x00000800

Definition at line 4225 of file stm32g431xx.h.

◆ FDCAN_PSR_RESI_Pos

#define FDCAN_PSR_RESI_Pos (11U)

Definition at line 4224 of file stm32g431xx.h.

◆ FDCAN_PSR_TDCV

#define FDCAN_PSR_TDCV FDCAN_PSR_TDCV_Msk

Transmitter Delay Compensation Value

Definition at line 4238 of file stm32g431xx.h.

◆ FDCAN_PSR_TDCV_Msk

#define FDCAN_PSR_TDCV_Msk (0x7FUL << FDCAN_PSR_TDCV_Pos)

0x007F0000

Definition at line 4237 of file stm32g431xx.h.

◆ FDCAN_PSR_TDCV_Pos

#define FDCAN_PSR_TDCV_Pos (16U)

Definition at line 4236 of file stm32g431xx.h.

◆ FDCAN_RWD_WDC

#define FDCAN_RWD_WDC FDCAN_RWD_WDC_Msk

Watchdog configuration

Definition at line 4099 of file stm32g431xx.h.

◆ FDCAN_RWD_WDC_Msk

#define FDCAN_RWD_WDC_Msk (0xFFUL << FDCAN_RWD_WDC_Pos)

0x000000FF

Definition at line 4098 of file stm32g431xx.h.

◆ FDCAN_RWD_WDC_Pos

#define FDCAN_RWD_WDC_Pos (0U)

Definition at line 4097 of file stm32g431xx.h.

◆ FDCAN_RWD_WDV

#define FDCAN_RWD_WDV FDCAN_RWD_WDV_Msk

Watchdog value

Definition at line 4102 of file stm32g431xx.h.

◆ FDCAN_RWD_WDV_Msk

#define FDCAN_RWD_WDV_Msk (0xFFUL << FDCAN_RWD_WDV_Pos)

0x0000FF00

Definition at line 4101 of file stm32g431xx.h.

◆ FDCAN_RWD_WDV_Pos

#define FDCAN_RWD_WDV_Pos (8U)

Definition at line 4100 of file stm32g431xx.h.

◆ FDCAN_RXF0A_F0AI

#define FDCAN_RXF0A_F0AI FDCAN_RXF0A_F0AI_Msk

Rx FIFO 0 Acknowledge Index

Definition at line 4509 of file stm32g431xx.h.

◆ FDCAN_RXF0A_F0AI_Msk

#define FDCAN_RXF0A_F0AI_Msk (0x7UL << FDCAN_RXF0A_F0AI_Pos)

0x00000007

Definition at line 4508 of file stm32g431xx.h.

◆ FDCAN_RXF0A_F0AI_Pos

#define FDCAN_RXF0A_F0AI_Pos (0U)

Definition at line 4507 of file stm32g431xx.h.

◆ FDCAN_RXF0S_F0F

#define FDCAN_RXF0S_F0F FDCAN_RXF0S_F0F_Msk

Rx FIFO 0 Full

Definition at line 4501 of file stm32g431xx.h.

◆ FDCAN_RXF0S_F0F_Msk

#define FDCAN_RXF0S_F0F_Msk (0x1UL << FDCAN_RXF0S_F0F_Pos)

0x01000000

Definition at line 4500 of file stm32g431xx.h.

◆ FDCAN_RXF0S_F0F_Pos

#define FDCAN_RXF0S_F0F_Pos (24U)

Definition at line 4499 of file stm32g431xx.h.

◆ FDCAN_RXF0S_F0FL

#define FDCAN_RXF0S_F0FL FDCAN_RXF0S_F0FL_Msk

Rx FIFO 0 Fill Level

Definition at line 4492 of file stm32g431xx.h.

◆ FDCAN_RXF0S_F0FL_Msk

#define FDCAN_RXF0S_F0FL_Msk (0xFUL << FDCAN_RXF0S_F0FL_Pos)

0x0000000F

Definition at line 4491 of file stm32g431xx.h.

◆ FDCAN_RXF0S_F0FL_Pos

#define FDCAN_RXF0S_F0FL_Pos (0U)

Definition at line 4490 of file stm32g431xx.h.

◆ FDCAN_RXF0S_F0GI

#define FDCAN_RXF0S_F0GI FDCAN_RXF0S_F0GI_Msk

Rx FIFO 0 Get Index

Definition at line 4495 of file stm32g431xx.h.

◆ FDCAN_RXF0S_F0GI_Msk

#define FDCAN_RXF0S_F0GI_Msk (0x3UL << FDCAN_RXF0S_F0GI_Pos)

0x00000300

Definition at line 4494 of file stm32g431xx.h.

◆ FDCAN_RXF0S_F0GI_Pos

#define FDCAN_RXF0S_F0GI_Pos (8U)

Definition at line 4493 of file stm32g431xx.h.

◆ FDCAN_RXF0S_F0PI

#define FDCAN_RXF0S_F0PI FDCAN_RXF0S_F0PI_Msk

Rx FIFO 0 Put Index

Definition at line 4498 of file stm32g431xx.h.

◆ FDCAN_RXF0S_F0PI_Msk

#define FDCAN_RXF0S_F0PI_Msk (0x3UL << FDCAN_RXF0S_F0PI_Pos)

0x00030000

Definition at line 4497 of file stm32g431xx.h.

◆ FDCAN_RXF0S_F0PI_Pos

#define FDCAN_RXF0S_F0PI_Pos (16U)

Definition at line 4496 of file stm32g431xx.h.

◆ FDCAN_RXF0S_RF0L

#define FDCAN_RXF0S_RF0L FDCAN_RXF0S_RF0L_Msk

Rx FIFO 0 Message Lost

Definition at line 4504 of file stm32g431xx.h.

◆ FDCAN_RXF0S_RF0L_Msk

#define FDCAN_RXF0S_RF0L_Msk (0x1UL << FDCAN_RXF0S_RF0L_Pos)

0x02000000

Definition at line 4503 of file stm32g431xx.h.

◆ FDCAN_RXF0S_RF0L_Pos

#define FDCAN_RXF0S_RF0L_Pos (25U)

Definition at line 4502 of file stm32g431xx.h.

◆ FDCAN_RXF1A_F1AI

#define FDCAN_RXF1A_F1AI FDCAN_RXF1A_F1AI_Msk

Rx FIFO 1 Acknowledge Index

Definition at line 4531 of file stm32g431xx.h.

◆ FDCAN_RXF1A_F1AI_Msk

#define FDCAN_RXF1A_F1AI_Msk (0x7UL << FDCAN_RXF1A_F1AI_Pos)

0x00000007

Definition at line 4530 of file stm32g431xx.h.

◆ FDCAN_RXF1A_F1AI_Pos

#define FDCAN_RXF1A_F1AI_Pos (0U)

Definition at line 4529 of file stm32g431xx.h.

◆ FDCAN_RXF1S_F1F

#define FDCAN_RXF1S_F1F FDCAN_RXF1S_F1F_Msk

Rx FIFO 1 Full

Definition at line 4523 of file stm32g431xx.h.

◆ FDCAN_RXF1S_F1F_Msk

#define FDCAN_RXF1S_F1F_Msk (0x1UL << FDCAN_RXF1S_F1F_Pos)

0x01000000

Definition at line 4522 of file stm32g431xx.h.

◆ FDCAN_RXF1S_F1F_Pos

#define FDCAN_RXF1S_F1F_Pos (24U)

Definition at line 4521 of file stm32g431xx.h.

◆ FDCAN_RXF1S_F1FL

#define FDCAN_RXF1S_F1FL FDCAN_RXF1S_F1FL_Msk

Rx FIFO 1 Fill Level

Definition at line 4514 of file stm32g431xx.h.

◆ FDCAN_RXF1S_F1FL_Msk

#define FDCAN_RXF1S_F1FL_Msk (0xFUL << FDCAN_RXF1S_F1FL_Pos)

0x0000000F

Definition at line 4513 of file stm32g431xx.h.

◆ FDCAN_RXF1S_F1FL_Pos

#define FDCAN_RXF1S_F1FL_Pos (0U)

Definition at line 4512 of file stm32g431xx.h.

◆ FDCAN_RXF1S_F1GI

#define FDCAN_RXF1S_F1GI FDCAN_RXF1S_F1GI_Msk

Rx FIFO 1 Get Index

Definition at line 4517 of file stm32g431xx.h.

◆ FDCAN_RXF1S_F1GI_Msk

#define FDCAN_RXF1S_F1GI_Msk (0x3UL << FDCAN_RXF1S_F1GI_Pos)

0x00000300

Definition at line 4516 of file stm32g431xx.h.

◆ FDCAN_RXF1S_F1GI_Pos

#define FDCAN_RXF1S_F1GI_Pos (8U)

Definition at line 4515 of file stm32g431xx.h.

◆ FDCAN_RXF1S_F1PI

#define FDCAN_RXF1S_F1PI FDCAN_RXF1S_F1PI_Msk

Rx FIFO 1 Put Index

Definition at line 4520 of file stm32g431xx.h.

◆ FDCAN_RXF1S_F1PI_Msk

#define FDCAN_RXF1S_F1PI_Msk (0x3UL << FDCAN_RXF1S_F1PI_Pos)

0x00030000

Definition at line 4519 of file stm32g431xx.h.

◆ FDCAN_RXF1S_F1PI_Pos

#define FDCAN_RXF1S_F1PI_Pos (16U)

Definition at line 4518 of file stm32g431xx.h.

◆ FDCAN_RXF1S_RF1L

#define FDCAN_RXF1S_RF1L FDCAN_RXF1S_RF1L_Msk

Rx FIFO 1 Message Lost

Definition at line 4526 of file stm32g431xx.h.

◆ FDCAN_RXF1S_RF1L_Msk

#define FDCAN_RXF1S_RF1L_Msk (0x1UL << FDCAN_RXF1S_RF1L_Pos)

0x02000000

Definition at line 4525 of file stm32g431xx.h.

◆ FDCAN_RXF1S_RF1L_Pos

#define FDCAN_RXF1S_RF1L_Pos (25U)

Definition at line 4524 of file stm32g431xx.h.

◆ FDCAN_RXGFC_ANFE

#define FDCAN_RXGFC_ANFE FDCAN_RXGFC_ANFE_Msk

Accept Non-matching Frames Extended

Definition at line 4453 of file stm32g431xx.h.

◆ FDCAN_RXGFC_ANFE_Msk

#define FDCAN_RXGFC_ANFE_Msk (0x3UL << FDCAN_RXGFC_ANFE_Pos)

0x0000000C

Definition at line 4452 of file stm32g431xx.h.

◆ FDCAN_RXGFC_ANFE_Pos

#define FDCAN_RXGFC_ANFE_Pos (2U)

Definition at line 4451 of file stm32g431xx.h.

◆ FDCAN_RXGFC_ANFS

#define FDCAN_RXGFC_ANFS FDCAN_RXGFC_ANFS_Msk

Accept Non-matching Frames Standard

Definition at line 4456 of file stm32g431xx.h.

◆ FDCAN_RXGFC_ANFS_Msk

#define FDCAN_RXGFC_ANFS_Msk (0x3UL << FDCAN_RXGFC_ANFS_Pos)

0x00000030

Definition at line 4455 of file stm32g431xx.h.

◆ FDCAN_RXGFC_ANFS_Pos

#define FDCAN_RXGFC_ANFS_Pos (4U)

Definition at line 4454 of file stm32g431xx.h.

◆ FDCAN_RXGFC_F0OM

#define FDCAN_RXGFC_F0OM FDCAN_RXGFC_F0OM_Msk

FIFO 0 operation mode

Definition at line 4462 of file stm32g431xx.h.

◆ FDCAN_RXGFC_F0OM_Msk

#define FDCAN_RXGFC_F0OM_Msk (0x1UL << FDCAN_RXGFC_F0OM_Pos)

0x00000200

Definition at line 4461 of file stm32g431xx.h.

◆ FDCAN_RXGFC_F0OM_Pos

#define FDCAN_RXGFC_F0OM_Pos (9U)

Definition at line 4460 of file stm32g431xx.h.

◆ FDCAN_RXGFC_F1OM

#define FDCAN_RXGFC_F1OM FDCAN_RXGFC_F1OM_Msk

FIFO 1 operation mode

Definition at line 4459 of file stm32g431xx.h.

◆ FDCAN_RXGFC_F1OM_Msk

#define FDCAN_RXGFC_F1OM_Msk (0x1UL << FDCAN_RXGFC_F1OM_Pos)

0x00000100

Definition at line 4458 of file stm32g431xx.h.

◆ FDCAN_RXGFC_F1OM_Pos

#define FDCAN_RXGFC_F1OM_Pos (8U)

Definition at line 4457 of file stm32g431xx.h.

◆ FDCAN_RXGFC_LSE

#define FDCAN_RXGFC_LSE FDCAN_RXGFC_LSE_Msk

List Size Extended

Definition at line 4468 of file stm32g431xx.h.

◆ FDCAN_RXGFC_LSE_Msk

#define FDCAN_RXGFC_LSE_Msk (0xFUL << FDCAN_RXGFC_LSE_Pos)

0x0F000000

Definition at line 4467 of file stm32g431xx.h.

◆ FDCAN_RXGFC_LSE_Pos

#define FDCAN_RXGFC_LSE_Pos (24U)

Definition at line 4466 of file stm32g431xx.h.

◆ FDCAN_RXGFC_LSS

#define FDCAN_RXGFC_LSS FDCAN_RXGFC_LSS_Msk

List Size Standard

Definition at line 4465 of file stm32g431xx.h.

◆ FDCAN_RXGFC_LSS_Msk

#define FDCAN_RXGFC_LSS_Msk (0x1FUL << FDCAN_RXGFC_LSS_Pos)

0x001F0000

Definition at line 4464 of file stm32g431xx.h.

◆ FDCAN_RXGFC_LSS_Pos

#define FDCAN_RXGFC_LSS_Pos (16U)

Definition at line 4463 of file stm32g431xx.h.

◆ FDCAN_RXGFC_RRFE

#define FDCAN_RXGFC_RRFE FDCAN_RXGFC_RRFE_Msk

Reject Remote Frames Extended

Definition at line 4447 of file stm32g431xx.h.

◆ FDCAN_RXGFC_RRFE_Msk

#define FDCAN_RXGFC_RRFE_Msk (0x1UL << FDCAN_RXGFC_RRFE_Pos)

0x00000001

Definition at line 4446 of file stm32g431xx.h.

◆ FDCAN_RXGFC_RRFE_Pos

#define FDCAN_RXGFC_RRFE_Pos (0U)

Definition at line 4445 of file stm32g431xx.h.

◆ FDCAN_RXGFC_RRFS

#define FDCAN_RXGFC_RRFS FDCAN_RXGFC_RRFS_Msk

Reject Remote Frames Standard

Definition at line 4450 of file stm32g431xx.h.

◆ FDCAN_RXGFC_RRFS_Msk

#define FDCAN_RXGFC_RRFS_Msk (0x1UL << FDCAN_RXGFC_RRFS_Pos)

0x00000002

Definition at line 4449 of file stm32g431xx.h.

◆ FDCAN_RXGFC_RRFS_Pos

#define FDCAN_RXGFC_RRFS_Pos (1U)

Definition at line 4448 of file stm32g431xx.h.

◆ FDCAN_TDCR_TDCF

#define FDCAN_TDCR_TDCF FDCAN_TDCR_TDCF_Msk

Transmitter Delay Compensation Filter

Definition at line 4243 of file stm32g431xx.h.

◆ FDCAN_TDCR_TDCF_Msk

#define FDCAN_TDCR_TDCF_Msk (0x7FUL << FDCAN_TDCR_TDCF_Pos)

0x0000007F

Definition at line 4242 of file stm32g431xx.h.

◆ FDCAN_TDCR_TDCF_Pos

#define FDCAN_TDCR_TDCF_Pos (0U)

Definition at line 4241 of file stm32g431xx.h.

◆ FDCAN_TDCR_TDCO

#define FDCAN_TDCR_TDCO FDCAN_TDCR_TDCO_Msk

Transmitter Delay Compensation Offset

Definition at line 4246 of file stm32g431xx.h.

◆ FDCAN_TDCR_TDCO_Msk

#define FDCAN_TDCR_TDCO_Msk (0x7FUL << FDCAN_TDCR_TDCO_Pos)

0x00007F00

Definition at line 4245 of file stm32g431xx.h.

◆ FDCAN_TDCR_TDCO_Pos

#define FDCAN_TDCR_TDCO_Pos (8U)

Definition at line 4244 of file stm32g431xx.h.

◆ FDCAN_TEST_LBCK

#define FDCAN_TEST_LBCK FDCAN_TEST_LBCK_Msk

Loop Back mode

Definition at line 4088 of file stm32g431xx.h.

◆ FDCAN_TEST_LBCK_Msk

#define FDCAN_TEST_LBCK_Msk (0x1UL << FDCAN_TEST_LBCK_Pos)

0x00000010

Definition at line 4087 of file stm32g431xx.h.

◆ FDCAN_TEST_LBCK_Pos

#define FDCAN_TEST_LBCK_Pos (4U)

Definition at line 4086 of file stm32g431xx.h.

◆ FDCAN_TEST_RX

#define FDCAN_TEST_RX FDCAN_TEST_RX_Msk

Receive Pin

Definition at line 4094 of file stm32g431xx.h.

◆ FDCAN_TEST_RX_Msk

#define FDCAN_TEST_RX_Msk (0x1UL << FDCAN_TEST_RX_Pos)

0x00000080

Definition at line 4093 of file stm32g431xx.h.

◆ FDCAN_TEST_RX_Pos

#define FDCAN_TEST_RX_Pos (7U)

Definition at line 4092 of file stm32g431xx.h.

◆ FDCAN_TEST_TX

#define FDCAN_TEST_TX FDCAN_TEST_TX_Msk

Control of Transmit Pin

Definition at line 4091 of file stm32g431xx.h.

◆ FDCAN_TEST_TX_Msk

#define FDCAN_TEST_TX_Msk (0x3UL << FDCAN_TEST_TX_Pos)

0x00000060

Definition at line 4090 of file stm32g431xx.h.

◆ FDCAN_TEST_TX_Pos

#define FDCAN_TEST_TX_Pos (5U)

Definition at line 4089 of file stm32g431xx.h.

◆ FDCAN_TOCC_ETOC

#define FDCAN_TOCC_ETOC FDCAN_TOCC_ETOC_Msk

Enable Timeout Counter

Definition at line 4178 of file stm32g431xx.h.

◆ FDCAN_TOCC_ETOC_Msk

#define FDCAN_TOCC_ETOC_Msk (0x1UL << FDCAN_TOCC_ETOC_Pos)

0x00000001

Definition at line 4177 of file stm32g431xx.h.

◆ FDCAN_TOCC_ETOC_Pos

#define FDCAN_TOCC_ETOC_Pos (0U)

Definition at line 4176 of file stm32g431xx.h.

◆ FDCAN_TOCC_TOP

#define FDCAN_TOCC_TOP FDCAN_TOCC_TOP_Msk

Timeout Period

Definition at line 4184 of file stm32g431xx.h.

◆ FDCAN_TOCC_TOP_Msk

#define FDCAN_TOCC_TOP_Msk (0xFFFFUL << FDCAN_TOCC_TOP_Pos)

0xFFFF0000

Definition at line 4183 of file stm32g431xx.h.

◆ FDCAN_TOCC_TOP_Pos

#define FDCAN_TOCC_TOP_Pos (16U)

Definition at line 4182 of file stm32g431xx.h.

◆ FDCAN_TOCC_TOS

#define FDCAN_TOCC_TOS FDCAN_TOCC_TOS_Msk

Timeout Select

Definition at line 4181 of file stm32g431xx.h.

◆ FDCAN_TOCC_TOS_Msk

#define FDCAN_TOCC_TOS_Msk (0x3UL << FDCAN_TOCC_TOS_Pos)

0x00000006

Definition at line 4180 of file stm32g431xx.h.

◆ FDCAN_TOCC_TOS_Pos

#define FDCAN_TOCC_TOS_Pos (1U)

Definition at line 4179 of file stm32g431xx.h.

◆ FDCAN_TOCV_TOC

#define FDCAN_TOCV_TOC FDCAN_TOCV_TOC_Msk

Timeout Counter

Definition at line 4189 of file stm32g431xx.h.

◆ FDCAN_TOCV_TOC_Msk

#define FDCAN_TOCV_TOC_Msk (0xFFFFUL << FDCAN_TOCV_TOC_Pos)

0x0000FFFF

Definition at line 4188 of file stm32g431xx.h.

◆ FDCAN_TOCV_TOC_Pos

#define FDCAN_TOCV_TOC_Pos (0U)

Definition at line 4187 of file stm32g431xx.h.

◆ FDCAN_TSCC_TCP

#define FDCAN_TSCC_TCP FDCAN_TSCC_TCP_Msk

Timestamp Counter Prescaler

Definition at line 4168 of file stm32g431xx.h.

◆ FDCAN_TSCC_TCP_Msk

#define FDCAN_TSCC_TCP_Msk (0xFUL << FDCAN_TSCC_TCP_Pos)

0x000F0000

Definition at line 4167 of file stm32g431xx.h.

◆ FDCAN_TSCC_TCP_Pos

#define FDCAN_TSCC_TCP_Pos (16U)

Definition at line 4166 of file stm32g431xx.h.

◆ FDCAN_TSCC_TSS

#define FDCAN_TSCC_TSS FDCAN_TSCC_TSS_Msk

Timestamp Select

Definition at line 4165 of file stm32g431xx.h.

◆ FDCAN_TSCC_TSS_Msk

#define FDCAN_TSCC_TSS_Msk (0x3UL << FDCAN_TSCC_TSS_Pos)

0x00000003

Definition at line 4164 of file stm32g431xx.h.

◆ FDCAN_TSCC_TSS_Pos

#define FDCAN_TSCC_TSS_Pos (0U)

Definition at line 4163 of file stm32g431xx.h.

◆ FDCAN_TSCV_TSC

#define FDCAN_TSCV_TSC FDCAN_TSCV_TSC_Msk

Timestamp Counter

Definition at line 4173 of file stm32g431xx.h.

◆ FDCAN_TSCV_TSC_Msk

#define FDCAN_TSCV_TSC_Msk (0xFFFFUL << FDCAN_TSCV_TSC_Pos)

0x0000FFFF

Definition at line 4172 of file stm32g431xx.h.

◆ FDCAN_TSCV_TSC_Pos

#define FDCAN_TSCV_TSC_Pos (0U)

Definition at line 4171 of file stm32g431xx.h.

◆ FDCAN_TXBAR_AR

#define FDCAN_TXBAR_AR FDCAN_TXBAR_AR_Msk

Add Request

Definition at line 4560 of file stm32g431xx.h.

◆ FDCAN_TXBAR_AR_Msk

#define FDCAN_TXBAR_AR_Msk (0x7UL << FDCAN_TXBAR_AR_Pos)

0x00000007

Definition at line 4559 of file stm32g431xx.h.

◆ FDCAN_TXBAR_AR_Pos

#define FDCAN_TXBAR_AR_Pos (0U)

Definition at line 4558 of file stm32g431xx.h.

◆ FDCAN_TXBC_TFQM

#define FDCAN_TXBC_TFQM FDCAN_TXBC_TFQM_Msk

Tx FIFO/Queue Mode

Definition at line 4536 of file stm32g431xx.h.

◆ FDCAN_TXBC_TFQM_Msk

#define FDCAN_TXBC_TFQM_Msk (0x1UL << FDCAN_TXBC_TFQM_Pos)

0x01000000

Definition at line 4535 of file stm32g431xx.h.

◆ FDCAN_TXBC_TFQM_Pos

#define FDCAN_TXBC_TFQM_Pos (24U)

Definition at line 4534 of file stm32g431xx.h.

◆ FDCAN_TXBCF_CF

#define FDCAN_TXBCF_CF FDCAN_TXBCF_CF_Msk

Cancellation Finished

Definition at line 4575 of file stm32g431xx.h.

◆ FDCAN_TXBCF_CF_Msk

#define FDCAN_TXBCF_CF_Msk (0x7UL << FDCAN_TXBCF_CF_Pos)

0x00000007

Definition at line 4574 of file stm32g431xx.h.

◆ FDCAN_TXBCF_CF_Pos

#define FDCAN_TXBCF_CF_Pos (0U)

Definition at line 4573 of file stm32g431xx.h.

◆ FDCAN_TXBCIE_CFIE

#define FDCAN_TXBCIE_CFIE FDCAN_TXBCIE_CFIE_Msk

Cancellation Finished Interrupt Enable

Definition at line 4585 of file stm32g431xx.h.

◆ FDCAN_TXBCIE_CFIE_Msk

#define FDCAN_TXBCIE_CFIE_Msk (0x7UL << FDCAN_TXBCIE_CFIE_Pos)

0x00000007

Definition at line 4584 of file stm32g431xx.h.

◆ FDCAN_TXBCIE_CFIE_Pos

#define FDCAN_TXBCIE_CFIE_Pos (0U)

Definition at line 4583 of file stm32g431xx.h.

◆ FDCAN_TXBCR_CR

#define FDCAN_TXBCR_CR FDCAN_TXBCR_CR_Msk

Cancellation Request

Definition at line 4565 of file stm32g431xx.h.

◆ FDCAN_TXBCR_CR_Msk

#define FDCAN_TXBCR_CR_Msk (0x7UL << FDCAN_TXBCR_CR_Pos)

0x00000007

Definition at line 4564 of file stm32g431xx.h.

◆ FDCAN_TXBCR_CR_Pos

#define FDCAN_TXBCR_CR_Pos (0U)

Definition at line 4563 of file stm32g431xx.h.

◆ FDCAN_TXBRP_TRP

#define FDCAN_TXBRP_TRP FDCAN_TXBRP_TRP_Msk

Transmission Request Pending

Definition at line 4555 of file stm32g431xx.h.

◆ FDCAN_TXBRP_TRP_Msk

#define FDCAN_TXBRP_TRP_Msk (0x7UL << FDCAN_TXBRP_TRP_Pos)

0x00000007

Definition at line 4554 of file stm32g431xx.h.

◆ FDCAN_TXBRP_TRP_Pos

#define FDCAN_TXBRP_TRP_Pos (0U)

Definition at line 4553 of file stm32g431xx.h.

◆ FDCAN_TXBTIE_TIE

#define FDCAN_TXBTIE_TIE FDCAN_TXBTIE_TIE_Msk

Transmission Interrupt Enable

Definition at line 4580 of file stm32g431xx.h.

◆ FDCAN_TXBTIE_TIE_Msk

#define FDCAN_TXBTIE_TIE_Msk (0x7UL << FDCAN_TXBTIE_TIE_Pos)

0x00000007

Definition at line 4579 of file stm32g431xx.h.

◆ FDCAN_TXBTIE_TIE_Pos

#define FDCAN_TXBTIE_TIE_Pos (0U)

Definition at line 4578 of file stm32g431xx.h.

◆ FDCAN_TXBTO_TO

#define FDCAN_TXBTO_TO FDCAN_TXBTO_TO_Msk

Transmission Occurred

Definition at line 4570 of file stm32g431xx.h.

◆ FDCAN_TXBTO_TO_Msk

#define FDCAN_TXBTO_TO_Msk (0x7UL << FDCAN_TXBTO_TO_Pos)

0x00000007

Definition at line 4569 of file stm32g431xx.h.

◆ FDCAN_TXBTO_TO_Pos

#define FDCAN_TXBTO_TO_Pos (0U)

Definition at line 4568 of file stm32g431xx.h.

◆ FDCAN_TXEFA_EFAI

#define FDCAN_TXEFA_EFAI FDCAN_TXEFA_EFAI_Msk

Event FIFO Acknowledge Index
FDCAN config registers

Definition at line 4610 of file stm32g431xx.h.

◆ FDCAN_TXEFA_EFAI_Msk

#define FDCAN_TXEFA_EFAI_Msk (0x3UL << FDCAN_TXEFA_EFAI_Pos)

0x00000003

Definition at line 4606 of file stm32g431xx.h.

◆ FDCAN_TXEFA_EFAI_Pos

#define FDCAN_TXEFA_EFAI_Pos (0U)

Definition at line 4605 of file stm32g431xx.h.

◆ FDCAN_TXEFS_EFF

#define FDCAN_TXEFS_EFF FDCAN_TXEFS_EFF_Msk

Event FIFO Full

Definition at line 4599 of file stm32g431xx.h.

◆ FDCAN_TXEFS_EFF_Msk

#define FDCAN_TXEFS_EFF_Msk (0x1UL << FDCAN_TXEFS_EFF_Pos)

0x01000000

Definition at line 4598 of file stm32g431xx.h.

◆ FDCAN_TXEFS_EFF_Pos

#define FDCAN_TXEFS_EFF_Pos (24U)

Definition at line 4597 of file stm32g431xx.h.

◆ FDCAN_TXEFS_EFFL

#define FDCAN_TXEFS_EFFL FDCAN_TXEFS_EFFL_Msk

Event FIFO Fill Level

Definition at line 4590 of file stm32g431xx.h.

◆ FDCAN_TXEFS_EFFL_Msk

#define FDCAN_TXEFS_EFFL_Msk (0x7UL << FDCAN_TXEFS_EFFL_Pos)

0x00000007

Definition at line 4589 of file stm32g431xx.h.

◆ FDCAN_TXEFS_EFFL_Pos

#define FDCAN_TXEFS_EFFL_Pos (0U)

Definition at line 4588 of file stm32g431xx.h.

◆ FDCAN_TXEFS_EFGI

#define FDCAN_TXEFS_EFGI FDCAN_TXEFS_EFGI_Msk

Event FIFO Get Index

Definition at line 4593 of file stm32g431xx.h.

◆ FDCAN_TXEFS_EFGI_Msk

#define FDCAN_TXEFS_EFGI_Msk (0x3UL << FDCAN_TXEFS_EFGI_Pos)

0x00000300

Definition at line 4592 of file stm32g431xx.h.

◆ FDCAN_TXEFS_EFGI_Pos

#define FDCAN_TXEFS_EFGI_Pos (8U)

Definition at line 4591 of file stm32g431xx.h.

◆ FDCAN_TXEFS_EFPI

#define FDCAN_TXEFS_EFPI FDCAN_TXEFS_EFPI_Msk

Event FIFO Put Index

Definition at line 4596 of file stm32g431xx.h.

◆ FDCAN_TXEFS_EFPI_Msk

#define FDCAN_TXEFS_EFPI_Msk (0x3UL << FDCAN_TXEFS_EFPI_Pos)

0x00030000

Definition at line 4595 of file stm32g431xx.h.

◆ FDCAN_TXEFS_EFPI_Pos

#define FDCAN_TXEFS_EFPI_Pos (16U)

Definition at line 4594 of file stm32g431xx.h.

◆ FDCAN_TXEFS_TEFL

#define FDCAN_TXEFS_TEFL FDCAN_TXEFS_TEFL_Msk

Tx Event FIFO Element Lost

Definition at line 4602 of file stm32g431xx.h.

◆ FDCAN_TXEFS_TEFL_Msk

#define FDCAN_TXEFS_TEFL_Msk (0x1UL << FDCAN_TXEFS_TEFL_Pos)

0x02000000

Definition at line 4601 of file stm32g431xx.h.

◆ FDCAN_TXEFS_TEFL_Pos

#define FDCAN_TXEFS_TEFL_Pos (25U)

Definition at line 4600 of file stm32g431xx.h.

◆ FDCAN_TXFQS_TFFL

#define FDCAN_TXFQS_TFFL FDCAN_TXFQS_TFFL_Msk

Tx FIFO Free Level

Definition at line 4541 of file stm32g431xx.h.

◆ FDCAN_TXFQS_TFFL_Msk

#define FDCAN_TXFQS_TFFL_Msk (0x7UL << FDCAN_TXFQS_TFFL_Pos)

0x00000007

Definition at line 4540 of file stm32g431xx.h.

◆ FDCAN_TXFQS_TFFL_Pos

#define FDCAN_TXFQS_TFFL_Pos (0U)

Definition at line 4539 of file stm32g431xx.h.

◆ FDCAN_TXFQS_TFGI

#define FDCAN_TXFQS_TFGI FDCAN_TXFQS_TFGI_Msk

Tx FIFO Get Index

Definition at line 4544 of file stm32g431xx.h.

◆ FDCAN_TXFQS_TFGI_Msk

#define FDCAN_TXFQS_TFGI_Msk (0x3UL << FDCAN_TXFQS_TFGI_Pos)

0x00000300

Definition at line 4543 of file stm32g431xx.h.

◆ FDCAN_TXFQS_TFGI_Pos

#define FDCAN_TXFQS_TFGI_Pos (8U)

Definition at line 4542 of file stm32g431xx.h.

◆ FDCAN_TXFQS_TFQF

#define FDCAN_TXFQS_TFQF FDCAN_TXFQS_TFQF_Msk

Tx FIFO/Queue Full

Definition at line 4550 of file stm32g431xx.h.

◆ FDCAN_TXFQS_TFQF_Msk

#define FDCAN_TXFQS_TFQF_Msk (0x1UL << FDCAN_TXFQS_TFQF_Pos)

0x00200000

Definition at line 4549 of file stm32g431xx.h.

◆ FDCAN_TXFQS_TFQF_Pos

#define FDCAN_TXFQS_TFQF_Pos (21U)

Definition at line 4548 of file stm32g431xx.h.

◆ FDCAN_TXFQS_TFQPI

#define FDCAN_TXFQS_TFQPI FDCAN_TXFQS_TFQPI_Msk

Tx FIFO/Queue Put Index

Definition at line 4547 of file stm32g431xx.h.

◆ FDCAN_TXFQS_TFQPI_Msk

#define FDCAN_TXFQS_TFQPI_Msk (0x3UL << FDCAN_TXFQS_TFQPI_Pos)

0x00030000

Definition at line 4546 of file stm32g431xx.h.

◆ FDCAN_TXFQS_TFQPI_Pos

#define FDCAN_TXFQS_TFQPI_Pos (16U)

Definition at line 4545 of file stm32g431xx.h.

◆ FDCAN_XIDAM_EIDM

#define FDCAN_XIDAM_EIDM FDCAN_XIDAM_EIDM_Msk

Extended ID Mask

Definition at line 4473 of file stm32g431xx.h.

◆ FDCAN_XIDAM_EIDM_Msk

#define FDCAN_XIDAM_EIDM_Msk (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos)

0x1FFFFFFF

Definition at line 4472 of file stm32g431xx.h.

◆ FDCAN_XIDAM_EIDM_Pos

#define FDCAN_XIDAM_EIDM_Pos (0U)

Definition at line 4471 of file stm32g431xx.h.

◆ FLASH_ACR_DBG_SWEN

#define FLASH_ACR_DBG_SWEN FLASH_ACR_DBG_SWEN_Msk

Software disable for debugger

Definition at line 4664 of file stm32g431xx.h.

◆ FLASH_ACR_DBG_SWEN_Msk

#define FLASH_ACR_DBG_SWEN_Msk (0x1UL << FLASH_ACR_DBG_SWEN_Pos)

0x00040000

Definition at line 4663 of file stm32g431xx.h.

◆ FLASH_ACR_DBG_SWEN_Pos

#define FLASH_ACR_DBG_SWEN_Pos (18U)

Definition at line 4662 of file stm32g431xx.h.

◆ FLASH_ACR_DCEN

#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk

Definition at line 4649 of file stm32g431xx.h.

◆ FLASH_ACR_DCEN_Msk

#define FLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos)

0x00000400

Definition at line 4648 of file stm32g431xx.h.

◆ FLASH_ACR_DCEN_Pos

#define FLASH_ACR_DCEN_Pos (10U)

Definition at line 4647 of file stm32g431xx.h.

◆ FLASH_ACR_DCRST

#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk

Definition at line 4655 of file stm32g431xx.h.

◆ FLASH_ACR_DCRST_Msk

#define FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos)

0x00001000

Definition at line 4654 of file stm32g431xx.h.

◆ FLASH_ACR_DCRST_Pos

#define FLASH_ACR_DCRST_Pos (12U)

Definition at line 4653 of file stm32g431xx.h.

◆ FLASH_ACR_ICEN

#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk

Definition at line 4646 of file stm32g431xx.h.

◆ FLASH_ACR_ICEN_Msk

#define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos)

0x00000200

Definition at line 4645 of file stm32g431xx.h.

◆ FLASH_ACR_ICEN_Pos

#define FLASH_ACR_ICEN_Pos (9U)

Definition at line 4644 of file stm32g431xx.h.

◆ FLASH_ACR_ICRST

#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk

Definition at line 4652 of file stm32g431xx.h.

◆ FLASH_ACR_ICRST_Msk

#define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos)

0x00000800

Definition at line 4651 of file stm32g431xx.h.

◆ FLASH_ACR_ICRST_Pos

#define FLASH_ACR_ICRST_Pos (11U)

Definition at line 4650 of file stm32g431xx.h.

◆ FLASH_ACR_LATENCY

#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk

Definition at line 4624 of file stm32g431xx.h.

◆ FLASH_ACR_LATENCY_0WS

#define FLASH_ACR_LATENCY_0WS (0x00000000U)

Definition at line 4625 of file stm32g431xx.h.

◆ FLASH_ACR_LATENCY_10WS

#define FLASH_ACR_LATENCY_10WS (0x0000000AU)

Definition at line 4635 of file stm32g431xx.h.

◆ FLASH_ACR_LATENCY_11WS

#define FLASH_ACR_LATENCY_11WS (0x0000000BU)

Definition at line 4636 of file stm32g431xx.h.

◆ FLASH_ACR_LATENCY_12WS

#define FLASH_ACR_LATENCY_12WS (0x0000000CU)

Definition at line 4637 of file stm32g431xx.h.

◆ FLASH_ACR_LATENCY_13WS

#define FLASH_ACR_LATENCY_13WS (0x0000000DU)

Definition at line 4638 of file stm32g431xx.h.

◆ FLASH_ACR_LATENCY_14WS

#define FLASH_ACR_LATENCY_14WS (0x0000000EU)

Definition at line 4639 of file stm32g431xx.h.

◆ FLASH_ACR_LATENCY_15WS

#define FLASH_ACR_LATENCY_15WS (0x0000000FU)

Definition at line 4640 of file stm32g431xx.h.

◆ FLASH_ACR_LATENCY_1WS

#define FLASH_ACR_LATENCY_1WS (0x00000001U)

Definition at line 4626 of file stm32g431xx.h.

◆ FLASH_ACR_LATENCY_2WS

#define FLASH_ACR_LATENCY_2WS (0x00000002U)

Definition at line 4627 of file stm32g431xx.h.

◆ FLASH_ACR_LATENCY_3WS

#define FLASH_ACR_LATENCY_3WS (0x00000003U)

Definition at line 4628 of file stm32g431xx.h.

◆ FLASH_ACR_LATENCY_4WS

#define FLASH_ACR_LATENCY_4WS (0x00000004U)

Definition at line 4629 of file stm32g431xx.h.

◆ FLASH_ACR_LATENCY_5WS

#define FLASH_ACR_LATENCY_5WS (0x00000005U)

Definition at line 4630 of file stm32g431xx.h.

◆ FLASH_ACR_LATENCY_6WS

#define FLASH_ACR_LATENCY_6WS (0x00000006U)

Definition at line 4631 of file stm32g431xx.h.

◆ FLASH_ACR_LATENCY_7WS

#define FLASH_ACR_LATENCY_7WS (0x00000007U)

Definition at line 4632 of file stm32g431xx.h.

◆ FLASH_ACR_LATENCY_8WS

#define FLASH_ACR_LATENCY_8WS (0x00000008U)

Definition at line 4633 of file stm32g431xx.h.

◆ FLASH_ACR_LATENCY_9WS

#define FLASH_ACR_LATENCY_9WS (0x00000009U)

Definition at line 4634 of file stm32g431xx.h.

◆ FLASH_ACR_LATENCY_Msk

#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos)

0x0000000F

Definition at line 4623 of file stm32g431xx.h.

◆ FLASH_ACR_LATENCY_Pos

#define FLASH_ACR_LATENCY_Pos (0U)

Definition at line 4622 of file stm32g431xx.h.

◆ FLASH_ACR_PRFTEN

#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk

Definition at line 4643 of file stm32g431xx.h.

◆ FLASH_ACR_PRFTEN_Msk

#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos)

0x00000100

Definition at line 4642 of file stm32g431xx.h.

◆ FLASH_ACR_PRFTEN_Pos

#define FLASH_ACR_PRFTEN_Pos (8U)

Definition at line 4641 of file stm32g431xx.h.

◆ FLASH_ACR_RUN_PD

#define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk

Flash power down mode during run

Definition at line 4658 of file stm32g431xx.h.

◆ FLASH_ACR_RUN_PD_Msk

#define FLASH_ACR_RUN_PD_Msk (0x1UL << FLASH_ACR_RUN_PD_Pos)

0x00002000

Definition at line 4657 of file stm32g431xx.h.

◆ FLASH_ACR_RUN_PD_Pos

#define FLASH_ACR_RUN_PD_Pos (13U)

Definition at line 4656 of file stm32g431xx.h.

◆ FLASH_ACR_SLEEP_PD

#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk

Flash power down mode during sleep

Definition at line 4661 of file stm32g431xx.h.

◆ FLASH_ACR_SLEEP_PD_Msk

#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos)

0x00004000

Definition at line 4660 of file stm32g431xx.h.

◆ FLASH_ACR_SLEEP_PD_Pos

#define FLASH_ACR_SLEEP_PD_Pos (14U)

Definition at line 4659 of file stm32g431xx.h.

◆ FLASH_CR_EOPIE

#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk

Definition at line 4728 of file stm32g431xx.h.

◆ FLASH_CR_EOPIE_Msk

#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos)

0x01000000

Definition at line 4727 of file stm32g431xx.h.

◆ FLASH_CR_EOPIE_Pos

#define FLASH_CR_EOPIE_Pos (24U)

Definition at line 4726 of file stm32g431xx.h.

◆ FLASH_CR_ERRIE

#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk

Definition at line 4731 of file stm32g431xx.h.

◆ FLASH_CR_ERRIE_Msk

#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos)

0x02000000

Definition at line 4730 of file stm32g431xx.h.

◆ FLASH_CR_ERRIE_Pos

#define FLASH_CR_ERRIE_Pos (25U)

Definition at line 4729 of file stm32g431xx.h.

◆ FLASH_CR_FSTPG

#define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk

Definition at line 4725 of file stm32g431xx.h.

◆ FLASH_CR_FSTPG_Msk

#define FLASH_CR_FSTPG_Msk (0x1UL << FLASH_CR_FSTPG_Pos)

0x00040000

Definition at line 4724 of file stm32g431xx.h.

◆ FLASH_CR_FSTPG_Pos

#define FLASH_CR_FSTPG_Pos (18U)

Definition at line 4723 of file stm32g431xx.h.

◆ FLASH_CR_LOCK

#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk

Definition at line 4746 of file stm32g431xx.h.

◆ FLASH_CR_LOCK_Msk

#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos)

0x80000000

Definition at line 4745 of file stm32g431xx.h.

◆ FLASH_CR_LOCK_Pos

#define FLASH_CR_LOCK_Pos (31U)

Definition at line 4744 of file stm32g431xx.h.

◆ FLASH_CR_MER1

#define FLASH_CR_MER1 FLASH_CR_MER1_Msk

Definition at line 4713 of file stm32g431xx.h.

◆ FLASH_CR_MER1_Msk

#define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos)

0x00000004

Definition at line 4712 of file stm32g431xx.h.

◆ FLASH_CR_MER1_Pos

#define FLASH_CR_MER1_Pos (2U)

Definition at line 4711 of file stm32g431xx.h.

◆ FLASH_CR_OBL_LAUNCH

#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk

Definition at line 4737 of file stm32g431xx.h.

◆ FLASH_CR_OBL_LAUNCH_Msk

#define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos)

0x08000000

Definition at line 4736 of file stm32g431xx.h.

◆ FLASH_CR_OBL_LAUNCH_Pos

#define FLASH_CR_OBL_LAUNCH_Pos (27U)

Definition at line 4735 of file stm32g431xx.h.

◆ FLASH_CR_OPTLOCK

#define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk

Definition at line 4743 of file stm32g431xx.h.

◆ FLASH_CR_OPTLOCK_Msk

#define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos)

0x40000000

Definition at line 4742 of file stm32g431xx.h.

◆ FLASH_CR_OPTLOCK_Pos

#define FLASH_CR_OPTLOCK_Pos (30U)

Definition at line 4741 of file stm32g431xx.h.

◆ FLASH_CR_OPTSTRT

#define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk

Definition at line 4722 of file stm32g431xx.h.

◆ FLASH_CR_OPTSTRT_Msk

#define FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos)

0x00020000

Definition at line 4721 of file stm32g431xx.h.

◆ FLASH_CR_OPTSTRT_Pos

#define FLASH_CR_OPTSTRT_Pos (17U)

Definition at line 4720 of file stm32g431xx.h.

◆ FLASH_CR_PER

#define FLASH_CR_PER FLASH_CR_PER_Msk

Definition at line 4710 of file stm32g431xx.h.

◆ FLASH_CR_PER_Msk

#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos)

0x00000002

Definition at line 4709 of file stm32g431xx.h.

◆ FLASH_CR_PER_Pos

#define FLASH_CR_PER_Pos (1U)

Definition at line 4708 of file stm32g431xx.h.

◆ FLASH_CR_PG

#define FLASH_CR_PG FLASH_CR_PG_Msk

Definition at line 4707 of file stm32g431xx.h.

◆ FLASH_CR_PG_Msk

#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos)

0x00000001

Definition at line 4706 of file stm32g431xx.h.

◆ FLASH_CR_PG_Pos

#define FLASH_CR_PG_Pos (0U)

Definition at line 4705 of file stm32g431xx.h.

◆ FLASH_CR_PNB

#define FLASH_CR_PNB FLASH_CR_PNB_Msk

Definition at line 4716 of file stm32g431xx.h.

◆ FLASH_CR_PNB_Msk

#define FLASH_CR_PNB_Msk (0x3FUL << FLASH_CR_PNB_Pos)

0x000001F8

Definition at line 4715 of file stm32g431xx.h.

◆ FLASH_CR_PNB_Pos

#define FLASH_CR_PNB_Pos (3U)

Definition at line 4714 of file stm32g431xx.h.

◆ FLASH_CR_RDERRIE

#define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk

Definition at line 4734 of file stm32g431xx.h.

◆ FLASH_CR_RDERRIE_Msk

#define FLASH_CR_RDERRIE_Msk (0x1UL << FLASH_CR_RDERRIE_Pos)

0x04000000

Definition at line 4733 of file stm32g431xx.h.

◆ FLASH_CR_RDERRIE_Pos

#define FLASH_CR_RDERRIE_Pos (26U)

Definition at line 4732 of file stm32g431xx.h.

◆ FLASH_CR_SEC_PROT1

#define FLASH_CR_SEC_PROT1 FLASH_CR_SEC_PROT1_Msk

Definition at line 4740 of file stm32g431xx.h.

◆ FLASH_CR_SEC_PROT1_Msk

#define FLASH_CR_SEC_PROT1_Msk (0x1UL << FLASH_CR_SEC_PROT1_Pos)

0x10000000

Definition at line 4739 of file stm32g431xx.h.

◆ FLASH_CR_SEC_PROT1_Pos

#define FLASH_CR_SEC_PROT1_Pos (28U)

Definition at line 4738 of file stm32g431xx.h.

◆ FLASH_CR_STRT

#define FLASH_CR_STRT FLASH_CR_STRT_Msk

Definition at line 4719 of file stm32g431xx.h.

◆ FLASH_CR_STRT_Msk

#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos)

0x00010000

Definition at line 4718 of file stm32g431xx.h.

◆ FLASH_CR_STRT_Pos

#define FLASH_CR_STRT_Pos (16U)

Definition at line 4717 of file stm32g431xx.h.

◆ FLASH_ECCR_ADDR_ECC

#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk

Definition at line 4751 of file stm32g431xx.h.

◆ FLASH_ECCR_ADDR_ECC_Msk

#define FLASH_ECCR_ADDR_ECC_Msk (0x3FFFFUL << FLASH_ECCR_ADDR_ECC_Pos)

0x0003FFFF

Definition at line 4750 of file stm32g431xx.h.

◆ FLASH_ECCR_ADDR_ECC_Pos

#define FLASH_ECCR_ADDR_ECC_Pos (0U)

Definition at line 4749 of file stm32g431xx.h.

◆ FLASH_ECCR_ECCC

#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk

Definition at line 4760 of file stm32g431xx.h.

◆ FLASH_ECCR_ECCC_Msk

#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos)

0x40000000

Definition at line 4759 of file stm32g431xx.h.

◆ FLASH_ECCR_ECCC_Pos

#define FLASH_ECCR_ECCC_Pos (30U)

Definition at line 4758 of file stm32g431xx.h.

◆ FLASH_ECCR_ECCD

#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk

Definition at line 4763 of file stm32g431xx.h.

◆ FLASH_ECCR_ECCD_Msk

#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos)

0x80000000

Definition at line 4762 of file stm32g431xx.h.

◆ FLASH_ECCR_ECCD_Pos

#define FLASH_ECCR_ECCD_Pos (31U)

Definition at line 4761 of file stm32g431xx.h.

◆ FLASH_ECCR_ECCIE

#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk

Definition at line 4757 of file stm32g431xx.h.

◆ FLASH_ECCR_ECCIE_Msk

#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos)

0x01000000

Definition at line 4756 of file stm32g431xx.h.

◆ FLASH_ECCR_ECCIE_Pos

#define FLASH_ECCR_ECCIE_Pos (24U)

Definition at line 4755 of file stm32g431xx.h.

◆ FLASH_ECCR_SYSF_ECC

#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk

Definition at line 4754 of file stm32g431xx.h.

◆ FLASH_ECCR_SYSF_ECC_Msk

#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos)

0x00400000

Definition at line 4753 of file stm32g431xx.h.

◆ FLASH_ECCR_SYSF_ECC_Pos

#define FLASH_ECCR_SYSF_ECC_Pos (22U)

Definition at line 4752 of file stm32g431xx.h.

◆ FLASH_OPTR_BOR_LEV

#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk

Definition at line 4771 of file stm32g431xx.h.

◆ FLASH_OPTR_BOR_LEV_0

#define FLASH_OPTR_BOR_LEV_0 (0x0UL << FLASH_OPTR_BOR_LEV_Pos)

0x00000000

Definition at line 4772 of file stm32g431xx.h.

◆ FLASH_OPTR_BOR_LEV_1

#define FLASH_OPTR_BOR_LEV_1 (0x1UL << FLASH_OPTR_BOR_LEV_Pos)

0x00000100

Definition at line 4773 of file stm32g431xx.h.

◆ FLASH_OPTR_BOR_LEV_2

#define FLASH_OPTR_BOR_LEV_2 (0x2UL << FLASH_OPTR_BOR_LEV_Pos)

0x00000200

Definition at line 4774 of file stm32g431xx.h.

◆ FLASH_OPTR_BOR_LEV_3

#define FLASH_OPTR_BOR_LEV_3 (0x3UL << FLASH_OPTR_BOR_LEV_Pos)

0x00000300

Definition at line 4775 of file stm32g431xx.h.

◆ FLASH_OPTR_BOR_LEV_4

#define FLASH_OPTR_BOR_LEV_4 (0x4UL << FLASH_OPTR_BOR_LEV_Pos)

0x00000400

Definition at line 4776 of file stm32g431xx.h.

◆ FLASH_OPTR_BOR_LEV_Msk

#define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos)

0x00000700

Definition at line 4770 of file stm32g431xx.h.

◆ FLASH_OPTR_BOR_LEV_Pos

#define FLASH_OPTR_BOR_LEV_Pos (8U)

Definition at line 4769 of file stm32g431xx.h.

◆ FLASH_OPTR_CCMSRAM_RST

#define FLASH_OPTR_CCMSRAM_RST FLASH_OPTR_CCMSRAM_RST_Msk

Definition at line 4806 of file stm32g431xx.h.

◆ FLASH_OPTR_CCMSRAM_RST_Msk

#define FLASH_OPTR_CCMSRAM_RST_Msk (0x1UL << FLASH_OPTR_CCMSRAM_RST_Pos)

0x02000000

Definition at line 4805 of file stm32g431xx.h.

◆ FLASH_OPTR_CCMSRAM_RST_Pos

#define FLASH_OPTR_CCMSRAM_RST_Pos (25U)

Definition at line 4804 of file stm32g431xx.h.

◆ FLASH_OPTR_IRHEN

#define FLASH_OPTR_IRHEN FLASH_OPTR_IRHEN_Msk

Definition at line 4820 of file stm32g431xx.h.

◆ FLASH_OPTR_IRHEN_Msk

#define FLASH_OPTR_IRHEN_Msk (0x1UL << FLASH_OPTR_IRHEN_Pos)

0x40000000

Definition at line 4819 of file stm32g431xx.h.

◆ FLASH_OPTR_IRHEN_Pos

#define FLASH_OPTR_IRHEN_Pos (30U)

Definition at line 4818 of file stm32g431xx.h.

◆ FLASH_OPTR_IWDG_STDBY

#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk

Definition at line 4794 of file stm32g431xx.h.

◆ FLASH_OPTR_IWDG_STDBY_Msk

#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos)

0x00040000

Definition at line 4793 of file stm32g431xx.h.

◆ FLASH_OPTR_IWDG_STDBY_Pos

#define FLASH_OPTR_IWDG_STDBY_Pos (18U)

Definition at line 4792 of file stm32g431xx.h.

◆ FLASH_OPTR_IWDG_STOP

#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk

Definition at line 4791 of file stm32g431xx.h.

◆ FLASH_OPTR_IWDG_STOP_Msk

#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos)

0x00020000

Definition at line 4790 of file stm32g431xx.h.

◆ FLASH_OPTR_IWDG_STOP_Pos

#define FLASH_OPTR_IWDG_STOP_Pos (17U)

Definition at line 4789 of file stm32g431xx.h.

◆ FLASH_OPTR_IWDG_SW

#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk

Definition at line 4788 of file stm32g431xx.h.

◆ FLASH_OPTR_IWDG_SW_Msk

#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos)

0x00010000

Definition at line 4787 of file stm32g431xx.h.

◆ FLASH_OPTR_IWDG_SW_Pos

#define FLASH_OPTR_IWDG_SW_Pos (16U)

Definition at line 4786 of file stm32g431xx.h.

◆ FLASH_OPTR_nBOOT0

#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk

Definition at line 4812 of file stm32g431xx.h.

◆ FLASH_OPTR_nBOOT0_Msk

#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos)

0x08000000

Definition at line 4811 of file stm32g431xx.h.

◆ FLASH_OPTR_nBOOT0_Pos

#define FLASH_OPTR_nBOOT0_Pos (27U)

Definition at line 4810 of file stm32g431xx.h.

◆ FLASH_OPTR_nBOOT1

#define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk

Definition at line 4800 of file stm32g431xx.h.

◆ FLASH_OPTR_nBOOT1_Msk

#define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos)

0x00800000

Definition at line 4799 of file stm32g431xx.h.

◆ FLASH_OPTR_nBOOT1_Pos

#define FLASH_OPTR_nBOOT1_Pos (23U)

Definition at line 4798 of file stm32g431xx.h.

◆ FLASH_OPTR_NRST_MODE

#define FLASH_OPTR_NRST_MODE FLASH_OPTR_NRST_MODE_Msk

Definition at line 4815 of file stm32g431xx.h.

◆ FLASH_OPTR_NRST_MODE_0

#define FLASH_OPTR_NRST_MODE_0 (0x1UL << FLASH_OPTR_NRST_MODE_Pos)

0x10000000

Definition at line 4816 of file stm32g431xx.h.

◆ FLASH_OPTR_NRST_MODE_1

#define FLASH_OPTR_NRST_MODE_1 (0x2UL << FLASH_OPTR_NRST_MODE_Pos)

0x20000000

Definition at line 4817 of file stm32g431xx.h.

◆ FLASH_OPTR_NRST_MODE_Msk

#define FLASH_OPTR_NRST_MODE_Msk (0x3UL << FLASH_OPTR_NRST_MODE_Pos)

0x30000000

Definition at line 4814 of file stm32g431xx.h.

◆ FLASH_OPTR_NRST_MODE_Pos

#define FLASH_OPTR_NRST_MODE_Pos (28U)

Definition at line 4813 of file stm32g431xx.h.

◆ FLASH_OPTR_nRST_SHDW

#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk

Definition at line 4785 of file stm32g431xx.h.

◆ FLASH_OPTR_nRST_SHDW_Msk

#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos)

0x00004000

Definition at line 4784 of file stm32g431xx.h.

◆ FLASH_OPTR_nRST_SHDW_Pos

#define FLASH_OPTR_nRST_SHDW_Pos (14U)

Definition at line 4783 of file stm32g431xx.h.

◆ FLASH_OPTR_nRST_STDBY

#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk

Definition at line 4782 of file stm32g431xx.h.

◆ FLASH_OPTR_nRST_STDBY_Msk

#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos)

0x00002000

Definition at line 4781 of file stm32g431xx.h.

◆ FLASH_OPTR_nRST_STDBY_Pos

#define FLASH_OPTR_nRST_STDBY_Pos (13U)

Definition at line 4780 of file stm32g431xx.h.

◆ FLASH_OPTR_nRST_STOP

#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk

Definition at line 4779 of file stm32g431xx.h.

◆ FLASH_OPTR_nRST_STOP_Msk

#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos)

0x00001000

Definition at line 4778 of file stm32g431xx.h.

◆ FLASH_OPTR_nRST_STOP_Pos

#define FLASH_OPTR_nRST_STOP_Pos (12U)

Definition at line 4777 of file stm32g431xx.h.

◆ FLASH_OPTR_nSWBOOT0

#define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk

Definition at line 4809 of file stm32g431xx.h.

◆ FLASH_OPTR_nSWBOOT0_Msk

#define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos)

0x04000000

Definition at line 4808 of file stm32g431xx.h.

◆ FLASH_OPTR_nSWBOOT0_Pos

#define FLASH_OPTR_nSWBOOT0_Pos (26U)

Definition at line 4807 of file stm32g431xx.h.

◆ FLASH_OPTR_RDP

#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk

Definition at line 4768 of file stm32g431xx.h.

◆ FLASH_OPTR_RDP_Msk

#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos)

0x000000FF

Definition at line 4767 of file stm32g431xx.h.

◆ FLASH_OPTR_RDP_Pos

#define FLASH_OPTR_RDP_Pos (0U)

Definition at line 4766 of file stm32g431xx.h.

◆ FLASH_OPTR_SRAM_PE

#define FLASH_OPTR_SRAM_PE FLASH_OPTR_SRAM_PE_Msk

Definition at line 4803 of file stm32g431xx.h.

◆ FLASH_OPTR_SRAM_PE_Msk

#define FLASH_OPTR_SRAM_PE_Msk (0x1UL << FLASH_OPTR_SRAM_PE_Pos)

0x01000000

Definition at line 4802 of file stm32g431xx.h.

◆ FLASH_OPTR_SRAM_PE_Pos

#define FLASH_OPTR_SRAM_PE_Pos (24U)

Definition at line 4801 of file stm32g431xx.h.

◆ FLASH_OPTR_WWDG_SW

#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk

Definition at line 4797 of file stm32g431xx.h.

◆ FLASH_OPTR_WWDG_SW_Msk

#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos)

0x00080000

Definition at line 4796 of file stm32g431xx.h.

◆ FLASH_OPTR_WWDG_SW_Pos

#define FLASH_OPTR_WWDG_SW_Pos (19U)

Definition at line 4795 of file stm32g431xx.h.

◆ FLASH_PCROP1ER_PCROP1_END

#define FLASH_PCROP1ER_PCROP1_END FLASH_PCROP1ER_PCROP1_END_Msk

Definition at line 4830 of file stm32g431xx.h.

◆ FLASH_PCROP1ER_PCROP1_END_Msk

#define FLASH_PCROP1ER_PCROP1_END_Msk (0x3FFFUL << FLASH_PCROP1ER_PCROP1_END_Pos)

0x00003FFF

Definition at line 4829 of file stm32g431xx.h.

◆ FLASH_PCROP1ER_PCROP1_END_Pos

#define FLASH_PCROP1ER_PCROP1_END_Pos (0U)

Definition at line 4828 of file stm32g431xx.h.

◆ FLASH_PCROP1ER_PCROP_RDP

#define FLASH_PCROP1ER_PCROP_RDP FLASH_PCROP1ER_PCROP_RDP_Msk

Definition at line 4833 of file stm32g431xx.h.

◆ FLASH_PCROP1ER_PCROP_RDP_Msk

#define FLASH_PCROP1ER_PCROP_RDP_Msk (0x1UL << FLASH_PCROP1ER_PCROP_RDP_Pos)

0x80000000

Definition at line 4832 of file stm32g431xx.h.

◆ FLASH_PCROP1ER_PCROP_RDP_Pos

#define FLASH_PCROP1ER_PCROP_RDP_Pos (31U)

Definition at line 4831 of file stm32g431xx.h.

◆ FLASH_PCROP1SR_PCROP1_STRT

#define FLASH_PCROP1SR_PCROP1_STRT FLASH_PCROP1SR_PCROP1_STRT_Msk

Definition at line 4825 of file stm32g431xx.h.

◆ FLASH_PCROP1SR_PCROP1_STRT_Msk

#define FLASH_PCROP1SR_PCROP1_STRT_Msk (0x3FFFUL << FLASH_PCROP1SR_PCROP1_STRT_Pos)

0x00003FFF

Definition at line 4824 of file stm32g431xx.h.

◆ FLASH_PCROP1SR_PCROP1_STRT_Pos

#define FLASH_PCROP1SR_PCROP1_STRT_Pos (0U)

Definition at line 4823 of file stm32g431xx.h.

◆ FLASH_SEC1R_BOOT_LOCK

#define FLASH_SEC1R_BOOT_LOCK FLASH_SEC1R_BOOT_LOCK_Msk

Definition at line 4858 of file stm32g431xx.h.

◆ FLASH_SEC1R_BOOT_LOCK_Msk

#define FLASH_SEC1R_BOOT_LOCK_Msk (0x1UL << FLASH_SEC1R_BOOT_LOCK_Pos)

0x00010000

Definition at line 4857 of file stm32g431xx.h.

◆ FLASH_SEC1R_BOOT_LOCK_Pos

#define FLASH_SEC1R_BOOT_LOCK_Pos (16U)

Definition at line 4856 of file stm32g431xx.h.

◆ FLASH_SEC1R_SEC_SIZE1

#define FLASH_SEC1R_SEC_SIZE1 FLASH_SEC1R_SEC_SIZE1_Msk

Definition at line 4855 of file stm32g431xx.h.

◆ FLASH_SEC1R_SEC_SIZE1_Msk

#define FLASH_SEC1R_SEC_SIZE1_Msk (0x7FUL << FLASH_SEC1R_SEC_SIZE1_Pos)

0x0000007F

Definition at line 4854 of file stm32g431xx.h.

◆ FLASH_SEC1R_SEC_SIZE1_Pos

#define FLASH_SEC1R_SEC_SIZE1_Pos (0U)

Definition at line 4853 of file stm32g431xx.h.

◆ FLASH_SR_BSY

#define FLASH_SR_BSY FLASH_SR_BSY_Msk

Definition at line 4702 of file stm32g431xx.h.

◆ FLASH_SR_BSY_Msk

#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos)

0x00010000

Definition at line 4701 of file stm32g431xx.h.

◆ FLASH_SR_BSY_Pos

#define FLASH_SR_BSY_Pos (16U)

Definition at line 4700 of file stm32g431xx.h.

◆ FLASH_SR_EOP

#define FLASH_SR_EOP FLASH_SR_EOP_Msk

Definition at line 4669 of file stm32g431xx.h.

◆ FLASH_SR_EOP_Msk

#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos)

0x00000001

Definition at line 4668 of file stm32g431xx.h.

◆ FLASH_SR_EOP_Pos

#define FLASH_SR_EOP_Pos (0U)

Definition at line 4667 of file stm32g431xx.h.

◆ FLASH_SR_FASTERR

#define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk

Definition at line 4693 of file stm32g431xx.h.

◆ FLASH_SR_FASTERR_Msk

#define FLASH_SR_FASTERR_Msk (0x1UL << FLASH_SR_FASTERR_Pos)

0x00000200

Definition at line 4692 of file stm32g431xx.h.

◆ FLASH_SR_FASTERR_Pos

#define FLASH_SR_FASTERR_Pos (9U)

Definition at line 4691 of file stm32g431xx.h.

◆ FLASH_SR_MISERR

#define FLASH_SR_MISERR FLASH_SR_MISERR_Msk

Definition at line 4690 of file stm32g431xx.h.

◆ FLASH_SR_MISERR_Msk

#define FLASH_SR_MISERR_Msk (0x1UL << FLASH_SR_MISERR_Pos)

0x00000100

Definition at line 4689 of file stm32g431xx.h.

◆ FLASH_SR_MISERR_Pos

#define FLASH_SR_MISERR_Pos (8U)

Definition at line 4688 of file stm32g431xx.h.

◆ FLASH_SR_OPERR

#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk

Definition at line 4672 of file stm32g431xx.h.

◆ FLASH_SR_OPERR_Msk

#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos)

0x00000002

Definition at line 4671 of file stm32g431xx.h.

◆ FLASH_SR_OPERR_Pos

#define FLASH_SR_OPERR_Pos (1U)

Definition at line 4670 of file stm32g431xx.h.

◆ FLASH_SR_OPTVERR

#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk

Definition at line 4699 of file stm32g431xx.h.

◆ FLASH_SR_OPTVERR_Msk

#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos)

0x00008000

Definition at line 4698 of file stm32g431xx.h.

◆ FLASH_SR_OPTVERR_Pos

#define FLASH_SR_OPTVERR_Pos (15U)

Definition at line 4697 of file stm32g431xx.h.

◆ FLASH_SR_PGAERR

#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk

Definition at line 4681 of file stm32g431xx.h.

◆ FLASH_SR_PGAERR_Msk

#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos)

0x00000020

Definition at line 4680 of file stm32g431xx.h.

◆ FLASH_SR_PGAERR_Pos

#define FLASH_SR_PGAERR_Pos (5U)

Definition at line 4679 of file stm32g431xx.h.

◆ FLASH_SR_PGSERR

#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk

Definition at line 4687 of file stm32g431xx.h.

◆ FLASH_SR_PGSERR_Msk

#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos)

0x00000080

Definition at line 4686 of file stm32g431xx.h.

◆ FLASH_SR_PGSERR_Pos

#define FLASH_SR_PGSERR_Pos (7U)

Definition at line 4685 of file stm32g431xx.h.

◆ FLASH_SR_PROGERR

#define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk

Definition at line 4675 of file stm32g431xx.h.

◆ FLASH_SR_PROGERR_Msk

#define FLASH_SR_PROGERR_Msk (0x1UL << FLASH_SR_PROGERR_Pos)

0x00000008

Definition at line 4674 of file stm32g431xx.h.

◆ FLASH_SR_PROGERR_Pos

#define FLASH_SR_PROGERR_Pos (3U)

Definition at line 4673 of file stm32g431xx.h.

◆ FLASH_SR_RDERR

#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk

Definition at line 4696 of file stm32g431xx.h.

◆ FLASH_SR_RDERR_Msk

#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos)

0x00004000

Definition at line 4695 of file stm32g431xx.h.

◆ FLASH_SR_RDERR_Pos

#define FLASH_SR_RDERR_Pos (14U)

Definition at line 4694 of file stm32g431xx.h.

◆ FLASH_SR_SIZERR

#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk

Definition at line 4684 of file stm32g431xx.h.

◆ FLASH_SR_SIZERR_Msk

#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos)

0x00000040

Definition at line 4683 of file stm32g431xx.h.

◆ FLASH_SR_SIZERR_Pos

#define FLASH_SR_SIZERR_Pos (6U)

Definition at line 4682 of file stm32g431xx.h.

◆ FLASH_SR_WRPERR

#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk

Definition at line 4678 of file stm32g431xx.h.

◆ FLASH_SR_WRPERR_Msk

#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos)

0x00000010

Definition at line 4677 of file stm32g431xx.h.

◆ FLASH_SR_WRPERR_Pos

#define FLASH_SR_WRPERR_Pos (4U)

Definition at line 4676 of file stm32g431xx.h.

◆ FLASH_WRP1AR_WRP1A_END

#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk

Definition at line 4841 of file stm32g431xx.h.

◆ FLASH_WRP1AR_WRP1A_END_Msk

#define FLASH_WRP1AR_WRP1A_END_Msk (0x3FUL << FLASH_WRP1AR_WRP1A_END_Pos)

0x003F0000

Definition at line 4840 of file stm32g431xx.h.

◆ FLASH_WRP1AR_WRP1A_END_Pos

#define FLASH_WRP1AR_WRP1A_END_Pos (16U)

Definition at line 4839 of file stm32g431xx.h.

◆ FLASH_WRP1AR_WRP1A_STRT

#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk

Definition at line 4838 of file stm32g431xx.h.

◆ FLASH_WRP1AR_WRP1A_STRT_Msk

#define FLASH_WRP1AR_WRP1A_STRT_Msk (0x3FUL << FLASH_WRP1AR_WRP1A_STRT_Pos)

0x0000003F

Definition at line 4837 of file stm32g431xx.h.

◆ FLASH_WRP1AR_WRP1A_STRT_Pos

#define FLASH_WRP1AR_WRP1A_STRT_Pos (0U)

Definition at line 4836 of file stm32g431xx.h.

◆ FLASH_WRP1BR_WRP1B_END

#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk

Definition at line 4849 of file stm32g431xx.h.

◆ FLASH_WRP1BR_WRP1B_END_Msk

#define FLASH_WRP1BR_WRP1B_END_Msk (0x3FUL << FLASH_WRP1BR_WRP1B_END_Pos)

0x003F0000

Definition at line 4848 of file stm32g431xx.h.

◆ FLASH_WRP1BR_WRP1B_END_Pos

#define FLASH_WRP1BR_WRP1B_END_Pos (16U)

Definition at line 4847 of file stm32g431xx.h.

◆ FLASH_WRP1BR_WRP1B_STRT

#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk

Definition at line 4846 of file stm32g431xx.h.

◆ FLASH_WRP1BR_WRP1B_STRT_Msk

#define FLASH_WRP1BR_WRP1B_STRT_Msk (0x3FUL << FLASH_WRP1BR_WRP1B_STRT_Pos)

0x0000003F

Definition at line 4845 of file stm32g431xx.h.

◆ FLASH_WRP1BR_WRP1B_STRT_Pos

#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U)

Definition at line 4844 of file stm32g431xx.h.

◆ FMAC_CR_CLIPEN

#define FMAC_CR_CLIPEN FMAC_CR_CLIPEN_Msk

Enable clipping

Definition at line 4940 of file stm32g431xx.h.

◆ FMAC_CR_CLIPEN_Msk

#define FMAC_CR_CLIPEN_Msk (0x1UL << FMAC_CR_CLIPEN_Pos)

0x00008000

Definition at line 4939 of file stm32g431xx.h.

◆ FMAC_CR_CLIPEN_Pos

#define FMAC_CR_CLIPEN_Pos (15U)

Definition at line 4938 of file stm32g431xx.h.

◆ FMAC_CR_DMAREN

#define FMAC_CR_DMAREN FMAC_CR_DMAREN_Msk

Enable DMA read channel requests

Definition at line 4934 of file stm32g431xx.h.

◆ FMAC_CR_DMAREN_Msk

#define FMAC_CR_DMAREN_Msk (0x1UL << FMAC_CR_DMAREN_Pos)

0x00000100

Definition at line 4933 of file stm32g431xx.h.

◆ FMAC_CR_DMAREN_Pos

#define FMAC_CR_DMAREN_Pos (8U)

Definition at line 4932 of file stm32g431xx.h.

◆ FMAC_CR_DMAWEN

#define FMAC_CR_DMAWEN FMAC_CR_DMAWEN_Msk

Enable DMA write channel requests

Definition at line 4937 of file stm32g431xx.h.

◆ FMAC_CR_DMAWEN_Msk

#define FMAC_CR_DMAWEN_Msk (0x1UL << FMAC_CR_DMAWEN_Pos)

0x00000200

Definition at line 4936 of file stm32g431xx.h.

◆ FMAC_CR_DMAWEN_Pos

#define FMAC_CR_DMAWEN_Pos (9U)

Definition at line 4935 of file stm32g431xx.h.

◆ FMAC_CR_OVFLIEN

#define FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN_Msk

Enable overflow error interrupts

Definition at line 4925 of file stm32g431xx.h.

◆ FMAC_CR_OVFLIEN_Msk

#define FMAC_CR_OVFLIEN_Msk (0x1UL << FMAC_CR_OVFLIEN_Pos)

0x00000004

Definition at line 4924 of file stm32g431xx.h.

◆ FMAC_CR_OVFLIEN_Pos

#define FMAC_CR_OVFLIEN_Pos (2U)

Definition at line 4923 of file stm32g431xx.h.

◆ FMAC_CR_RESET

#define FMAC_CR_RESET FMAC_CR_RESET_Msk

Reset filter mathematical accelerator unit

Definition at line 4943 of file stm32g431xx.h.

◆ FMAC_CR_RESET_Msk

#define FMAC_CR_RESET_Msk (0x1UL << FMAC_CR_RESET_Pos)

0x00010000

Definition at line 4942 of file stm32g431xx.h.

◆ FMAC_CR_RESET_Pos

#define FMAC_CR_RESET_Pos (16U)

Definition at line 4941 of file stm32g431xx.h.

◆ FMAC_CR_RIEN

#define FMAC_CR_RIEN FMAC_CR_RIEN_Msk

Enable read interrupt

Definition at line 4919 of file stm32g431xx.h.

◆ FMAC_CR_RIEN_Msk

#define FMAC_CR_RIEN_Msk (0x1UL << FMAC_CR_RIEN_Pos)

0x00000001

Definition at line 4918 of file stm32g431xx.h.

◆ FMAC_CR_RIEN_Pos

#define FMAC_CR_RIEN_Pos (0U)

Definition at line 4917 of file stm32g431xx.h.

◆ FMAC_CR_SATIEN

#define FMAC_CR_SATIEN FMAC_CR_SATIEN_Msk

Enable saturation error interrupts

Definition at line 4931 of file stm32g431xx.h.

◆ FMAC_CR_SATIEN_Msk

#define FMAC_CR_SATIEN_Msk (0x1UL << FMAC_CR_SATIEN_Pos)

0x00000010

Definition at line 4930 of file stm32g431xx.h.

◆ FMAC_CR_SATIEN_Pos

#define FMAC_CR_SATIEN_Pos (4U)

Definition at line 4929 of file stm32g431xx.h.

◆ FMAC_CR_UNFLIEN

#define FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN_Msk

Enable underflow error interrupts

Definition at line 4928 of file stm32g431xx.h.

◆ FMAC_CR_UNFLIEN_Msk

#define FMAC_CR_UNFLIEN_Msk (0x1UL << FMAC_CR_UNFLIEN_Pos)

0x00000008

Definition at line 4927 of file stm32g431xx.h.

◆ FMAC_CR_UNFLIEN_Pos

#define FMAC_CR_UNFLIEN_Pos (3U)

Definition at line 4926 of file stm32g431xx.h.

◆ FMAC_CR_WIEN

#define FMAC_CR_WIEN FMAC_CR_WIEN_Msk

Enable write interrupt

Definition at line 4922 of file stm32g431xx.h.

◆ FMAC_CR_WIEN_Msk

#define FMAC_CR_WIEN_Msk (0x1UL << FMAC_CR_WIEN_Pos)

0x00000002

Definition at line 4921 of file stm32g431xx.h.

◆ FMAC_CR_WIEN_Pos

#define FMAC_CR_WIEN_Pos (1U)

Definition at line 4920 of file stm32g431xx.h.

◆ FMAC_PARAM_FUNC

#define FMAC_PARAM_FUNC FMAC_PARAM_FUNC_Msk

Function

Definition at line 4905 of file stm32g431xx.h.

◆ FMAC_PARAM_FUNC_0

#define FMAC_PARAM_FUNC_0 (0x1UL << FMAC_PARAM_FUNC_Pos)

0x01000000

Definition at line 4906 of file stm32g431xx.h.

◆ FMAC_PARAM_FUNC_1

#define FMAC_PARAM_FUNC_1 (0x2UL << FMAC_PARAM_FUNC_Pos)

0x02000000

Definition at line 4907 of file stm32g431xx.h.

◆ FMAC_PARAM_FUNC_2

#define FMAC_PARAM_FUNC_2 (0x4UL << FMAC_PARAM_FUNC_Pos)

0x04000000

Definition at line 4908 of file stm32g431xx.h.

◆ FMAC_PARAM_FUNC_3

#define FMAC_PARAM_FUNC_3 (0x8UL << FMAC_PARAM_FUNC_Pos)

0x08000000

Definition at line 4909 of file stm32g431xx.h.

◆ FMAC_PARAM_FUNC_4

#define FMAC_PARAM_FUNC_4 (0x10UL << FMAC_PARAM_FUNC_Pos)

0x10000000

Definition at line 4910 of file stm32g431xx.h.

◆ FMAC_PARAM_FUNC_5

#define FMAC_PARAM_FUNC_5 (0x20UL << FMAC_PARAM_FUNC_Pos)

0x20000000

Definition at line 4911 of file stm32g431xx.h.

◆ FMAC_PARAM_FUNC_6

#define FMAC_PARAM_FUNC_6 (0x40UL << FMAC_PARAM_FUNC_Pos)

0x40000000

Definition at line 4912 of file stm32g431xx.h.

◆ FMAC_PARAM_FUNC_Msk

#define FMAC_PARAM_FUNC_Msk (0x7FUL << FMAC_PARAM_FUNC_Pos)

0x7F000000

Definition at line 4904 of file stm32g431xx.h.

◆ FMAC_PARAM_FUNC_Pos

#define FMAC_PARAM_FUNC_Pos (24U)

Definition at line 4903 of file stm32g431xx.h.

◆ FMAC_PARAM_P

#define FMAC_PARAM_P FMAC_PARAM_P_Msk

Input parameter P

Definition at line 4896 of file stm32g431xx.h.

◆ FMAC_PARAM_P_Msk

#define FMAC_PARAM_P_Msk (0xFFUL << FMAC_PARAM_P_Pos)

0x000000FF

Definition at line 4895 of file stm32g431xx.h.

◆ FMAC_PARAM_P_Pos

#define FMAC_PARAM_P_Pos (0U)

Definition at line 4894 of file stm32g431xx.h.

◆ FMAC_PARAM_Q

#define FMAC_PARAM_Q FMAC_PARAM_Q_Msk

Input parameter Q

Definition at line 4899 of file stm32g431xx.h.

◆ FMAC_PARAM_Q_Msk

#define FMAC_PARAM_Q_Msk (0xFFUL << FMAC_PARAM_Q_Pos)

0x0000FF00

Definition at line 4898 of file stm32g431xx.h.

◆ FMAC_PARAM_Q_Pos

#define FMAC_PARAM_Q_Pos (8U)

Definition at line 4897 of file stm32g431xx.h.

◆ FMAC_PARAM_R

#define FMAC_PARAM_R FMAC_PARAM_R_Msk

Input parameter R

Definition at line 4902 of file stm32g431xx.h.

◆ FMAC_PARAM_R_Msk

#define FMAC_PARAM_R_Msk (0xFFUL << FMAC_PARAM_R_Pos)

0x00FF0000

Definition at line 4901 of file stm32g431xx.h.

◆ FMAC_PARAM_R_Pos

#define FMAC_PARAM_R_Pos (16U)

Definition at line 4900 of file stm32g431xx.h.

◆ FMAC_PARAM_START

#define FMAC_PARAM_START FMAC_PARAM_START_Msk

Enable execution

Definition at line 4915 of file stm32g431xx.h.

◆ FMAC_PARAM_START_Msk

#define FMAC_PARAM_START_Msk (0x1UL << FMAC_PARAM_START_Pos)

0x80000000

Definition at line 4914 of file stm32g431xx.h.

◆ FMAC_PARAM_START_Pos

#define FMAC_PARAM_START_Pos (31U)

Definition at line 4913 of file stm32g431xx.h.

◆ FMAC_RDATA_RDATA

#define FMAC_RDATA_RDATA FMAC_RDATA_RDATA_Msk

Read data

Definition at line 4967 of file stm32g431xx.h.

◆ FMAC_RDATA_RDATA_Msk

#define FMAC_RDATA_RDATA_Msk (0xFFFFUL << FMAC_RDATA_RDATA_Pos)

0x0000FFFF

Definition at line 4966 of file stm32g431xx.h.

◆ FMAC_RDATA_RDATA_Pos

#define FMAC_RDATA_RDATA_Pos (0U)

Definition at line 4965 of file stm32g431xx.h.

◆ FMAC_SR_OVFL

#define FMAC_SR_OVFL FMAC_SR_OVFL_Msk

Overflow error flag

Definition at line 4953 of file stm32g431xx.h.

◆ FMAC_SR_OVFL_Msk

#define FMAC_SR_OVFL_Msk (0x1UL << FMAC_SR_OVFL_Pos)

0x00000100

Definition at line 4952 of file stm32g431xx.h.

◆ FMAC_SR_OVFL_Pos

#define FMAC_SR_OVFL_Pos (8U)

Definition at line 4951 of file stm32g431xx.h.

◆ FMAC_SR_SAT

#define FMAC_SR_SAT FMAC_SR_SAT_Msk

Saturation error flag

Definition at line 4959 of file stm32g431xx.h.

◆ FMAC_SR_SAT_Msk

#define FMAC_SR_SAT_Msk (0x1UL << FMAC_SR_SAT_Pos)

0x00000400

Definition at line 4958 of file stm32g431xx.h.

◆ FMAC_SR_SAT_Pos

#define FMAC_SR_SAT_Pos (10U)

Definition at line 4957 of file stm32g431xx.h.

◆ FMAC_SR_UNFL

#define FMAC_SR_UNFL FMAC_SR_UNFL_Msk

Underflow error flag

Definition at line 4956 of file stm32g431xx.h.

◆ FMAC_SR_UNFL_Msk

#define FMAC_SR_UNFL_Msk (0x1UL << FMAC_SR_UNFL_Pos)

0x00000200

Definition at line 4955 of file stm32g431xx.h.

◆ FMAC_SR_UNFL_Pos

#define FMAC_SR_UNFL_Pos (9U)

Definition at line 4954 of file stm32g431xx.h.

◆ FMAC_SR_X1FULL

#define FMAC_SR_X1FULL FMAC_SR_X1FULL_Msk

X1 buffer full flag

Definition at line 4950 of file stm32g431xx.h.

◆ FMAC_SR_X1FULL_Msk

#define FMAC_SR_X1FULL_Msk (0x1UL << FMAC_SR_X1FULL_Pos)

0x00000002

Definition at line 4949 of file stm32g431xx.h.

◆ FMAC_SR_X1FULL_Pos

#define FMAC_SR_X1FULL_Pos (1U)

Definition at line 4948 of file stm32g431xx.h.

◆ FMAC_SR_YEMPTY

#define FMAC_SR_YEMPTY FMAC_SR_YEMPTY_Msk

Y buffer empty flag

Definition at line 4947 of file stm32g431xx.h.

◆ FMAC_SR_YEMPTY_Msk

#define FMAC_SR_YEMPTY_Msk (0x1UL << FMAC_SR_YEMPTY_Pos)

0x00000001

Definition at line 4946 of file stm32g431xx.h.

◆ FMAC_SR_YEMPTY_Pos

#define FMAC_SR_YEMPTY_Pos (0U)

Definition at line 4945 of file stm32g431xx.h.

◆ FMAC_WDATA_WDATA

#define FMAC_WDATA_WDATA FMAC_WDATA_WDATA_Msk

Write data

Definition at line 4963 of file stm32g431xx.h.

◆ FMAC_WDATA_WDATA_Msk

#define FMAC_WDATA_WDATA_Msk (0xFFFFUL << FMAC_WDATA_WDATA_Pos)

0x0000FFFF

Definition at line 4962 of file stm32g431xx.h.

◆ FMAC_WDATA_WDATA_Pos

#define FMAC_WDATA_WDATA_Pos (0U)

Definition at line 4961 of file stm32g431xx.h.

◆ FMAC_X1BUFCFG_FULL_WM

#define FMAC_X1BUFCFG_FULL_WM FMAC_X1BUFCFG_FULL_WM_Msk

Watermark for buffer full flag

Definition at line 4875 of file stm32g431xx.h.

◆ FMAC_X1BUFCFG_FULL_WM_Msk

#define FMAC_X1BUFCFG_FULL_WM_Msk (0x3UL << FMAC_X1BUFCFG_FULL_WM_Pos)

0x03000000

Definition at line 4874 of file stm32g431xx.h.

◆ FMAC_X1BUFCFG_FULL_WM_Pos

#define FMAC_X1BUFCFG_FULL_WM_Pos (24U)

Definition at line 4873 of file stm32g431xx.h.

◆ FMAC_X1BUFCFG_X1_BASE

#define FMAC_X1BUFCFG_X1_BASE FMAC_X1BUFCFG_X1_BASE_Msk

Base address of X1 buffer

Definition at line 4869 of file stm32g431xx.h.

◆ FMAC_X1BUFCFG_X1_BASE_Msk

#define FMAC_X1BUFCFG_X1_BASE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BASE_Pos)

0x000000FF

Definition at line 4868 of file stm32g431xx.h.

◆ FMAC_X1BUFCFG_X1_BASE_Pos

#define FMAC_X1BUFCFG_X1_BASE_Pos (0U)

Definition at line 4867 of file stm32g431xx.h.

◆ FMAC_X1BUFCFG_X1_BUF_SIZE

#define FMAC_X1BUFCFG_X1_BUF_SIZE FMAC_X1BUFCFG_X1_BUF_SIZE_Msk

Allocated size of X1 buffer in 16-bit words

Definition at line 4872 of file stm32g431xx.h.

◆ FMAC_X1BUFCFG_X1_BUF_SIZE_Msk

#define FMAC_X1BUFCFG_X1_BUF_SIZE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos)

0x0000FF00

Definition at line 4871 of file stm32g431xx.h.

◆ FMAC_X1BUFCFG_X1_BUF_SIZE_Pos

#define FMAC_X1BUFCFG_X1_BUF_SIZE_Pos (8U)

Definition at line 4870 of file stm32g431xx.h.

◆ FMAC_X2BUFCFG_X2_BASE

#define FMAC_X2BUFCFG_X2_BASE FMAC_X2BUFCFG_X2_BASE_Msk

Base address of X2 buffer

Definition at line 4879 of file stm32g431xx.h.

◆ FMAC_X2BUFCFG_X2_BASE_Msk

#define FMAC_X2BUFCFG_X2_BASE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BASE_Pos)

0x000000FF

Definition at line 4878 of file stm32g431xx.h.

◆ FMAC_X2BUFCFG_X2_BASE_Pos

#define FMAC_X2BUFCFG_X2_BASE_Pos (0U)

Definition at line 4877 of file stm32g431xx.h.

◆ FMAC_X2BUFCFG_X2_BUF_SIZE

#define FMAC_X2BUFCFG_X2_BUF_SIZE FMAC_X2BUFCFG_X2_BUF_SIZE_Msk

Size of X2 buffer in 16-bit words

Definition at line 4882 of file stm32g431xx.h.

◆ FMAC_X2BUFCFG_X2_BUF_SIZE_Msk

#define FMAC_X2BUFCFG_X2_BUF_SIZE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos)

0x0000FF00

Definition at line 4881 of file stm32g431xx.h.

◆ FMAC_X2BUFCFG_X2_BUF_SIZE_Pos

#define FMAC_X2BUFCFG_X2_BUF_SIZE_Pos (8U)

Definition at line 4880 of file stm32g431xx.h.

◆ FMAC_YBUFCFG_EMPTY_WM

#define FMAC_YBUFCFG_EMPTY_WM FMAC_YBUFCFG_EMPTY_WM_Msk

Watermark for buffer empty flag

Definition at line 4892 of file stm32g431xx.h.

◆ FMAC_YBUFCFG_EMPTY_WM_Msk

#define FMAC_YBUFCFG_EMPTY_WM_Msk (0x3UL << FMAC_YBUFCFG_EMPTY_WM_Pos)

0x03000000

Definition at line 4891 of file stm32g431xx.h.

◆ FMAC_YBUFCFG_EMPTY_WM_Pos

#define FMAC_YBUFCFG_EMPTY_WM_Pos (24U)

Definition at line 4890 of file stm32g431xx.h.

◆ FMAC_YBUFCFG_Y_BASE

#define FMAC_YBUFCFG_Y_BASE FMAC_YBUFCFG_Y_BASE_Msk

Base address of Y buffer

Definition at line 4886 of file stm32g431xx.h.

◆ FMAC_YBUFCFG_Y_BASE_Msk

#define FMAC_YBUFCFG_Y_BASE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BASE_Pos)

0x000000FF

Definition at line 4885 of file stm32g431xx.h.

◆ FMAC_YBUFCFG_Y_BASE_Pos

#define FMAC_YBUFCFG_Y_BASE_Pos (0U)

Definition at line 4884 of file stm32g431xx.h.

◆ FMAC_YBUFCFG_Y_BUF_SIZE

#define FMAC_YBUFCFG_Y_BUF_SIZE FMAC_YBUFCFG_Y_BUF_SIZE_Msk

Size of Y buffer in 16-bit words

Definition at line 4889 of file stm32g431xx.h.

◆ FMAC_YBUFCFG_Y_BUF_SIZE_Msk

#define FMAC_YBUFCFG_Y_BUF_SIZE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BUF_SIZE_Pos)

0x0000FF00

Definition at line 4888 of file stm32g431xx.h.

◆ FMAC_YBUFCFG_Y_BUF_SIZE_Pos

#define FMAC_YBUFCFG_Y_BUF_SIZE_Pos (8U)

Definition at line 4887 of file stm32g431xx.h.

◆ GPIO_AFRH_AFRH0

#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8

Definition at line 5923 of file stm32g431xx.h.

◆ GPIO_AFRH_AFRH1

#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9

Definition at line 5924 of file stm32g431xx.h.

◆ GPIO_AFRH_AFRH2

#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10

Definition at line 5925 of file stm32g431xx.h.

◆ GPIO_AFRH_AFRH3

#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11

Definition at line 5926 of file stm32g431xx.h.

◆ GPIO_AFRH_AFRH4

#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12

Definition at line 5927 of file stm32g431xx.h.

◆ GPIO_AFRH_AFRH5

#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13

Definition at line 5928 of file stm32g431xx.h.

◆ GPIO_AFRH_AFRH6

#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14

Definition at line 5929 of file stm32g431xx.h.

◆ GPIO_AFRH_AFRH7

#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15

Definition at line 5930 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL10

#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk

Definition at line 5881 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL10_0

#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos)

0x00000100

Definition at line 5882 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL10_1

#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos)

0x00000200

Definition at line 5883 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL10_2

#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos)

0x00000400

Definition at line 5884 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL10_3

#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos)

0x00000800

Definition at line 5885 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL10_Msk

#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos)

0x00000F00

Definition at line 5880 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL10_Pos

#define GPIO_AFRH_AFSEL10_Pos (8U)

Definition at line 5879 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL11

#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk

Definition at line 5888 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL11_0

#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos)

0x00001000

Definition at line 5889 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL11_1

#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos)

0x00002000

Definition at line 5890 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL11_2

#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos)

0x00004000

Definition at line 5891 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL11_3

#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos)

0x00008000

Definition at line 5892 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL11_Msk

#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos)

0x0000F000

Definition at line 5887 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL11_Pos

#define GPIO_AFRH_AFSEL11_Pos (12U)

Definition at line 5886 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL12

#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk

Definition at line 5895 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL12_0

#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos)

0x00010000

Definition at line 5896 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL12_1

#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos)

0x00020000

Definition at line 5897 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL12_2

#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos)

0x00040000

Definition at line 5898 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL12_3

#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos)

0x00080000

Definition at line 5899 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL12_Msk

#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos)

0x000F0000

Definition at line 5894 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL12_Pos

#define GPIO_AFRH_AFSEL12_Pos (16U)

Definition at line 5893 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL13

#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk

Definition at line 5902 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL13_0

#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos)

0x00100000

Definition at line 5903 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL13_1

#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos)

0x00200000

Definition at line 5904 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL13_2

#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos)

0x00400000

Definition at line 5905 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL13_3

#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos)

0x00800000

Definition at line 5906 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL13_Msk

#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos)

0x00F00000

Definition at line 5901 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL13_Pos

#define GPIO_AFRH_AFSEL13_Pos (20U)

Definition at line 5900 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL14

#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk

Definition at line 5909 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL14_0

#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos)

0x01000000

Definition at line 5910 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL14_1

#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos)

0x02000000

Definition at line 5911 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL14_2

#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos)

0x04000000

Definition at line 5912 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL14_3

#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos)

0x08000000

Definition at line 5913 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL14_Msk

#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos)

0x0F000000

Definition at line 5908 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL14_Pos

#define GPIO_AFRH_AFSEL14_Pos (24U)

Definition at line 5907 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL15

#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk

Definition at line 5916 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL15_0

#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos)

0x10000000

Definition at line 5917 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL15_1

#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos)

0x20000000

Definition at line 5918 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL15_2

#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos)

0x40000000

Definition at line 5919 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL15_3

#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos)

0x80000000

Definition at line 5920 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL15_Msk

#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos)

0xF0000000

Definition at line 5915 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL15_Pos

#define GPIO_AFRH_AFSEL15_Pos (28U)

Definition at line 5914 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL8

#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk

Definition at line 5867 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL8_0

#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos)

0x00000001

Definition at line 5868 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL8_1

#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos)

0x00000002

Definition at line 5869 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL8_2

#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos)

0x00000004

Definition at line 5870 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL8_3

#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos)

0x00000008

Definition at line 5871 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL8_Msk

#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos)

0x0000000F

Definition at line 5866 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL8_Pos

#define GPIO_AFRH_AFSEL8_Pos (0U)

Definition at line 5865 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL9

#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk

Definition at line 5874 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL9_0

#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos)

0x00000010

Definition at line 5875 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL9_1

#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos)

0x00000020

Definition at line 5876 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL9_2

#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos)

0x00000040

Definition at line 5877 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL9_3

#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos)

0x00000080

Definition at line 5878 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL9_Msk

#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos)

0x000000F0

Definition at line 5873 of file stm32g431xx.h.

◆ GPIO_AFRH_AFSEL9_Pos

#define GPIO_AFRH_AFSEL9_Pos (4U)

Definition at line 5872 of file stm32g431xx.h.

◆ GPIO_AFRL_AFRL0

#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0

Definition at line 5855 of file stm32g431xx.h.

◆ GPIO_AFRL_AFRL1

#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1

Definition at line 5856 of file stm32g431xx.h.

◆ GPIO_AFRL_AFRL2

#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2

Definition at line 5857 of file stm32g431xx.h.

◆ GPIO_AFRL_AFRL3

#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3

Definition at line 5858 of file stm32g431xx.h.

◆ GPIO_AFRL_AFRL4

#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4

Definition at line 5859 of file stm32g431xx.h.

◆ GPIO_AFRL_AFRL5

#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5

Definition at line 5860 of file stm32g431xx.h.

◆ GPIO_AFRL_AFRL6

#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6

Definition at line 5861 of file stm32g431xx.h.

◆ GPIO_AFRL_AFRL7

#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7

Definition at line 5862 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL0

#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk

Definition at line 5799 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL0_0

#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos)

0x00000001

Definition at line 5800 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL0_1

#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos)

0x00000002

Definition at line 5801 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL0_2

#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos)

0x00000004

Definition at line 5802 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL0_3

#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos)

0x00000008

Definition at line 5803 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL0_Msk

#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos)

0x0000000F

Definition at line 5798 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL0_Pos

#define GPIO_AFRL_AFSEL0_Pos (0U)

Definition at line 5797 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL1

#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk

Definition at line 5806 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL1_0

#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos)

0x00000010

Definition at line 5807 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL1_1

#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos)

0x00000020

Definition at line 5808 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL1_2

#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos)

0x00000040

Definition at line 5809 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL1_3

#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos)

0x00000080

Definition at line 5810 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL1_Msk

#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos)

0x000000F0

Definition at line 5805 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL1_Pos

#define GPIO_AFRL_AFSEL1_Pos (4U)

Definition at line 5804 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL2

#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk

Definition at line 5813 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL2_0

#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos)

0x00000100

Definition at line 5814 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL2_1

#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos)

0x00000200

Definition at line 5815 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL2_2

#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos)

0x00000400

Definition at line 5816 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL2_3

#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos)

0x00000800

Definition at line 5817 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL2_Msk

#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos)

0x00000F00

Definition at line 5812 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL2_Pos

#define GPIO_AFRL_AFSEL2_Pos (8U)

Definition at line 5811 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL3

#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk

Definition at line 5820 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL3_0

#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos)

0x00001000

Definition at line 5821 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL3_1

#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos)

0x00002000

Definition at line 5822 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL3_2

#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos)

0x00004000

Definition at line 5823 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL3_3

#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos)

0x00008000

Definition at line 5824 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL3_Msk

#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos)

0x0000F000

Definition at line 5819 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL3_Pos

#define GPIO_AFRL_AFSEL3_Pos (12U)

Definition at line 5818 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL4

#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk

Definition at line 5827 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL4_0

#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos)

0x00010000

Definition at line 5828 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL4_1

#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos)

0x00020000

Definition at line 5829 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL4_2

#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos)

0x00040000

Definition at line 5830 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL4_3

#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos)

0x00080000

Definition at line 5831 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL4_Msk

#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos)

0x000F0000

Definition at line 5826 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL4_Pos

#define GPIO_AFRL_AFSEL4_Pos (16U)

Definition at line 5825 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL5

#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk

Definition at line 5834 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL5_0

#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos)

0x00100000

Definition at line 5835 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL5_1

#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos)

0x00200000

Definition at line 5836 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL5_2

#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos)

0x00400000

Definition at line 5837 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL5_3

#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos)

0x00800000

Definition at line 5838 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL5_Msk

#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos)

0x00F00000

Definition at line 5833 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL5_Pos

#define GPIO_AFRL_AFSEL5_Pos (20U)

Definition at line 5832 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL6

#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk

Definition at line 5841 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL6_0

#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos)

0x01000000

Definition at line 5842 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL6_1

#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos)

0x02000000

Definition at line 5843 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL6_2

#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos)

0x04000000

Definition at line 5844 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL6_3

#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos)

0x08000000

Definition at line 5845 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL6_Msk

#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos)

0x0F000000

Definition at line 5840 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL6_Pos

#define GPIO_AFRL_AFSEL6_Pos (24U)

Definition at line 5839 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL7

#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk

Definition at line 5848 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL7_0

#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos)

0x10000000

Definition at line 5849 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL7_1

#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos)

0x20000000

Definition at line 5850 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL7_2

#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos)

0x40000000

Definition at line 5851 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL7_3

#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos)

0x80000000

Definition at line 5852 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL7_Msk

#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos)

0xF0000000

Definition at line 5847 of file stm32g431xx.h.

◆ GPIO_AFRL_AFSEL7_Pos

#define GPIO_AFRL_AFSEL7_Pos (28U)

Definition at line 5846 of file stm32g431xx.h.

◆ GPIO_BRR_BR0

#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk

Definition at line 5935 of file stm32g431xx.h.

◆ GPIO_BRR_BR0_Msk

#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos)

0x00000001

Definition at line 5934 of file stm32g431xx.h.

◆ GPIO_BRR_BR0_Pos

#define GPIO_BRR_BR0_Pos (0U)

Definition at line 5933 of file stm32g431xx.h.

◆ GPIO_BRR_BR1

#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk

Definition at line 5938 of file stm32g431xx.h.

◆ GPIO_BRR_BR10

#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk

Definition at line 5965 of file stm32g431xx.h.

◆ GPIO_BRR_BR10_Msk

#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos)

0x00000400

Definition at line 5964 of file stm32g431xx.h.

◆ GPIO_BRR_BR10_Pos

#define GPIO_BRR_BR10_Pos (10U)

Definition at line 5963 of file stm32g431xx.h.

◆ GPIO_BRR_BR11

#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk

Definition at line 5968 of file stm32g431xx.h.

◆ GPIO_BRR_BR11_Msk

#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos)

0x00000800

Definition at line 5967 of file stm32g431xx.h.

◆ GPIO_BRR_BR11_Pos

#define GPIO_BRR_BR11_Pos (11U)

Definition at line 5966 of file stm32g431xx.h.

◆ GPIO_BRR_BR12

#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk

Definition at line 5971 of file stm32g431xx.h.

◆ GPIO_BRR_BR12_Msk

#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos)

0x00001000

Definition at line 5970 of file stm32g431xx.h.

◆ GPIO_BRR_BR12_Pos

#define GPIO_BRR_BR12_Pos (12U)

Definition at line 5969 of file stm32g431xx.h.

◆ GPIO_BRR_BR13

#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk

Definition at line 5974 of file stm32g431xx.h.

◆ GPIO_BRR_BR13_Msk

#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos)

0x00002000

Definition at line 5973 of file stm32g431xx.h.

◆ GPIO_BRR_BR13_Pos

#define GPIO_BRR_BR13_Pos (13U)

Definition at line 5972 of file stm32g431xx.h.

◆ GPIO_BRR_BR14

#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk

Definition at line 5977 of file stm32g431xx.h.

◆ GPIO_BRR_BR14_Msk

#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos)

0x00004000

Definition at line 5976 of file stm32g431xx.h.

◆ GPIO_BRR_BR14_Pos

#define GPIO_BRR_BR14_Pos (14U)

Definition at line 5975 of file stm32g431xx.h.

◆ GPIO_BRR_BR15

#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk

Definition at line 5980 of file stm32g431xx.h.

◆ GPIO_BRR_BR15_Msk

#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos)

0x00008000

Definition at line 5979 of file stm32g431xx.h.

◆ GPIO_BRR_BR15_Pos

#define GPIO_BRR_BR15_Pos (15U)

Definition at line 5978 of file stm32g431xx.h.

◆ GPIO_BRR_BR1_Msk

#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos)

0x00000002

Definition at line 5937 of file stm32g431xx.h.

◆ GPIO_BRR_BR1_Pos

#define GPIO_BRR_BR1_Pos (1U)

Definition at line 5936 of file stm32g431xx.h.

◆ GPIO_BRR_BR2

#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk

Definition at line 5941 of file stm32g431xx.h.

◆ GPIO_BRR_BR2_Msk

#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos)

0x00000004

Definition at line 5940 of file stm32g431xx.h.

◆ GPIO_BRR_BR2_Pos

#define GPIO_BRR_BR2_Pos (2U)

Definition at line 5939 of file stm32g431xx.h.

◆ GPIO_BRR_BR3

#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk

Definition at line 5944 of file stm32g431xx.h.

◆ GPIO_BRR_BR3_Msk

#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos)

0x00000008

Definition at line 5943 of file stm32g431xx.h.

◆ GPIO_BRR_BR3_Pos

#define GPIO_BRR_BR3_Pos (3U)

Definition at line 5942 of file stm32g431xx.h.

◆ GPIO_BRR_BR4

#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk

Definition at line 5947 of file stm32g431xx.h.

◆ GPIO_BRR_BR4_Msk

#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos)

0x00000010

Definition at line 5946 of file stm32g431xx.h.

◆ GPIO_BRR_BR4_Pos

#define GPIO_BRR_BR4_Pos (4U)

Definition at line 5945 of file stm32g431xx.h.

◆ GPIO_BRR_BR5

#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk

Definition at line 5950 of file stm32g431xx.h.

◆ GPIO_BRR_BR5_Msk

#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos)

0x00000020

Definition at line 5949 of file stm32g431xx.h.

◆ GPIO_BRR_BR5_Pos

#define GPIO_BRR_BR5_Pos (5U)

Definition at line 5948 of file stm32g431xx.h.

◆ GPIO_BRR_BR6

#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk

Definition at line 5953 of file stm32g431xx.h.

◆ GPIO_BRR_BR6_Msk

#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos)

0x00000040

Definition at line 5952 of file stm32g431xx.h.

◆ GPIO_BRR_BR6_Pos

#define GPIO_BRR_BR6_Pos (6U)

Definition at line 5951 of file stm32g431xx.h.

◆ GPIO_BRR_BR7

#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk

Definition at line 5956 of file stm32g431xx.h.

◆ GPIO_BRR_BR7_Msk

#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos)

0x00000080

Definition at line 5955 of file stm32g431xx.h.

◆ GPIO_BRR_BR7_Pos

#define GPIO_BRR_BR7_Pos (7U)

Definition at line 5954 of file stm32g431xx.h.

◆ GPIO_BRR_BR8

#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk

Definition at line 5959 of file stm32g431xx.h.

◆ GPIO_BRR_BR8_Msk

#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos)

0x00000100

Definition at line 5958 of file stm32g431xx.h.

◆ GPIO_BRR_BR8_Pos

#define GPIO_BRR_BR8_Pos (8U)

Definition at line 5957 of file stm32g431xx.h.

◆ GPIO_BRR_BR9

#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk

Definition at line 5962 of file stm32g431xx.h.

◆ GPIO_BRR_BR9_Msk

#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos)

0x00000200

Definition at line 5961 of file stm32g431xx.h.

◆ GPIO_BRR_BR9_Pos

#define GPIO_BRR_BR9_Pos (9U)

Definition at line 5960 of file stm32g431xx.h.

◆ GPIO_BRR_BR_0

#define GPIO_BRR_BR_0 GPIO_BRR_BR0

Definition at line 5983 of file stm32g431xx.h.

◆ GPIO_BRR_BR_1

#define GPIO_BRR_BR_1 GPIO_BRR_BR1

Definition at line 5984 of file stm32g431xx.h.

◆ GPIO_BRR_BR_10

#define GPIO_BRR_BR_10 GPIO_BRR_BR10

Definition at line 5993 of file stm32g431xx.h.

◆ GPIO_BRR_BR_11

#define GPIO_BRR_BR_11 GPIO_BRR_BR11

Definition at line 5994 of file stm32g431xx.h.

◆ GPIO_BRR_BR_12

#define GPIO_BRR_BR_12 GPIO_BRR_BR12

Definition at line 5995 of file stm32g431xx.h.

◆ GPIO_BRR_BR_13

#define GPIO_BRR_BR_13 GPIO_BRR_BR13

Definition at line 5996 of file stm32g431xx.h.

◆ GPIO_BRR_BR_14

#define GPIO_BRR_BR_14 GPIO_BRR_BR14

Definition at line 5997 of file stm32g431xx.h.

◆ GPIO_BRR_BR_15

#define GPIO_BRR_BR_15 GPIO_BRR_BR15

Definition at line 5998 of file stm32g431xx.h.

◆ GPIO_BRR_BR_2

#define GPIO_BRR_BR_2 GPIO_BRR_BR2

Definition at line 5985 of file stm32g431xx.h.

◆ GPIO_BRR_BR_3

#define GPIO_BRR_BR_3 GPIO_BRR_BR3

Definition at line 5986 of file stm32g431xx.h.

◆ GPIO_BRR_BR_4

#define GPIO_BRR_BR_4 GPIO_BRR_BR4

Definition at line 5987 of file stm32g431xx.h.

◆ GPIO_BRR_BR_5

#define GPIO_BRR_BR_5 GPIO_BRR_BR5

Definition at line 5988 of file stm32g431xx.h.

◆ GPIO_BRR_BR_6

#define GPIO_BRR_BR_6 GPIO_BRR_BR6

Definition at line 5989 of file stm32g431xx.h.

◆ GPIO_BRR_BR_7

#define GPIO_BRR_BR_7 GPIO_BRR_BR7

Definition at line 5990 of file stm32g431xx.h.

◆ GPIO_BRR_BR_8

#define GPIO_BRR_BR_8 GPIO_BRR_BR8

Definition at line 5991 of file stm32g431xx.h.

◆ GPIO_BRR_BR_9

#define GPIO_BRR_BR_9 GPIO_BRR_BR9

Definition at line 5992 of file stm32g431xx.h.

◆ GPIO_BSRR_BR0

#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk

Definition at line 5662 of file stm32g431xx.h.

◆ GPIO_BSRR_BR0_Msk

#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos)

0x00010000

Definition at line 5661 of file stm32g431xx.h.

◆ GPIO_BSRR_BR0_Pos

#define GPIO_BSRR_BR0_Pos (16U)

Definition at line 5660 of file stm32g431xx.h.

◆ GPIO_BSRR_BR1

#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk

Definition at line 5665 of file stm32g431xx.h.

◆ GPIO_BSRR_BR10

#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk

Definition at line 5692 of file stm32g431xx.h.

◆ GPIO_BSRR_BR10_Msk

#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos)

0x04000000

Definition at line 5691 of file stm32g431xx.h.

◆ GPIO_BSRR_BR10_Pos

#define GPIO_BSRR_BR10_Pos (26U)

Definition at line 5690 of file stm32g431xx.h.

◆ GPIO_BSRR_BR11

#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk

Definition at line 5695 of file stm32g431xx.h.

◆ GPIO_BSRR_BR11_Msk

#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos)

0x08000000

Definition at line 5694 of file stm32g431xx.h.

◆ GPIO_BSRR_BR11_Pos

#define GPIO_BSRR_BR11_Pos (27U)

Definition at line 5693 of file stm32g431xx.h.

◆ GPIO_BSRR_BR12

#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk

Definition at line 5698 of file stm32g431xx.h.

◆ GPIO_BSRR_BR12_Msk

#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos)

0x10000000

Definition at line 5697 of file stm32g431xx.h.

◆ GPIO_BSRR_BR12_Pos

#define GPIO_BSRR_BR12_Pos (28U)

Definition at line 5696 of file stm32g431xx.h.

◆ GPIO_BSRR_BR13

#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk

Definition at line 5701 of file stm32g431xx.h.

◆ GPIO_BSRR_BR13_Msk

#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos)

0x20000000

Definition at line 5700 of file stm32g431xx.h.

◆ GPIO_BSRR_BR13_Pos

#define GPIO_BSRR_BR13_Pos (29U)

Definition at line 5699 of file stm32g431xx.h.

◆ GPIO_BSRR_BR14

#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk

Definition at line 5704 of file stm32g431xx.h.

◆ GPIO_BSRR_BR14_Msk

#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos)

0x40000000

Definition at line 5703 of file stm32g431xx.h.

◆ GPIO_BSRR_BR14_Pos

#define GPIO_BSRR_BR14_Pos (30U)

Definition at line 5702 of file stm32g431xx.h.

◆ GPIO_BSRR_BR15

#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk

Definition at line 5707 of file stm32g431xx.h.

◆ GPIO_BSRR_BR15_Msk

#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos)

0x80000000

Definition at line 5706 of file stm32g431xx.h.

◆ GPIO_BSRR_BR15_Pos

#define GPIO_BSRR_BR15_Pos (31U)

Definition at line 5705 of file stm32g431xx.h.

◆ GPIO_BSRR_BR1_Msk

#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos)

0x00020000

Definition at line 5664 of file stm32g431xx.h.

◆ GPIO_BSRR_BR1_Pos

#define GPIO_BSRR_BR1_Pos (17U)

Definition at line 5663 of file stm32g431xx.h.

◆ GPIO_BSRR_BR2

#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk

Definition at line 5668 of file stm32g431xx.h.

◆ GPIO_BSRR_BR2_Msk

#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos)

0x00040000

Definition at line 5667 of file stm32g431xx.h.

◆ GPIO_BSRR_BR2_Pos

#define GPIO_BSRR_BR2_Pos (18U)

Definition at line 5666 of file stm32g431xx.h.

◆ GPIO_BSRR_BR3

#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk

Definition at line 5671 of file stm32g431xx.h.

◆ GPIO_BSRR_BR3_Msk

#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos)

0x00080000

Definition at line 5670 of file stm32g431xx.h.

◆ GPIO_BSRR_BR3_Pos

#define GPIO_BSRR_BR3_Pos (19U)

Definition at line 5669 of file stm32g431xx.h.

◆ GPIO_BSRR_BR4

#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk

Definition at line 5674 of file stm32g431xx.h.

◆ GPIO_BSRR_BR4_Msk

#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos)

0x00100000

Definition at line 5673 of file stm32g431xx.h.

◆ GPIO_BSRR_BR4_Pos

#define GPIO_BSRR_BR4_Pos (20U)

Definition at line 5672 of file stm32g431xx.h.

◆ GPIO_BSRR_BR5

#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk

Definition at line 5677 of file stm32g431xx.h.

◆ GPIO_BSRR_BR5_Msk

#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos)

0x00200000

Definition at line 5676 of file stm32g431xx.h.

◆ GPIO_BSRR_BR5_Pos

#define GPIO_BSRR_BR5_Pos (21U)

Definition at line 5675 of file stm32g431xx.h.

◆ GPIO_BSRR_BR6

#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk

Definition at line 5680 of file stm32g431xx.h.

◆ GPIO_BSRR_BR6_Msk

#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos)

0x00400000

Definition at line 5679 of file stm32g431xx.h.

◆ GPIO_BSRR_BR6_Pos

#define GPIO_BSRR_BR6_Pos (22U)

Definition at line 5678 of file stm32g431xx.h.

◆ GPIO_BSRR_BR7

#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk

Definition at line 5683 of file stm32g431xx.h.

◆ GPIO_BSRR_BR7_Msk

#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos)

0x00800000

Definition at line 5682 of file stm32g431xx.h.

◆ GPIO_BSRR_BR7_Pos

#define GPIO_BSRR_BR7_Pos (23U)

Definition at line 5681 of file stm32g431xx.h.

◆ GPIO_BSRR_BR8

#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk

Definition at line 5686 of file stm32g431xx.h.

◆ GPIO_BSRR_BR8_Msk

#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos)

0x01000000

Definition at line 5685 of file stm32g431xx.h.

◆ GPIO_BSRR_BR8_Pos

#define GPIO_BSRR_BR8_Pos (24U)

Definition at line 5684 of file stm32g431xx.h.

◆ GPIO_BSRR_BR9

#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk

Definition at line 5689 of file stm32g431xx.h.

◆ GPIO_BSRR_BR9_Msk

#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos)

0x02000000

Definition at line 5688 of file stm32g431xx.h.

◆ GPIO_BSRR_BR9_Pos

#define GPIO_BSRR_BR9_Pos (25U)

Definition at line 5687 of file stm32g431xx.h.

◆ GPIO_BSRR_BR_0

#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0

Definition at line 5726 of file stm32g431xx.h.

◆ GPIO_BSRR_BR_1

#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1

Definition at line 5727 of file stm32g431xx.h.

◆ GPIO_BSRR_BR_10

#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10

Definition at line 5736 of file stm32g431xx.h.

◆ GPIO_BSRR_BR_11

#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11

Definition at line 5737 of file stm32g431xx.h.

◆ GPIO_BSRR_BR_12

#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12

Definition at line 5738 of file stm32g431xx.h.

◆ GPIO_BSRR_BR_13

#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13

Definition at line 5739 of file stm32g431xx.h.

◆ GPIO_BSRR_BR_14

#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14

Definition at line 5740 of file stm32g431xx.h.

◆ GPIO_BSRR_BR_15

#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15

Definition at line 5741 of file stm32g431xx.h.

◆ GPIO_BSRR_BR_2

#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2

Definition at line 5728 of file stm32g431xx.h.

◆ GPIO_BSRR_BR_3

#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3

Definition at line 5729 of file stm32g431xx.h.

◆ GPIO_BSRR_BR_4

#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4

Definition at line 5730 of file stm32g431xx.h.

◆ GPIO_BSRR_BR_5

#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5

Definition at line 5731 of file stm32g431xx.h.

◆ GPIO_BSRR_BR_6

#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6

Definition at line 5732 of file stm32g431xx.h.

◆ GPIO_BSRR_BR_7

#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7

Definition at line 5733 of file stm32g431xx.h.

◆ GPIO_BSRR_BR_8

#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8

Definition at line 5734 of file stm32g431xx.h.

◆ GPIO_BSRR_BR_9

#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9

Definition at line 5735 of file stm32g431xx.h.

◆ GPIO_BSRR_BS0

#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk

Definition at line 5614 of file stm32g431xx.h.

◆ GPIO_BSRR_BS0_Msk

#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos)

0x00000001

Definition at line 5613 of file stm32g431xx.h.

◆ GPIO_BSRR_BS0_Pos

#define GPIO_BSRR_BS0_Pos (0U)

Definition at line 5612 of file stm32g431xx.h.

◆ GPIO_BSRR_BS1

#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk

Definition at line 5617 of file stm32g431xx.h.

◆ GPIO_BSRR_BS10

#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk

Definition at line 5644 of file stm32g431xx.h.

◆ GPIO_BSRR_BS10_Msk

#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos)

0x00000400

Definition at line 5643 of file stm32g431xx.h.

◆ GPIO_BSRR_BS10_Pos

#define GPIO_BSRR_BS10_Pos (10U)

Definition at line 5642 of file stm32g431xx.h.

◆ GPIO_BSRR_BS11

#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk

Definition at line 5647 of file stm32g431xx.h.

◆ GPIO_BSRR_BS11_Msk

#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos)

0x00000800

Definition at line 5646 of file stm32g431xx.h.

◆ GPIO_BSRR_BS11_Pos

#define GPIO_BSRR_BS11_Pos (11U)

Definition at line 5645 of file stm32g431xx.h.

◆ GPIO_BSRR_BS12

#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk

Definition at line 5650 of file stm32g431xx.h.

◆ GPIO_BSRR_BS12_Msk

#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos)

0x00001000

Definition at line 5649 of file stm32g431xx.h.

◆ GPIO_BSRR_BS12_Pos

#define GPIO_BSRR_BS12_Pos (12U)

Definition at line 5648 of file stm32g431xx.h.

◆ GPIO_BSRR_BS13

#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk

Definition at line 5653 of file stm32g431xx.h.

◆ GPIO_BSRR_BS13_Msk

#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos)

0x00002000

Definition at line 5652 of file stm32g431xx.h.

◆ GPIO_BSRR_BS13_Pos

#define GPIO_BSRR_BS13_Pos (13U)

Definition at line 5651 of file stm32g431xx.h.

◆ GPIO_BSRR_BS14

#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk

Definition at line 5656 of file stm32g431xx.h.

◆ GPIO_BSRR_BS14_Msk

#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos)

0x00004000

Definition at line 5655 of file stm32g431xx.h.

◆ GPIO_BSRR_BS14_Pos

#define GPIO_BSRR_BS14_Pos (14U)

Definition at line 5654 of file stm32g431xx.h.

◆ GPIO_BSRR_BS15

#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk

Definition at line 5659 of file stm32g431xx.h.

◆ GPIO_BSRR_BS15_Msk

#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos)

0x00008000

Definition at line 5658 of file stm32g431xx.h.

◆ GPIO_BSRR_BS15_Pos

#define GPIO_BSRR_BS15_Pos (15U)

Definition at line 5657 of file stm32g431xx.h.

◆ GPIO_BSRR_BS1_Msk

#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos)

0x00000002

Definition at line 5616 of file stm32g431xx.h.

◆ GPIO_BSRR_BS1_Pos

#define GPIO_BSRR_BS1_Pos (1U)

Definition at line 5615 of file stm32g431xx.h.

◆ GPIO_BSRR_BS2

#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk

Definition at line 5620 of file stm32g431xx.h.

◆ GPIO_BSRR_BS2_Msk

#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos)

0x00000004

Definition at line 5619 of file stm32g431xx.h.

◆ GPIO_BSRR_BS2_Pos

#define GPIO_BSRR_BS2_Pos (2U)

Definition at line 5618 of file stm32g431xx.h.

◆ GPIO_BSRR_BS3

#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk

Definition at line 5623 of file stm32g431xx.h.

◆ GPIO_BSRR_BS3_Msk

#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos)

0x00000008

Definition at line 5622 of file stm32g431xx.h.

◆ GPIO_BSRR_BS3_Pos

#define GPIO_BSRR_BS3_Pos (3U)

Definition at line 5621 of file stm32g431xx.h.

◆ GPIO_BSRR_BS4

#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk

Definition at line 5626 of file stm32g431xx.h.

◆ GPIO_BSRR_BS4_Msk

#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos)

0x00000010

Definition at line 5625 of file stm32g431xx.h.

◆ GPIO_BSRR_BS4_Pos

#define GPIO_BSRR_BS4_Pos (4U)

Definition at line 5624 of file stm32g431xx.h.

◆ GPIO_BSRR_BS5

#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk

Definition at line 5629 of file stm32g431xx.h.

◆ GPIO_BSRR_BS5_Msk

#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos)

0x00000020

Definition at line 5628 of file stm32g431xx.h.

◆ GPIO_BSRR_BS5_Pos

#define GPIO_BSRR_BS5_Pos (5U)

Definition at line 5627 of file stm32g431xx.h.

◆ GPIO_BSRR_BS6

#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk

Definition at line 5632 of file stm32g431xx.h.

◆ GPIO_BSRR_BS6_Msk

#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos)

0x00000040

Definition at line 5631 of file stm32g431xx.h.

◆ GPIO_BSRR_BS6_Pos

#define GPIO_BSRR_BS6_Pos (6U)

Definition at line 5630 of file stm32g431xx.h.

◆ GPIO_BSRR_BS7

#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk

Definition at line 5635 of file stm32g431xx.h.

◆ GPIO_BSRR_BS7_Msk

#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos)

0x00000080

Definition at line 5634 of file stm32g431xx.h.

◆ GPIO_BSRR_BS7_Pos

#define GPIO_BSRR_BS7_Pos (7U)

Definition at line 5633 of file stm32g431xx.h.

◆ GPIO_BSRR_BS8

#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk

Definition at line 5638 of file stm32g431xx.h.

◆ GPIO_BSRR_BS8_Msk

#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos)

0x00000100

Definition at line 5637 of file stm32g431xx.h.

◆ GPIO_BSRR_BS8_Pos

#define GPIO_BSRR_BS8_Pos (8U)

Definition at line 5636 of file stm32g431xx.h.

◆ GPIO_BSRR_BS9

#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk

Definition at line 5641 of file stm32g431xx.h.

◆ GPIO_BSRR_BS9_Msk

#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos)

0x00000200

Definition at line 5640 of file stm32g431xx.h.

◆ GPIO_BSRR_BS9_Pos

#define GPIO_BSRR_BS9_Pos (9U)

Definition at line 5639 of file stm32g431xx.h.

◆ GPIO_BSRR_BS_0

#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0

Definition at line 5710 of file stm32g431xx.h.

◆ GPIO_BSRR_BS_1

#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1

Definition at line 5711 of file stm32g431xx.h.

◆ GPIO_BSRR_BS_10

#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10

Definition at line 5720 of file stm32g431xx.h.

◆ GPIO_BSRR_BS_11

#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11

Definition at line 5721 of file stm32g431xx.h.

◆ GPIO_BSRR_BS_12

#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12

Definition at line 5722 of file stm32g431xx.h.

◆ GPIO_BSRR_BS_13

#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13

Definition at line 5723 of file stm32g431xx.h.

◆ GPIO_BSRR_BS_14

#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14

Definition at line 5724 of file stm32g431xx.h.

◆ GPIO_BSRR_BS_15

#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15

Definition at line 5725 of file stm32g431xx.h.

◆ GPIO_BSRR_BS_2

#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2

Definition at line 5712 of file stm32g431xx.h.

◆ GPIO_BSRR_BS_3

#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3

Definition at line 5713 of file stm32g431xx.h.

◆ GPIO_BSRR_BS_4

#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4

Definition at line 5714 of file stm32g431xx.h.

◆ GPIO_BSRR_BS_5

#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5

Definition at line 5715 of file stm32g431xx.h.

◆ GPIO_BSRR_BS_6

#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6

Definition at line 5716 of file stm32g431xx.h.

◆ GPIO_BSRR_BS_7

#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7

Definition at line 5717 of file stm32g431xx.h.

◆ GPIO_BSRR_BS_8

#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8

Definition at line 5718 of file stm32g431xx.h.

◆ GPIO_BSRR_BS_9

#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9

Definition at line 5719 of file stm32g431xx.h.

◆ GPIO_IDR_ID0

#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk

Definition at line 5442 of file stm32g431xx.h.

◆ GPIO_IDR_ID0_Msk

#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos)

0x00000001

Definition at line 5441 of file stm32g431xx.h.

◆ GPIO_IDR_ID0_Pos

#define GPIO_IDR_ID0_Pos (0U)

Definition at line 5440 of file stm32g431xx.h.

◆ GPIO_IDR_ID1

#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk

Definition at line 5445 of file stm32g431xx.h.

◆ GPIO_IDR_ID10

#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk

Definition at line 5472 of file stm32g431xx.h.

◆ GPIO_IDR_ID10_Msk

#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos)

0x00000400

Definition at line 5471 of file stm32g431xx.h.

◆ GPIO_IDR_ID10_Pos

#define GPIO_IDR_ID10_Pos (10U)

Definition at line 5470 of file stm32g431xx.h.

◆ GPIO_IDR_ID11

#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk

Definition at line 5475 of file stm32g431xx.h.

◆ GPIO_IDR_ID11_Msk

#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos)

0x00000800

Definition at line 5474 of file stm32g431xx.h.

◆ GPIO_IDR_ID11_Pos

#define GPIO_IDR_ID11_Pos (11U)

Definition at line 5473 of file stm32g431xx.h.

◆ GPIO_IDR_ID12

#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk

Definition at line 5478 of file stm32g431xx.h.

◆ GPIO_IDR_ID12_Msk

#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos)

0x00001000

Definition at line 5477 of file stm32g431xx.h.

◆ GPIO_IDR_ID12_Pos

#define GPIO_IDR_ID12_Pos (12U)

Definition at line 5476 of file stm32g431xx.h.

◆ GPIO_IDR_ID13

#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk

Definition at line 5481 of file stm32g431xx.h.

◆ GPIO_IDR_ID13_Msk

#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos)

0x00002000

Definition at line 5480 of file stm32g431xx.h.

◆ GPIO_IDR_ID13_Pos

#define GPIO_IDR_ID13_Pos (13U)

Definition at line 5479 of file stm32g431xx.h.

◆ GPIO_IDR_ID14

#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk

Definition at line 5484 of file stm32g431xx.h.

◆ GPIO_IDR_ID14_Msk

#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos)

0x00004000

Definition at line 5483 of file stm32g431xx.h.

◆ GPIO_IDR_ID14_Pos

#define GPIO_IDR_ID14_Pos (14U)

Definition at line 5482 of file stm32g431xx.h.

◆ GPIO_IDR_ID15

#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk

Definition at line 5487 of file stm32g431xx.h.

◆ GPIO_IDR_ID15_Msk

#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos)

0x00008000

Definition at line 5486 of file stm32g431xx.h.

◆ GPIO_IDR_ID15_Pos

#define GPIO_IDR_ID15_Pos (15U)

Definition at line 5485 of file stm32g431xx.h.

◆ GPIO_IDR_ID1_Msk

#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos)

0x00000002

Definition at line 5444 of file stm32g431xx.h.

◆ GPIO_IDR_ID1_Pos

#define GPIO_IDR_ID1_Pos (1U)

Definition at line 5443 of file stm32g431xx.h.

◆ GPIO_IDR_ID2

#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk

Definition at line 5448 of file stm32g431xx.h.

◆ GPIO_IDR_ID2_Msk

#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos)

0x00000004

Definition at line 5447 of file stm32g431xx.h.

◆ GPIO_IDR_ID2_Pos

#define GPIO_IDR_ID2_Pos (2U)

Definition at line 5446 of file stm32g431xx.h.

◆ GPIO_IDR_ID3

#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk

Definition at line 5451 of file stm32g431xx.h.

◆ GPIO_IDR_ID3_Msk

#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos)

0x00000008

Definition at line 5450 of file stm32g431xx.h.

◆ GPIO_IDR_ID3_Pos

#define GPIO_IDR_ID3_Pos (3U)

Definition at line 5449 of file stm32g431xx.h.

◆ GPIO_IDR_ID4

#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk

Definition at line 5454 of file stm32g431xx.h.

◆ GPIO_IDR_ID4_Msk

#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos)

0x00000010

Definition at line 5453 of file stm32g431xx.h.

◆ GPIO_IDR_ID4_Pos

#define GPIO_IDR_ID4_Pos (4U)

Definition at line 5452 of file stm32g431xx.h.

◆ GPIO_IDR_ID5

#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk

Definition at line 5457 of file stm32g431xx.h.

◆ GPIO_IDR_ID5_Msk

#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos)

0x00000020

Definition at line 5456 of file stm32g431xx.h.

◆ GPIO_IDR_ID5_Pos

#define GPIO_IDR_ID5_Pos (5U)

Definition at line 5455 of file stm32g431xx.h.

◆ GPIO_IDR_ID6

#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk

Definition at line 5460 of file stm32g431xx.h.

◆ GPIO_IDR_ID6_Msk

#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos)

0x00000040

Definition at line 5459 of file stm32g431xx.h.

◆ GPIO_IDR_ID6_Pos

#define GPIO_IDR_ID6_Pos (6U)

Definition at line 5458 of file stm32g431xx.h.

◆ GPIO_IDR_ID7

#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk

Definition at line 5463 of file stm32g431xx.h.

◆ GPIO_IDR_ID7_Msk

#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos)

0x00000080

Definition at line 5462 of file stm32g431xx.h.

◆ GPIO_IDR_ID7_Pos

#define GPIO_IDR_ID7_Pos (7U)

Definition at line 5461 of file stm32g431xx.h.

◆ GPIO_IDR_ID8

#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk

Definition at line 5466 of file stm32g431xx.h.

◆ GPIO_IDR_ID8_Msk

#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos)

0x00000100

Definition at line 5465 of file stm32g431xx.h.

◆ GPIO_IDR_ID8_Pos

#define GPIO_IDR_ID8_Pos (8U)

Definition at line 5464 of file stm32g431xx.h.

◆ GPIO_IDR_ID9

#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk

Definition at line 5469 of file stm32g431xx.h.

◆ GPIO_IDR_ID9_Msk

#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos)

0x00000200

Definition at line 5468 of file stm32g431xx.h.

◆ GPIO_IDR_ID9_Pos

#define GPIO_IDR_ID9_Pos (9U)

Definition at line 5467 of file stm32g431xx.h.

◆ GPIO_IDR_IDR_0

#define GPIO_IDR_IDR_0 GPIO_IDR_ID0

Definition at line 5490 of file stm32g431xx.h.

◆ GPIO_IDR_IDR_1

#define GPIO_IDR_IDR_1 GPIO_IDR_ID1

Definition at line 5491 of file stm32g431xx.h.

◆ GPIO_IDR_IDR_10

#define GPIO_IDR_IDR_10 GPIO_IDR_ID10

Definition at line 5500 of file stm32g431xx.h.

◆ GPIO_IDR_IDR_11

#define GPIO_IDR_IDR_11 GPIO_IDR_ID11

Definition at line 5501 of file stm32g431xx.h.

◆ GPIO_IDR_IDR_12

#define GPIO_IDR_IDR_12 GPIO_IDR_ID12

Definition at line 5502 of file stm32g431xx.h.

◆ GPIO_IDR_IDR_13

#define GPIO_IDR_IDR_13 GPIO_IDR_ID13

Definition at line 5503 of file stm32g431xx.h.

◆ GPIO_IDR_IDR_14

#define GPIO_IDR_IDR_14 GPIO_IDR_ID14

Definition at line 5504 of file stm32g431xx.h.

◆ GPIO_IDR_IDR_15

#define GPIO_IDR_IDR_15 GPIO_IDR_ID15

Definition at line 5505 of file stm32g431xx.h.

◆ GPIO_IDR_IDR_2

#define GPIO_IDR_IDR_2 GPIO_IDR_ID2

Definition at line 5492 of file stm32g431xx.h.

◆ GPIO_IDR_IDR_3

#define GPIO_IDR_IDR_3 GPIO_IDR_ID3

Definition at line 5493 of file stm32g431xx.h.

◆ GPIO_IDR_IDR_4

#define GPIO_IDR_IDR_4 GPIO_IDR_ID4

Definition at line 5494 of file stm32g431xx.h.

◆ GPIO_IDR_IDR_5

#define GPIO_IDR_IDR_5 GPIO_IDR_ID5

Definition at line 5495 of file stm32g431xx.h.

◆ GPIO_IDR_IDR_6

#define GPIO_IDR_IDR_6 GPIO_IDR_ID6

Definition at line 5496 of file stm32g431xx.h.

◆ GPIO_IDR_IDR_7

#define GPIO_IDR_IDR_7 GPIO_IDR_ID7

Definition at line 5497 of file stm32g431xx.h.

◆ GPIO_IDR_IDR_8

#define GPIO_IDR_IDR_8 GPIO_IDR_ID8

Definition at line 5498 of file stm32g431xx.h.

◆ GPIO_IDR_IDR_9

#define GPIO_IDR_IDR_9 GPIO_IDR_ID9

Definition at line 5499 of file stm32g431xx.h.

◆ GPIO_LCKR_LCK0

#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk

Definition at line 5746 of file stm32g431xx.h.

◆ GPIO_LCKR_LCK0_Msk

#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos)

0x00000001

Definition at line 5745 of file stm32g431xx.h.

◆ GPIO_LCKR_LCK0_Pos

#define GPIO_LCKR_LCK0_Pos (0U)

Definition at line 5744 of file stm32g431xx.h.

◆ GPIO_LCKR_LCK1

#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk

Definition at line 5749 of file stm32g431xx.h.

◆ GPIO_LCKR_LCK10

#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk

Definition at line 5776 of file stm32g431xx.h.

◆ GPIO_LCKR_LCK10_Msk

#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos)

0x00000400

Definition at line 5775 of file stm32g431xx.h.

◆ GPIO_LCKR_LCK10_Pos

#define GPIO_LCKR_LCK10_Pos (10U)

Definition at line 5774 of file stm32g431xx.h.

◆ GPIO_LCKR_LCK11

#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk

Definition at line 5779 of file stm32g431xx.h.

◆ GPIO_LCKR_LCK11_Msk

#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos)

0x00000800

Definition at line 5778 of file stm32g431xx.h.

◆ GPIO_LCKR_LCK11_Pos

#define GPIO_LCKR_LCK11_Pos (11U)

Definition at line 5777 of file stm32g431xx.h.

◆ GPIO_LCKR_LCK12

#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk

Definition at line 5782 of file stm32g431xx.h.

◆ GPIO_LCKR_LCK12_Msk

#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos)

0x00001000

Definition at line 5781 of file stm32g431xx.h.

◆ GPIO_LCKR_LCK12_Pos

#define GPIO_LCKR_LCK12_Pos (12U)

Definition at line 5780 of file stm32g431xx.h.

◆ GPIO_LCKR_LCK13

#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk

Definition at line 5785 of file stm32g431xx.h.

◆ GPIO_LCKR_LCK13_Msk

#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos)

0x00002000

Definition at line 5784 of file stm32g431xx.h.

◆ GPIO_LCKR_LCK13_Pos

#define GPIO_LCKR_LCK13_Pos (13U)

Definition at line 5783 of file stm32g431xx.h.

◆ GPIO_LCKR_LCK14

#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk

Definition at line 5788 of file stm32g431xx.h.

◆ GPIO_LCKR_LCK14_Msk

#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos)

0x00004000

Definition at line 5787 of file stm32g431xx.h.

◆ GPIO_LCKR_LCK14_Pos

#define GPIO_LCKR_LCK14_Pos (14U)

Definition at line 5786 of file stm32g431xx.h.

◆ GPIO_LCKR_LCK15

#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk

Definition at line 5791 of file stm32g431xx.h.

◆ GPIO_LCKR_LCK15_Msk

#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos)

0x00008000

Definition at line 5790 of file stm32g431xx.h.

◆ GPIO_LCKR_LCK15_Pos

#define GPIO_LCKR_LCK15_Pos (15U)

Definition at line 5789 of file stm32g431xx.h.

◆ GPIO_LCKR_LCK1_Msk

#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos)

0x00000002

Definition at line 5748 of file stm32g431xx.h.

◆ GPIO_LCKR_LCK1_Pos

#define GPIO_LCKR_LCK1_Pos (1U)

Definition at line 5747 of file stm32g431xx.h.

◆ GPIO_LCKR_LCK2

#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk

Definition at line 5752 of file stm32g431xx.h.

◆ GPIO_LCKR_LCK2_Msk

#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos)

0x00000004

Definition at line 5751 of file stm32g431xx.h.

◆ GPIO_LCKR_LCK2_Pos

#define GPIO_LCKR_LCK2_Pos (2U)

Definition at line 5750 of file stm32g431xx.h.

◆ GPIO_LCKR_LCK3

#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk

Definition at line 5755 of file stm32g431xx.h.

◆ GPIO_LCKR_LCK3_Msk

#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos)

0x00000008

Definition at line 5754 of file stm32g431xx.h.

◆ GPIO_LCKR_LCK3_Pos

#define GPIO_LCKR_LCK3_Pos (3U)

Definition at line 5753 of file stm32g431xx.h.

◆ GPIO_LCKR_LCK4

#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk

Definition at line 5758 of file stm32g431xx.h.

◆ GPIO_LCKR_LCK4_Msk

#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos)

0x00000010

Definition at line 5757 of file stm32g431xx.h.

◆ GPIO_LCKR_LCK4_Pos

#define GPIO_LCKR_LCK4_Pos (4U)

Definition at line 5756 of file stm32g431xx.h.

◆ GPIO_LCKR_LCK5

#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk

Definition at line 5761 of file stm32g431xx.h.

◆ GPIO_LCKR_LCK5_Msk

#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos)

0x00000020

Definition at line 5760 of file stm32g431xx.h.

◆ GPIO_LCKR_LCK5_Pos

#define GPIO_LCKR_LCK5_Pos (5U)

Definition at line 5759 of file stm32g431xx.h.

◆ GPIO_LCKR_LCK6

#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk

Definition at line 5764 of file stm32g431xx.h.

◆ GPIO_LCKR_LCK6_Msk

#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos)

0x00000040

Definition at line 5763 of file stm32g431xx.h.

◆ GPIO_LCKR_LCK6_Pos

#define GPIO_LCKR_LCK6_Pos (6U)

Definition at line 5762 of file stm32g431xx.h.

◆ GPIO_LCKR_LCK7

#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk

Definition at line 5767 of file stm32g431xx.h.

◆ GPIO_LCKR_LCK7_Msk

#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos)

0x00000080

Definition at line 5766 of file stm32g431xx.h.

◆ GPIO_LCKR_LCK7_Pos

#define GPIO_LCKR_LCK7_Pos (7U)

Definition at line 5765 of file stm32g431xx.h.

◆ GPIO_LCKR_LCK8

#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk

Definition at line 5770 of file stm32g431xx.h.

◆ GPIO_LCKR_LCK8_Msk

#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos)

0x00000100

Definition at line 5769 of file stm32g431xx.h.

◆ GPIO_LCKR_LCK8_Pos

#define GPIO_LCKR_LCK8_Pos (8U)

Definition at line 5768 of file stm32g431xx.h.

◆ GPIO_LCKR_LCK9

#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk

Definition at line 5773 of file stm32g431xx.h.

◆ GPIO_LCKR_LCK9_Msk

#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos)

0x00000200

Definition at line 5772 of file stm32g431xx.h.

◆ GPIO_LCKR_LCK9_Pos

#define GPIO_LCKR_LCK9_Pos (9U)

Definition at line 5771 of file stm32g431xx.h.

◆ GPIO_LCKR_LCKK

#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk

Definition at line 5794 of file stm32g431xx.h.

◆ GPIO_LCKR_LCKK_Msk

#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos)

0x00010000

Definition at line 5793 of file stm32g431xx.h.

◆ GPIO_LCKR_LCKK_Pos

#define GPIO_LCKR_LCKK_Pos (16U)

Definition at line 5792 of file stm32g431xx.h.

◆ GPIO_MODER_MODE0

#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk

Definition at line 4978 of file stm32g431xx.h.

◆ GPIO_MODER_MODE0_0

#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos)

0x00000001

Definition at line 4979 of file stm32g431xx.h.

◆ GPIO_MODER_MODE0_1

#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos)

0x00000002

Definition at line 4980 of file stm32g431xx.h.

◆ GPIO_MODER_MODE0_Msk

#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos)

0x00000003

Definition at line 4977 of file stm32g431xx.h.

◆ GPIO_MODER_MODE0_Pos

#define GPIO_MODER_MODE0_Pos (0U)

Definition at line 4976 of file stm32g431xx.h.

◆ GPIO_MODER_MODE1

#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk

Definition at line 4983 of file stm32g431xx.h.

◆ GPIO_MODER_MODE10

#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk

Definition at line 5028 of file stm32g431xx.h.

◆ GPIO_MODER_MODE10_0

#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos)

0x00100000

Definition at line 5029 of file stm32g431xx.h.

◆ GPIO_MODER_MODE10_1

#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos)

0x00200000

Definition at line 5030 of file stm32g431xx.h.

◆ GPIO_MODER_MODE10_Msk

#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos)

0x00300000

Definition at line 5027 of file stm32g431xx.h.

◆ GPIO_MODER_MODE10_Pos

#define GPIO_MODER_MODE10_Pos (20U)

Definition at line 5026 of file stm32g431xx.h.

◆ GPIO_MODER_MODE11

#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk

Definition at line 5033 of file stm32g431xx.h.

◆ GPIO_MODER_MODE11_0

#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos)

0x00400000

Definition at line 5034 of file stm32g431xx.h.

◆ GPIO_MODER_MODE11_1

#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos)

0x00800000

Definition at line 5035 of file stm32g431xx.h.

◆ GPIO_MODER_MODE11_Msk

#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos)

0x00C00000

Definition at line 5032 of file stm32g431xx.h.

◆ GPIO_MODER_MODE11_Pos

#define GPIO_MODER_MODE11_Pos (22U)

Definition at line 5031 of file stm32g431xx.h.

◆ GPIO_MODER_MODE12

#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk

Definition at line 5038 of file stm32g431xx.h.

◆ GPIO_MODER_MODE12_0

#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos)

0x01000000

Definition at line 5039 of file stm32g431xx.h.

◆ GPIO_MODER_MODE12_1

#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos)

0x02000000

Definition at line 5040 of file stm32g431xx.h.

◆ GPIO_MODER_MODE12_Msk

#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos)

0x03000000

Definition at line 5037 of file stm32g431xx.h.

◆ GPIO_MODER_MODE12_Pos

#define GPIO_MODER_MODE12_Pos (24U)

Definition at line 5036 of file stm32g431xx.h.

◆ GPIO_MODER_MODE13

#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk

Definition at line 5043 of file stm32g431xx.h.

◆ GPIO_MODER_MODE13_0

#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos)

0x04000000

Definition at line 5044 of file stm32g431xx.h.

◆ GPIO_MODER_MODE13_1

#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos)

0x08000000

Definition at line 5045 of file stm32g431xx.h.

◆ GPIO_MODER_MODE13_Msk

#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos)

0x0C000000

Definition at line 5042 of file stm32g431xx.h.

◆ GPIO_MODER_MODE13_Pos

#define GPIO_MODER_MODE13_Pos (26U)

Definition at line 5041 of file stm32g431xx.h.

◆ GPIO_MODER_MODE14

#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk

Definition at line 5048 of file stm32g431xx.h.

◆ GPIO_MODER_MODE14_0

#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos)

0x10000000

Definition at line 5049 of file stm32g431xx.h.

◆ GPIO_MODER_MODE14_1

#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos)

0x20000000

Definition at line 5050 of file stm32g431xx.h.

◆ GPIO_MODER_MODE14_Msk

#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos)

0x30000000

Definition at line 5047 of file stm32g431xx.h.

◆ GPIO_MODER_MODE14_Pos

#define GPIO_MODER_MODE14_Pos (28U)

Definition at line 5046 of file stm32g431xx.h.

◆ GPIO_MODER_MODE15

#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk

Definition at line 5053 of file stm32g431xx.h.

◆ GPIO_MODER_MODE15_0

#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos)

0x40000000

Definition at line 5054 of file stm32g431xx.h.

◆ GPIO_MODER_MODE15_1

#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos)

0x80000000

Definition at line 5055 of file stm32g431xx.h.

◆ GPIO_MODER_MODE15_Msk

#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos)

0xC0000000

Definition at line 5052 of file stm32g431xx.h.

◆ GPIO_MODER_MODE15_Pos

#define GPIO_MODER_MODE15_Pos (30U)

Definition at line 5051 of file stm32g431xx.h.

◆ GPIO_MODER_MODE1_0

#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos)

0x00000004

Definition at line 4984 of file stm32g431xx.h.

◆ GPIO_MODER_MODE1_1

#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos)

0x00000008

Definition at line 4985 of file stm32g431xx.h.

◆ GPIO_MODER_MODE1_Msk

#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos)

0x0000000C

Definition at line 4982 of file stm32g431xx.h.

◆ GPIO_MODER_MODE1_Pos

#define GPIO_MODER_MODE1_Pos (2U)

Definition at line 4981 of file stm32g431xx.h.

◆ GPIO_MODER_MODE2

#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk

Definition at line 4988 of file stm32g431xx.h.

◆ GPIO_MODER_MODE2_0

#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos)

0x00000010

Definition at line 4989 of file stm32g431xx.h.

◆ GPIO_MODER_MODE2_1

#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos)

0x00000020

Definition at line 4990 of file stm32g431xx.h.

◆ GPIO_MODER_MODE2_Msk

#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos)

0x00000030

Definition at line 4987 of file stm32g431xx.h.

◆ GPIO_MODER_MODE2_Pos

#define GPIO_MODER_MODE2_Pos (4U)

Definition at line 4986 of file stm32g431xx.h.

◆ GPIO_MODER_MODE3

#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk

Definition at line 4993 of file stm32g431xx.h.

◆ GPIO_MODER_MODE3_0

#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos)

0x00000040

Definition at line 4994 of file stm32g431xx.h.

◆ GPIO_MODER_MODE3_1

#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos)

0x00000080

Definition at line 4995 of file stm32g431xx.h.

◆ GPIO_MODER_MODE3_Msk

#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos)

0x000000C0

Definition at line 4992 of file stm32g431xx.h.

◆ GPIO_MODER_MODE3_Pos

#define GPIO_MODER_MODE3_Pos (6U)

Definition at line 4991 of file stm32g431xx.h.

◆ GPIO_MODER_MODE4

#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk

Definition at line 4998 of file stm32g431xx.h.

◆ GPIO_MODER_MODE4_0

#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos)

0x00000100

Definition at line 4999 of file stm32g431xx.h.

◆ GPIO_MODER_MODE4_1

#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos)

0x00000200

Definition at line 5000 of file stm32g431xx.h.

◆ GPIO_MODER_MODE4_Msk

#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos)

0x00000300

Definition at line 4997 of file stm32g431xx.h.

◆ GPIO_MODER_MODE4_Pos

#define GPIO_MODER_MODE4_Pos (8U)

Definition at line 4996 of file stm32g431xx.h.

◆ GPIO_MODER_MODE5

#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk

Definition at line 5003 of file stm32g431xx.h.

◆ GPIO_MODER_MODE5_0

#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos)

0x00000400

Definition at line 5004 of file stm32g431xx.h.

◆ GPIO_MODER_MODE5_1

#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos)

0x00000800

Definition at line 5005 of file stm32g431xx.h.

◆ GPIO_MODER_MODE5_Msk

#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos)

0x00000C00

Definition at line 5002 of file stm32g431xx.h.

◆ GPIO_MODER_MODE5_Pos

#define GPIO_MODER_MODE5_Pos (10U)

Definition at line 5001 of file stm32g431xx.h.

◆ GPIO_MODER_MODE6

#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk

Definition at line 5008 of file stm32g431xx.h.

◆ GPIO_MODER_MODE6_0

#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos)

0x00001000

Definition at line 5009 of file stm32g431xx.h.

◆ GPIO_MODER_MODE6_1

#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos)

0x00002000

Definition at line 5010 of file stm32g431xx.h.

◆ GPIO_MODER_MODE6_Msk

#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos)

0x00003000

Definition at line 5007 of file stm32g431xx.h.

◆ GPIO_MODER_MODE6_Pos

#define GPIO_MODER_MODE6_Pos (12U)

Definition at line 5006 of file stm32g431xx.h.

◆ GPIO_MODER_MODE7

#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk

Definition at line 5013 of file stm32g431xx.h.

◆ GPIO_MODER_MODE7_0

#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos)

0x00004000

Definition at line 5014 of file stm32g431xx.h.

◆ GPIO_MODER_MODE7_1

#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos)

0x00008000

Definition at line 5015 of file stm32g431xx.h.

◆ GPIO_MODER_MODE7_Msk

#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos)

0x0000C000

Definition at line 5012 of file stm32g431xx.h.

◆ GPIO_MODER_MODE7_Pos

#define GPIO_MODER_MODE7_Pos (14U)

Definition at line 5011 of file stm32g431xx.h.

◆ GPIO_MODER_MODE8

#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk

Definition at line 5018 of file stm32g431xx.h.

◆ GPIO_MODER_MODE8_0

#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos)

0x00010000

Definition at line 5019 of file stm32g431xx.h.

◆ GPIO_MODER_MODE8_1

#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos)

0x00020000

Definition at line 5020 of file stm32g431xx.h.

◆ GPIO_MODER_MODE8_Msk

#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos)

0x00030000

Definition at line 5017 of file stm32g431xx.h.

◆ GPIO_MODER_MODE8_Pos

#define GPIO_MODER_MODE8_Pos (16U)

Definition at line 5016 of file stm32g431xx.h.

◆ GPIO_MODER_MODE9

#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk

Definition at line 5023 of file stm32g431xx.h.

◆ GPIO_MODER_MODE9_0

#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos)

0x00040000

Definition at line 5024 of file stm32g431xx.h.

◆ GPIO_MODER_MODE9_1

#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos)

0x00080000

Definition at line 5025 of file stm32g431xx.h.

◆ GPIO_MODER_MODE9_Msk

#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos)

0x000C0000

Definition at line 5022 of file stm32g431xx.h.

◆ GPIO_MODER_MODE9_Pos

#define GPIO_MODER_MODE9_Pos (18U)

Definition at line 5021 of file stm32g431xx.h.

◆ GPIO_MODER_MODER0

#define GPIO_MODER_MODER0 GPIO_MODER_MODE0

Definition at line 5058 of file stm32g431xx.h.

◆ GPIO_MODER_MODER0_0

#define GPIO_MODER_MODER0_0 GPIO_MODER_MODE0_0

Definition at line 5059 of file stm32g431xx.h.

◆ GPIO_MODER_MODER0_1

#define GPIO_MODER_MODER0_1 GPIO_MODER_MODE0_1

Definition at line 5060 of file stm32g431xx.h.

◆ GPIO_MODER_MODER1

#define GPIO_MODER_MODER1 GPIO_MODER_MODE1

Definition at line 5061 of file stm32g431xx.h.

◆ GPIO_MODER_MODER10

#define GPIO_MODER_MODER10 GPIO_MODER_MODE10

Definition at line 5088 of file stm32g431xx.h.

◆ GPIO_MODER_MODER10_0

#define GPIO_MODER_MODER10_0 GPIO_MODER_MODE10_0

Definition at line 5089 of file stm32g431xx.h.

◆ GPIO_MODER_MODER10_1

#define GPIO_MODER_MODER10_1 GPIO_MODER_MODE10_1

Definition at line 5090 of file stm32g431xx.h.

◆ GPIO_MODER_MODER11

#define GPIO_MODER_MODER11 GPIO_MODER_MODE11

Definition at line 5091 of file stm32g431xx.h.

◆ GPIO_MODER_MODER11_0

#define GPIO_MODER_MODER11_0 GPIO_MODER_MODE11_0

Definition at line 5092 of file stm32g431xx.h.

◆ GPIO_MODER_MODER11_1

#define GPIO_MODER_MODER11_1 GPIO_MODER_MODE11_1

Definition at line 5093 of file stm32g431xx.h.

◆ GPIO_MODER_MODER12

#define GPIO_MODER_MODER12 GPIO_MODER_MODE12

Definition at line 5094 of file stm32g431xx.h.

◆ GPIO_MODER_MODER12_0

#define GPIO_MODER_MODER12_0 GPIO_MODER_MODE12_0

Definition at line 5095 of file stm32g431xx.h.

◆ GPIO_MODER_MODER12_1

#define GPIO_MODER_MODER12_1 GPIO_MODER_MODE12_1

Definition at line 5096 of file stm32g431xx.h.

◆ GPIO_MODER_MODER13

#define GPIO_MODER_MODER13 GPIO_MODER_MODE13

Definition at line 5097 of file stm32g431xx.h.

◆ GPIO_MODER_MODER13_0

#define GPIO_MODER_MODER13_0 GPIO_MODER_MODE13_0

Definition at line 5098 of file stm32g431xx.h.

◆ GPIO_MODER_MODER13_1

#define GPIO_MODER_MODER13_1 GPIO_MODER_MODE13_1

Definition at line 5099 of file stm32g431xx.h.

◆ GPIO_MODER_MODER14

#define GPIO_MODER_MODER14 GPIO_MODER_MODE14

Definition at line 5100 of file stm32g431xx.h.

◆ GPIO_MODER_MODER14_0

#define GPIO_MODER_MODER14_0 GPIO_MODER_MODE14_0

Definition at line 5101 of file stm32g431xx.h.

◆ GPIO_MODER_MODER14_1

#define GPIO_MODER_MODER14_1 GPIO_MODER_MODE14_1

Definition at line 5102 of file stm32g431xx.h.

◆ GPIO_MODER_MODER15

#define GPIO_MODER_MODER15 GPIO_MODER_MODE15

Definition at line 5103 of file stm32g431xx.h.

◆ GPIO_MODER_MODER15_0

#define GPIO_MODER_MODER15_0 GPIO_MODER_MODE15_0

Definition at line 5104 of file stm32g431xx.h.

◆ GPIO_MODER_MODER15_1

#define GPIO_MODER_MODER15_1 GPIO_MODER_MODE15_1

Definition at line 5105 of file stm32g431xx.h.

◆ GPIO_MODER_MODER1_0

#define GPIO_MODER_MODER1_0 GPIO_MODER_MODE1_0

Definition at line 5062 of file stm32g431xx.h.

◆ GPIO_MODER_MODER1_1

#define GPIO_MODER_MODER1_1 GPIO_MODER_MODE1_1

Definition at line 5063 of file stm32g431xx.h.

◆ GPIO_MODER_MODER2

#define GPIO_MODER_MODER2 GPIO_MODER_MODE2

Definition at line 5064 of file stm32g431xx.h.

◆ GPIO_MODER_MODER2_0

#define GPIO_MODER_MODER2_0 GPIO_MODER_MODE2_0

Definition at line 5065 of file stm32g431xx.h.

◆ GPIO_MODER_MODER2_1

#define GPIO_MODER_MODER2_1 GPIO_MODER_MODE2_1

Definition at line 5066 of file stm32g431xx.h.

◆ GPIO_MODER_MODER3

#define GPIO_MODER_MODER3 GPIO_MODER_MODE3

Definition at line 5067 of file stm32g431xx.h.

◆ GPIO_MODER_MODER3_0

#define GPIO_MODER_MODER3_0 GPIO_MODER_MODE3_0

Definition at line 5068 of file stm32g431xx.h.

◆ GPIO_MODER_MODER3_1

#define GPIO_MODER_MODER3_1 GPIO_MODER_MODE3_1

Definition at line 5069 of file stm32g431xx.h.

◆ GPIO_MODER_MODER4

#define GPIO_MODER_MODER4 GPIO_MODER_MODE4

Definition at line 5070 of file stm32g431xx.h.

◆ GPIO_MODER_MODER4_0

#define GPIO_MODER_MODER4_0 GPIO_MODER_MODE4_0

Definition at line 5071 of file stm32g431xx.h.

◆ GPIO_MODER_MODER4_1

#define GPIO_MODER_MODER4_1 GPIO_MODER_MODE4_1

Definition at line 5072 of file stm32g431xx.h.

◆ GPIO_MODER_MODER5

#define GPIO_MODER_MODER5 GPIO_MODER_MODE5

Definition at line 5073 of file stm32g431xx.h.

◆ GPIO_MODER_MODER5_0

#define GPIO_MODER_MODER5_0 GPIO_MODER_MODE5_0

Definition at line 5074 of file stm32g431xx.h.

◆ GPIO_MODER_MODER5_1

#define GPIO_MODER_MODER5_1 GPIO_MODER_MODE5_1

Definition at line 5075 of file stm32g431xx.h.

◆ GPIO_MODER_MODER6

#define GPIO_MODER_MODER6 GPIO_MODER_MODE6

Definition at line 5076 of file stm32g431xx.h.

◆ GPIO_MODER_MODER6_0

#define GPIO_MODER_MODER6_0 GPIO_MODER_MODE6_0

Definition at line 5077 of file stm32g431xx.h.

◆ GPIO_MODER_MODER6_1

#define GPIO_MODER_MODER6_1 GPIO_MODER_MODE6_1

Definition at line 5078 of file stm32g431xx.h.

◆ GPIO_MODER_MODER7

#define GPIO_MODER_MODER7 GPIO_MODER_MODE7

Definition at line 5079 of file stm32g431xx.h.

◆ GPIO_MODER_MODER7_0

#define GPIO_MODER_MODER7_0 GPIO_MODER_MODE7_0

Definition at line 5080 of file stm32g431xx.h.

◆ GPIO_MODER_MODER7_1

#define GPIO_MODER_MODER7_1 GPIO_MODER_MODE7_1

Definition at line 5081 of file stm32g431xx.h.

◆ GPIO_MODER_MODER8

#define GPIO_MODER_MODER8 GPIO_MODER_MODE8

Definition at line 5082 of file stm32g431xx.h.

◆ GPIO_MODER_MODER8_0

#define GPIO_MODER_MODER8_0 GPIO_MODER_MODE8_0

Definition at line 5083 of file stm32g431xx.h.

◆ GPIO_MODER_MODER8_1

#define GPIO_MODER_MODER8_1 GPIO_MODER_MODE8_1

Definition at line 5084 of file stm32g431xx.h.

◆ GPIO_MODER_MODER9

#define GPIO_MODER_MODER9 GPIO_MODER_MODE9

Definition at line 5085 of file stm32g431xx.h.

◆ GPIO_MODER_MODER9_0

#define GPIO_MODER_MODER9_0 GPIO_MODER_MODE9_0

Definition at line 5086 of file stm32g431xx.h.

◆ GPIO_MODER_MODER9_1

#define GPIO_MODER_MODER9_1 GPIO_MODER_MODE9_1

Definition at line 5087 of file stm32g431xx.h.

◆ GPIO_ODR_OD0

#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk

Definition at line 5528 of file stm32g431xx.h.

◆ GPIO_ODR_OD0_Msk

#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos)

0x00000001

Definition at line 5527 of file stm32g431xx.h.

◆ GPIO_ODR_OD0_Pos

#define GPIO_ODR_OD0_Pos (0U)

Definition at line 5526 of file stm32g431xx.h.

◆ GPIO_ODR_OD1

#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk

Definition at line 5531 of file stm32g431xx.h.

◆ GPIO_ODR_OD10

#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk

Definition at line 5558 of file stm32g431xx.h.

◆ GPIO_ODR_OD10_Msk

#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos)

0x00000400

Definition at line 5557 of file stm32g431xx.h.

◆ GPIO_ODR_OD10_Pos

#define GPIO_ODR_OD10_Pos (10U)

Definition at line 5556 of file stm32g431xx.h.

◆ GPIO_ODR_OD11

#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk

Definition at line 5561 of file stm32g431xx.h.

◆ GPIO_ODR_OD11_Msk

#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos)

0x00000800

Definition at line 5560 of file stm32g431xx.h.

◆ GPIO_ODR_OD11_Pos

#define GPIO_ODR_OD11_Pos (11U)

Definition at line 5559 of file stm32g431xx.h.

◆ GPIO_ODR_OD12

#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk

Definition at line 5564 of file stm32g431xx.h.

◆ GPIO_ODR_OD12_Msk

#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos)

0x00001000

Definition at line 5563 of file stm32g431xx.h.

◆ GPIO_ODR_OD12_Pos

#define GPIO_ODR_OD12_Pos (12U)

Definition at line 5562 of file stm32g431xx.h.

◆ GPIO_ODR_OD13

#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk

Definition at line 5567 of file stm32g431xx.h.

◆ GPIO_ODR_OD13_Msk

#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos)

0x00002000

Definition at line 5566 of file stm32g431xx.h.

◆ GPIO_ODR_OD13_Pos

#define GPIO_ODR_OD13_Pos (13U)

Definition at line 5565 of file stm32g431xx.h.

◆ GPIO_ODR_OD14

#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk

Definition at line 5570 of file stm32g431xx.h.

◆ GPIO_ODR_OD14_Msk

#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos)

0x00004000

Definition at line 5569 of file stm32g431xx.h.

◆ GPIO_ODR_OD14_Pos

#define GPIO_ODR_OD14_Pos (14U)

Definition at line 5568 of file stm32g431xx.h.

◆ GPIO_ODR_OD15

#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk

Definition at line 5573 of file stm32g431xx.h.

◆ GPIO_ODR_OD15_Msk

#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos)

0x00008000

Definition at line 5572 of file stm32g431xx.h.

◆ GPIO_ODR_OD15_Pos

#define GPIO_ODR_OD15_Pos (15U)

Definition at line 5571 of file stm32g431xx.h.

◆ GPIO_ODR_OD1_Msk

#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos)

0x00000002

Definition at line 5530 of file stm32g431xx.h.

◆ GPIO_ODR_OD1_Pos

#define GPIO_ODR_OD1_Pos (1U)

Definition at line 5529 of file stm32g431xx.h.

◆ GPIO_ODR_OD2

#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk

Definition at line 5534 of file stm32g431xx.h.

◆ GPIO_ODR_OD2_Msk

#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos)

0x00000004

Definition at line 5533 of file stm32g431xx.h.

◆ GPIO_ODR_OD2_Pos

#define GPIO_ODR_OD2_Pos (2U)

Definition at line 5532 of file stm32g431xx.h.

◆ GPIO_ODR_OD3

#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk

Definition at line 5537 of file stm32g431xx.h.

◆ GPIO_ODR_OD3_Msk

#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos)

0x00000008

Definition at line 5536 of file stm32g431xx.h.

◆ GPIO_ODR_OD3_Pos

#define GPIO_ODR_OD3_Pos (3U)

Definition at line 5535 of file stm32g431xx.h.

◆ GPIO_ODR_OD4

#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk

Definition at line 5540 of file stm32g431xx.h.

◆ GPIO_ODR_OD4_Msk

#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos)

0x00000010

Definition at line 5539 of file stm32g431xx.h.

◆ GPIO_ODR_OD4_Pos

#define GPIO_ODR_OD4_Pos (4U)

Definition at line 5538 of file stm32g431xx.h.

◆ GPIO_ODR_OD5

#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk

Definition at line 5543 of file stm32g431xx.h.

◆ GPIO_ODR_OD5_Msk

#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos)

0x00000020

Definition at line 5542 of file stm32g431xx.h.

◆ GPIO_ODR_OD5_Pos

#define GPIO_ODR_OD5_Pos (5U)

Definition at line 5541 of file stm32g431xx.h.

◆ GPIO_ODR_OD6

#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk

Definition at line 5546 of file stm32g431xx.h.

◆ GPIO_ODR_OD6_Msk

#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos)

0x00000040

Definition at line 5545 of file stm32g431xx.h.

◆ GPIO_ODR_OD6_Pos

#define GPIO_ODR_OD6_Pos (6U)

Definition at line 5544 of file stm32g431xx.h.

◆ GPIO_ODR_OD7

#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk

Definition at line 5549 of file stm32g431xx.h.

◆ GPIO_ODR_OD7_Msk

#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos)

0x00000080

Definition at line 5548 of file stm32g431xx.h.

◆ GPIO_ODR_OD7_Pos

#define GPIO_ODR_OD7_Pos (7U)

Definition at line 5547 of file stm32g431xx.h.

◆ GPIO_ODR_OD8

#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk

Definition at line 5552 of file stm32g431xx.h.

◆ GPIO_ODR_OD8_Msk

#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos)

0x00000100

Definition at line 5551 of file stm32g431xx.h.

◆ GPIO_ODR_OD8_Pos

#define GPIO_ODR_OD8_Pos (8U)

Definition at line 5550 of file stm32g431xx.h.

◆ GPIO_ODR_OD9

#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk

Definition at line 5555 of file stm32g431xx.h.

◆ GPIO_ODR_OD9_Msk

#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos)

0x00000200

Definition at line 5554 of file stm32g431xx.h.

◆ GPIO_ODR_OD9_Pos

#define GPIO_ODR_OD9_Pos (9U)

Definition at line 5553 of file stm32g431xx.h.

◆ GPIO_ODR_ODR_0

#define GPIO_ODR_ODR_0 GPIO_ODR_OD0

Definition at line 5576 of file stm32g431xx.h.

◆ GPIO_ODR_ODR_1

#define GPIO_ODR_ODR_1 GPIO_ODR_OD1

Definition at line 5577 of file stm32g431xx.h.

◆ GPIO_ODR_ODR_10

#define GPIO_ODR_ODR_10 GPIO_ODR_OD10

Definition at line 5586 of file stm32g431xx.h.

◆ GPIO_ODR_ODR_11

#define GPIO_ODR_ODR_11 GPIO_ODR_OD11

Definition at line 5587 of file stm32g431xx.h.

◆ GPIO_ODR_ODR_12

#define GPIO_ODR_ODR_12 GPIO_ODR_OD12

Definition at line 5588 of file stm32g431xx.h.

◆ GPIO_ODR_ODR_13

#define GPIO_ODR_ODR_13 GPIO_ODR_OD13

Definition at line 5589 of file stm32g431xx.h.

◆ GPIO_ODR_ODR_14

#define GPIO_ODR_ODR_14 GPIO_ODR_OD14

Definition at line 5590 of file stm32g431xx.h.

◆ GPIO_ODR_ODR_15

#define GPIO_ODR_ODR_15 GPIO_ODR_OD15

Definition at line 5591 of file stm32g431xx.h.

◆ GPIO_ODR_ODR_2

#define GPIO_ODR_ODR_2 GPIO_ODR_OD2

Definition at line 5578 of file stm32g431xx.h.

◆ GPIO_ODR_ODR_3

#define GPIO_ODR_ODR_3 GPIO_ODR_OD3

Definition at line 5579 of file stm32g431xx.h.

◆ GPIO_ODR_ODR_4

#define GPIO_ODR_ODR_4 GPIO_ODR_OD4

Definition at line 5580 of file stm32g431xx.h.

◆ GPIO_ODR_ODR_5

#define GPIO_ODR_ODR_5 GPIO_ODR_OD5

Definition at line 5581 of file stm32g431xx.h.

◆ GPIO_ODR_ODR_6

#define GPIO_ODR_ODR_6 GPIO_ODR_OD6

Definition at line 5582 of file stm32g431xx.h.

◆ GPIO_ODR_ODR_7

#define GPIO_ODR_ODR_7 GPIO_ODR_OD7

Definition at line 5583 of file stm32g431xx.h.

◆ GPIO_ODR_ODR_8

#define GPIO_ODR_ODR_8 GPIO_ODR_OD8

Definition at line 5584 of file stm32g431xx.h.

◆ GPIO_ODR_ODR_9

#define GPIO_ODR_ODR_9 GPIO_ODR_OD9

Definition at line 5585 of file stm32g431xx.h.

◆ GPIO_OSPEEDER_OSPEEDR0

#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0

Definition at line 5258 of file stm32g431xx.h.

◆ GPIO_OSPEEDER_OSPEEDR0_0

#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0

Definition at line 5259 of file stm32g431xx.h.

◆ GPIO_OSPEEDER_OSPEEDR0_1

#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1

Definition at line 5260 of file stm32g431xx.h.

◆ GPIO_OSPEEDER_OSPEEDR1

#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1

Definition at line 5261 of file stm32g431xx.h.

◆ GPIO_OSPEEDER_OSPEEDR10

#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10

Definition at line 5288 of file stm32g431xx.h.

◆ GPIO_OSPEEDER_OSPEEDR10_0

#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0

Definition at line 5289 of file stm32g431xx.h.

◆ GPIO_OSPEEDER_OSPEEDR10_1

#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1

Definition at line 5290 of file stm32g431xx.h.

◆ GPIO_OSPEEDER_OSPEEDR11

#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11

Definition at line 5291 of file stm32g431xx.h.

◆ GPIO_OSPEEDER_OSPEEDR11_0

#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0

Definition at line 5292 of file stm32g431xx.h.

◆ GPIO_OSPEEDER_OSPEEDR11_1

#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1

Definition at line 5293 of file stm32g431xx.h.

◆ GPIO_OSPEEDER_OSPEEDR12

#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12

Definition at line 5294 of file stm32g431xx.h.

◆ GPIO_OSPEEDER_OSPEEDR12_0

#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0

Definition at line 5295 of file stm32g431xx.h.

◆ GPIO_OSPEEDER_OSPEEDR12_1

#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1

Definition at line 5296 of file stm32g431xx.h.

◆ GPIO_OSPEEDER_OSPEEDR13

#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13

Definition at line 5297 of file stm32g431xx.h.

◆ GPIO_OSPEEDER_OSPEEDR13_0

#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0

Definition at line 5298 of file stm32g431xx.h.

◆ GPIO_OSPEEDER_OSPEEDR13_1

#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1

Definition at line 5299 of file stm32g431xx.h.

◆ GPIO_OSPEEDER_OSPEEDR14

#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14

Definition at line 5300 of file stm32g431xx.h.

◆ GPIO_OSPEEDER_OSPEEDR14_0

#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0

Definition at line 5301 of file stm32g431xx.h.

◆ GPIO_OSPEEDER_OSPEEDR14_1

#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1

Definition at line 5302 of file stm32g431xx.h.

◆ GPIO_OSPEEDER_OSPEEDR15

#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15

Definition at line 5303 of file stm32g431xx.h.

◆ GPIO_OSPEEDER_OSPEEDR15_0

#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0

Definition at line 5304 of file stm32g431xx.h.

◆ GPIO_OSPEEDER_OSPEEDR15_1

#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1

Definition at line 5305 of file stm32g431xx.h.

◆ GPIO_OSPEEDER_OSPEEDR1_0

#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0

Definition at line 5262 of file stm32g431xx.h.

◆ GPIO_OSPEEDER_OSPEEDR1_1

#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1

Definition at line 5263 of file stm32g431xx.h.

◆ GPIO_OSPEEDER_OSPEEDR2

#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2

Definition at line 5264 of file stm32g431xx.h.

◆ GPIO_OSPEEDER_OSPEEDR2_0

#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0

Definition at line 5265 of file stm32g431xx.h.

◆ GPIO_OSPEEDER_OSPEEDR2_1

#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1

Definition at line 5266 of file stm32g431xx.h.

◆ GPIO_OSPEEDER_OSPEEDR3

#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3

Definition at line 5267 of file stm32g431xx.h.

◆ GPIO_OSPEEDER_OSPEEDR3_0

#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0

Definition at line 5268 of file stm32g431xx.h.

◆ GPIO_OSPEEDER_OSPEEDR3_1

#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1

Definition at line 5269 of file stm32g431xx.h.

◆ GPIO_OSPEEDER_OSPEEDR4

#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4

Definition at line 5270 of file stm32g431xx.h.

◆ GPIO_OSPEEDER_OSPEEDR4_0

#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0

Definition at line 5271 of file stm32g431xx.h.

◆ GPIO_OSPEEDER_OSPEEDR4_1

#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1

Definition at line 5272 of file stm32g431xx.h.

◆ GPIO_OSPEEDER_OSPEEDR5

#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5

Definition at line 5273 of file stm32g431xx.h.

◆ GPIO_OSPEEDER_OSPEEDR5_0

#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0

Definition at line 5274 of file stm32g431xx.h.

◆ GPIO_OSPEEDER_OSPEEDR5_1

#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1

Definition at line 5275 of file stm32g431xx.h.

◆ GPIO_OSPEEDER_OSPEEDR6

#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6

Definition at line 5276 of file stm32g431xx.h.

◆ GPIO_OSPEEDER_OSPEEDR6_0

#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0

Definition at line 5277 of file stm32g431xx.h.

◆ GPIO_OSPEEDER_OSPEEDR6_1

#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1

Definition at line 5278 of file stm32g431xx.h.

◆ GPIO_OSPEEDER_OSPEEDR7

#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7

Definition at line 5279 of file stm32g431xx.h.

◆ GPIO_OSPEEDER_OSPEEDR7_0

#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0

Definition at line 5280 of file stm32g431xx.h.

◆ GPIO_OSPEEDER_OSPEEDR7_1

#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1

Definition at line 5281 of file stm32g431xx.h.

◆ GPIO_OSPEEDER_OSPEEDR8

#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8

Definition at line 5282 of file stm32g431xx.h.

◆ GPIO_OSPEEDER_OSPEEDR8_0

#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0

Definition at line 5283 of file stm32g431xx.h.

◆ GPIO_OSPEEDER_OSPEEDR8_1

#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1

Definition at line 5284 of file stm32g431xx.h.

◆ GPIO_OSPEEDER_OSPEEDR9

#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9

Definition at line 5285 of file stm32g431xx.h.

◆ GPIO_OSPEEDER_OSPEEDR9_0

#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0

Definition at line 5286 of file stm32g431xx.h.

◆ GPIO_OSPEEDER_OSPEEDR9_1

#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1

Definition at line 5287 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED0

#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk

Definition at line 5178 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED0_0

#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)

0x00000001

Definition at line 5179 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED0_1

#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)

0x00000002

Definition at line 5180 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED0_Msk

#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)

0x00000003

Definition at line 5177 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED0_Pos

#define GPIO_OSPEEDR_OSPEED0_Pos (0U)

Definition at line 5176 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED1

#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk

Definition at line 5183 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED10

#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk

Definition at line 5228 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED10_0

#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)

0x00100000

Definition at line 5229 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED10_1

#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)

0x00200000

Definition at line 5230 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED10_Msk

#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)

0x00300000

Definition at line 5227 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED10_Pos

#define GPIO_OSPEEDR_OSPEED10_Pos (20U)

Definition at line 5226 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED11

#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk

Definition at line 5233 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED11_0

#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)

0x00400000

Definition at line 5234 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED11_1

#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)

0x00800000

Definition at line 5235 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED11_Msk

#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)

0x00C00000

Definition at line 5232 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED11_Pos

#define GPIO_OSPEEDR_OSPEED11_Pos (22U)

Definition at line 5231 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED12

#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk

Definition at line 5238 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED12_0

#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)

0x01000000

Definition at line 5239 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED12_1

#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)

0x02000000

Definition at line 5240 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED12_Msk

#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)

0x03000000

Definition at line 5237 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED12_Pos

#define GPIO_OSPEEDR_OSPEED12_Pos (24U)

Definition at line 5236 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED13

#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk

Definition at line 5243 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED13_0

#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)

0x04000000

Definition at line 5244 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED13_1

#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)

0x08000000

Definition at line 5245 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED13_Msk

#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)

0x0C000000

Definition at line 5242 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED13_Pos

#define GPIO_OSPEEDR_OSPEED13_Pos (26U)

Definition at line 5241 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED14

#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk

Definition at line 5248 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED14_0

#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)

0x10000000

Definition at line 5249 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED14_1

#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)

0x20000000

Definition at line 5250 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED14_Msk

#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)

0x30000000

Definition at line 5247 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED14_Pos

#define GPIO_OSPEEDR_OSPEED14_Pos (28U)

Definition at line 5246 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED15

#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk

Definition at line 5253 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED15_0

#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)

0x40000000

Definition at line 5254 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED15_1

#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)

0x80000000

Definition at line 5255 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED15_Msk

#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)

0xC0000000

Definition at line 5252 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED15_Pos

#define GPIO_OSPEEDR_OSPEED15_Pos (30U)

Definition at line 5251 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED1_0

#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)

0x00000004

Definition at line 5184 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED1_1

#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)

0x00000008

Definition at line 5185 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED1_Msk

#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)

0x0000000C

Definition at line 5182 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED1_Pos

#define GPIO_OSPEEDR_OSPEED1_Pos (2U)

Definition at line 5181 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED2

#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk

Definition at line 5188 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED2_0

#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)

0x00000010

Definition at line 5189 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED2_1

#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)

0x00000020

Definition at line 5190 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED2_Msk

#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)

0x00000030

Definition at line 5187 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED2_Pos

#define GPIO_OSPEEDR_OSPEED2_Pos (4U)

Definition at line 5186 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED3

#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk

Definition at line 5193 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED3_0

#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)

0x00000040

Definition at line 5194 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED3_1

#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)

0x00000080

Definition at line 5195 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED3_Msk

#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)

0x000000C0

Definition at line 5192 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED3_Pos

#define GPIO_OSPEEDR_OSPEED3_Pos (6U)

Definition at line 5191 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED4

#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk

Definition at line 5198 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED4_0

#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)

0x00000100

Definition at line 5199 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED4_1

#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)

0x00000200

Definition at line 5200 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED4_Msk

#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)

0x00000300

Definition at line 5197 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED4_Pos

#define GPIO_OSPEEDR_OSPEED4_Pos (8U)

Definition at line 5196 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED5

#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk

Definition at line 5203 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED5_0

#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)

0x00000400

Definition at line 5204 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED5_1

#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)

0x00000800

Definition at line 5205 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED5_Msk

#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)

0x00000C00

Definition at line 5202 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED5_Pos

#define GPIO_OSPEEDR_OSPEED5_Pos (10U)

Definition at line 5201 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED6

#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk

Definition at line 5208 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED6_0

#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)

0x00001000

Definition at line 5209 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED6_1

#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)

0x00002000

Definition at line 5210 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED6_Msk

#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)

0x00003000

Definition at line 5207 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED6_Pos

#define GPIO_OSPEEDR_OSPEED6_Pos (12U)

Definition at line 5206 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED7

#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk

Definition at line 5213 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED7_0

#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)

0x00004000

Definition at line 5214 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED7_1

#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)

0x00008000

Definition at line 5215 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED7_Msk

#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)

0x0000C000

Definition at line 5212 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED7_Pos

#define GPIO_OSPEEDR_OSPEED7_Pos (14U)

Definition at line 5211 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED8

#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk

Definition at line 5218 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED8_0

#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)

0x00010000

Definition at line 5219 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED8_1

#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)

0x00020000

Definition at line 5220 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED8_Msk

#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)

0x00030000

Definition at line 5217 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED8_Pos

#define GPIO_OSPEEDR_OSPEED8_Pos (16U)

Definition at line 5216 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED9

#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk

Definition at line 5223 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED9_0

#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)

0x00040000

Definition at line 5224 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED9_1

#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)

0x00080000

Definition at line 5225 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED9_Msk

#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)

0x000C0000

Definition at line 5222 of file stm32g431xx.h.

◆ GPIO_OSPEEDR_OSPEED9_Pos

#define GPIO_OSPEEDR_OSPEED9_Pos (18U)

Definition at line 5221 of file stm32g431xx.h.

◆ GPIO_OTYPER_IDR_0

#define GPIO_OTYPER_IDR_0 GPIO_IDR_ID0

Definition at line 5508 of file stm32g431xx.h.

◆ GPIO_OTYPER_IDR_1

#define GPIO_OTYPER_IDR_1 GPIO_IDR_ID1

Definition at line 5509 of file stm32g431xx.h.

◆ GPIO_OTYPER_IDR_10

#define GPIO_OTYPER_IDR_10 GPIO_IDR_ID10

Definition at line 5518 of file stm32g431xx.h.

◆ GPIO_OTYPER_IDR_11

#define GPIO_OTYPER_IDR_11 GPIO_IDR_ID11

Definition at line 5519 of file stm32g431xx.h.

◆ GPIO_OTYPER_IDR_12

#define GPIO_OTYPER_IDR_12 GPIO_IDR_ID12

Definition at line 5520 of file stm32g431xx.h.

◆ GPIO_OTYPER_IDR_13

#define GPIO_OTYPER_IDR_13 GPIO_IDR_ID13

Definition at line 5521 of file stm32g431xx.h.

◆ GPIO_OTYPER_IDR_14

#define GPIO_OTYPER_IDR_14 GPIO_IDR_ID14

Definition at line 5522 of file stm32g431xx.h.

◆ GPIO_OTYPER_IDR_15

#define GPIO_OTYPER_IDR_15 GPIO_IDR_ID15

Definition at line 5523 of file stm32g431xx.h.

◆ GPIO_OTYPER_IDR_2

#define GPIO_OTYPER_IDR_2 GPIO_IDR_ID2

Definition at line 5510 of file stm32g431xx.h.

◆ GPIO_OTYPER_IDR_3

#define GPIO_OTYPER_IDR_3 GPIO_IDR_ID3

Definition at line 5511 of file stm32g431xx.h.

◆ GPIO_OTYPER_IDR_4

#define GPIO_OTYPER_IDR_4 GPIO_IDR_ID4

Definition at line 5512 of file stm32g431xx.h.

◆ GPIO_OTYPER_IDR_5

#define GPIO_OTYPER_IDR_5 GPIO_IDR_ID5

Definition at line 5513 of file stm32g431xx.h.

◆ GPIO_OTYPER_IDR_6

#define GPIO_OTYPER_IDR_6 GPIO_IDR_ID6

Definition at line 5514 of file stm32g431xx.h.

◆ GPIO_OTYPER_IDR_7

#define GPIO_OTYPER_IDR_7 GPIO_IDR_ID7

Definition at line 5515 of file stm32g431xx.h.

◆ GPIO_OTYPER_IDR_8

#define GPIO_OTYPER_IDR_8 GPIO_IDR_ID8

Definition at line 5516 of file stm32g431xx.h.

◆ GPIO_OTYPER_IDR_9

#define GPIO_OTYPER_IDR_9 GPIO_IDR_ID9

Definition at line 5517 of file stm32g431xx.h.

◆ GPIO_OTYPER_ODR_0

#define GPIO_OTYPER_ODR_0 GPIO_ODR_OD0

Definition at line 5594 of file stm32g431xx.h.

◆ GPIO_OTYPER_ODR_1

#define GPIO_OTYPER_ODR_1 GPIO_ODR_OD1

Definition at line 5595 of file stm32g431xx.h.

◆ GPIO_OTYPER_ODR_10

#define GPIO_OTYPER_ODR_10 GPIO_ODR_OD10

Definition at line 5604 of file stm32g431xx.h.

◆ GPIO_OTYPER_ODR_11

#define GPIO_OTYPER_ODR_11 GPIO_ODR_OD11

Definition at line 5605 of file stm32g431xx.h.

◆ GPIO_OTYPER_ODR_12

#define GPIO_OTYPER_ODR_12 GPIO_ODR_OD12

Definition at line 5606 of file stm32g431xx.h.

◆ GPIO_OTYPER_ODR_13

#define GPIO_OTYPER_ODR_13 GPIO_ODR_OD13

Definition at line 5607 of file stm32g431xx.h.

◆ GPIO_OTYPER_ODR_14

#define GPIO_OTYPER_ODR_14 GPIO_ODR_OD14

Definition at line 5608 of file stm32g431xx.h.

◆ GPIO_OTYPER_ODR_15

#define GPIO_OTYPER_ODR_15 GPIO_ODR_OD15

Definition at line 5609 of file stm32g431xx.h.

◆ GPIO_OTYPER_ODR_2

#define GPIO_OTYPER_ODR_2 GPIO_ODR_OD2

Definition at line 5596 of file stm32g431xx.h.

◆ GPIO_OTYPER_ODR_3

#define GPIO_OTYPER_ODR_3 GPIO_ODR_OD3

Definition at line 5597 of file stm32g431xx.h.

◆ GPIO_OTYPER_ODR_4

#define GPIO_OTYPER_ODR_4 GPIO_ODR_OD4

Definition at line 5598 of file stm32g431xx.h.

◆ GPIO_OTYPER_ODR_5

#define GPIO_OTYPER_ODR_5 GPIO_ODR_OD5

Definition at line 5599 of file stm32g431xx.h.

◆ GPIO_OTYPER_ODR_6

#define GPIO_OTYPER_ODR_6 GPIO_ODR_OD6

Definition at line 5600 of file stm32g431xx.h.

◆ GPIO_OTYPER_ODR_7

#define GPIO_OTYPER_ODR_7 GPIO_ODR_OD7

Definition at line 5601 of file stm32g431xx.h.

◆ GPIO_OTYPER_ODR_8

#define GPIO_OTYPER_ODR_8 GPIO_ODR_OD8

Definition at line 5602 of file stm32g431xx.h.

◆ GPIO_OTYPER_ODR_9

#define GPIO_OTYPER_ODR_9 GPIO_ODR_OD9

Definition at line 5603 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT0

#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk

Definition at line 5110 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT0_Msk

#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos)

0x00000001

Definition at line 5109 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT0_Pos

#define GPIO_OTYPER_OT0_Pos (0U)

Definition at line 5108 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT1

#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk

Definition at line 5113 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT10

#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk

Definition at line 5140 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT10_Msk

#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos)

0x00000400

Definition at line 5139 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT10_Pos

#define GPIO_OTYPER_OT10_Pos (10U)

Definition at line 5138 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT11

#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk

Definition at line 5143 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT11_Msk

#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos)

0x00000800

Definition at line 5142 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT11_Pos

#define GPIO_OTYPER_OT11_Pos (11U)

Definition at line 5141 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT12

#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk

Definition at line 5146 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT12_Msk

#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos)

0x00001000

Definition at line 5145 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT12_Pos

#define GPIO_OTYPER_OT12_Pos (12U)

Definition at line 5144 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT13

#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk

Definition at line 5149 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT13_Msk

#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos)

0x00002000

Definition at line 5148 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT13_Pos

#define GPIO_OTYPER_OT13_Pos (13U)

Definition at line 5147 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT14

#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk

Definition at line 5152 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT14_Msk

#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos)

0x00004000

Definition at line 5151 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT14_Pos

#define GPIO_OTYPER_OT14_Pos (14U)

Definition at line 5150 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT15

#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk

Definition at line 5155 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT15_Msk

#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos)

0x00008000

Definition at line 5154 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT15_Pos

#define GPIO_OTYPER_OT15_Pos (15U)

Definition at line 5153 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT1_Msk

#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos)

0x00000002

Definition at line 5112 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT1_Pos

#define GPIO_OTYPER_OT1_Pos (1U)

Definition at line 5111 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT2

#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk

Definition at line 5116 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT2_Msk

#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos)

0x00000004

Definition at line 5115 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT2_Pos

#define GPIO_OTYPER_OT2_Pos (2U)

Definition at line 5114 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT3

#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk

Definition at line 5119 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT3_Msk

#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos)

0x00000008

Definition at line 5118 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT3_Pos

#define GPIO_OTYPER_OT3_Pos (3U)

Definition at line 5117 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT4

#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk

Definition at line 5122 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT4_Msk

#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos)

0x00000010

Definition at line 5121 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT4_Pos

#define GPIO_OTYPER_OT4_Pos (4U)

Definition at line 5120 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT5

#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk

Definition at line 5125 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT5_Msk

#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos)

0x00000020

Definition at line 5124 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT5_Pos

#define GPIO_OTYPER_OT5_Pos (5U)

Definition at line 5123 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT6

#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk

Definition at line 5128 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT6_Msk

#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos)

0x00000040

Definition at line 5127 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT6_Pos

#define GPIO_OTYPER_OT6_Pos (6U)

Definition at line 5126 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT7

#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk

Definition at line 5131 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT7_Msk

#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos)

0x00000080

Definition at line 5130 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT7_Pos

#define GPIO_OTYPER_OT7_Pos (7U)

Definition at line 5129 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT8

#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk

Definition at line 5134 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT8_Msk

#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos)

0x00000100

Definition at line 5133 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT8_Pos

#define GPIO_OTYPER_OT8_Pos (8U)

Definition at line 5132 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT9

#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk

Definition at line 5137 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT9_Msk

#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos)

0x00000200

Definition at line 5136 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT9_Pos

#define GPIO_OTYPER_OT9_Pos (9U)

Definition at line 5135 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT_0

#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0

Definition at line 5158 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT_1

#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1

Definition at line 5159 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT_10

#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10

Definition at line 5168 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT_11

#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11

Definition at line 5169 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT_12

#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12

Definition at line 5170 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT_13

#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13

Definition at line 5171 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT_14

#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14

Definition at line 5172 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT_15

#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15

Definition at line 5173 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT_2

#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2

Definition at line 5160 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT_3

#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3

Definition at line 5161 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT_4

#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4

Definition at line 5162 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT_5

#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5

Definition at line 5163 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT_6

#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6

Definition at line 5164 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT_7

#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7

Definition at line 5165 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT_8

#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8

Definition at line 5166 of file stm32g431xx.h.

◆ GPIO_OTYPER_OT_9

#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9

Definition at line 5167 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD0

#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk

Definition at line 5310 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD0_0

#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos)

0x00000001

Definition at line 5311 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD0_1

#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos)

0x00000002

Definition at line 5312 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD0_Msk

#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos)

0x00000003

Definition at line 5309 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD0_Pos

#define GPIO_PUPDR_PUPD0_Pos (0U)

Definition at line 5308 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD1

#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk

Definition at line 5315 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD10

#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk

Definition at line 5360 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD10_0

#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos)

0x00100000

Definition at line 5361 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD10_1

#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos)

0x00200000

Definition at line 5362 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD10_Msk

#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos)

0x00300000

Definition at line 5359 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD10_Pos

#define GPIO_PUPDR_PUPD10_Pos (20U)

Definition at line 5358 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD11

#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk

Definition at line 5365 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD11_0

#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos)

0x00400000

Definition at line 5366 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD11_1

#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos)

0x00800000

Definition at line 5367 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD11_Msk

#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos)

0x00C00000

Definition at line 5364 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD11_Pos

#define GPIO_PUPDR_PUPD11_Pos (22U)

Definition at line 5363 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD12

#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk

Definition at line 5370 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD12_0

#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos)

0x01000000

Definition at line 5371 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD12_1

#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos)

0x02000000

Definition at line 5372 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD12_Msk

#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos)

0x03000000

Definition at line 5369 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD12_Pos

#define GPIO_PUPDR_PUPD12_Pos (24U)

Definition at line 5368 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD13

#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk

Definition at line 5375 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD13_0

#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos)

0x04000000

Definition at line 5376 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD13_1

#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos)

0x08000000

Definition at line 5377 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD13_Msk

#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos)

0x0C000000

Definition at line 5374 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD13_Pos

#define GPIO_PUPDR_PUPD13_Pos (26U)

Definition at line 5373 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD14

#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk

Definition at line 5380 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD14_0

#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos)

0x10000000

Definition at line 5381 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD14_1

#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos)

0x20000000

Definition at line 5382 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD14_Msk

#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos)

0x30000000

Definition at line 5379 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD14_Pos

#define GPIO_PUPDR_PUPD14_Pos (28U)

Definition at line 5378 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD15

#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk

Definition at line 5385 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD15_0

#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos)

0x40000000

Definition at line 5386 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD15_1

#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos)

0x80000000

Definition at line 5387 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD15_Msk

#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos)

0xC0000000

Definition at line 5384 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD15_Pos

#define GPIO_PUPDR_PUPD15_Pos (30U)

Definition at line 5383 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD1_0

#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos)

0x00000004

Definition at line 5316 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD1_1

#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos)

0x00000008

Definition at line 5317 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD1_Msk

#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos)

0x0000000C

Definition at line 5314 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD1_Pos

#define GPIO_PUPDR_PUPD1_Pos (2U)

Definition at line 5313 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD2

#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk

Definition at line 5320 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD2_0

#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos)

0x00000010

Definition at line 5321 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD2_1

#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos)

0x00000020

Definition at line 5322 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD2_Msk

#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos)

0x00000030

Definition at line 5319 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD2_Pos

#define GPIO_PUPDR_PUPD2_Pos (4U)

Definition at line 5318 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD3

#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk

Definition at line 5325 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD3_0

#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos)

0x00000040

Definition at line 5326 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD3_1

#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos)

0x00000080

Definition at line 5327 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD3_Msk

#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos)

0x000000C0

Definition at line 5324 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD3_Pos

#define GPIO_PUPDR_PUPD3_Pos (6U)

Definition at line 5323 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD4

#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk

Definition at line 5330 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD4_0

#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos)

0x00000100

Definition at line 5331 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD4_1

#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos)

0x00000200

Definition at line 5332 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD4_Msk

#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos)

0x00000300

Definition at line 5329 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD4_Pos

#define GPIO_PUPDR_PUPD4_Pos (8U)

Definition at line 5328 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD5

#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk

Definition at line 5335 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD5_0

#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos)

0x00000400

Definition at line 5336 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD5_1

#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos)

0x00000800

Definition at line 5337 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD5_Msk

#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos)

0x00000C00

Definition at line 5334 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD5_Pos

#define GPIO_PUPDR_PUPD5_Pos (10U)

Definition at line 5333 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD6

#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk

Definition at line 5340 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD6_0

#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos)

0x00001000

Definition at line 5341 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD6_1

#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos)

0x00002000

Definition at line 5342 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD6_Msk

#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos)

0x00003000

Definition at line 5339 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD6_Pos

#define GPIO_PUPDR_PUPD6_Pos (12U)

Definition at line 5338 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD7

#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk

Definition at line 5345 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD7_0

#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos)

0x00004000

Definition at line 5346 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD7_1

#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos)

0x00008000

Definition at line 5347 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD7_Msk

#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos)

0x0000C000

Definition at line 5344 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD7_Pos

#define GPIO_PUPDR_PUPD7_Pos (14U)

Definition at line 5343 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD8

#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk

Definition at line 5350 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD8_0

#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos)

0x00010000

Definition at line 5351 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD8_1

#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos)

0x00020000

Definition at line 5352 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD8_Msk

#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos)

0x00030000

Definition at line 5349 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD8_Pos

#define GPIO_PUPDR_PUPD8_Pos (16U)

Definition at line 5348 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD9

#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk

Definition at line 5355 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD9_0

#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos)

0x00040000

Definition at line 5356 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD9_1

#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos)

0x00080000

Definition at line 5357 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD9_Msk

#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos)

0x000C0000

Definition at line 5354 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPD9_Pos

#define GPIO_PUPDR_PUPD9_Pos (18U)

Definition at line 5353 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPDR0

#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0

Definition at line 5390 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPDR0_0

#define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0

Definition at line 5391 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPDR0_1

#define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1

Definition at line 5392 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPDR1

#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1

Definition at line 5393 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPDR10

#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10

Definition at line 5420 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPDR10_0

#define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0

Definition at line 5421 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPDR10_1

#define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1

Definition at line 5422 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPDR11

#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11

Definition at line 5423 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPDR11_0

#define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0

Definition at line 5424 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPDR11_1

#define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1

Definition at line 5425 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPDR12

#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12

Definition at line 5426 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPDR12_0

#define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0

Definition at line 5427 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPDR12_1

#define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1

Definition at line 5428 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPDR13

#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13

Definition at line 5429 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPDR13_0

#define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0

Definition at line 5430 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPDR13_1

#define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1

Definition at line 5431 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPDR14

#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14

Definition at line 5432 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPDR14_0

#define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0

Definition at line 5433 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPDR14_1

#define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1

Definition at line 5434 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPDR15

#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15

Definition at line 5435 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPDR15_0

#define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0

Definition at line 5436 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPDR15_1

#define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1

Definition at line 5437 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPDR1_0

#define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0

Definition at line 5394 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPDR1_1

#define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1

Definition at line 5395 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPDR2

#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2

Definition at line 5396 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPDR2_0

#define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0

Definition at line 5397 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPDR2_1

#define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1

Definition at line 5398 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPDR3

#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3

Definition at line 5399 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPDR3_0

#define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0

Definition at line 5400 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPDR3_1

#define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1

Definition at line 5401 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPDR4

#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4

Definition at line 5402 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPDR4_0

#define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0

Definition at line 5403 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPDR4_1

#define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1

Definition at line 5404 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPDR5

#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5

Definition at line 5405 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPDR5_0

#define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0

Definition at line 5406 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPDR5_1

#define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1

Definition at line 5407 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPDR6

#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6

Definition at line 5408 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPDR6_0

#define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0

Definition at line 5409 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPDR6_1

#define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1

Definition at line 5410 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPDR7

#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7

Definition at line 5411 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPDR7_0

#define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0

Definition at line 5412 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPDR7_1

#define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1

Definition at line 5413 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPDR8

#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8

Definition at line 5414 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPDR8_0

#define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0

Definition at line 5415 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPDR8_1

#define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1

Definition at line 5416 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPDR9

#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9

Definition at line 5417 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPDR9_0

#define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0

Definition at line 5418 of file stm32g431xx.h.

◆ GPIO_PUPDR_PUPDR9_1

#define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1

Definition at line 5419 of file stm32g431xx.h.

◆ I2C_CR1_ADDRIE

#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk

Address match interrupt enable

Definition at line 6018 of file stm32g431xx.h.

◆ I2C_CR1_ADDRIE_Msk

#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos)

0x00000008

Definition at line 6017 of file stm32g431xx.h.

◆ I2C_CR1_ADDRIE_Pos

#define I2C_CR1_ADDRIE_Pos (3U)

Definition at line 6016 of file stm32g431xx.h.

◆ I2C_CR1_ALERTEN

#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk

SMBus alert enable

Definition at line 6066 of file stm32g431xx.h.

◆ I2C_CR1_ALERTEN_Msk

#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos)

0x00400000

Definition at line 6065 of file stm32g431xx.h.

◆ I2C_CR1_ALERTEN_Pos

#define I2C_CR1_ALERTEN_Pos (22U)

Definition at line 6064 of file stm32g431xx.h.

◆ I2C_CR1_ANFOFF

#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk

Analog noise filter OFF

Definition at line 6036 of file stm32g431xx.h.

◆ I2C_CR1_ANFOFF_Msk

#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos)

0x00001000

Definition at line 6035 of file stm32g431xx.h.

◆ I2C_CR1_ANFOFF_Pos

#define I2C_CR1_ANFOFF_Pos (12U)

Definition at line 6034 of file stm32g431xx.h.

◆ I2C_CR1_DNF

#define I2C_CR1_DNF I2C_CR1_DNF_Msk

Digital noise filter

Definition at line 6033 of file stm32g431xx.h.

◆ I2C_CR1_DNF_Msk

#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos)

0x00000F00

Definition at line 6032 of file stm32g431xx.h.

◆ I2C_CR1_DNF_Pos

#define I2C_CR1_DNF_Pos (8U)

Definition at line 6031 of file stm32g431xx.h.

◆ I2C_CR1_ERRIE

#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk

Errors interrupt enable

Definition at line 6030 of file stm32g431xx.h.

◆ I2C_CR1_ERRIE_Msk

#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos)

0x00000080

Definition at line 6029 of file stm32g431xx.h.

◆ I2C_CR1_ERRIE_Pos

#define I2C_CR1_ERRIE_Pos (7U)

Definition at line 6028 of file stm32g431xx.h.

◆ I2C_CR1_GCEN

#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk

General call enable

Definition at line 6057 of file stm32g431xx.h.

◆ I2C_CR1_GCEN_Msk

#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos)

0x00080000

Definition at line 6056 of file stm32g431xx.h.

◆ I2C_CR1_GCEN_Pos

#define I2C_CR1_GCEN_Pos (19U)

Definition at line 6055 of file stm32g431xx.h.

◆ I2C_CR1_NACKIE

#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk

NACK received interrupt enable

Definition at line 6021 of file stm32g431xx.h.

◆ I2C_CR1_NACKIE_Msk

#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos)

0x00000010

Definition at line 6020 of file stm32g431xx.h.

◆ I2C_CR1_NACKIE_Pos

#define I2C_CR1_NACKIE_Pos (4U)

Definition at line 6019 of file stm32g431xx.h.

◆ I2C_CR1_NOSTRETCH

#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk

Clock stretching disable

Definition at line 6051 of file stm32g431xx.h.

◆ I2C_CR1_NOSTRETCH_Msk

#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos)

0x00020000

Definition at line 6050 of file stm32g431xx.h.

◆ I2C_CR1_NOSTRETCH_Pos

#define I2C_CR1_NOSTRETCH_Pos (17U)

Definition at line 6049 of file stm32g431xx.h.

◆ I2C_CR1_PE

#define I2C_CR1_PE I2C_CR1_PE_Msk

Peripheral enable

Definition at line 6009 of file stm32g431xx.h.

◆ I2C_CR1_PE_Msk

#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos)

0x00000001

Definition at line 6008 of file stm32g431xx.h.

◆ I2C_CR1_PE_Pos

#define I2C_CR1_PE_Pos (0U)

Definition at line 6007 of file stm32g431xx.h.

◆ I2C_CR1_PECEN

#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk

PEC enable

Definition at line 6069 of file stm32g431xx.h.

◆ I2C_CR1_PECEN_Msk

#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos)

0x00800000

Definition at line 6068 of file stm32g431xx.h.

◆ I2C_CR1_PECEN_Pos

#define I2C_CR1_PECEN_Pos (23U)

Definition at line 6067 of file stm32g431xx.h.

◆ I2C_CR1_RXDMAEN

#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk

DMA reception requests enable

Definition at line 6045 of file stm32g431xx.h.

◆ I2C_CR1_RXDMAEN_Msk

#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos)

0x00008000

Definition at line 6044 of file stm32g431xx.h.

◆ I2C_CR1_RXDMAEN_Pos

#define I2C_CR1_RXDMAEN_Pos (15U)

Definition at line 6043 of file stm32g431xx.h.

◆ I2C_CR1_RXIE

#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk

RX interrupt enable

Definition at line 6015 of file stm32g431xx.h.

◆ I2C_CR1_RXIE_Msk

#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos)

0x00000004

Definition at line 6014 of file stm32g431xx.h.

◆ I2C_CR1_RXIE_Pos

#define I2C_CR1_RXIE_Pos (2U)

Definition at line 6013 of file stm32g431xx.h.

◆ I2C_CR1_SBC

#define I2C_CR1_SBC I2C_CR1_SBC_Msk

Slave byte control

Definition at line 6048 of file stm32g431xx.h.

◆ I2C_CR1_SBC_Msk

#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos)

0x00010000

Definition at line 6047 of file stm32g431xx.h.

◆ I2C_CR1_SBC_Pos

#define I2C_CR1_SBC_Pos (16U)

Definition at line 6046 of file stm32g431xx.h.

◆ I2C_CR1_SMBDEN

#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk

SMBus device default address enable

Definition at line 6063 of file stm32g431xx.h.

◆ I2C_CR1_SMBDEN_Msk

#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos)

0x00200000

Definition at line 6062 of file stm32g431xx.h.

◆ I2C_CR1_SMBDEN_Pos

#define I2C_CR1_SMBDEN_Pos (21U)

Definition at line 6061 of file stm32g431xx.h.

◆ I2C_CR1_SMBHEN

#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk

SMBus host address enable

Definition at line 6060 of file stm32g431xx.h.

◆ I2C_CR1_SMBHEN_Msk

#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos)

0x00100000

Definition at line 6059 of file stm32g431xx.h.

◆ I2C_CR1_SMBHEN_Pos

#define I2C_CR1_SMBHEN_Pos (20U)

Definition at line 6058 of file stm32g431xx.h.

◆ I2C_CR1_STOPIE

#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk

STOP detection interrupt enable

Definition at line 6024 of file stm32g431xx.h.

◆ I2C_CR1_STOPIE_Msk

#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos)

0x00000020

Definition at line 6023 of file stm32g431xx.h.

◆ I2C_CR1_STOPIE_Pos

#define I2C_CR1_STOPIE_Pos (5U)

Definition at line 6022 of file stm32g431xx.h.

◆ I2C_CR1_SWRST

#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk

Software reset

Definition at line 6039 of file stm32g431xx.h.

◆ I2C_CR1_SWRST_Msk

#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos)

0x00002000

Definition at line 6038 of file stm32g431xx.h.

◆ I2C_CR1_SWRST_Pos

#define I2C_CR1_SWRST_Pos (13U)

Definition at line 6037 of file stm32g431xx.h.

◆ I2C_CR1_TCIE

#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk

Transfer complete interrupt enable

Definition at line 6027 of file stm32g431xx.h.

◆ I2C_CR1_TCIE_Msk

#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos)

0x00000040

Definition at line 6026 of file stm32g431xx.h.

◆ I2C_CR1_TCIE_Pos

#define I2C_CR1_TCIE_Pos (6U)

Definition at line 6025 of file stm32g431xx.h.

◆ I2C_CR1_TXDMAEN

#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk

DMA transmission requests enable

Definition at line 6042 of file stm32g431xx.h.

◆ I2C_CR1_TXDMAEN_Msk

#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos)

0x00004000

Definition at line 6041 of file stm32g431xx.h.

◆ I2C_CR1_TXDMAEN_Pos

#define I2C_CR1_TXDMAEN_Pos (14U)

Definition at line 6040 of file stm32g431xx.h.

◆ I2C_CR1_TXIE

#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk

TX interrupt enable

Definition at line 6012 of file stm32g431xx.h.

◆ I2C_CR1_TXIE_Msk

#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos)

0x00000002

Definition at line 6011 of file stm32g431xx.h.

◆ I2C_CR1_TXIE_Pos

#define I2C_CR1_TXIE_Pos (1U)

Definition at line 6010 of file stm32g431xx.h.

◆ I2C_CR1_WUPEN

#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk

Wakeup from STOP enable

Definition at line 6054 of file stm32g431xx.h.

◆ I2C_CR1_WUPEN_Msk

#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos)

0x00040000

Definition at line 6053 of file stm32g431xx.h.

◆ I2C_CR1_WUPEN_Pos

#define I2C_CR1_WUPEN_Pos (18U)

Definition at line 6052 of file stm32g431xx.h.

◆ I2C_CR2_ADD10

#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk

10-bit addressing mode (master mode)

Definition at line 6080 of file stm32g431xx.h.

◆ I2C_CR2_ADD10_Msk

#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos)

0x00000800

Definition at line 6079 of file stm32g431xx.h.

◆ I2C_CR2_ADD10_Pos

#define I2C_CR2_ADD10_Pos (11U)

Definition at line 6078 of file stm32g431xx.h.

◆ I2C_CR2_AUTOEND

#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk

Automatic end mode (master mode)

Definition at line 6101 of file stm32g431xx.h.

◆ I2C_CR2_AUTOEND_Msk

#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos)

0x02000000

Definition at line 6100 of file stm32g431xx.h.

◆ I2C_CR2_AUTOEND_Pos

#define I2C_CR2_AUTOEND_Pos (25U)

Definition at line 6099 of file stm32g431xx.h.

◆ I2C_CR2_HEAD10R

#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk

10-bit address header only read direction (master mode)

Definition at line 6083 of file stm32g431xx.h.

◆ I2C_CR2_HEAD10R_Msk

#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos)

0x00001000

Definition at line 6082 of file stm32g431xx.h.

◆ I2C_CR2_HEAD10R_Pos

#define I2C_CR2_HEAD10R_Pos (12U)

Definition at line 6081 of file stm32g431xx.h.

◆ I2C_CR2_NACK

#define I2C_CR2_NACK I2C_CR2_NACK_Msk

NACK generation (slave mode)

Definition at line 6092 of file stm32g431xx.h.

◆ I2C_CR2_NACK_Msk

#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos)

0x00008000

Definition at line 6091 of file stm32g431xx.h.

◆ I2C_CR2_NACK_Pos

#define I2C_CR2_NACK_Pos (15U)

Definition at line 6090 of file stm32g431xx.h.

◆ I2C_CR2_NBYTES

#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk

Number of bytes

Definition at line 6095 of file stm32g431xx.h.

◆ I2C_CR2_NBYTES_Msk

#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos)

0x00FF0000

Definition at line 6094 of file stm32g431xx.h.

◆ I2C_CR2_NBYTES_Pos

#define I2C_CR2_NBYTES_Pos (16U)

Definition at line 6093 of file stm32g431xx.h.

◆ I2C_CR2_PECBYTE

#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk

Packet error checking byte

Definition at line 6104 of file stm32g431xx.h.

◆ I2C_CR2_PECBYTE_Msk

#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos)

0x04000000

Definition at line 6103 of file stm32g431xx.h.

◆ I2C_CR2_PECBYTE_Pos

#define I2C_CR2_PECBYTE_Pos (26U)

Definition at line 6102 of file stm32g431xx.h.

◆ I2C_CR2_RD_WRN

#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk

Transfer direction (master mode)

Definition at line 6077 of file stm32g431xx.h.

◆ I2C_CR2_RD_WRN_Msk

#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos)

0x00000400

Definition at line 6076 of file stm32g431xx.h.

◆ I2C_CR2_RD_WRN_Pos

#define I2C_CR2_RD_WRN_Pos (10U)

Definition at line 6075 of file stm32g431xx.h.

◆ I2C_CR2_RELOAD

#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk

NBYTES reload mode

Definition at line 6098 of file stm32g431xx.h.

◆ I2C_CR2_RELOAD_Msk

#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos)

0x01000000

Definition at line 6097 of file stm32g431xx.h.

◆ I2C_CR2_RELOAD_Pos

#define I2C_CR2_RELOAD_Pos (24U)

Definition at line 6096 of file stm32g431xx.h.

◆ I2C_CR2_SADD

#define I2C_CR2_SADD I2C_CR2_SADD_Msk

Slave address (master mode)

Definition at line 6074 of file stm32g431xx.h.

◆ I2C_CR2_SADD_Msk

#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos)

0x000003FF

Definition at line 6073 of file stm32g431xx.h.

◆ I2C_CR2_SADD_Pos

#define I2C_CR2_SADD_Pos (0U)

Definition at line 6072 of file stm32g431xx.h.

◆ I2C_CR2_START

#define I2C_CR2_START I2C_CR2_START_Msk

START generation

Definition at line 6086 of file stm32g431xx.h.

◆ I2C_CR2_START_Msk

#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos)

0x00002000

Definition at line 6085 of file stm32g431xx.h.

◆ I2C_CR2_START_Pos

#define I2C_CR2_START_Pos (13U)

Definition at line 6084 of file stm32g431xx.h.

◆ I2C_CR2_STOP

#define I2C_CR2_STOP I2C_CR2_STOP_Msk

STOP generation (master mode)

Definition at line 6089 of file stm32g431xx.h.

◆ I2C_CR2_STOP_Msk

#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos)

0x00004000

Definition at line 6088 of file stm32g431xx.h.

◆ I2C_CR2_STOP_Pos

#define I2C_CR2_STOP_Pos (14U)

Definition at line 6087 of file stm32g431xx.h.

◆ I2C_ICR_ADDRCF

#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk

Address matched clear flag

Definition at line 6240 of file stm32g431xx.h.

◆ I2C_ICR_ADDRCF_Msk

#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos)

0x00000008

Definition at line 6239 of file stm32g431xx.h.

◆ I2C_ICR_ADDRCF_Pos

#define I2C_ICR_ADDRCF_Pos (3U)

Definition at line 6238 of file stm32g431xx.h.

◆ I2C_ICR_ALERTCF

#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk

Alert clear flag

Definition at line 6264 of file stm32g431xx.h.

◆ I2C_ICR_ALERTCF_Msk

#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos)

0x00002000

Definition at line 6263 of file stm32g431xx.h.

◆ I2C_ICR_ALERTCF_Pos

#define I2C_ICR_ALERTCF_Pos (13U)

Definition at line 6262 of file stm32g431xx.h.

◆ I2C_ICR_ARLOCF

#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk

Arbitration lost clear flag

Definition at line 6252 of file stm32g431xx.h.

◆ I2C_ICR_ARLOCF_Msk

#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos)

0x00000200

Definition at line 6251 of file stm32g431xx.h.

◆ I2C_ICR_ARLOCF_Pos

#define I2C_ICR_ARLOCF_Pos (9U)

Definition at line 6250 of file stm32g431xx.h.

◆ I2C_ICR_BERRCF

#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk

Bus error clear flag

Definition at line 6249 of file stm32g431xx.h.

◆ I2C_ICR_BERRCF_Msk

#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos)

0x00000100

Definition at line 6248 of file stm32g431xx.h.

◆ I2C_ICR_BERRCF_Pos

#define I2C_ICR_BERRCF_Pos (8U)

Definition at line 6247 of file stm32g431xx.h.

◆ I2C_ICR_NACKCF

#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk

NACK clear flag

Definition at line 6243 of file stm32g431xx.h.

◆ I2C_ICR_NACKCF_Msk

#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos)

0x00000010

Definition at line 6242 of file stm32g431xx.h.

◆ I2C_ICR_NACKCF_Pos

#define I2C_ICR_NACKCF_Pos (4U)

Definition at line 6241 of file stm32g431xx.h.

◆ I2C_ICR_OVRCF

#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk

Overrun/Underrun clear flag

Definition at line 6255 of file stm32g431xx.h.

◆ I2C_ICR_OVRCF_Msk

#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos)

0x00000400

Definition at line 6254 of file stm32g431xx.h.

◆ I2C_ICR_OVRCF_Pos

#define I2C_ICR_OVRCF_Pos (10U)

Definition at line 6253 of file stm32g431xx.h.

◆ I2C_ICR_PECCF

#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk

PAC error clear flag

Definition at line 6258 of file stm32g431xx.h.

◆ I2C_ICR_PECCF_Msk

#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos)

0x00000800

Definition at line 6257 of file stm32g431xx.h.

◆ I2C_ICR_PECCF_Pos

#define I2C_ICR_PECCF_Pos (11U)

Definition at line 6256 of file stm32g431xx.h.

◆ I2C_ICR_STOPCF

#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk

STOP detection clear flag

Definition at line 6246 of file stm32g431xx.h.

◆ I2C_ICR_STOPCF_Msk

#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos)

0x00000020

Definition at line 6245 of file stm32g431xx.h.

◆ I2C_ICR_STOPCF_Pos

#define I2C_ICR_STOPCF_Pos (5U)

Definition at line 6244 of file stm32g431xx.h.

◆ I2C_ICR_TIMOUTCF

#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk

Timeout clear flag

Definition at line 6261 of file stm32g431xx.h.

◆ I2C_ICR_TIMOUTCF_Msk

#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos)

0x00001000

Definition at line 6260 of file stm32g431xx.h.

◆ I2C_ICR_TIMOUTCF_Pos

#define I2C_ICR_TIMOUTCF_Pos (12U)

Definition at line 6259 of file stm32g431xx.h.

◆ I2C_ISR_ADDCODE

#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk

Address match code (slave mode)

Definition at line 6235 of file stm32g431xx.h.

◆ I2C_ISR_ADDCODE_Msk

#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos)

0x00FE0000

Definition at line 6234 of file stm32g431xx.h.

◆ I2C_ISR_ADDCODE_Pos

#define I2C_ISR_ADDCODE_Pos (17U)

Definition at line 6233 of file stm32g431xx.h.

◆ I2C_ISR_ADDR

#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk

Address matched (slave mode)

Definition at line 6196 of file stm32g431xx.h.

◆ I2C_ISR_ADDR_Msk

#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos)

0x00000008

Definition at line 6195 of file stm32g431xx.h.

◆ I2C_ISR_ADDR_Pos

#define I2C_ISR_ADDR_Pos (3U)

Definition at line 6194 of file stm32g431xx.h.

◆ I2C_ISR_ALERT

#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk

SMBus alert

Definition at line 6226 of file stm32g431xx.h.

◆ I2C_ISR_ALERT_Msk

#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos)

0x00002000

Definition at line 6225 of file stm32g431xx.h.

◆ I2C_ISR_ALERT_Pos

#define I2C_ISR_ALERT_Pos (13U)

Definition at line 6224 of file stm32g431xx.h.

◆ I2C_ISR_ARLO

#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk

Arbitration lost

Definition at line 6214 of file stm32g431xx.h.

◆ I2C_ISR_ARLO_Msk

#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos)

0x00000200

Definition at line 6213 of file stm32g431xx.h.

◆ I2C_ISR_ARLO_Pos

#define I2C_ISR_ARLO_Pos (9U)

Definition at line 6212 of file stm32g431xx.h.

◆ I2C_ISR_BERR

#define I2C_ISR_BERR I2C_ISR_BERR_Msk

Bus error

Definition at line 6211 of file stm32g431xx.h.

◆ I2C_ISR_BERR_Msk

#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos)

0x00000100

Definition at line 6210 of file stm32g431xx.h.

◆ I2C_ISR_BERR_Pos

#define I2C_ISR_BERR_Pos (8U)

Definition at line 6209 of file stm32g431xx.h.

◆ I2C_ISR_BUSY

#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk

Bus busy

Definition at line 6229 of file stm32g431xx.h.

◆ I2C_ISR_BUSY_Msk

#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos)

0x00008000

Definition at line 6228 of file stm32g431xx.h.

◆ I2C_ISR_BUSY_Pos

#define I2C_ISR_BUSY_Pos (15U)

Definition at line 6227 of file stm32g431xx.h.

◆ I2C_ISR_DIR

#define I2C_ISR_DIR I2C_ISR_DIR_Msk

Transfer direction (slave mode)

Definition at line 6232 of file stm32g431xx.h.

◆ I2C_ISR_DIR_Msk

#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos)

0x00010000

Definition at line 6231 of file stm32g431xx.h.

◆ I2C_ISR_DIR_Pos

#define I2C_ISR_DIR_Pos (16U)

Definition at line 6230 of file stm32g431xx.h.

◆ I2C_ISR_NACKF

#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk

NACK received flag

Definition at line 6199 of file stm32g431xx.h.

◆ I2C_ISR_NACKF_Msk

#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos)

0x00000010

Definition at line 6198 of file stm32g431xx.h.

◆ I2C_ISR_NACKF_Pos

#define I2C_ISR_NACKF_Pos (4U)

Definition at line 6197 of file stm32g431xx.h.

◆ I2C_ISR_OVR

#define I2C_ISR_OVR I2C_ISR_OVR_Msk

Overrun/Underrun

Definition at line 6217 of file stm32g431xx.h.

◆ I2C_ISR_OVR_Msk

#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos)

0x00000400

Definition at line 6216 of file stm32g431xx.h.

◆ I2C_ISR_OVR_Pos

#define I2C_ISR_OVR_Pos (10U)

Definition at line 6215 of file stm32g431xx.h.

◆ I2C_ISR_PECERR

#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk

PEC error in reception

Definition at line 6220 of file stm32g431xx.h.

◆ I2C_ISR_PECERR_Msk

#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos)

0x00000800

Definition at line 6219 of file stm32g431xx.h.

◆ I2C_ISR_PECERR_Pos

#define I2C_ISR_PECERR_Pos (11U)

Definition at line 6218 of file stm32g431xx.h.

◆ I2C_ISR_RXNE

#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk

Receive data register not empty

Definition at line 6193 of file stm32g431xx.h.

◆ I2C_ISR_RXNE_Msk

#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos)

0x00000004

Definition at line 6192 of file stm32g431xx.h.

◆ I2C_ISR_RXNE_Pos

#define I2C_ISR_RXNE_Pos (2U)

Definition at line 6191 of file stm32g431xx.h.

◆ I2C_ISR_STOPF

#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk

STOP detection flag

Definition at line 6202 of file stm32g431xx.h.

◆ I2C_ISR_STOPF_Msk

#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos)

0x00000020

Definition at line 6201 of file stm32g431xx.h.

◆ I2C_ISR_STOPF_Pos

#define I2C_ISR_STOPF_Pos (5U)

Definition at line 6200 of file stm32g431xx.h.

◆ I2C_ISR_TC

#define I2C_ISR_TC I2C_ISR_TC_Msk

Transfer complete (master mode)

Definition at line 6205 of file stm32g431xx.h.

◆ I2C_ISR_TC_Msk

#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos)

0x00000040

Definition at line 6204 of file stm32g431xx.h.

◆ I2C_ISR_TC_Pos

#define I2C_ISR_TC_Pos (6U)

Definition at line 6203 of file stm32g431xx.h.

◆ I2C_ISR_TCR

#define I2C_ISR_TCR I2C_ISR_TCR_Msk

Transfer complete reload

Definition at line 6208 of file stm32g431xx.h.

◆ I2C_ISR_TCR_Msk

#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos)

0x00000080

Definition at line 6207 of file stm32g431xx.h.

◆ I2C_ISR_TCR_Pos

#define I2C_ISR_TCR_Pos (7U)

Definition at line 6206 of file stm32g431xx.h.

◆ I2C_ISR_TIMEOUT

#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk

Timeout or Tlow detection flag

Definition at line 6223 of file stm32g431xx.h.

◆ I2C_ISR_TIMEOUT_Msk

#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos)

0x00001000

Definition at line 6222 of file stm32g431xx.h.

◆ I2C_ISR_TIMEOUT_Pos

#define I2C_ISR_TIMEOUT_Pos (12U)

Definition at line 6221 of file stm32g431xx.h.

◆ I2C_ISR_TXE

#define I2C_ISR_TXE I2C_ISR_TXE_Msk

Transmit data register empty

Definition at line 6187 of file stm32g431xx.h.

◆ I2C_ISR_TXE_Msk

#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos)

0x00000001

Definition at line 6186 of file stm32g431xx.h.

◆ I2C_ISR_TXE_Pos

#define I2C_ISR_TXE_Pos (0U)

Definition at line 6185 of file stm32g431xx.h.

◆ I2C_ISR_TXIS

#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk

Transmit interrupt status

Definition at line 6190 of file stm32g431xx.h.

◆ I2C_ISR_TXIS_Msk

#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos)

0x00000002

Definition at line 6189 of file stm32g431xx.h.

◆ I2C_ISR_TXIS_Pos

#define I2C_ISR_TXIS_Pos (1U)

Definition at line 6188 of file stm32g431xx.h.

◆ I2C_OAR1_OA1

#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk

Interface own address 1

Definition at line 6109 of file stm32g431xx.h.

◆ I2C_OAR1_OA1_Msk

#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos)

0x000003FF

Definition at line 6108 of file stm32g431xx.h.

◆ I2C_OAR1_OA1_Pos

#define I2C_OAR1_OA1_Pos (0U)

Definition at line 6107 of file stm32g431xx.h.

◆ I2C_OAR1_OA1EN

#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk

Own address 1 enable

Definition at line 6115 of file stm32g431xx.h.

◆ I2C_OAR1_OA1EN_Msk

#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos)

0x00008000

Definition at line 6114 of file stm32g431xx.h.

◆ I2C_OAR1_OA1EN_Pos

#define I2C_OAR1_OA1EN_Pos (15U)

Definition at line 6113 of file stm32g431xx.h.

◆ I2C_OAR1_OA1MODE

#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk

Own address 1 10-bit mode

Definition at line 6112 of file stm32g431xx.h.

◆ I2C_OAR1_OA1MODE_Msk

#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos)

0x00000400

Definition at line 6111 of file stm32g431xx.h.

◆ I2C_OAR1_OA1MODE_Pos

#define I2C_OAR1_OA1MODE_Pos (10U)

Definition at line 6110 of file stm32g431xx.h.

◆ I2C_OAR2_OA2

#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk

Interface own address 2

Definition at line 6120 of file stm32g431xx.h.

◆ I2C_OAR2_OA2_Msk

#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos)

0x000000FE

Definition at line 6119 of file stm32g431xx.h.

◆ I2C_OAR2_OA2_Pos

#define I2C_OAR2_OA2_Pos (1U)

Definition at line 6118 of file stm32g431xx.h.

◆ I2C_OAR2_OA2EN

#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk

Own address 2 enable

Definition at line 6148 of file stm32g431xx.h.

◆ I2C_OAR2_OA2EN_Msk

#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos)

0x00008000

Definition at line 6147 of file stm32g431xx.h.

◆ I2C_OAR2_OA2EN_Pos

#define I2C_OAR2_OA2EN_Pos (15U)

Definition at line 6146 of file stm32g431xx.h.

◆ I2C_OAR2_OA2MASK01

#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk

OA2[1] is masked, Only OA2[7:2] are compared

Definition at line 6127 of file stm32g431xx.h.

◆ I2C_OAR2_OA2MASK01_Msk

#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos)

0x00000100

Definition at line 6126 of file stm32g431xx.h.

◆ I2C_OAR2_OA2MASK01_Pos

#define I2C_OAR2_OA2MASK01_Pos (8U)

Definition at line 6125 of file stm32g431xx.h.

◆ I2C_OAR2_OA2MASK02

#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk

OA2[2:1] is masked, Only OA2[7:3] are compared

Definition at line 6130 of file stm32g431xx.h.

◆ I2C_OAR2_OA2MASK02_Msk

#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos)

0x00000200

Definition at line 6129 of file stm32g431xx.h.

◆ I2C_OAR2_OA2MASK02_Pos

#define I2C_OAR2_OA2MASK02_Pos (9U)

Definition at line 6128 of file stm32g431xx.h.

◆ I2C_OAR2_OA2MASK03

#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk

OA2[3:1] is masked, Only OA2[7:4] are compared

Definition at line 6133 of file stm32g431xx.h.

◆ I2C_OAR2_OA2MASK03_Msk

#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos)

0x00000300

Definition at line 6132 of file stm32g431xx.h.

◆ I2C_OAR2_OA2MASK03_Pos

#define I2C_OAR2_OA2MASK03_Pos (8U)

Definition at line 6131 of file stm32g431xx.h.

◆ I2C_OAR2_OA2MASK04

#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk

OA2[4:1] is masked, Only OA2[7:5] are compared

Definition at line 6136 of file stm32g431xx.h.

◆ I2C_OAR2_OA2MASK04_Msk

#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos)

0x00000400

Definition at line 6135 of file stm32g431xx.h.

◆ I2C_OAR2_OA2MASK04_Pos

#define I2C_OAR2_OA2MASK04_Pos (10U)

Definition at line 6134 of file stm32g431xx.h.

◆ I2C_OAR2_OA2MASK05

#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk

OA2[5:1] is masked, Only OA2[7:6] are compared

Definition at line 6139 of file stm32g431xx.h.

◆ I2C_OAR2_OA2MASK05_Msk

#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos)

0x00000500

Definition at line 6138 of file stm32g431xx.h.

◆ I2C_OAR2_OA2MASK05_Pos

#define I2C_OAR2_OA2MASK05_Pos (8U)

Definition at line 6137 of file stm32g431xx.h.

◆ I2C_OAR2_OA2MASK06

#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk

OA2[6:1] is masked, Only OA2[7] are compared

Definition at line 6142 of file stm32g431xx.h.

◆ I2C_OAR2_OA2MASK06_Msk

#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos)

0x00000600

Definition at line 6141 of file stm32g431xx.h.

◆ I2C_OAR2_OA2MASK06_Pos

#define I2C_OAR2_OA2MASK06_Pos (9U)

Definition at line 6140 of file stm32g431xx.h.

◆ I2C_OAR2_OA2MASK07

#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk

OA2[7:1] is masked, No comparison is done

Definition at line 6145 of file stm32g431xx.h.

◆ I2C_OAR2_OA2MASK07_Msk

#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos)

0x00000700

Definition at line 6144 of file stm32g431xx.h.

◆ I2C_OAR2_OA2MASK07_Pos

#define I2C_OAR2_OA2MASK07_Pos (8U)

Definition at line 6143 of file stm32g431xx.h.

◆ I2C_OAR2_OA2MSK

#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk

Own address 2 masks

Definition at line 6123 of file stm32g431xx.h.

◆ I2C_OAR2_OA2MSK_Msk

#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos)

0x00000700

Definition at line 6122 of file stm32g431xx.h.

◆ I2C_OAR2_OA2MSK_Pos

#define I2C_OAR2_OA2MSK_Pos (8U)

Definition at line 6121 of file stm32g431xx.h.

◆ I2C_OAR2_OA2NOMASK

#define I2C_OAR2_OA2NOMASK (0x00000000U)

No mask

Definition at line 6124 of file stm32g431xx.h.

◆ I2C_PECR_PEC

#define I2C_PECR_PEC I2C_PECR_PEC_Msk

PEC register

Definition at line 6269 of file stm32g431xx.h.

◆ I2C_PECR_PEC_Msk

#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos)

0x000000FF

Definition at line 6268 of file stm32g431xx.h.

◆ I2C_PECR_PEC_Pos

#define I2C_PECR_PEC_Pos (0U)

Definition at line 6267 of file stm32g431xx.h.

◆ I2C_RXDR_RXDATA

#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk

8-bit receive data

Definition at line 6274 of file stm32g431xx.h.

◆ I2C_RXDR_RXDATA_Msk

#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos)

0x000000FF

Definition at line 6273 of file stm32g431xx.h.

◆ I2C_RXDR_RXDATA_Pos

#define I2C_RXDR_RXDATA_Pos (0U)

Definition at line 6272 of file stm32g431xx.h.

◆ I2C_TIMEOUTR_TEXTEN

#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk

Extended clock timeout enable

Definition at line 6182 of file stm32g431xx.h.

◆ I2C_TIMEOUTR_TEXTEN_Msk

#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)

0x80000000

Definition at line 6181 of file stm32g431xx.h.

◆ I2C_TIMEOUTR_TEXTEN_Pos

#define I2C_TIMEOUTR_TEXTEN_Pos (31U)

Definition at line 6180 of file stm32g431xx.h.

◆ I2C_TIMEOUTR_TIDLE

#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk

Idle clock timeout detection

Definition at line 6173 of file stm32g431xx.h.

◆ I2C_TIMEOUTR_TIDLE_Msk

#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)

0x00001000

Definition at line 6172 of file stm32g431xx.h.

◆ I2C_TIMEOUTR_TIDLE_Pos

#define I2C_TIMEOUTR_TIDLE_Pos (12U)

Definition at line 6171 of file stm32g431xx.h.

◆ I2C_TIMEOUTR_TIMEOUTA

#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk

Bus timeout A

Definition at line 6170 of file stm32g431xx.h.

◆ I2C_TIMEOUTR_TIMEOUTA_Msk

#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)

0x00000FFF

Definition at line 6169 of file stm32g431xx.h.

◆ I2C_TIMEOUTR_TIMEOUTA_Pos

#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)

Definition at line 6168 of file stm32g431xx.h.

◆ I2C_TIMEOUTR_TIMEOUTB

#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk

Bus timeout B

Definition at line 6179 of file stm32g431xx.h.

◆ I2C_TIMEOUTR_TIMEOUTB_Msk

#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)

0x0FFF0000

Definition at line 6178 of file stm32g431xx.h.

◆ I2C_TIMEOUTR_TIMEOUTB_Pos

#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)

Definition at line 6177 of file stm32g431xx.h.

◆ I2C_TIMEOUTR_TIMOUTEN

#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk

Clock timeout enable

Definition at line 6176 of file stm32g431xx.h.

◆ I2C_TIMEOUTR_TIMOUTEN_Msk

#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)

0x00008000

Definition at line 6175 of file stm32g431xx.h.

◆ I2C_TIMEOUTR_TIMOUTEN_Pos

#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)

Definition at line 6174 of file stm32g431xx.h.

◆ I2C_TIMINGR_PRESC

#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk

Timings prescaler

Definition at line 6165 of file stm32g431xx.h.

◆ I2C_TIMINGR_PRESC_Msk

#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos)

0xF0000000

Definition at line 6164 of file stm32g431xx.h.

◆ I2C_TIMINGR_PRESC_Pos

#define I2C_TIMINGR_PRESC_Pos (28U)

Definition at line 6163 of file stm32g431xx.h.

◆ I2C_TIMINGR_SCLDEL

#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk

Data setup time

Definition at line 6162 of file stm32g431xx.h.

◆ I2C_TIMINGR_SCLDEL_Msk

#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos)

0x00F00000

Definition at line 6161 of file stm32g431xx.h.

◆ I2C_TIMINGR_SCLDEL_Pos

#define I2C_TIMINGR_SCLDEL_Pos (20U)

Definition at line 6160 of file stm32g431xx.h.

◆ I2C_TIMINGR_SCLH

#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk

SCL high period (master mode)

Definition at line 6156 of file stm32g431xx.h.

◆ I2C_TIMINGR_SCLH_Msk

#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos)

0x0000FF00

Definition at line 6155 of file stm32g431xx.h.

◆ I2C_TIMINGR_SCLH_Pos

#define I2C_TIMINGR_SCLH_Pos (8U)

Definition at line 6154 of file stm32g431xx.h.

◆ I2C_TIMINGR_SCLL

#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk

SCL low period (master mode)

Definition at line 6153 of file stm32g431xx.h.

◆ I2C_TIMINGR_SCLL_Msk

#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos)

0x000000FF

Definition at line 6152 of file stm32g431xx.h.

◆ I2C_TIMINGR_SCLL_Pos

#define I2C_TIMINGR_SCLL_Pos (0U)

Definition at line 6151 of file stm32g431xx.h.

◆ I2C_TIMINGR_SDADEL

#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk

Data hold time

Definition at line 6159 of file stm32g431xx.h.

◆ I2C_TIMINGR_SDADEL_Msk

#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos)

0x000F0000

Definition at line 6158 of file stm32g431xx.h.

◆ I2C_TIMINGR_SDADEL_Pos

#define I2C_TIMINGR_SDADEL_Pos (16U)

Definition at line 6157 of file stm32g431xx.h.

◆ I2C_TXDR_TXDATA

#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk

8-bit transmit data

Definition at line 6279 of file stm32g431xx.h.

◆ I2C_TXDR_TXDATA_Msk

#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos)

0x000000FF

Definition at line 6278 of file stm32g431xx.h.

◆ I2C_TXDR_TXDATA_Pos

#define I2C_TXDR_TXDATA_Pos (0U)

Definition at line 6277 of file stm32g431xx.h.

◆ IWDG_KR_KEY

#define IWDG_KR_KEY IWDG_KR_KEY_Msk

Key value (write only, read 0000h)

Definition at line 6289 of file stm32g431xx.h.

◆ IWDG_KR_KEY_Msk

#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos)

0x0000FFFF

Definition at line 6288 of file stm32g431xx.h.

◆ IWDG_KR_KEY_Pos

#define IWDG_KR_KEY_Pos (0U)

Definition at line 6287 of file stm32g431xx.h.

◆ IWDG_PR_PR

#define IWDG_PR_PR IWDG_PR_PR_Msk

PR[2:0] (Prescaler divider)

Definition at line 6294 of file stm32g431xx.h.

◆ IWDG_PR_PR_0

#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos)

0x00000001

Definition at line 6295 of file stm32g431xx.h.

◆ IWDG_PR_PR_1

#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos)

0x00000002

Definition at line 6296 of file stm32g431xx.h.

◆ IWDG_PR_PR_2

#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos)

0x00000004

Definition at line 6297 of file stm32g431xx.h.

◆ IWDG_PR_PR_Msk

#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos)

0x00000007

Definition at line 6293 of file stm32g431xx.h.

◆ IWDG_PR_PR_Pos

#define IWDG_PR_PR_Pos (0U)

Definition at line 6292 of file stm32g431xx.h.

◆ IWDG_RLR_RL

#define IWDG_RLR_RL IWDG_RLR_RL_Msk

Watchdog counter reload value

Definition at line 6302 of file stm32g431xx.h.

◆ IWDG_RLR_RL_Msk

#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos)

0x00000FFF

Definition at line 6301 of file stm32g431xx.h.

◆ IWDG_RLR_RL_Pos

#define IWDG_RLR_RL_Pos (0U)

Definition at line 6300 of file stm32g431xx.h.

◆ IWDG_SR_PVU

#define IWDG_SR_PVU IWDG_SR_PVU_Msk

Watchdog prescaler value update

Definition at line 6307 of file stm32g431xx.h.

◆ IWDG_SR_PVU_Msk

#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos)

0x00000001

Definition at line 6306 of file stm32g431xx.h.

◆ IWDG_SR_PVU_Pos

#define IWDG_SR_PVU_Pos (0U)

Definition at line 6305 of file stm32g431xx.h.

◆ IWDG_SR_RVU

#define IWDG_SR_RVU IWDG_SR_RVU_Msk

Watchdog counter reload value update

Definition at line 6310 of file stm32g431xx.h.

◆ IWDG_SR_RVU_Msk

#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos)

0x00000002

Definition at line 6309 of file stm32g431xx.h.

◆ IWDG_SR_RVU_Pos

#define IWDG_SR_RVU_Pos (1U)

Definition at line 6308 of file stm32g431xx.h.

◆ IWDG_SR_WVU

#define IWDG_SR_WVU IWDG_SR_WVU_Msk

Watchdog counter window value update

Definition at line 6313 of file stm32g431xx.h.

◆ IWDG_SR_WVU_Msk

#define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos)

0x00000004

Definition at line 6312 of file stm32g431xx.h.

◆ IWDG_SR_WVU_Pos

#define IWDG_SR_WVU_Pos (2U)

Definition at line 6311 of file stm32g431xx.h.

◆ IWDG_WINR_WIN

#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk

Watchdog counter window value

Definition at line 6318 of file stm32g431xx.h.

◆ IWDG_WINR_WIN_Msk

#define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos)

0x00000FFF

Definition at line 6317 of file stm32g431xx.h.

◆ IWDG_WINR_WIN_Pos

#define IWDG_WINR_WIN_Pos (0U)

Definition at line 6316 of file stm32g431xx.h.

◆ LPTIM_ARR_ARR

#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk

Auto reload register

Definition at line 11009 of file stm32g431xx.h.

◆ LPTIM_ARR_ARR_Msk

#define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos)

0x0000FFFF

Definition at line 11008 of file stm32g431xx.h.

◆ LPTIM_ARR_ARR_Pos

#define LPTIM_ARR_ARR_Pos (0U)

Definition at line 11007 of file stm32g431xx.h.

◆ LPTIM_CFGR_CKFLT

#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk

CKFLT[1:0] bits (Configurable digital filter for external clock)

Definition at line 10934 of file stm32g431xx.h.

◆ LPTIM_CFGR_CKFLT_0

#define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos)

0x00000008

Definition at line 10935 of file stm32g431xx.h.

◆ LPTIM_CFGR_CKFLT_1

#define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos)

0x00000010

Definition at line 10936 of file stm32g431xx.h.

◆ LPTIM_CFGR_CKFLT_Msk

#define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos)

0x00000018

Definition at line 10933 of file stm32g431xx.h.

◆ LPTIM_CFGR_CKFLT_Pos

#define LPTIM_CFGR_CKFLT_Pos (3U)

Definition at line 10932 of file stm32g431xx.h.

◆ LPTIM_CFGR_CKPOL

#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk

CKPOL[1:0] bits (Clock polarity)

Definition at line 10928 of file stm32g431xx.h.

◆ LPTIM_CFGR_CKPOL_0

#define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos)

0x00000002

Definition at line 10929 of file stm32g431xx.h.

◆ LPTIM_CFGR_CKPOL_1

#define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos)

0x00000004

Definition at line 10930 of file stm32g431xx.h.

◆ LPTIM_CFGR_CKPOL_Msk

#define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos)

0x00000006

Definition at line 10927 of file stm32g431xx.h.

◆ LPTIM_CFGR_CKPOL_Pos

#define LPTIM_CFGR_CKPOL_Pos (1U)

Definition at line 10926 of file stm32g431xx.h.

◆ LPTIM_CFGR_CKSEL

#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk

Clock selector

Definition at line 10924 of file stm32g431xx.h.

◆ LPTIM_CFGR_CKSEL_Msk

#define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos)

0x00000001

Definition at line 10923 of file stm32g431xx.h.

◆ LPTIM_CFGR_CKSEL_Pos

#define LPTIM_CFGR_CKSEL_Pos (0U)

Definition at line 10922 of file stm32g431xx.h.

◆ LPTIM_CFGR_COUNTMODE

#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk

Counter mode enable

Definition at line 10979 of file stm32g431xx.h.

◆ LPTIM_CFGR_COUNTMODE_Msk

#define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)

0x00800000

Definition at line 10978 of file stm32g431xx.h.

◆ LPTIM_CFGR_COUNTMODE_Pos

#define LPTIM_CFGR_COUNTMODE_Pos (23U)

Definition at line 10977 of file stm32g431xx.h.

◆ LPTIM_CFGR_ENC

#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk

Encoder mode enable

Definition at line 10982 of file stm32g431xx.h.

◆ LPTIM_CFGR_ENC_Msk

#define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos)

0x01000000

Definition at line 10981 of file stm32g431xx.h.

◆ LPTIM_CFGR_ENC_Pos

#define LPTIM_CFGR_ENC_Pos (24U)

Definition at line 10980 of file stm32g431xx.h.

◆ LPTIM_CFGR_PRELOAD

#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk

Reg update mode

Definition at line 10976 of file stm32g431xx.h.

◆ LPTIM_CFGR_PRELOAD_Msk

#define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos)

0x00400000

Definition at line 10975 of file stm32g431xx.h.

◆ LPTIM_CFGR_PRELOAD_Pos

#define LPTIM_CFGR_PRELOAD_Pos (22U)

Definition at line 10974 of file stm32g431xx.h.

◆ LPTIM_CFGR_PRESC

#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk

PRESC[2:0] bits (Clock prescaler)

Definition at line 10946 of file stm32g431xx.h.

◆ LPTIM_CFGR_PRESC_0

#define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos)

0x00000200

Definition at line 10947 of file stm32g431xx.h.

◆ LPTIM_CFGR_PRESC_1

#define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos)

0x00000400

Definition at line 10948 of file stm32g431xx.h.

◆ LPTIM_CFGR_PRESC_2

#define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos)

0x00000800

Definition at line 10949 of file stm32g431xx.h.

◆ LPTIM_CFGR_PRESC_Msk

#define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos)

0x00000E00

Definition at line 10945 of file stm32g431xx.h.

◆ LPTIM_CFGR_PRESC_Pos

#define LPTIM_CFGR_PRESC_Pos (9U)

Definition at line 10944 of file stm32g431xx.h.

◆ LPTIM_CFGR_TIMOUT

#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk

Timout enable

Definition at line 10967 of file stm32g431xx.h.

◆ LPTIM_CFGR_TIMOUT_Msk

#define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos)

0x00080000

Definition at line 10966 of file stm32g431xx.h.

◆ LPTIM_CFGR_TIMOUT_Pos

#define LPTIM_CFGR_TIMOUT_Pos (19U)

Definition at line 10965 of file stm32g431xx.h.

◆ LPTIM_CFGR_TRGFLT

#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk

TRGFLT[1:0] bits (Configurable digital filter for trigger)

Definition at line 10940 of file stm32g431xx.h.

◆ LPTIM_CFGR_TRGFLT_0

#define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos)

0x00000040

Definition at line 10941 of file stm32g431xx.h.

◆ LPTIM_CFGR_TRGFLT_1

#define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos)

0x00000080

Definition at line 10942 of file stm32g431xx.h.

◆ LPTIM_CFGR_TRGFLT_Msk

#define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos)

0x000000C0

Definition at line 10939 of file stm32g431xx.h.

◆ LPTIM_CFGR_TRGFLT_Pos

#define LPTIM_CFGR_TRGFLT_Pos (6U)

Definition at line 10938 of file stm32g431xx.h.

◆ LPTIM_CFGR_TRIGEN

#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk

TRIGEN[1:0] bits (Trigger enable and polarity)

Definition at line 10961 of file stm32g431xx.h.

◆ LPTIM_CFGR_TRIGEN_0

#define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos)

0x00020000

Definition at line 10962 of file stm32g431xx.h.

◆ LPTIM_CFGR_TRIGEN_1

#define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos)

0x00040000

Definition at line 10963 of file stm32g431xx.h.

◆ LPTIM_CFGR_TRIGEN_Msk

#define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos)

0x00060000

Definition at line 10960 of file stm32g431xx.h.

◆ LPTIM_CFGR_TRIGEN_Pos

#define LPTIM_CFGR_TRIGEN_Pos (17U)

Definition at line 10959 of file stm32g431xx.h.

◆ LPTIM_CFGR_TRIGSEL

#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk

TRIGSEL[2:0]] bits (Trigger selector)

Definition at line 10953 of file stm32g431xx.h.

◆ LPTIM_CFGR_TRIGSEL_0

#define LPTIM_CFGR_TRIGSEL_0 (0x00001UL << LPTIM_CFGR_TRIGSEL_Pos)

0x00002000

Definition at line 10954 of file stm32g431xx.h.

◆ LPTIM_CFGR_TRIGSEL_1

#define LPTIM_CFGR_TRIGSEL_1 (0x00002UL << LPTIM_CFGR_TRIGSEL_Pos)

0x00004000

Definition at line 10955 of file stm32g431xx.h.

◆ LPTIM_CFGR_TRIGSEL_2

#define LPTIM_CFGR_TRIGSEL_2 (0x00004UL << LPTIM_CFGR_TRIGSEL_Pos)

0x00008000

Definition at line 10956 of file stm32g431xx.h.

◆ LPTIM_CFGR_TRIGSEL_3

#define LPTIM_CFGR_TRIGSEL_3 (0x10000UL << LPTIM_CFGR_TRIGSEL_Pos)

0x02000000

Definition at line 10957 of file stm32g431xx.h.

◆ LPTIM_CFGR_TRIGSEL_Msk

#define LPTIM_CFGR_TRIGSEL_Msk (0x10007UL << LPTIM_CFGR_TRIGSEL_Pos)

0x0200E000

Definition at line 10952 of file stm32g431xx.h.

◆ LPTIM_CFGR_TRIGSEL_Pos

#define LPTIM_CFGR_TRIGSEL_Pos (13U)

Definition at line 10951 of file stm32g431xx.h.

◆ LPTIM_CFGR_WAVE

#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk

Waveform shape

Definition at line 10970 of file stm32g431xx.h.

◆ LPTIM_CFGR_WAVE_Msk

#define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos)

0x00100000

Definition at line 10969 of file stm32g431xx.h.

◆ LPTIM_CFGR_WAVE_Pos

#define LPTIM_CFGR_WAVE_Pos (20U)

Definition at line 10968 of file stm32g431xx.h.

◆ LPTIM_CFGR_WAVPOL

#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk

Waveform shape polarity

Definition at line 10973 of file stm32g431xx.h.

◆ LPTIM_CFGR_WAVPOL_Msk

#define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos)

0x00200000

Definition at line 10972 of file stm32g431xx.h.

◆ LPTIM_CFGR_WAVPOL_Pos

#define LPTIM_CFGR_WAVPOL_Pos (21U)

Definition at line 10971 of file stm32g431xx.h.

◆ LPTIM_CMP_CMP

#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk

Compare register

Definition at line 11004 of file stm32g431xx.h.

◆ LPTIM_CMP_CMP_Msk

#define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos)

0x0000FFFF

Definition at line 11003 of file stm32g431xx.h.

◆ LPTIM_CMP_CMP_Pos

#define LPTIM_CMP_CMP_Pos (0U)

Definition at line 11002 of file stm32g431xx.h.

◆ LPTIM_CNT_CNT

#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk

Counter register

Definition at line 11014 of file stm32g431xx.h.

◆ LPTIM_CNT_CNT_Msk

#define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos)

0x0000FFFF

Definition at line 11013 of file stm32g431xx.h.

◆ LPTIM_CNT_CNT_Pos

#define LPTIM_CNT_CNT_Pos (0U)

Definition at line 11012 of file stm32g431xx.h.

◆ LPTIM_CR_CNTSTRT

#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk

Timer start in continuous mode

Definition at line 10993 of file stm32g431xx.h.

◆ LPTIM_CR_CNTSTRT_Msk

#define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos)

0x00000004

Definition at line 10992 of file stm32g431xx.h.

◆ LPTIM_CR_CNTSTRT_Pos

#define LPTIM_CR_CNTSTRT_Pos (2U)

Definition at line 10991 of file stm32g431xx.h.

◆ LPTIM_CR_COUNTRST

#define LPTIM_CR_COUNTRST LPTIM_CR_COUNTRST_Msk

Counter reset

Definition at line 10996 of file stm32g431xx.h.

◆ LPTIM_CR_COUNTRST_Msk

#define LPTIM_CR_COUNTRST_Msk (0x1UL << LPTIM_CR_COUNTRST_Pos)

0x00000008

Definition at line 10995 of file stm32g431xx.h.

◆ LPTIM_CR_COUNTRST_Pos

#define LPTIM_CR_COUNTRST_Pos (3U)

Definition at line 10994 of file stm32g431xx.h.

◆ LPTIM_CR_ENABLE

#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk

LPTIMer enable

Definition at line 10987 of file stm32g431xx.h.

◆ LPTIM_CR_ENABLE_Msk

#define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos)

0x00000001

Definition at line 10986 of file stm32g431xx.h.

◆ LPTIM_CR_ENABLE_Pos

#define LPTIM_CR_ENABLE_Pos (0U)

Definition at line 10985 of file stm32g431xx.h.

◆ LPTIM_CR_RSTARE

#define LPTIM_CR_RSTARE LPTIM_CR_RSTARE_Msk

Reset after read enable

Definition at line 10999 of file stm32g431xx.h.

◆ LPTIM_CR_RSTARE_Msk

#define LPTIM_CR_RSTARE_Msk (0x1UL << LPTIM_CR_RSTARE_Pos)

0x00000010

Definition at line 10998 of file stm32g431xx.h.

◆ LPTIM_CR_RSTARE_Pos

#define LPTIM_CR_RSTARE_Pos (4U)

Definition at line 10997 of file stm32g431xx.h.

◆ LPTIM_CR_SNGSTRT

#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk

Timer start in single mode

Definition at line 10990 of file stm32g431xx.h.

◆ LPTIM_CR_SNGSTRT_Msk

#define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos)

0x00000002

Definition at line 10989 of file stm32g431xx.h.

◆ LPTIM_CR_SNGSTRT_Pos

#define LPTIM_CR_SNGSTRT_Pos (1U)

Definition at line 10988 of file stm32g431xx.h.

◆ LPTIM_ICR_ARRMCF

#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk

Autoreload match Clear Flag

Definition at line 10881 of file stm32g431xx.h.

◆ LPTIM_ICR_ARRMCF_Msk

#define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos)

0x00000002

Definition at line 10880 of file stm32g431xx.h.

◆ LPTIM_ICR_ARRMCF_Pos

#define LPTIM_ICR_ARRMCF_Pos (1U)

Definition at line 10879 of file stm32g431xx.h.

◆ LPTIM_ICR_ARROKCF

#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk

Autoreload register update OK Clear Flag

Definition at line 10890 of file stm32g431xx.h.

◆ LPTIM_ICR_ARROKCF_Msk

#define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos)

0x00000010

Definition at line 10889 of file stm32g431xx.h.

◆ LPTIM_ICR_ARROKCF_Pos

#define LPTIM_ICR_ARROKCF_Pos (4U)

Definition at line 10888 of file stm32g431xx.h.

◆ LPTIM_ICR_CMPMCF

#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk

Compare match Clear Flag

Definition at line 10878 of file stm32g431xx.h.

◆ LPTIM_ICR_CMPMCF_Msk

#define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos)

0x00000001

Definition at line 10877 of file stm32g431xx.h.

◆ LPTIM_ICR_CMPMCF_Pos

#define LPTIM_ICR_CMPMCF_Pos (0U)

Definition at line 10876 of file stm32g431xx.h.

◆ LPTIM_ICR_CMPOKCF

#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk

Compare register update OK Clear Flag

Definition at line 10887 of file stm32g431xx.h.

◆ LPTIM_ICR_CMPOKCF_Msk

#define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos)

0x00000008

Definition at line 10886 of file stm32g431xx.h.

◆ LPTIM_ICR_CMPOKCF_Pos

#define LPTIM_ICR_CMPOKCF_Pos (3U)

Definition at line 10885 of file stm32g431xx.h.

◆ LPTIM_ICR_DOWNCF

#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk

Counter direction change up to down Clear Flag

Definition at line 10896 of file stm32g431xx.h.

◆ LPTIM_ICR_DOWNCF_Msk

#define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos)

0x00000040

Definition at line 10895 of file stm32g431xx.h.

◆ LPTIM_ICR_DOWNCF_Pos

#define LPTIM_ICR_DOWNCF_Pos (6U)

Definition at line 10894 of file stm32g431xx.h.

◆ LPTIM_ICR_EXTTRIGCF

#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk

External trigger edge event Clear Flag

Definition at line 10884 of file stm32g431xx.h.

◆ LPTIM_ICR_EXTTRIGCF_Msk

#define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)

0x00000004

Definition at line 10883 of file stm32g431xx.h.

◆ LPTIM_ICR_EXTTRIGCF_Pos

#define LPTIM_ICR_EXTTRIGCF_Pos (2U)

Definition at line 10882 of file stm32g431xx.h.

◆ LPTIM_ICR_UPCF

#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk

Counter direction change down to up Clear Flag

Definition at line 10893 of file stm32g431xx.h.

◆ LPTIM_ICR_UPCF_Msk

#define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos)

0x00000020

Definition at line 10892 of file stm32g431xx.h.

◆ LPTIM_ICR_UPCF_Pos

#define LPTIM_ICR_UPCF_Pos (5U)

Definition at line 10891 of file stm32g431xx.h.

◆ LPTIM_IER_ARRMIE

#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk

Autoreload match Interrupt Enable

Definition at line 10904 of file stm32g431xx.h.

◆ LPTIM_IER_ARRMIE_Msk

#define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos)

0x00000002

Definition at line 10903 of file stm32g431xx.h.

◆ LPTIM_IER_ARRMIE_Pos

#define LPTIM_IER_ARRMIE_Pos (1U)

Definition at line 10902 of file stm32g431xx.h.

◆ LPTIM_IER_ARROKIE

#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk

Autoreload register update OK Interrupt Enable

Definition at line 10913 of file stm32g431xx.h.

◆ LPTIM_IER_ARROKIE_Msk

#define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos)

0x00000010

Definition at line 10912 of file stm32g431xx.h.

◆ LPTIM_IER_ARROKIE_Pos

#define LPTIM_IER_ARROKIE_Pos (4U)

Definition at line 10911 of file stm32g431xx.h.

◆ LPTIM_IER_CMPMIE

#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk

Compare match Interrupt Enable

Definition at line 10901 of file stm32g431xx.h.

◆ LPTIM_IER_CMPMIE_Msk

#define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos)

0x00000001

Definition at line 10900 of file stm32g431xx.h.

◆ LPTIM_IER_CMPMIE_Pos

#define LPTIM_IER_CMPMIE_Pos (0U)

Definition at line 10899 of file stm32g431xx.h.

◆ LPTIM_IER_CMPOKIE

#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk

Compare register update OK Interrupt Enable

Definition at line 10910 of file stm32g431xx.h.

◆ LPTIM_IER_CMPOKIE_Msk

#define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos)

0x00000008

Definition at line 10909 of file stm32g431xx.h.

◆ LPTIM_IER_CMPOKIE_Pos

#define LPTIM_IER_CMPOKIE_Pos (3U)

Definition at line 10908 of file stm32g431xx.h.

◆ LPTIM_IER_DOWNIE

#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk

Counter direction change up to down Interrupt Enable

Definition at line 10919 of file stm32g431xx.h.

◆ LPTIM_IER_DOWNIE_Msk

#define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos)

0x00000040

Definition at line 10918 of file stm32g431xx.h.

◆ LPTIM_IER_DOWNIE_Pos

#define LPTIM_IER_DOWNIE_Pos (6U)

Definition at line 10917 of file stm32g431xx.h.

◆ LPTIM_IER_EXTTRIGIE

#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk

External trigger edge event Interrupt Enable

Definition at line 10907 of file stm32g431xx.h.

◆ LPTIM_IER_EXTTRIGIE_Msk

#define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)

0x00000004

Definition at line 10906 of file stm32g431xx.h.

◆ LPTIM_IER_EXTTRIGIE_Pos

#define LPTIM_IER_EXTTRIGIE_Pos (2U)

Definition at line 10905 of file stm32g431xx.h.

◆ LPTIM_IER_UPIE

#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk

Counter direction change down to up Interrupt Enable

Definition at line 10916 of file stm32g431xx.h.

◆ LPTIM_IER_UPIE_Msk

#define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos)

0x00000020

Definition at line 10915 of file stm32g431xx.h.

◆ LPTIM_IER_UPIE_Pos

#define LPTIM_IER_UPIE_Pos (5U)

Definition at line 10914 of file stm32g431xx.h.

◆ LPTIM_ISR_ARRM

#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk

Autoreload match

Definition at line 10858 of file stm32g431xx.h.

◆ LPTIM_ISR_ARRM_Msk

#define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos)

0x00000002

Definition at line 10857 of file stm32g431xx.h.

◆ LPTIM_ISR_ARRM_Pos

#define LPTIM_ISR_ARRM_Pos (1U)

Definition at line 10856 of file stm32g431xx.h.

◆ LPTIM_ISR_ARROK

#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk

Autoreload register update OK

Definition at line 10867 of file stm32g431xx.h.

◆ LPTIM_ISR_ARROK_Msk

#define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos)

0x00000010

Definition at line 10866 of file stm32g431xx.h.

◆ LPTIM_ISR_ARROK_Pos

#define LPTIM_ISR_ARROK_Pos (4U)

Definition at line 10865 of file stm32g431xx.h.

◆ LPTIM_ISR_CMPM

#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk

Compare match

Definition at line 10855 of file stm32g431xx.h.

◆ LPTIM_ISR_CMPM_Msk

#define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos)

0x00000001

Definition at line 10854 of file stm32g431xx.h.

◆ LPTIM_ISR_CMPM_Pos

#define LPTIM_ISR_CMPM_Pos (0U)

Definition at line 10853 of file stm32g431xx.h.

◆ LPTIM_ISR_CMPOK

#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk

Compare register update OK

Definition at line 10864 of file stm32g431xx.h.

◆ LPTIM_ISR_CMPOK_Msk

#define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos)

0x00000008

Definition at line 10863 of file stm32g431xx.h.

◆ LPTIM_ISR_CMPOK_Pos

#define LPTIM_ISR_CMPOK_Pos (3U)

Definition at line 10862 of file stm32g431xx.h.

◆ LPTIM_ISR_DOWN

#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk

Counter direction change up to down

Definition at line 10873 of file stm32g431xx.h.

◆ LPTIM_ISR_DOWN_Msk

#define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos)

0x00000040

Definition at line 10872 of file stm32g431xx.h.

◆ LPTIM_ISR_DOWN_Pos

#define LPTIM_ISR_DOWN_Pos (6U)

Definition at line 10871 of file stm32g431xx.h.

◆ LPTIM_ISR_EXTTRIG

#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk

External trigger edge event

Definition at line 10861 of file stm32g431xx.h.

◆ LPTIM_ISR_EXTTRIG_Msk

#define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos)

0x00000004

Definition at line 10860 of file stm32g431xx.h.

◆ LPTIM_ISR_EXTTRIG_Pos

#define LPTIM_ISR_EXTTRIG_Pos (2U)

Definition at line 10859 of file stm32g431xx.h.

◆ LPTIM_ISR_UP

#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk

Counter direction change down to up

Definition at line 10870 of file stm32g431xx.h.

◆ LPTIM_ISR_UP_Msk

#define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos)

0x00000020

Definition at line 10869 of file stm32g431xx.h.

◆ LPTIM_ISR_UP_Pos

#define LPTIM_ISR_UP_Pos (5U)

Definition at line 10868 of file stm32g431xx.h.

◆ LPTIM_OR_IN1

#define LPTIM_OR_IN1 LPTIM_OR_IN1_Msk

IN1[2:0] bits (Remap selection)

Definition at line 11019 of file stm32g431xx.h.

◆ LPTIM_OR_IN1_0

#define LPTIM_OR_IN1_0 (0x1UL << LPTIM_OR_IN1_Pos)

0x00000001

Definition at line 11020 of file stm32g431xx.h.

◆ LPTIM_OR_IN1_1

#define LPTIM_OR_IN1_1 (0x4UL << LPTIM_OR_IN1_Pos)

0x00000004

Definition at line 11021 of file stm32g431xx.h.

◆ LPTIM_OR_IN1_2

#define LPTIM_OR_IN1_2 (0x8UL << LPTIM_OR_IN1_Pos)

0x00000008

Definition at line 11022 of file stm32g431xx.h.

◆ LPTIM_OR_IN1_Msk

#define LPTIM_OR_IN1_Msk (0xDUL << LPTIM_OR_IN1_Pos)

0x0000000D

Definition at line 11018 of file stm32g431xx.h.

◆ LPTIM_OR_IN1_Pos

#define LPTIM_OR_IN1_Pos (0U)

Definition at line 11017 of file stm32g431xx.h.

◆ LPTIM_OR_IN2

#define LPTIM_OR_IN2 LPTIM_OR_IN2_Msk

IN2[2:0] bits (Remap selection)

Definition at line 11026 of file stm32g431xx.h.

◆ LPTIM_OR_IN2_0

#define LPTIM_OR_IN2_0 (0x1UL << LPTIM_OR_IN2_Pos)

0x00000002

Definition at line 11027 of file stm32g431xx.h.

◆ LPTIM_OR_IN2_1

#define LPTIM_OR_IN2_1 (0x8UL << LPTIM_OR_IN2_Pos)

0x00000010

Definition at line 11028 of file stm32g431xx.h.

◆ LPTIM_OR_IN2_2

#define LPTIM_OR_IN2_2 (0x10UL << LPTIM_OR_IN2_Pos)

0x00000020

Definition at line 11029 of file stm32g431xx.h.

◆ LPTIM_OR_IN2_Msk

#define LPTIM_OR_IN2_Msk (0x19UL << LPTIM_OR_IN2_Pos)

0x00000032

Definition at line 11025 of file stm32g431xx.h.

◆ LPTIM_OR_IN2_Pos

#define LPTIM_OR_IN2_Pos (1U)

Definition at line 11024 of file stm32g431xx.h.

◆ OPAMP_CSR_CALON

#define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk

Calibration mode enable

Definition at line 6353 of file stm32g431xx.h.

◆ OPAMP_CSR_CALON_Msk

#define OPAMP_CSR_CALON_Msk (0x1UL << OPAMP_CSR_CALON_Pos)

0x00000800

Definition at line 6352 of file stm32g431xx.h.

◆ OPAMP_CSR_CALON_Pos

#define OPAMP_CSR_CALON_Pos (11U)

Definition at line 6351 of file stm32g431xx.h.

◆ OPAMP_CSR_CALSEL

#define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk

Calibration selection

Definition at line 6356 of file stm32g431xx.h.

◆ OPAMP_CSR_CALSEL_0

#define OPAMP_CSR_CALSEL_0 (0x1UL << OPAMP_CSR_CALSEL_Pos)

0x00001000

Definition at line 6357 of file stm32g431xx.h.

◆ OPAMP_CSR_CALSEL_1

#define OPAMP_CSR_CALSEL_1 (0x2UL << OPAMP_CSR_CALSEL_Pos)

0x00002000

Definition at line 6358 of file stm32g431xx.h.

◆ OPAMP_CSR_CALSEL_Msk

#define OPAMP_CSR_CALSEL_Msk (0x3UL << OPAMP_CSR_CALSEL_Pos)

0x00003000

Definition at line 6355 of file stm32g431xx.h.

◆ OPAMP_CSR_CALSEL_Pos

#define OPAMP_CSR_CALSEL_Pos (12U)

Definition at line 6354 of file stm32g431xx.h.

◆ OPAMP_CSR_FORCEVP

#define OPAMP_CSR_FORCEVP OPAMP_CSR_FORCEVP_Msk

Connect the internal references to the plus input of the OPAMPX

Definition at line 6331 of file stm32g431xx.h.

◆ OPAMP_CSR_FORCEVP_Msk

#define OPAMP_CSR_FORCEVP_Msk (0x1UL << OPAMP_CSR_FORCEVP_Pos)

0x00000002

Definition at line 6330 of file stm32g431xx.h.

◆ OPAMP_CSR_FORCEVP_Pos

#define OPAMP_CSR_FORCEVP_Pos (1U)

Definition at line 6329 of file stm32g431xx.h.

◆ OPAMP_CSR_HIGHSPEEDEN

#define OPAMP_CSR_HIGHSPEEDEN OPAMP_CSR_HIGHSPEEDEN_Msk

High speed mode enable

Definition at line 6347 of file stm32g431xx.h.

◆ OPAMP_CSR_HIGHSPEEDEN_Msk

#define OPAMP_CSR_HIGHSPEEDEN_Msk (0x1UL << OPAMP_CSR_HIGHSPEEDEN_Pos)

0x00000080

Definition at line 6346 of file stm32g431xx.h.

◆ OPAMP_CSR_HIGHSPEEDEN_Pos

#define OPAMP_CSR_HIGHSPEEDEN_Pos (7U)

Definition at line 6345 of file stm32g431xx.h.

◆ OPAMP_CSR_LOCK

#define OPAMP_CSR_LOCK OPAMP_CSR_LOCK_Msk

OPAMP control/status register lock

Definition at line 6378 of file stm32g431xx.h.

◆ OPAMP_CSR_LOCK_Msk

#define OPAMP_CSR_LOCK_Msk (0x1UL << OPAMP_CSR_LOCK_Pos)

0x80000000

Definition at line 6377 of file stm32g431xx.h.

◆ OPAMP_CSR_LOCK_Pos

#define OPAMP_CSR_LOCK_Pos (31U)

Definition at line 6376 of file stm32g431xx.h.

◆ OPAMP_CSR_OPAMPINTEN

#define OPAMP_CSR_OPAMPINTEN OPAMP_CSR_OPAMPINTEN_Msk

Internal output enable

Definition at line 6350 of file stm32g431xx.h.

◆ OPAMP_CSR_OPAMPINTEN_Msk

#define OPAMP_CSR_OPAMPINTEN_Msk (0x1UL << OPAMP_CSR_OPAMPINTEN_Pos)

0x00000100

Definition at line 6349 of file stm32g431xx.h.

◆ OPAMP_CSR_OPAMPINTEN_Pos

#define OPAMP_CSR_OPAMPINTEN_Pos (8U)

Definition at line 6348 of file stm32g431xx.h.

◆ OPAMP_CSR_OPAMPxEN

#define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk

OPAMP enable

Definition at line 6328 of file stm32g431xx.h.

◆ OPAMP_CSR_OPAMPxEN_Msk

#define OPAMP_CSR_OPAMPxEN_Msk (0x1UL << OPAMP_CSR_OPAMPxEN_Pos)

0x00000001

Definition at line 6327 of file stm32g431xx.h.

◆ OPAMP_CSR_OPAMPxEN_Pos

#define OPAMP_CSR_OPAMPxEN_Pos (0U)

Definition at line 6326 of file stm32g431xx.h.

◆ OPAMP_CSR_OUTCAL

#define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk

OPAMP ouput status flag

Definition at line 6375 of file stm32g431xx.h.

◆ OPAMP_CSR_OUTCAL_Msk

#define OPAMP_CSR_OUTCAL_Msk (0x1UL << OPAMP_CSR_OUTCAL_Pos)

0x40000000

Definition at line 6374 of file stm32g431xx.h.

◆ OPAMP_CSR_OUTCAL_Pos

#define OPAMP_CSR_OUTCAL_Pos (30U)

Definition at line 6373 of file stm32g431xx.h.

◆ OPAMP_CSR_PGGAIN

#define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk

Gain in PGA mode

Definition at line 6361 of file stm32g431xx.h.

◆ OPAMP_CSR_PGGAIN_0

#define OPAMP_CSR_PGGAIN_0 (0x1UL << OPAMP_CSR_PGGAIN_Pos)

0x00004000

Definition at line 6362 of file stm32g431xx.h.

◆ OPAMP_CSR_PGGAIN_1

#define OPAMP_CSR_PGGAIN_1 (0x2UL << OPAMP_CSR_PGGAIN_Pos)

0x00008000

Definition at line 6363 of file stm32g431xx.h.

◆ OPAMP_CSR_PGGAIN_2

#define OPAMP_CSR_PGGAIN_2 (0x4UL << OPAMP_CSR_PGGAIN_Pos)

0x00010000

Definition at line 6364 of file stm32g431xx.h.

◆ OPAMP_CSR_PGGAIN_3

#define OPAMP_CSR_PGGAIN_3 (0x8UL << OPAMP_CSR_PGGAIN_Pos)

0x00020000

Definition at line 6365 of file stm32g431xx.h.

◆ OPAMP_CSR_PGGAIN_4

#define OPAMP_CSR_PGGAIN_4 (0x10UL << OPAMP_CSR_PGGAIN_Pos)

0x00040000

Definition at line 6366 of file stm32g431xx.h.

◆ OPAMP_CSR_PGGAIN_Msk

#define OPAMP_CSR_PGGAIN_Msk (0x1FUL << OPAMP_CSR_PGGAIN_Pos)

0x0007C000

Definition at line 6360 of file stm32g431xx.h.

◆ OPAMP_CSR_PGGAIN_Pos

#define OPAMP_CSR_PGGAIN_Pos (14U)

Definition at line 6359 of file stm32g431xx.h.

◆ OPAMP_CSR_TRIMOFFSETN

#define OPAMP_CSR_TRIMOFFSETN OPAMP_CSR_TRIMOFFSETN_Msk

Offset trimming value (NMOS)

Definition at line 6372 of file stm32g431xx.h.

◆ OPAMP_CSR_TRIMOFFSETN_Msk

#define OPAMP_CSR_TRIMOFFSETN_Msk (0x1FUL << OPAMP_CSR_TRIMOFFSETN_Pos)

0x1F000000

Definition at line 6371 of file stm32g431xx.h.

◆ OPAMP_CSR_TRIMOFFSETN_Pos

#define OPAMP_CSR_TRIMOFFSETN_Pos (24U)

Definition at line 6370 of file stm32g431xx.h.

◆ OPAMP_CSR_TRIMOFFSETP

#define OPAMP_CSR_TRIMOFFSETP OPAMP_CSR_TRIMOFFSETP_Msk

Offset trimming value (PMOS)

Definition at line 6369 of file stm32g431xx.h.

◆ OPAMP_CSR_TRIMOFFSETP_Msk

#define OPAMP_CSR_TRIMOFFSETP_Msk (0x1FUL << OPAMP_CSR_TRIMOFFSETP_Pos)

0x00F80000

Definition at line 6368 of file stm32g431xx.h.

◆ OPAMP_CSR_TRIMOFFSETP_Pos

#define OPAMP_CSR_TRIMOFFSETP_Pos (19U)

Definition at line 6367 of file stm32g431xx.h.

◆ OPAMP_CSR_USERTRIM

#define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk

User trimming enable

Definition at line 6339 of file stm32g431xx.h.

◆ OPAMP_CSR_USERTRIM_Msk

#define OPAMP_CSR_USERTRIM_Msk (0x1UL << OPAMP_CSR_USERTRIM_Pos)

0x00000010

Definition at line 6338 of file stm32g431xx.h.

◆ OPAMP_CSR_USERTRIM_Pos

#define OPAMP_CSR_USERTRIM_Pos (4U)

Definition at line 6337 of file stm32g431xx.h.

◆ OPAMP_CSR_VMSEL

#define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk

Inverting input selection

Definition at line 6342 of file stm32g431xx.h.

◆ OPAMP_CSR_VMSEL_0

#define OPAMP_CSR_VMSEL_0 (0x1UL << OPAMP_CSR_VMSEL_Pos)

0x00000020

Definition at line 6343 of file stm32g431xx.h.

◆ OPAMP_CSR_VMSEL_1

#define OPAMP_CSR_VMSEL_1 (0x2UL << OPAMP_CSR_VMSEL_Pos)

0x00000040

Definition at line 6344 of file stm32g431xx.h.

◆ OPAMP_CSR_VMSEL_Msk

#define OPAMP_CSR_VMSEL_Msk (0x3UL << OPAMP_CSR_VMSEL_Pos)

0x00000060

Definition at line 6341 of file stm32g431xx.h.

◆ OPAMP_CSR_VMSEL_Pos

#define OPAMP_CSR_VMSEL_Pos (5U)

Definition at line 6340 of file stm32g431xx.h.

◆ OPAMP_CSR_VPSEL

#define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk

Non inverting input selection

Definition at line 6334 of file stm32g431xx.h.

◆ OPAMP_CSR_VPSEL_0

#define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos)

0x00000004

Definition at line 6335 of file stm32g431xx.h.

◆ OPAMP_CSR_VPSEL_1

#define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos)

0x00000008

Definition at line 6336 of file stm32g431xx.h.

◆ OPAMP_CSR_VPSEL_Msk

#define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos)

0x0000000C

Definition at line 6333 of file stm32g431xx.h.

◆ OPAMP_CSR_VPSEL_Pos

#define OPAMP_CSR_VPSEL_Pos (2U)

Definition at line 6332 of file stm32g431xx.h.

◆ OPAMP_TCMR_LOCK

#define OPAMP_TCMR_LOCK OPAMP_TCMR_LOCK_Msk

OPAMP SW control register lock

Definition at line 6401 of file stm32g431xx.h.

◆ OPAMP_TCMR_LOCK_Msk

#define OPAMP_TCMR_LOCK_Msk (0x1UL << OPAMP_TCMR_LOCK_Pos)

0x80000000

Definition at line 6400 of file stm32g431xx.h.

◆ OPAMP_TCMR_LOCK_Pos

#define OPAMP_TCMR_LOCK_Pos (31U)

Definition at line 6399 of file stm32g431xx.h.

◆ OPAMP_TCMR_T1CMEN

#define OPAMP_TCMR_T1CMEN OPAMP_TCMR_T1CMEN_Msk

Timer 1 controlled mux mode enable

Definition at line 6392 of file stm32g431xx.h.

◆ OPAMP_TCMR_T1CMEN_Msk

#define OPAMP_TCMR_T1CMEN_Msk (0x1UL << OPAMP_TCMR_T1CMEN_Pos)

0x00000008

Definition at line 6391 of file stm32g431xx.h.

◆ OPAMP_TCMR_T1CMEN_Pos

#define OPAMP_TCMR_T1CMEN_Pos (3U)

Definition at line 6390 of file stm32g431xx.h.

◆ OPAMP_TCMR_T20CMEN

#define OPAMP_TCMR_T20CMEN OPAMP_TCMR_T20CMEN_Msk

Timer 20 controlled mux mode enable

Definition at line 6398 of file stm32g431xx.h.

◆ OPAMP_TCMR_T20CMEN_Msk

#define OPAMP_TCMR_T20CMEN_Msk (0x1UL << OPAMP_TCMR_T20CMEN_Pos)

0x00000020

Definition at line 6397 of file stm32g431xx.h.

◆ OPAMP_TCMR_T20CMEN_Pos

#define OPAMP_TCMR_T20CMEN_Pos (5U)

Definition at line 6396 of file stm32g431xx.h.

◆ OPAMP_TCMR_T8CMEN

#define OPAMP_TCMR_T8CMEN OPAMP_TCMR_T8CMEN_Msk

Timer 8 controlled mux mode enable

Definition at line 6395 of file stm32g431xx.h.

◆ OPAMP_TCMR_T8CMEN_Msk

#define OPAMP_TCMR_T8CMEN_Msk (0x1UL << OPAMP_TCMR_T8CMEN_Pos)

0x00000010

Definition at line 6394 of file stm32g431xx.h.

◆ OPAMP_TCMR_T8CMEN_Pos

#define OPAMP_TCMR_T8CMEN_Pos (4U)

Definition at line 6393 of file stm32g431xx.h.

◆ OPAMP_TCMR_VMSSEL

#define OPAMP_TCMR_VMSSEL OPAMP_TCMR_VMSSEL_Msk

Secondary inverting input selection

Definition at line 6384 of file stm32g431xx.h.

◆ OPAMP_TCMR_VMSSEL_Msk

#define OPAMP_TCMR_VMSSEL_Msk (0x1UL << OPAMP_TCMR_VMSSEL_Pos)

0x00000001

Definition at line 6383 of file stm32g431xx.h.

◆ OPAMP_TCMR_VMSSEL_Pos

#define OPAMP_TCMR_VMSSEL_Pos (0U)

Definition at line 6382 of file stm32g431xx.h.

◆ OPAMP_TCMR_VPSSEL

#define OPAMP_TCMR_VPSSEL OPAMP_TCMR_VPSSEL_Msk

Secondary non inverting input selection

Definition at line 6387 of file stm32g431xx.h.

◆ OPAMP_TCMR_VPSSEL_0

#define OPAMP_TCMR_VPSSEL_0 (0x1UL << OPAMP_TCMR_VPSSEL_Pos)

0x00000002

Definition at line 6388 of file stm32g431xx.h.

◆ OPAMP_TCMR_VPSSEL_1

#define OPAMP_TCMR_VPSSEL_1 (0x2UL << OPAMP_TCMR_VPSSEL_Pos)

0x00000004

Definition at line 6389 of file stm32g431xx.h.

◆ OPAMP_TCMR_VPSSEL_Msk

#define OPAMP_TCMR_VPSSEL_Msk (0x3UL << OPAMP_TCMR_VPSSEL_Pos)

0x00000006

Definition at line 6386 of file stm32g431xx.h.

◆ OPAMP_TCMR_VPSSEL_Pos

#define OPAMP_TCMR_VPSSEL_Pos (1U)

Definition at line 6385 of file stm32g431xx.h.

◆ PWR_CR1_DBP

#define PWR_CR1_DBP PWR_CR1_DBP_Msk

Disable Back-up domain Protection

Definition at line 6422 of file stm32g431xx.h.

◆ PWR_CR1_DBP_Msk

#define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos)

0x00000100

Definition at line 6421 of file stm32g431xx.h.

◆ PWR_CR1_DBP_Pos

#define PWR_CR1_DBP_Pos (8U)

Definition at line 6420 of file stm32g431xx.h.

◆ PWR_CR1_LPMS

#define PWR_CR1_LPMS PWR_CR1_LPMS_Msk

Low-power mode selection field

Definition at line 6425 of file stm32g431xx.h.

◆ PWR_CR1_LPMS_Msk

#define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos)

0x00000007

Definition at line 6424 of file stm32g431xx.h.

◆ PWR_CR1_LPMS_Pos

#define PWR_CR1_LPMS_Pos (0U)

Definition at line 6423 of file stm32g431xx.h.

◆ PWR_CR1_LPMS_SHUTDOWN

#define PWR_CR1_LPMS_SHUTDOWN PWR_CR1_LPMS_SHUTDOWN_Msk

Shut-down mode

Definition at line 6435 of file stm32g431xx.h.

◆ PWR_CR1_LPMS_SHUTDOWN_Msk

#define PWR_CR1_LPMS_SHUTDOWN_Msk (0x1UL << PWR_CR1_LPMS_SHUTDOWN_Pos)

0x00000004

Definition at line 6434 of file stm32g431xx.h.

◆ PWR_CR1_LPMS_SHUTDOWN_Pos

#define PWR_CR1_LPMS_SHUTDOWN_Pos (2U)

Definition at line 6433 of file stm32g431xx.h.

◆ PWR_CR1_LPMS_STANDBY

#define PWR_CR1_LPMS_STANDBY PWR_CR1_LPMS_STANDBY_Msk

Stand-by mode

Definition at line 6432 of file stm32g431xx.h.

◆ PWR_CR1_LPMS_STANDBY_Msk

#define PWR_CR1_LPMS_STANDBY_Msk (0x3UL << PWR_CR1_LPMS_STANDBY_Pos)

0x00000003

Definition at line 6431 of file stm32g431xx.h.

◆ PWR_CR1_LPMS_STANDBY_Pos

#define PWR_CR1_LPMS_STANDBY_Pos (0U)

Definition at line 6430 of file stm32g431xx.h.

◆ PWR_CR1_LPMS_STOP0

#define PWR_CR1_LPMS_STOP0 (0x00000000U)

Stop 0 mode

Definition at line 6426 of file stm32g431xx.h.

◆ PWR_CR1_LPMS_STOP1

#define PWR_CR1_LPMS_STOP1 PWR_CR1_LPMS_STOP1_Msk

Stop 1 mode

Definition at line 6429 of file stm32g431xx.h.

◆ PWR_CR1_LPMS_STOP1_Msk

#define PWR_CR1_LPMS_STOP1_Msk (0x1UL << PWR_CR1_LPMS_STOP1_Pos)

0x00000001

Definition at line 6428 of file stm32g431xx.h.

◆ PWR_CR1_LPMS_STOP1_Pos

#define PWR_CR1_LPMS_STOP1_Pos (0U)

Definition at line 6427 of file stm32g431xx.h.

◆ PWR_CR1_LPR

#define PWR_CR1_LPR PWR_CR1_LPR_Msk

Regulator low-power mode

Definition at line 6414 of file stm32g431xx.h.

◆ PWR_CR1_LPR_Msk

#define PWR_CR1_LPR_Msk (0x1UL << PWR_CR1_LPR_Pos)

0x00004000

Definition at line 6413 of file stm32g431xx.h.

◆ PWR_CR1_LPR_Pos

#define PWR_CR1_LPR_Pos (14U)

Definition at line 6412 of file stm32g431xx.h.

◆ PWR_CR1_VOS

#define PWR_CR1_VOS PWR_CR1_VOS_Msk

VOS[1:0] bits (Regulator voltage scaling output selection)

Definition at line 6417 of file stm32g431xx.h.

◆ PWR_CR1_VOS_0

#define PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_Pos)

0x00000200

Definition at line 6418 of file stm32g431xx.h.

◆ PWR_CR1_VOS_1

#define PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_Pos)

0x00000400

Definition at line 6419 of file stm32g431xx.h.

◆ PWR_CR1_VOS_Msk

#define PWR_CR1_VOS_Msk (0x3UL << PWR_CR1_VOS_Pos)

0x00000600

Definition at line 6416 of file stm32g431xx.h.

◆ PWR_CR1_VOS_Pos

#define PWR_CR1_VOS_Pos (9U)

Definition at line 6415 of file stm32g431xx.h.

◆ PWR_CR2_PLS

#define PWR_CR2_PLS PWR_CR2_PLS_Msk

PVD level selection

Definition at line 6460 of file stm32g431xx.h.

◆ PWR_CR2_PLS_LEV0

#define PWR_CR2_PLS_LEV0 (0x00000000U)

PVD level 0

Definition at line 6461 of file stm32g431xx.h.

◆ PWR_CR2_PLS_LEV1

#define PWR_CR2_PLS_LEV1 PWR_CR2_PLS_LEV1_Msk

PVD level 1

Definition at line 6464 of file stm32g431xx.h.

◆ PWR_CR2_PLS_LEV1_Msk

#define PWR_CR2_PLS_LEV1_Msk (0x1UL << PWR_CR2_PLS_LEV1_Pos)

0x00000002

Definition at line 6463 of file stm32g431xx.h.

◆ PWR_CR2_PLS_LEV1_Pos

#define PWR_CR2_PLS_LEV1_Pos (1U)

Definition at line 6462 of file stm32g431xx.h.

◆ PWR_CR2_PLS_LEV2

#define PWR_CR2_PLS_LEV2 PWR_CR2_PLS_LEV2_Msk

PVD level 2

Definition at line 6467 of file stm32g431xx.h.

◆ PWR_CR2_PLS_LEV2_Msk

#define PWR_CR2_PLS_LEV2_Msk (0x1UL << PWR_CR2_PLS_LEV2_Pos)

0x00000004

Definition at line 6466 of file stm32g431xx.h.

◆ PWR_CR2_PLS_LEV2_Pos

#define PWR_CR2_PLS_LEV2_Pos (2U)

Definition at line 6465 of file stm32g431xx.h.

◆ PWR_CR2_PLS_LEV3

#define PWR_CR2_PLS_LEV3 PWR_CR2_PLS_LEV3_Msk

PVD level 3

Definition at line 6470 of file stm32g431xx.h.

◆ PWR_CR2_PLS_LEV3_Msk

#define PWR_CR2_PLS_LEV3_Msk (0x3UL << PWR_CR2_PLS_LEV3_Pos)

0x00000006

Definition at line 6469 of file stm32g431xx.h.

◆ PWR_CR2_PLS_LEV3_Pos

#define PWR_CR2_PLS_LEV3_Pos (1U)

Definition at line 6468 of file stm32g431xx.h.

◆ PWR_CR2_PLS_LEV4

#define PWR_CR2_PLS_LEV4 PWR_CR2_PLS_LEV4_Msk

PVD level 4

Definition at line 6473 of file stm32g431xx.h.

◆ PWR_CR2_PLS_LEV4_Msk

#define PWR_CR2_PLS_LEV4_Msk (0x1UL << PWR_CR2_PLS_LEV4_Pos)

0x00000008

Definition at line 6472 of file stm32g431xx.h.

◆ PWR_CR2_PLS_LEV4_Pos

#define PWR_CR2_PLS_LEV4_Pos (3U)

Definition at line 6471 of file stm32g431xx.h.

◆ PWR_CR2_PLS_LEV5

#define PWR_CR2_PLS_LEV5 PWR_CR2_PLS_LEV5_Msk

PVD level 5

Definition at line 6476 of file stm32g431xx.h.

◆ PWR_CR2_PLS_LEV5_Msk

#define PWR_CR2_PLS_LEV5_Msk (0x5UL << PWR_CR2_PLS_LEV5_Pos)

0x0000000A

Definition at line 6475 of file stm32g431xx.h.

◆ PWR_CR2_PLS_LEV5_Pos

#define PWR_CR2_PLS_LEV5_Pos (1U)

Definition at line 6474 of file stm32g431xx.h.

◆ PWR_CR2_PLS_LEV6

#define PWR_CR2_PLS_LEV6 PWR_CR2_PLS_LEV6_Msk

PVD level 6

Definition at line 6479 of file stm32g431xx.h.

◆ PWR_CR2_PLS_LEV6_Msk

#define PWR_CR2_PLS_LEV6_Msk (0x3UL << PWR_CR2_PLS_LEV6_Pos)

0x0000000C

Definition at line 6478 of file stm32g431xx.h.

◆ PWR_CR2_PLS_LEV6_Pos

#define PWR_CR2_PLS_LEV6_Pos (2U)

Definition at line 6477 of file stm32g431xx.h.

◆ PWR_CR2_PLS_LEV7

#define PWR_CR2_PLS_LEV7 PWR_CR2_PLS_LEV7_Msk

PVD level 7

Definition at line 6482 of file stm32g431xx.h.

◆ PWR_CR2_PLS_LEV7_Msk

#define PWR_CR2_PLS_LEV7_Msk (0x7UL << PWR_CR2_PLS_LEV7_Pos)

0x0000000E

Definition at line 6481 of file stm32g431xx.h.

◆ PWR_CR2_PLS_LEV7_Pos

#define PWR_CR2_PLS_LEV7_Pos (1U)

Definition at line 6480 of file stm32g431xx.h.

◆ PWR_CR2_PLS_Msk

#define PWR_CR2_PLS_Msk (0x7UL << PWR_CR2_PLS_Pos)

0x0000000E

Definition at line 6459 of file stm32g431xx.h.

◆ PWR_CR2_PLS_Pos

#define PWR_CR2_PLS_Pos (1U)

Definition at line 6458 of file stm32g431xx.h.

◆ PWR_CR2_PVDE

#define PWR_CR2_PVDE PWR_CR2_PVDE_Msk

Power Voltage Detector Enable

Definition at line 6485 of file stm32g431xx.h.

◆ PWR_CR2_PVDE_Msk

#define PWR_CR2_PVDE_Msk (0x1UL << PWR_CR2_PVDE_Pos)

0x00000001

Definition at line 6484 of file stm32g431xx.h.

◆ PWR_CR2_PVDE_Pos

#define PWR_CR2_PVDE_Pos (0U)

Definition at line 6483 of file stm32g431xx.h.

◆ PWR_CR2_PVME

#define PWR_CR2_PVME PWR_CR2_PVME_Msk

PVM bits field

Definition at line 6443 of file stm32g431xx.h.

◆ PWR_CR2_PVME1

#define PWR_CR2_PVME1 PWR_CR2_PVME1_Msk

PVM 1 Enable PVD level configuration

Definition at line 6457 of file stm32g431xx.h.

◆ PWR_CR2_PVME1_Msk

#define PWR_CR2_PVME1_Msk (0x1UL << PWR_CR2_PVME1_Pos)

0x00000010

Definition at line 6454 of file stm32g431xx.h.

◆ PWR_CR2_PVME1_Pos

#define PWR_CR2_PVME1_Pos (4U)

Definition at line 6453 of file stm32g431xx.h.

◆ PWR_CR2_PVME2

#define PWR_CR2_PVME2 PWR_CR2_PVME2_Msk

PVM 2 Enable

Definition at line 6452 of file stm32g431xx.h.

◆ PWR_CR2_PVME2_Msk

#define PWR_CR2_PVME2_Msk (0x1UL << PWR_CR2_PVME2_Pos)

0x00000020

Definition at line 6451 of file stm32g431xx.h.

◆ PWR_CR2_PVME2_Pos

#define PWR_CR2_PVME2_Pos (5U)

Definition at line 6450 of file stm32g431xx.h.

◆ PWR_CR2_PVME3

#define PWR_CR2_PVME3 PWR_CR2_PVME3_Msk

PVM 3 Enable

Definition at line 6449 of file stm32g431xx.h.

◆ PWR_CR2_PVME3_Msk

#define PWR_CR2_PVME3_Msk (0x1UL << PWR_CR2_PVME3_Pos)

0x00000040

Definition at line 6448 of file stm32g431xx.h.

◆ PWR_CR2_PVME3_Pos

#define PWR_CR2_PVME3_Pos (6U)

Definition at line 6447 of file stm32g431xx.h.

◆ PWR_CR2_PVME4

#define PWR_CR2_PVME4 PWR_CR2_PVME4_Msk

PVM 4 Enable

Definition at line 6446 of file stm32g431xx.h.

◆ PWR_CR2_PVME4_Msk

#define PWR_CR2_PVME4_Msk (0x1UL << PWR_CR2_PVME4_Pos)

0x00000080

Definition at line 6445 of file stm32g431xx.h.

◆ PWR_CR2_PVME4_Pos

#define PWR_CR2_PVME4_Pos (7U)

Definition at line 6444 of file stm32g431xx.h.

◆ PWR_CR2_PVME_Msk

#define PWR_CR2_PVME_Msk (0xFUL << PWR_CR2_PVME_Pos)

0x000000F0

Definition at line 6442 of file stm32g431xx.h.

◆ PWR_CR2_PVME_Pos

#define PWR_CR2_PVME_Pos (4U)

< PVME Peripheral Voltage Monitor Enable

Definition at line 6441 of file stm32g431xx.h.

◆ PWR_CR3_APC

#define PWR_CR3_APC PWR_CR3_APC_Msk

Apply pull-up and pull-down configuration

Definition at line 6499 of file stm32g431xx.h.

◆ PWR_CR3_APC_Msk

#define PWR_CR3_APC_Msk (0x1UL << PWR_CR3_APC_Pos)

0x00000400

Definition at line 6498 of file stm32g431xx.h.

◆ PWR_CR3_APC_Pos

#define PWR_CR3_APC_Pos (10U)

Definition at line 6497 of file stm32g431xx.h.

◆ PWR_CR3_EIWF

#define PWR_CR3_EIWF PWR_CR3_EIWF_Msk

Enable Internal Wake-up line

Definition at line 6490 of file stm32g431xx.h.

◆ PWR_CR3_EIWF_Msk

#define PWR_CR3_EIWF_Msk (0x1UL << PWR_CR3_EIWF_Pos)

0x00008000

Definition at line 6489 of file stm32g431xx.h.

◆ PWR_CR3_EIWF_Pos

#define PWR_CR3_EIWF_Pos (15U)

Definition at line 6488 of file stm32g431xx.h.

◆ PWR_CR3_EWUP

#define PWR_CR3_EWUP PWR_CR3_EWUP_Msk

Enable Wake-Up Pins

Definition at line 6520 of file stm32g431xx.h.

◆ PWR_CR3_EWUP1

#define PWR_CR3_EWUP1 PWR_CR3_EWUP1_Msk

Enable Wake-Up Pin 1

Definition at line 6517 of file stm32g431xx.h.

◆ PWR_CR3_EWUP1_Msk

#define PWR_CR3_EWUP1_Msk (0x1UL << PWR_CR3_EWUP1_Pos)

0x00000001

Definition at line 6516 of file stm32g431xx.h.

◆ PWR_CR3_EWUP1_Pos

#define PWR_CR3_EWUP1_Pos (0U)

Definition at line 6515 of file stm32g431xx.h.

◆ PWR_CR3_EWUP2

#define PWR_CR3_EWUP2 PWR_CR3_EWUP2_Msk

Enable Wake-Up Pin 2

Definition at line 6514 of file stm32g431xx.h.

◆ PWR_CR3_EWUP2_Msk

#define PWR_CR3_EWUP2_Msk (0x1UL << PWR_CR3_EWUP2_Pos)

0x00000002

Definition at line 6513 of file stm32g431xx.h.

◆ PWR_CR3_EWUP2_Pos

#define PWR_CR3_EWUP2_Pos (1U)

Definition at line 6512 of file stm32g431xx.h.

◆ PWR_CR3_EWUP3

#define PWR_CR3_EWUP3 PWR_CR3_EWUP3_Msk

Enable Wake-Up Pin 3

Definition at line 6511 of file stm32g431xx.h.

◆ PWR_CR3_EWUP3_Msk

#define PWR_CR3_EWUP3_Msk (0x1UL << PWR_CR3_EWUP3_Pos)

0x00000004

Definition at line 6510 of file stm32g431xx.h.

◆ PWR_CR3_EWUP3_Pos

#define PWR_CR3_EWUP3_Pos (2U)

Definition at line 6509 of file stm32g431xx.h.

◆ PWR_CR3_EWUP4

#define PWR_CR3_EWUP4 PWR_CR3_EWUP4_Msk

Enable Wake-Up Pin 4

Definition at line 6508 of file stm32g431xx.h.

◆ PWR_CR3_EWUP4_Msk

#define PWR_CR3_EWUP4_Msk (0x1UL << PWR_CR3_EWUP4_Pos)

0x00000008

Definition at line 6507 of file stm32g431xx.h.

◆ PWR_CR3_EWUP4_Pos

#define PWR_CR3_EWUP4_Pos (3U)

Definition at line 6506 of file stm32g431xx.h.

◆ PWR_CR3_EWUP5

#define PWR_CR3_EWUP5 PWR_CR3_EWUP5_Msk

Enable Wake-Up Pin 5

Definition at line 6505 of file stm32g431xx.h.

◆ PWR_CR3_EWUP5_Msk

#define PWR_CR3_EWUP5_Msk (0x1UL << PWR_CR3_EWUP5_Pos)

0x00000010

Definition at line 6504 of file stm32g431xx.h.

◆ PWR_CR3_EWUP5_Pos

#define PWR_CR3_EWUP5_Pos (4U)

Definition at line 6503 of file stm32g431xx.h.

◆ PWR_CR3_EWUP_Msk

#define PWR_CR3_EWUP_Msk (0x1FUL << PWR_CR3_EWUP_Pos)

0x0000001F

Definition at line 6519 of file stm32g431xx.h.

◆ PWR_CR3_EWUP_Pos

#define PWR_CR3_EWUP_Pos (0U)

Definition at line 6518 of file stm32g431xx.h.

◆ PWR_CR3_RRS

#define PWR_CR3_RRS PWR_CR3_RRS_Msk

SRAM2 Retention in Stand-by mode

Definition at line 6502 of file stm32g431xx.h.

◆ PWR_CR3_RRS_Msk

#define PWR_CR3_RRS_Msk (0x1UL << PWR_CR3_RRS_Pos)

0x00000100

Definition at line 6501 of file stm32g431xx.h.

◆ PWR_CR3_RRS_Pos

#define PWR_CR3_RRS_Pos (8U)

Definition at line 6500 of file stm32g431xx.h.

◆ PWR_CR3_UCPD_DBDIS

#define PWR_CR3_UCPD_DBDIS PWR_CR3_UCPD_DBDIS_Msk

USB Type-C and Power Delivery Dead Battery disable.

Definition at line 6493 of file stm32g431xx.h.

◆ PWR_CR3_UCPD_DBDIS_Msk

#define PWR_CR3_UCPD_DBDIS_Msk (0x1UL << PWR_CR3_UCPD_DBDIS_Pos)

0x00004000

Definition at line 6492 of file stm32g431xx.h.

◆ PWR_CR3_UCPD_DBDIS_Pos

#define PWR_CR3_UCPD_DBDIS_Pos (14U)

Definition at line 6491 of file stm32g431xx.h.

◆ PWR_CR3_UCPD_STDBY

#define PWR_CR3_UCPD_STDBY PWR_CR3_UCPD_STDBY_Msk

USB Type-C and Power Delivery standby mode.

Definition at line 6496 of file stm32g431xx.h.

◆ PWR_CR3_UCPD_STDBY_Msk

#define PWR_CR3_UCPD_STDBY_Msk (0x1UL << PWR_CR3_UCPD_STDBY_Pos)

0x00002000

Definition at line 6495 of file stm32g431xx.h.

◆ PWR_CR3_UCPD_STDBY_Pos

#define PWR_CR3_UCPD_STDBY_Pos (13U)

Definition at line 6494 of file stm32g431xx.h.

◆ PWR_CR4_VBE

#define PWR_CR4_VBE PWR_CR4_VBE_Msk

VBAT Battery charging Enable

Definition at line 6528 of file stm32g431xx.h.

◆ PWR_CR4_VBE_Msk

#define PWR_CR4_VBE_Msk (0x1UL << PWR_CR4_VBE_Pos)

0x00000100

Definition at line 6527 of file stm32g431xx.h.

◆ PWR_CR4_VBE_Pos

#define PWR_CR4_VBE_Pos (8U)

Definition at line 6526 of file stm32g431xx.h.

◆ PWR_CR4_VBRS

#define PWR_CR4_VBRS PWR_CR4_VBRS_Msk

VBAT Battery charging Resistor Selection

Definition at line 6525 of file stm32g431xx.h.

◆ PWR_CR4_VBRS_Msk

#define PWR_CR4_VBRS_Msk (0x1UL << PWR_CR4_VBRS_Pos)

0x00000200

Definition at line 6524 of file stm32g431xx.h.

◆ PWR_CR4_VBRS_Pos

#define PWR_CR4_VBRS_Pos (9U)

Definition at line 6523 of file stm32g431xx.h.

◆ PWR_CR4_WP1

#define PWR_CR4_WP1 PWR_CR4_WP1_Msk

Wake-Up Pin 1 polarity

Definition at line 6543 of file stm32g431xx.h.

◆ PWR_CR4_WP1_Msk

#define PWR_CR4_WP1_Msk (0x1UL << PWR_CR4_WP1_Pos)

0x00000001

Definition at line 6542 of file stm32g431xx.h.

◆ PWR_CR4_WP1_Pos

#define PWR_CR4_WP1_Pos (0U)

Definition at line 6541 of file stm32g431xx.h.

◆ PWR_CR4_WP2

#define PWR_CR4_WP2 PWR_CR4_WP2_Msk

Wake-Up Pin 2 polarity

Definition at line 6540 of file stm32g431xx.h.

◆ PWR_CR4_WP2_Msk

#define PWR_CR4_WP2_Msk (0x1UL << PWR_CR4_WP2_Pos)

0x00000002

Definition at line 6539 of file stm32g431xx.h.

◆ PWR_CR4_WP2_Pos

#define PWR_CR4_WP2_Pos (1U)

Definition at line 6538 of file stm32g431xx.h.

◆ PWR_CR4_WP3

#define PWR_CR4_WP3 PWR_CR4_WP3_Msk

Wake-Up Pin 3 polarity

Definition at line 6537 of file stm32g431xx.h.

◆ PWR_CR4_WP3_Msk

#define PWR_CR4_WP3_Msk (0x1UL << PWR_CR4_WP3_Pos)

0x00000004

Definition at line 6536 of file stm32g431xx.h.

◆ PWR_CR4_WP3_Pos

#define PWR_CR4_WP3_Pos (2U)

Definition at line 6535 of file stm32g431xx.h.

◆ PWR_CR4_WP4

#define PWR_CR4_WP4 PWR_CR4_WP4_Msk

Wake-Up Pin 4 polarity

Definition at line 6534 of file stm32g431xx.h.

◆ PWR_CR4_WP4_Msk

#define PWR_CR4_WP4_Msk (0x1UL << PWR_CR4_WP4_Pos)

0x00000008

Definition at line 6533 of file stm32g431xx.h.

◆ PWR_CR4_WP4_Pos

#define PWR_CR4_WP4_Pos (3U)

Definition at line 6532 of file stm32g431xx.h.

◆ PWR_CR4_WP5

#define PWR_CR4_WP5 PWR_CR4_WP5_Msk

Wake-Up Pin 5 polarity

Definition at line 6531 of file stm32g431xx.h.

◆ PWR_CR4_WP5_Msk

#define PWR_CR4_WP5_Msk (0x1UL << PWR_CR4_WP5_Pos)

0x00000010

Definition at line 6530 of file stm32g431xx.h.

◆ PWR_CR4_WP5_Pos

#define PWR_CR4_WP5_Pos (4U)

Definition at line 6529 of file stm32g431xx.h.

◆ PWR_CR5_R1MODE

#define PWR_CR5_R1MODE PWR_CR5_R1MODE_Msk

selection for Main Regulator in Range1

Definition at line 7219 of file stm32g431xx.h.

◆ PWR_CR5_R1MODE_Msk

#define PWR_CR5_R1MODE_Msk (0x1U << PWR_CR5_R1MODE_Pos)

0x00000100

Definition at line 7218 of file stm32g431xx.h.

◆ PWR_CR5_R1MODE_Pos

#define PWR_CR5_R1MODE_Pos (8U)

Definition at line 7217 of file stm32g431xx.h.

◆ PWR_PDCRA_PA0

#define PWR_PDCRA_PA0 PWR_PDCRA_PA0_Msk

Port PA0 Pull-Down set

Definition at line 6709 of file stm32g431xx.h.

◆ PWR_PDCRA_PA0_Msk

#define PWR_PDCRA_PA0_Msk (0x1UL << PWR_PDCRA_PA0_Pos)

0x00000001

Definition at line 6708 of file stm32g431xx.h.

◆ PWR_PDCRA_PA0_Pos

#define PWR_PDCRA_PA0_Pos (0U)

Definition at line 6707 of file stm32g431xx.h.

◆ PWR_PDCRA_PA1

#define PWR_PDCRA_PA1 PWR_PDCRA_PA1_Msk

Port PA1 Pull-Down set

Definition at line 6706 of file stm32g431xx.h.

◆ PWR_PDCRA_PA10

#define PWR_PDCRA_PA10 PWR_PDCRA_PA10_Msk

Port PA10 Pull-Down set

Definition at line 6679 of file stm32g431xx.h.

◆ PWR_PDCRA_PA10_Msk

#define PWR_PDCRA_PA10_Msk (0x1UL << PWR_PDCRA_PA10_Pos)

0x00000400

Definition at line 6678 of file stm32g431xx.h.

◆ PWR_PDCRA_PA10_Pos

#define PWR_PDCRA_PA10_Pos (10U)

Definition at line 6677 of file stm32g431xx.h.

◆ PWR_PDCRA_PA11

#define PWR_PDCRA_PA11 PWR_PDCRA_PA11_Msk

Port PA11 Pull-Down set

Definition at line 6676 of file stm32g431xx.h.

◆ PWR_PDCRA_PA11_Msk

#define PWR_PDCRA_PA11_Msk (0x1UL << PWR_PDCRA_PA11_Pos)

0x00000800

Definition at line 6675 of file stm32g431xx.h.

◆ PWR_PDCRA_PA11_Pos

#define PWR_PDCRA_PA11_Pos (11U)

Definition at line 6674 of file stm32g431xx.h.

◆ PWR_PDCRA_PA12

#define PWR_PDCRA_PA12 PWR_PDCRA_PA12_Msk

Port PA12 Pull-Down set

Definition at line 6673 of file stm32g431xx.h.

◆ PWR_PDCRA_PA12_Msk

#define PWR_PDCRA_PA12_Msk (0x1UL << PWR_PDCRA_PA12_Pos)

0x00001000

Definition at line 6672 of file stm32g431xx.h.

◆ PWR_PDCRA_PA12_Pos

#define PWR_PDCRA_PA12_Pos (12U)

Definition at line 6671 of file stm32g431xx.h.

◆ PWR_PDCRA_PA14

#define PWR_PDCRA_PA14 PWR_PDCRA_PA14_Msk

Port PA14 Pull-Down set

Definition at line 6670 of file stm32g431xx.h.

◆ PWR_PDCRA_PA14_Msk

#define PWR_PDCRA_PA14_Msk (0x1UL << PWR_PDCRA_PA14_Pos)

0x00004000

Definition at line 6669 of file stm32g431xx.h.

◆ PWR_PDCRA_PA14_Pos

#define PWR_PDCRA_PA14_Pos (14U)

Definition at line 6668 of file stm32g431xx.h.

◆ PWR_PDCRA_PA1_Msk

#define PWR_PDCRA_PA1_Msk (0x1UL << PWR_PDCRA_PA1_Pos)

0x00000002

Definition at line 6705 of file stm32g431xx.h.

◆ PWR_PDCRA_PA1_Pos

#define PWR_PDCRA_PA1_Pos (1U)

Definition at line 6704 of file stm32g431xx.h.

◆ PWR_PDCRA_PA2

#define PWR_PDCRA_PA2 PWR_PDCRA_PA2_Msk

Port PA2 Pull-Down set

Definition at line 6703 of file stm32g431xx.h.

◆ PWR_PDCRA_PA2_Msk

#define PWR_PDCRA_PA2_Msk (0x1UL << PWR_PDCRA_PA2_Pos)

0x00000004

Definition at line 6702 of file stm32g431xx.h.

◆ PWR_PDCRA_PA2_Pos

#define PWR_PDCRA_PA2_Pos (2U)

Definition at line 6701 of file stm32g431xx.h.

◆ PWR_PDCRA_PA3

#define PWR_PDCRA_PA3 PWR_PDCRA_PA3_Msk

Port PA3 Pull-Down set

Definition at line 6700 of file stm32g431xx.h.

◆ PWR_PDCRA_PA3_Msk

#define PWR_PDCRA_PA3_Msk (0x1UL << PWR_PDCRA_PA3_Pos)

0x00000008

Definition at line 6699 of file stm32g431xx.h.

◆ PWR_PDCRA_PA3_Pos

#define PWR_PDCRA_PA3_Pos (3U)

Definition at line 6698 of file stm32g431xx.h.

◆ PWR_PDCRA_PA4

#define PWR_PDCRA_PA4 PWR_PDCRA_PA4_Msk

Port PA4 Pull-Down set

Definition at line 6697 of file stm32g431xx.h.

◆ PWR_PDCRA_PA4_Msk

#define PWR_PDCRA_PA4_Msk (0x1UL << PWR_PDCRA_PA4_Pos)

0x00000010

Definition at line 6696 of file stm32g431xx.h.

◆ PWR_PDCRA_PA4_Pos

#define PWR_PDCRA_PA4_Pos (4U)

Definition at line 6695 of file stm32g431xx.h.

◆ PWR_PDCRA_PA5

#define PWR_PDCRA_PA5 PWR_PDCRA_PA5_Msk

Port PA5 Pull-Down set

Definition at line 6694 of file stm32g431xx.h.

◆ PWR_PDCRA_PA5_Msk

#define PWR_PDCRA_PA5_Msk (0x1UL << PWR_PDCRA_PA5_Pos)

0x00000020

Definition at line 6693 of file stm32g431xx.h.

◆ PWR_PDCRA_PA5_Pos

#define PWR_PDCRA_PA5_Pos (5U)

Definition at line 6692 of file stm32g431xx.h.

◆ PWR_PDCRA_PA6

#define PWR_PDCRA_PA6 PWR_PDCRA_PA6_Msk

Port PA6 Pull-Down set

Definition at line 6691 of file stm32g431xx.h.

◆ PWR_PDCRA_PA6_Msk

#define PWR_PDCRA_PA6_Msk (0x1UL << PWR_PDCRA_PA6_Pos)

0x00000040

Definition at line 6690 of file stm32g431xx.h.

◆ PWR_PDCRA_PA6_Pos

#define PWR_PDCRA_PA6_Pos (6U)

Definition at line 6689 of file stm32g431xx.h.

◆ PWR_PDCRA_PA7

#define PWR_PDCRA_PA7 PWR_PDCRA_PA7_Msk

Port PA7 Pull-Down set

Definition at line 6688 of file stm32g431xx.h.

◆ PWR_PDCRA_PA7_Msk

#define PWR_PDCRA_PA7_Msk (0x1UL << PWR_PDCRA_PA7_Pos)

0x00000080

Definition at line 6687 of file stm32g431xx.h.

◆ PWR_PDCRA_PA7_Pos

#define PWR_PDCRA_PA7_Pos (7U)

Definition at line 6686 of file stm32g431xx.h.

◆ PWR_PDCRA_PA8

#define PWR_PDCRA_PA8 PWR_PDCRA_PA8_Msk

Port PA8 Pull-Down set

Definition at line 6685 of file stm32g431xx.h.

◆ PWR_PDCRA_PA8_Msk

#define PWR_PDCRA_PA8_Msk (0x1UL << PWR_PDCRA_PA8_Pos)

0x00000100

Definition at line 6684 of file stm32g431xx.h.

◆ PWR_PDCRA_PA8_Pos

#define PWR_PDCRA_PA8_Pos (8U)

Definition at line 6683 of file stm32g431xx.h.

◆ PWR_PDCRA_PA9

#define PWR_PDCRA_PA9 PWR_PDCRA_PA9_Msk

Port PA9 Pull-Down set

Definition at line 6682 of file stm32g431xx.h.

◆ PWR_PDCRA_PA9_Msk

#define PWR_PDCRA_PA9_Msk (0x1UL << PWR_PDCRA_PA9_Pos)

0x00000200

Definition at line 6681 of file stm32g431xx.h.

◆ PWR_PDCRA_PA9_Pos

#define PWR_PDCRA_PA9_Pos (9U)

Definition at line 6680 of file stm32g431xx.h.

◆ PWR_PDCRB_PB0

#define PWR_PDCRB_PB0 PWR_PDCRB_PB0_Msk

Port PB0 Pull-Down set

Definition at line 6807 of file stm32g431xx.h.

◆ PWR_PDCRB_PB0_Msk

#define PWR_PDCRB_PB0_Msk (0x1UL << PWR_PDCRB_PB0_Pos)

0x00000001

Definition at line 6806 of file stm32g431xx.h.

◆ PWR_PDCRB_PB0_Pos

#define PWR_PDCRB_PB0_Pos (0U)

Definition at line 6805 of file stm32g431xx.h.

◆ PWR_PDCRB_PB1

#define PWR_PDCRB_PB1 PWR_PDCRB_PB1_Msk

Port PB1 Pull-Down set

Definition at line 6804 of file stm32g431xx.h.

◆ PWR_PDCRB_PB10

#define PWR_PDCRB_PB10 PWR_PDCRB_PB10_Msk

Port PB10 Pull-Down set

Definition at line 6780 of file stm32g431xx.h.

◆ PWR_PDCRB_PB10_Msk

#define PWR_PDCRB_PB10_Msk (0x1UL << PWR_PDCRB_PB10_Pos)

0x00000400

Definition at line 6779 of file stm32g431xx.h.

◆ PWR_PDCRB_PB10_Pos

#define PWR_PDCRB_PB10_Pos (10U)

Definition at line 6778 of file stm32g431xx.h.

◆ PWR_PDCRB_PB11

#define PWR_PDCRB_PB11 PWR_PDCRB_PB11_Msk

Port PB11 Pull-Down set

Definition at line 6777 of file stm32g431xx.h.

◆ PWR_PDCRB_PB11_Msk

#define PWR_PDCRB_PB11_Msk (0x1UL << PWR_PDCRB_PB11_Pos)

0x00000800

Definition at line 6776 of file stm32g431xx.h.

◆ PWR_PDCRB_PB11_Pos

#define PWR_PDCRB_PB11_Pos (11U)

Definition at line 6775 of file stm32g431xx.h.

◆ PWR_PDCRB_PB12

#define PWR_PDCRB_PB12 PWR_PDCRB_PB12_Msk

Port PB12 Pull-Down set

Definition at line 6774 of file stm32g431xx.h.

◆ PWR_PDCRB_PB12_Msk

#define PWR_PDCRB_PB12_Msk (0x1UL << PWR_PDCRB_PB12_Pos)

0x00001000

Definition at line 6773 of file stm32g431xx.h.

◆ PWR_PDCRB_PB12_Pos

#define PWR_PDCRB_PB12_Pos (12U)

Definition at line 6772 of file stm32g431xx.h.

◆ PWR_PDCRB_PB13

#define PWR_PDCRB_PB13 PWR_PDCRB_PB13_Msk

Port PB13 Pull-Down set

Definition at line 6771 of file stm32g431xx.h.

◆ PWR_PDCRB_PB13_Msk

#define PWR_PDCRB_PB13_Msk (0x1UL << PWR_PDCRB_PB13_Pos)

0x00002000

Definition at line 6770 of file stm32g431xx.h.

◆ PWR_PDCRB_PB13_Pos

#define PWR_PDCRB_PB13_Pos (13U)

Definition at line 6769 of file stm32g431xx.h.

◆ PWR_PDCRB_PB14

#define PWR_PDCRB_PB14 PWR_PDCRB_PB14_Msk

Port PB14 Pull-Down set

Definition at line 6768 of file stm32g431xx.h.

◆ PWR_PDCRB_PB14_Msk

#define PWR_PDCRB_PB14_Msk (0x1UL << PWR_PDCRB_PB14_Pos)

0x00004000

Definition at line 6767 of file stm32g431xx.h.

◆ PWR_PDCRB_PB14_Pos

#define PWR_PDCRB_PB14_Pos (14U)

Definition at line 6766 of file stm32g431xx.h.

◆ PWR_PDCRB_PB15

#define PWR_PDCRB_PB15 PWR_PDCRB_PB15_Msk

Port PB15 Pull-Down set

Definition at line 6765 of file stm32g431xx.h.

◆ PWR_PDCRB_PB15_Msk

#define PWR_PDCRB_PB15_Msk (0x1UL << PWR_PDCRB_PB15_Pos)

0x00008000

Definition at line 6764 of file stm32g431xx.h.

◆ PWR_PDCRB_PB15_Pos

#define PWR_PDCRB_PB15_Pos (15U)

Definition at line 6763 of file stm32g431xx.h.

◆ PWR_PDCRB_PB1_Msk

#define PWR_PDCRB_PB1_Msk (0x1UL << PWR_PDCRB_PB1_Pos)

0x00000002

Definition at line 6803 of file stm32g431xx.h.

◆ PWR_PDCRB_PB1_Pos

#define PWR_PDCRB_PB1_Pos (1U)

Definition at line 6802 of file stm32g431xx.h.

◆ PWR_PDCRB_PB2

#define PWR_PDCRB_PB2 PWR_PDCRB_PB2_Msk

Port PB2 Pull-Down set

Definition at line 6801 of file stm32g431xx.h.

◆ PWR_PDCRB_PB2_Msk

#define PWR_PDCRB_PB2_Msk (0x1UL << PWR_PDCRB_PB2_Pos)

0x00000004

Definition at line 6800 of file stm32g431xx.h.

◆ PWR_PDCRB_PB2_Pos

#define PWR_PDCRB_PB2_Pos (2U)

Definition at line 6799 of file stm32g431xx.h.

◆ PWR_PDCRB_PB3

#define PWR_PDCRB_PB3 PWR_PDCRB_PB3_Msk

Port PB3 Pull-Down set

Definition at line 6798 of file stm32g431xx.h.

◆ PWR_PDCRB_PB3_Msk

#define PWR_PDCRB_PB3_Msk (0x1UL << PWR_PDCRB_PB3_Pos)

0x00000008

Definition at line 6797 of file stm32g431xx.h.

◆ PWR_PDCRB_PB3_Pos

#define PWR_PDCRB_PB3_Pos (3U)

Definition at line 6796 of file stm32g431xx.h.

◆ PWR_PDCRB_PB5

#define PWR_PDCRB_PB5 PWR_PDCRB_PB5_Msk

Port PB5 Pull-Down set

Definition at line 6795 of file stm32g431xx.h.

◆ PWR_PDCRB_PB5_Msk

#define PWR_PDCRB_PB5_Msk (0x1UL << PWR_PDCRB_PB5_Pos)

0x00000020

Definition at line 6794 of file stm32g431xx.h.

◆ PWR_PDCRB_PB5_Pos

#define PWR_PDCRB_PB5_Pos (5U)

Definition at line 6793 of file stm32g431xx.h.

◆ PWR_PDCRB_PB6

#define PWR_PDCRB_PB6 PWR_PDCRB_PB6_Msk

Port PB6 Pull-Down set

Definition at line 6792 of file stm32g431xx.h.

◆ PWR_PDCRB_PB6_Msk

#define PWR_PDCRB_PB6_Msk (0x1UL << PWR_PDCRB_PB6_Pos)

0x00000040

Definition at line 6791 of file stm32g431xx.h.

◆ PWR_PDCRB_PB6_Pos

#define PWR_PDCRB_PB6_Pos (6U)

Definition at line 6790 of file stm32g431xx.h.

◆ PWR_PDCRB_PB7

#define PWR_PDCRB_PB7 PWR_PDCRB_PB7_Msk

Port PB7 Pull-Down set

Definition at line 6789 of file stm32g431xx.h.

◆ PWR_PDCRB_PB7_Msk

#define PWR_PDCRB_PB7_Msk (0x1UL << PWR_PDCRB_PB7_Pos)

0x00000080

Definition at line 6788 of file stm32g431xx.h.

◆ PWR_PDCRB_PB7_Pos

#define PWR_PDCRB_PB7_Pos (7U)

Definition at line 6787 of file stm32g431xx.h.

◆ PWR_PDCRB_PB8

#define PWR_PDCRB_PB8 PWR_PDCRB_PB8_Msk

Port PB8 Pull-Down set

Definition at line 6786 of file stm32g431xx.h.

◆ PWR_PDCRB_PB8_Msk

#define PWR_PDCRB_PB8_Msk (0x1UL << PWR_PDCRB_PB8_Pos)

0x00000100

Definition at line 6785 of file stm32g431xx.h.

◆ PWR_PDCRB_PB8_Pos

#define PWR_PDCRB_PB8_Pos (8U)

Definition at line 6784 of file stm32g431xx.h.

◆ PWR_PDCRB_PB9

#define PWR_PDCRB_PB9 PWR_PDCRB_PB9_Msk

Port PB9 Pull-Down set

Definition at line 6783 of file stm32g431xx.h.

◆ PWR_PDCRB_PB9_Msk

#define PWR_PDCRB_PB9_Msk (0x1UL << PWR_PDCRB_PB9_Pos)

0x00000200

Definition at line 6782 of file stm32g431xx.h.

◆ PWR_PDCRB_PB9_Pos

#define PWR_PDCRB_PB9_Pos (9U)

Definition at line 6781 of file stm32g431xx.h.

◆ PWR_PDCRC_PC0

#define PWR_PDCRC_PC0 PWR_PDCRC_PC0_Msk

Port PC0 Pull-Down set

Definition at line 6907 of file stm32g431xx.h.

◆ PWR_PDCRC_PC0_Msk

#define PWR_PDCRC_PC0_Msk (0x1UL << PWR_PDCRC_PC0_Pos)

0x00000001

Definition at line 6906 of file stm32g431xx.h.

◆ PWR_PDCRC_PC0_Pos

#define PWR_PDCRC_PC0_Pos (0U)

Definition at line 6905 of file stm32g431xx.h.

◆ PWR_PDCRC_PC1

#define PWR_PDCRC_PC1 PWR_PDCRC_PC1_Msk

Port PC1 Pull-Down set

Definition at line 6904 of file stm32g431xx.h.

◆ PWR_PDCRC_PC10

#define PWR_PDCRC_PC10 PWR_PDCRC_PC10_Msk

Port PC10 Pull-Down set

Definition at line 6877 of file stm32g431xx.h.

◆ PWR_PDCRC_PC10_Msk

#define PWR_PDCRC_PC10_Msk (0x1UL << PWR_PDCRC_PC10_Pos)

0x00000400

Definition at line 6876 of file stm32g431xx.h.

◆ PWR_PDCRC_PC10_Pos

#define PWR_PDCRC_PC10_Pos (10U)

Definition at line 6875 of file stm32g431xx.h.

◆ PWR_PDCRC_PC11

#define PWR_PDCRC_PC11 PWR_PDCRC_PC11_Msk

Port PC11 Pull-Down set

Definition at line 6874 of file stm32g431xx.h.

◆ PWR_PDCRC_PC11_Msk

#define PWR_PDCRC_PC11_Msk (0x1UL << PWR_PDCRC_PC11_Pos)

0x00000800

Definition at line 6873 of file stm32g431xx.h.

◆ PWR_PDCRC_PC11_Pos

#define PWR_PDCRC_PC11_Pos (11U)

Definition at line 6872 of file stm32g431xx.h.

◆ PWR_PDCRC_PC12

#define PWR_PDCRC_PC12 PWR_PDCRC_PC12_Msk

Port PC12 Pull-Down set

Definition at line 6871 of file stm32g431xx.h.

◆ PWR_PDCRC_PC12_Msk

#define PWR_PDCRC_PC12_Msk (0x1UL << PWR_PDCRC_PC12_Pos)

0x00001000

Definition at line 6870 of file stm32g431xx.h.

◆ PWR_PDCRC_PC12_Pos

#define PWR_PDCRC_PC12_Pos (12U)

Definition at line 6869 of file stm32g431xx.h.

◆ PWR_PDCRC_PC13

#define PWR_PDCRC_PC13 PWR_PDCRC_PC13_Msk

Port PC13 Pull-Down set

Definition at line 6868 of file stm32g431xx.h.

◆ PWR_PDCRC_PC13_Msk

#define PWR_PDCRC_PC13_Msk (0x1UL << PWR_PDCRC_PC13_Pos)

0x00002000

Definition at line 6867 of file stm32g431xx.h.

◆ PWR_PDCRC_PC13_Pos

#define PWR_PDCRC_PC13_Pos (13U)

Definition at line 6866 of file stm32g431xx.h.

◆ PWR_PDCRC_PC14

#define PWR_PDCRC_PC14 PWR_PDCRC_PC14_Msk

Port PC14 Pull-Down set

Definition at line 6865 of file stm32g431xx.h.

◆ PWR_PDCRC_PC14_Msk

#define PWR_PDCRC_PC14_Msk (0x1UL << PWR_PDCRC_PC14_Pos)

0x00004000

Definition at line 6864 of file stm32g431xx.h.

◆ PWR_PDCRC_PC14_Pos

#define PWR_PDCRC_PC14_Pos (14U)

Definition at line 6863 of file stm32g431xx.h.

◆ PWR_PDCRC_PC15

#define PWR_PDCRC_PC15 PWR_PDCRC_PC15_Msk

Port PC15 Pull-Down set

Definition at line 6862 of file stm32g431xx.h.

◆ PWR_PDCRC_PC15_Msk

#define PWR_PDCRC_PC15_Msk (0x1UL << PWR_PDCRC_PC15_Pos)

0x00008000

Definition at line 6861 of file stm32g431xx.h.

◆ PWR_PDCRC_PC15_Pos

#define PWR_PDCRC_PC15_Pos (15U)

Definition at line 6860 of file stm32g431xx.h.

◆ PWR_PDCRC_PC1_Msk

#define PWR_PDCRC_PC1_Msk (0x1UL << PWR_PDCRC_PC1_Pos)

0x00000002

Definition at line 6903 of file stm32g431xx.h.

◆ PWR_PDCRC_PC1_Pos

#define PWR_PDCRC_PC1_Pos (1U)

Definition at line 6902 of file stm32g431xx.h.

◆ PWR_PDCRC_PC2

#define PWR_PDCRC_PC2 PWR_PDCRC_PC2_Msk

Port PC2 Pull-Down set

Definition at line 6901 of file stm32g431xx.h.

◆ PWR_PDCRC_PC2_Msk

#define PWR_PDCRC_PC2_Msk (0x1UL << PWR_PDCRC_PC2_Pos)

0x00000004

Definition at line 6900 of file stm32g431xx.h.

◆ PWR_PDCRC_PC2_Pos

#define PWR_PDCRC_PC2_Pos (2U)

Definition at line 6899 of file stm32g431xx.h.

◆ PWR_PDCRC_PC3

#define PWR_PDCRC_PC3 PWR_PDCRC_PC3_Msk

Port PC3 Pull-Down set

Definition at line 6898 of file stm32g431xx.h.

◆ PWR_PDCRC_PC3_Msk

#define PWR_PDCRC_PC3_Msk (0x1UL << PWR_PDCRC_PC3_Pos)

0x00000008

Definition at line 6897 of file stm32g431xx.h.

◆ PWR_PDCRC_PC3_Pos

#define PWR_PDCRC_PC3_Pos (3U)

Definition at line 6896 of file stm32g431xx.h.

◆ PWR_PDCRC_PC4

#define PWR_PDCRC_PC4 PWR_PDCRC_PC4_Msk

Port PC4 Pull-Down set

Definition at line 6895 of file stm32g431xx.h.

◆ PWR_PDCRC_PC4_Msk

#define PWR_PDCRC_PC4_Msk (0x1UL << PWR_PDCRC_PC4_Pos)

0x00000010

Definition at line 6894 of file stm32g431xx.h.

◆ PWR_PDCRC_PC4_Pos

#define PWR_PDCRC_PC4_Pos (4U)

Definition at line 6893 of file stm32g431xx.h.

◆ PWR_PDCRC_PC5

#define PWR_PDCRC_PC5 PWR_PDCRC_PC5_Msk

Port PC5 Pull-Down set

Definition at line 6892 of file stm32g431xx.h.

◆ PWR_PDCRC_PC5_Msk

#define PWR_PDCRC_PC5_Msk (0x1UL << PWR_PDCRC_PC5_Pos)

0x00000020

Definition at line 6891 of file stm32g431xx.h.

◆ PWR_PDCRC_PC5_Pos

#define PWR_PDCRC_PC5_Pos (5U)

Definition at line 6890 of file stm32g431xx.h.

◆ PWR_PDCRC_PC6

#define PWR_PDCRC_PC6 PWR_PDCRC_PC6_Msk

Port PC6 Pull-Down set

Definition at line 6889 of file stm32g431xx.h.

◆ PWR_PDCRC_PC6_Msk

#define PWR_PDCRC_PC6_Msk (0x1UL << PWR_PDCRC_PC6_Pos)

0x00000040

Definition at line 6888 of file stm32g431xx.h.

◆ PWR_PDCRC_PC6_Pos

#define PWR_PDCRC_PC6_Pos (6U)

Definition at line 6887 of file stm32g431xx.h.

◆ PWR_PDCRC_PC7

#define PWR_PDCRC_PC7 PWR_PDCRC_PC7_Msk

Port PC7 Pull-Down set

Definition at line 6886 of file stm32g431xx.h.

◆ PWR_PDCRC_PC7_Msk

#define PWR_PDCRC_PC7_Msk (0x1UL << PWR_PDCRC_PC7_Pos)

0x00000080

Definition at line 6885 of file stm32g431xx.h.

◆ PWR_PDCRC_PC7_Pos

#define PWR_PDCRC_PC7_Pos (7U)

Definition at line 6884 of file stm32g431xx.h.

◆ PWR_PDCRC_PC8

#define PWR_PDCRC_PC8 PWR_PDCRC_PC8_Msk

Port PC8 Pull-Down set

Definition at line 6883 of file stm32g431xx.h.

◆ PWR_PDCRC_PC8_Msk

#define PWR_PDCRC_PC8_Msk (0x1UL << PWR_PDCRC_PC8_Pos)

0x00000100

Definition at line 6882 of file stm32g431xx.h.

◆ PWR_PDCRC_PC8_Pos

#define PWR_PDCRC_PC8_Pos (8U)

Definition at line 6881 of file stm32g431xx.h.

◆ PWR_PDCRC_PC9

#define PWR_PDCRC_PC9 PWR_PDCRC_PC9_Msk

Port PC9 Pull-Down set

Definition at line 6880 of file stm32g431xx.h.

◆ PWR_PDCRC_PC9_Msk

#define PWR_PDCRC_PC9_Msk (0x1UL << PWR_PDCRC_PC9_Pos)

0x00000200

Definition at line 6879 of file stm32g431xx.h.

◆ PWR_PDCRC_PC9_Pos

#define PWR_PDCRC_PC9_Pos (9U)

Definition at line 6878 of file stm32g431xx.h.

◆ PWR_PDCRD_PD0

#define PWR_PDCRD_PD0 PWR_PDCRD_PD0_Msk

Port PD0 Pull-Down set

Definition at line 7007 of file stm32g431xx.h.

◆ PWR_PDCRD_PD0_Msk

#define PWR_PDCRD_PD0_Msk (0x1UL << PWR_PDCRD_PD0_Pos)

0x00000001

Definition at line 7006 of file stm32g431xx.h.

◆ PWR_PDCRD_PD0_Pos

#define PWR_PDCRD_PD0_Pos (0U)

Definition at line 7005 of file stm32g431xx.h.

◆ PWR_PDCRD_PD1

#define PWR_PDCRD_PD1 PWR_PDCRD_PD1_Msk

Port PD1 Pull-Down set

Definition at line 7004 of file stm32g431xx.h.

◆ PWR_PDCRD_PD10

#define PWR_PDCRD_PD10 PWR_PDCRD_PD10_Msk

Port PD10 Pull-Down set

Definition at line 6977 of file stm32g431xx.h.

◆ PWR_PDCRD_PD10_Msk

#define PWR_PDCRD_PD10_Msk (0x1UL << PWR_PDCRD_PD10_Pos)

0x00000400

Definition at line 6976 of file stm32g431xx.h.

◆ PWR_PDCRD_PD10_Pos

#define PWR_PDCRD_PD10_Pos (10U)

Definition at line 6975 of file stm32g431xx.h.

◆ PWR_PDCRD_PD11

#define PWR_PDCRD_PD11 PWR_PDCRD_PD11_Msk

Port PD11 Pull-Down set

Definition at line 6974 of file stm32g431xx.h.

◆ PWR_PDCRD_PD11_Msk

#define PWR_PDCRD_PD11_Msk (0x1UL << PWR_PDCRD_PD11_Pos)

0x00000800

Definition at line 6973 of file stm32g431xx.h.

◆ PWR_PDCRD_PD11_Pos

#define PWR_PDCRD_PD11_Pos (11U)

Definition at line 6972 of file stm32g431xx.h.

◆ PWR_PDCRD_PD12

#define PWR_PDCRD_PD12 PWR_PDCRD_PD12_Msk

Port PD12 Pull-Down set

Definition at line 6971 of file stm32g431xx.h.

◆ PWR_PDCRD_PD12_Msk

#define PWR_PDCRD_PD12_Msk (0x1UL << PWR_PDCRD_PD12_Pos)

0x00001000

Definition at line 6970 of file stm32g431xx.h.

◆ PWR_PDCRD_PD12_Pos

#define PWR_PDCRD_PD12_Pos (12U)

Definition at line 6969 of file stm32g431xx.h.

◆ PWR_PDCRD_PD13

#define PWR_PDCRD_PD13 PWR_PDCRD_PD13_Msk

Port PD13 Pull-Down set

Definition at line 6968 of file stm32g431xx.h.

◆ PWR_PDCRD_PD13_Msk

#define PWR_PDCRD_PD13_Msk (0x1UL << PWR_PDCRD_PD13_Pos)

0x00002000

Definition at line 6967 of file stm32g431xx.h.

◆ PWR_PDCRD_PD13_Pos

#define PWR_PDCRD_PD13_Pos (13U)

Definition at line 6966 of file stm32g431xx.h.

◆ PWR_PDCRD_PD14

#define PWR_PDCRD_PD14 PWR_PDCRD_PD14_Msk

Port PD14 Pull-Down set

Definition at line 6965 of file stm32g431xx.h.

◆ PWR_PDCRD_PD14_Msk

#define PWR_PDCRD_PD14_Msk (0x1UL << PWR_PDCRD_PD14_Pos)

0x00004000

Definition at line 6964 of file stm32g431xx.h.

◆ PWR_PDCRD_PD14_Pos

#define PWR_PDCRD_PD14_Pos (14U)

Definition at line 6963 of file stm32g431xx.h.

◆ PWR_PDCRD_PD15

#define PWR_PDCRD_PD15 PWR_PDCRD_PD15_Msk

Port PD15 Pull-Down set

Definition at line 6962 of file stm32g431xx.h.

◆ PWR_PDCRD_PD15_Msk

#define PWR_PDCRD_PD15_Msk (0x1UL << PWR_PDCRD_PD15_Pos)

0x00008000

Definition at line 6961 of file stm32g431xx.h.

◆ PWR_PDCRD_PD15_Pos

#define PWR_PDCRD_PD15_Pos (15U)

Definition at line 6960 of file stm32g431xx.h.

◆ PWR_PDCRD_PD1_Msk

#define PWR_PDCRD_PD1_Msk (0x1UL << PWR_PDCRD_PD1_Pos)

0x00000002

Definition at line 7003 of file stm32g431xx.h.

◆ PWR_PDCRD_PD1_Pos

#define PWR_PDCRD_PD1_Pos (1U)

Definition at line 7002 of file stm32g431xx.h.

◆ PWR_PDCRD_PD2

#define PWR_PDCRD_PD2 PWR_PDCRD_PD2_Msk

Port PD2 Pull-Down set

Definition at line 7001 of file stm32g431xx.h.

◆ PWR_PDCRD_PD2_Msk

#define PWR_PDCRD_PD2_Msk (0x1UL << PWR_PDCRD_PD2_Pos)

0x00000004

Definition at line 7000 of file stm32g431xx.h.

◆ PWR_PDCRD_PD2_Pos

#define PWR_PDCRD_PD2_Pos (2U)

Definition at line 6999 of file stm32g431xx.h.

◆ PWR_PDCRD_PD3

#define PWR_PDCRD_PD3 PWR_PDCRD_PD3_Msk

Port PD3 Pull-Down set

Definition at line 6998 of file stm32g431xx.h.

◆ PWR_PDCRD_PD3_Msk

#define PWR_PDCRD_PD3_Msk (0x1UL << PWR_PDCRD_PD3_Pos)

0x00000008

Definition at line 6997 of file stm32g431xx.h.

◆ PWR_PDCRD_PD3_Pos

#define PWR_PDCRD_PD3_Pos (3U)

Definition at line 6996 of file stm32g431xx.h.

◆ PWR_PDCRD_PD4

#define PWR_PDCRD_PD4 PWR_PDCRD_PD4_Msk

Port PD4 Pull-Down set

Definition at line 6995 of file stm32g431xx.h.

◆ PWR_PDCRD_PD4_Msk

#define PWR_PDCRD_PD4_Msk (0x1UL << PWR_PDCRD_PD4_Pos)

0x00000010

Definition at line 6994 of file stm32g431xx.h.

◆ PWR_PDCRD_PD4_Pos

#define PWR_PDCRD_PD4_Pos (4U)

Definition at line 6993 of file stm32g431xx.h.

◆ PWR_PDCRD_PD5

#define PWR_PDCRD_PD5 PWR_PDCRD_PD5_Msk

Port PD5 Pull-Down set

Definition at line 6992 of file stm32g431xx.h.

◆ PWR_PDCRD_PD5_Msk

#define PWR_PDCRD_PD5_Msk (0x1UL << PWR_PDCRD_PD5_Pos)

0x00000020

Definition at line 6991 of file stm32g431xx.h.

◆ PWR_PDCRD_PD5_Pos

#define PWR_PDCRD_PD5_Pos (5U)

Definition at line 6990 of file stm32g431xx.h.

◆ PWR_PDCRD_PD6

#define PWR_PDCRD_PD6 PWR_PDCRD_PD6_Msk

Port PD6 Pull-Down set

Definition at line 6989 of file stm32g431xx.h.

◆ PWR_PDCRD_PD6_Msk

#define PWR_PDCRD_PD6_Msk (0x1UL << PWR_PDCRD_PD6_Pos)

0x00000040

Definition at line 6988 of file stm32g431xx.h.

◆ PWR_PDCRD_PD6_Pos

#define PWR_PDCRD_PD6_Pos (6U)

Definition at line 6987 of file stm32g431xx.h.

◆ PWR_PDCRD_PD7

#define PWR_PDCRD_PD7 PWR_PDCRD_PD7_Msk

Port PD7 Pull-Down set

Definition at line 6986 of file stm32g431xx.h.

◆ PWR_PDCRD_PD7_Msk

#define PWR_PDCRD_PD7_Msk (0x1UL << PWR_PDCRD_PD7_Pos)

0x00000080

Definition at line 6985 of file stm32g431xx.h.

◆ PWR_PDCRD_PD7_Pos

#define PWR_PDCRD_PD7_Pos (7U)

Definition at line 6984 of file stm32g431xx.h.

◆ PWR_PDCRD_PD8

#define PWR_PDCRD_PD8 PWR_PDCRD_PD8_Msk

Port PD8 Pull-Down set

Definition at line 6983 of file stm32g431xx.h.

◆ PWR_PDCRD_PD8_Msk

#define PWR_PDCRD_PD8_Msk (0x1UL << PWR_PDCRD_PD8_Pos)

0x00000100

Definition at line 6982 of file stm32g431xx.h.

◆ PWR_PDCRD_PD8_Pos

#define PWR_PDCRD_PD8_Pos (8U)

Definition at line 6981 of file stm32g431xx.h.

◆ PWR_PDCRD_PD9

#define PWR_PDCRD_PD9 PWR_PDCRD_PD9_Msk

Port PD9 Pull-Down set

Definition at line 6980 of file stm32g431xx.h.

◆ PWR_PDCRD_PD9_Msk

#define PWR_PDCRD_PD9_Msk (0x1UL << PWR_PDCRD_PD9_Pos)

0x00000200

Definition at line 6979 of file stm32g431xx.h.

◆ PWR_PDCRD_PD9_Pos

#define PWR_PDCRD_PD9_Pos (9U)

Definition at line 6978 of file stm32g431xx.h.

◆ PWR_PDCRE_PE0

#define PWR_PDCRE_PE0 PWR_PDCRE_PE0_Msk

Port PE0 Pull-Down set

Definition at line 7107 of file stm32g431xx.h.

◆ PWR_PDCRE_PE0_Msk

#define PWR_PDCRE_PE0_Msk (0x1UL << PWR_PDCRE_PE0_Pos)

0x00000001

Definition at line 7106 of file stm32g431xx.h.

◆ PWR_PDCRE_PE0_Pos

#define PWR_PDCRE_PE0_Pos (0U)

Definition at line 7105 of file stm32g431xx.h.

◆ PWR_PDCRE_PE1

#define PWR_PDCRE_PE1 PWR_PDCRE_PE1_Msk

Port PE1 Pull-Down set

Definition at line 7104 of file stm32g431xx.h.

◆ PWR_PDCRE_PE10

#define PWR_PDCRE_PE10 PWR_PDCRE_PE10_Msk

Port PE10 Pull-Down set

Definition at line 7077 of file stm32g431xx.h.

◆ PWR_PDCRE_PE10_Msk

#define PWR_PDCRE_PE10_Msk (0x1UL << PWR_PDCRE_PE10_Pos)

0x00000400

Definition at line 7076 of file stm32g431xx.h.

◆ PWR_PDCRE_PE10_Pos

#define PWR_PDCRE_PE10_Pos (10U)

Definition at line 7075 of file stm32g431xx.h.

◆ PWR_PDCRE_PE11

#define PWR_PDCRE_PE11 PWR_PDCRE_PE11_Msk

Port PE11 Pull-Down set

Definition at line 7074 of file stm32g431xx.h.

◆ PWR_PDCRE_PE11_Msk

#define PWR_PDCRE_PE11_Msk (0x1UL << PWR_PDCRE_PE11_Pos)

0x00000800

Definition at line 7073 of file stm32g431xx.h.

◆ PWR_PDCRE_PE11_Pos

#define PWR_PDCRE_PE11_Pos (11U)

Definition at line 7072 of file stm32g431xx.h.

◆ PWR_PDCRE_PE12

#define PWR_PDCRE_PE12 PWR_PDCRE_PE12_Msk

Port PE12 Pull-Down set

Definition at line 7071 of file stm32g431xx.h.

◆ PWR_PDCRE_PE12_Msk

#define PWR_PDCRE_PE12_Msk (0x1UL << PWR_PDCRE_PE12_Pos)

0x00001000

Definition at line 7070 of file stm32g431xx.h.

◆ PWR_PDCRE_PE12_Pos

#define PWR_PDCRE_PE12_Pos (12U)

Definition at line 7069 of file stm32g431xx.h.

◆ PWR_PDCRE_PE13

#define PWR_PDCRE_PE13 PWR_PDCRE_PE13_Msk

Port PE13 Pull-Down set

Definition at line 7068 of file stm32g431xx.h.

◆ PWR_PDCRE_PE13_Msk

#define PWR_PDCRE_PE13_Msk (0x1UL << PWR_PDCRE_PE13_Pos)

0x00002000

Definition at line 7067 of file stm32g431xx.h.

◆ PWR_PDCRE_PE13_Pos

#define PWR_PDCRE_PE13_Pos (13U)

Definition at line 7066 of file stm32g431xx.h.

◆ PWR_PDCRE_PE14

#define PWR_PDCRE_PE14 PWR_PDCRE_PE14_Msk

Port PE14 Pull-Down set

Definition at line 7065 of file stm32g431xx.h.

◆ PWR_PDCRE_PE14_Msk

#define PWR_PDCRE_PE14_Msk (0x1UL << PWR_PDCRE_PE14_Pos)

0x00004000

Definition at line 7064 of file stm32g431xx.h.

◆ PWR_PDCRE_PE14_Pos

#define PWR_PDCRE_PE14_Pos (14U)

Definition at line 7063 of file stm32g431xx.h.

◆ PWR_PDCRE_PE15

#define PWR_PDCRE_PE15 PWR_PDCRE_PE15_Msk

Port PE15 Pull-Down set

Definition at line 7062 of file stm32g431xx.h.

◆ PWR_PDCRE_PE15_Msk

#define PWR_PDCRE_PE15_Msk (0x1UL << PWR_PDCRE_PE15_Pos)

0x00008000

Definition at line 7061 of file stm32g431xx.h.

◆ PWR_PDCRE_PE15_Pos

#define PWR_PDCRE_PE15_Pos (15U)

Definition at line 7060 of file stm32g431xx.h.

◆ PWR_PDCRE_PE1_Msk

#define PWR_PDCRE_PE1_Msk (0x1UL << PWR_PDCRE_PE1_Pos)

0x00000002

Definition at line 7103 of file stm32g431xx.h.

◆ PWR_PDCRE_PE1_Pos

#define PWR_PDCRE_PE1_Pos (1U)

Definition at line 7102 of file stm32g431xx.h.

◆ PWR_PDCRE_PE2

#define PWR_PDCRE_PE2 PWR_PDCRE_PE2_Msk

Port PE2 Pull-Down set

Definition at line 7101 of file stm32g431xx.h.

◆ PWR_PDCRE_PE2_Msk

#define PWR_PDCRE_PE2_Msk (0x1UL << PWR_PDCRE_PE2_Pos)

0x00000004

Definition at line 7100 of file stm32g431xx.h.

◆ PWR_PDCRE_PE2_Pos

#define PWR_PDCRE_PE2_Pos (2U)

Definition at line 7099 of file stm32g431xx.h.

◆ PWR_PDCRE_PE3

#define PWR_PDCRE_PE3 PWR_PDCRE_PE3_Msk

Port PE3 Pull-Down set

Definition at line 7098 of file stm32g431xx.h.

◆ PWR_PDCRE_PE3_Msk

#define PWR_PDCRE_PE3_Msk (0x1UL << PWR_PDCRE_PE3_Pos)

0x00000008

Definition at line 7097 of file stm32g431xx.h.

◆ PWR_PDCRE_PE3_Pos

#define PWR_PDCRE_PE3_Pos (3U)

Definition at line 7096 of file stm32g431xx.h.

◆ PWR_PDCRE_PE4

#define PWR_PDCRE_PE4 PWR_PDCRE_PE4_Msk

Port PE4 Pull-Down set

Definition at line 7095 of file stm32g431xx.h.

◆ PWR_PDCRE_PE4_Msk

#define PWR_PDCRE_PE4_Msk (0x1UL << PWR_PDCRE_PE4_Pos)

0x00000010

Definition at line 7094 of file stm32g431xx.h.

◆ PWR_PDCRE_PE4_Pos

#define PWR_PDCRE_PE4_Pos (4U)

Definition at line 7093 of file stm32g431xx.h.

◆ PWR_PDCRE_PE5

#define PWR_PDCRE_PE5 PWR_PDCRE_PE5_Msk

Port PE5 Pull-Down set

Definition at line 7092 of file stm32g431xx.h.

◆ PWR_PDCRE_PE5_Msk

#define PWR_PDCRE_PE5_Msk (0x1UL << PWR_PDCRE_PE5_Pos)

0x00000020

Definition at line 7091 of file stm32g431xx.h.

◆ PWR_PDCRE_PE5_Pos

#define PWR_PDCRE_PE5_Pos (5U)

Definition at line 7090 of file stm32g431xx.h.

◆ PWR_PDCRE_PE6

#define PWR_PDCRE_PE6 PWR_PDCRE_PE6_Msk

Port PE6 Pull-Down set

Definition at line 7089 of file stm32g431xx.h.

◆ PWR_PDCRE_PE6_Msk

#define PWR_PDCRE_PE6_Msk (0x1UL << PWR_PDCRE_PE6_Pos)

0x00000040

Definition at line 7088 of file stm32g431xx.h.

◆ PWR_PDCRE_PE6_Pos

#define PWR_PDCRE_PE6_Pos (6U)

Definition at line 7087 of file stm32g431xx.h.

◆ PWR_PDCRE_PE7

#define PWR_PDCRE_PE7 PWR_PDCRE_PE7_Msk

Port PE7 Pull-Down set

Definition at line 7086 of file stm32g431xx.h.

◆ PWR_PDCRE_PE7_Msk

#define PWR_PDCRE_PE7_Msk (0x1UL << PWR_PDCRE_PE7_Pos)

0x00000080

Definition at line 7085 of file stm32g431xx.h.

◆ PWR_PDCRE_PE7_Pos

#define PWR_PDCRE_PE7_Pos (7U)

Definition at line 7084 of file stm32g431xx.h.

◆ PWR_PDCRE_PE8

#define PWR_PDCRE_PE8 PWR_PDCRE_PE8_Msk

Port PE8 Pull-Down set

Definition at line 7083 of file stm32g431xx.h.

◆ PWR_PDCRE_PE8_Msk

#define PWR_PDCRE_PE8_Msk (0x1UL << PWR_PDCRE_PE8_Pos)

0x00000100

Definition at line 7082 of file stm32g431xx.h.

◆ PWR_PDCRE_PE8_Pos

#define PWR_PDCRE_PE8_Pos (8U)

Definition at line 7081 of file stm32g431xx.h.

◆ PWR_PDCRE_PE9

#define PWR_PDCRE_PE9 PWR_PDCRE_PE9_Msk

Port PE9 Pull-Down set

Definition at line 7080 of file stm32g431xx.h.

◆ PWR_PDCRE_PE9_Msk

#define PWR_PDCRE_PE9_Msk (0x1UL << PWR_PDCRE_PE9_Pos)

0x00000200

Definition at line 7079 of file stm32g431xx.h.

◆ PWR_PDCRE_PE9_Pos

#define PWR_PDCRE_PE9_Pos (9U)

Definition at line 7078 of file stm32g431xx.h.

◆ PWR_PDCRF_PF0

#define PWR_PDCRF_PF0 PWR_PDCRF_PF0_Msk

Port PF0 Pull-Down set

Definition at line 7174 of file stm32g431xx.h.

◆ PWR_PDCRF_PF0_Msk

#define PWR_PDCRF_PF0_Msk (0x1UL << PWR_PDCRF_PF0_Pos)

0x00000001

Definition at line 7173 of file stm32g431xx.h.

◆ PWR_PDCRF_PF0_Pos

#define PWR_PDCRF_PF0_Pos (0U)

Definition at line 7172 of file stm32g431xx.h.

◆ PWR_PDCRF_PF1

#define PWR_PDCRF_PF1 PWR_PDCRF_PF1_Msk

Port PF1 Pull-Down set

Definition at line 7171 of file stm32g431xx.h.

◆ PWR_PDCRF_PF10

#define PWR_PDCRF_PF10 PWR_PDCRF_PF10_Msk

Port PF10 Pull-Down set

Definition at line 7162 of file stm32g431xx.h.

◆ PWR_PDCRF_PF10_Msk

#define PWR_PDCRF_PF10_Msk (0x1UL << PWR_PDCRF_PF10_Pos)

0x00000400

Definition at line 7161 of file stm32g431xx.h.

◆ PWR_PDCRF_PF10_Pos

#define PWR_PDCRF_PF10_Pos (10U)

Definition at line 7160 of file stm32g431xx.h.

◆ PWR_PDCRF_PF1_Msk

#define PWR_PDCRF_PF1_Msk (0x1UL << PWR_PDCRF_PF1_Pos)

0x00000002

Definition at line 7170 of file stm32g431xx.h.

◆ PWR_PDCRF_PF1_Pos

#define PWR_PDCRF_PF1_Pos (1U)

Definition at line 7169 of file stm32g431xx.h.

◆ PWR_PDCRF_PF2

#define PWR_PDCRF_PF2 PWR_PDCRF_PF2_Msk

Port PF2 Pull-Down set

Definition at line 7168 of file stm32g431xx.h.

◆ PWR_PDCRF_PF2_Msk

#define PWR_PDCRF_PF2_Msk (0x1UL << PWR_PDCRF_PF2_Pos)

0x00000004

Definition at line 7167 of file stm32g431xx.h.

◆ PWR_PDCRF_PF2_Pos

#define PWR_PDCRF_PF2_Pos (2U)

Definition at line 7166 of file stm32g431xx.h.

◆ PWR_PDCRF_PF9

#define PWR_PDCRF_PF9 PWR_PDCRF_PF9_Msk

Port PF9 Pull-Down set

Definition at line 7165 of file stm32g431xx.h.

◆ PWR_PDCRF_PF9_Msk

#define PWR_PDCRF_PF9_Msk (0x1UL << PWR_PDCRF_PF9_Pos)

0x00000200

Definition at line 7164 of file stm32g431xx.h.

◆ PWR_PDCRF_PF9_Pos

#define PWR_PDCRF_PF9_Pos (9U)

Definition at line 7163 of file stm32g431xx.h.

◆ PWR_PDCRG_PG0

#define PWR_PDCRG_PG0 PWR_PDCRG_PG0_Msk

Port PG0 Pull-Down set

Definition at line 7214 of file stm32g431xx.h.

◆ PWR_PDCRG_PG0_Msk

#define PWR_PDCRG_PG0_Msk (0x1UL << PWR_PDCRG_PG0_Pos)

0x00000001

Definition at line 7213 of file stm32g431xx.h.

◆ PWR_PDCRG_PG0_Pos

#define PWR_PDCRG_PG0_Pos (0U)

Definition at line 7212 of file stm32g431xx.h.

◆ PWR_PDCRG_PG1

#define PWR_PDCRG_PG1 PWR_PDCRG_PG1_Msk

Port PG1 Pull-Down set

Definition at line 7211 of file stm32g431xx.h.

◆ PWR_PDCRG_PG10

#define PWR_PDCRG_PG10 PWR_PDCRG_PG10_Msk

Port PG10 Pull-Down set

Definition at line 7184 of file stm32g431xx.h.

◆ PWR_PDCRG_PG10_Msk

#define PWR_PDCRG_PG10_Msk (0x1UL << PWR_PDCRG_PG10_Pos)

0x00000400

Definition at line 7183 of file stm32g431xx.h.

◆ PWR_PDCRG_PG10_Pos

#define PWR_PDCRG_PG10_Pos (10U)

Definition at line 7182 of file stm32g431xx.h.

◆ PWR_PDCRG_PG1_Msk

#define PWR_PDCRG_PG1_Msk (0x1UL << PWR_PDCRG_PG1_Pos)

0x00000002

Definition at line 7210 of file stm32g431xx.h.

◆ PWR_PDCRG_PG1_Pos

#define PWR_PDCRG_PG1_Pos (1U)

Definition at line 7209 of file stm32g431xx.h.

◆ PWR_PDCRG_PG2

#define PWR_PDCRG_PG2 PWR_PDCRG_PG2_Msk

Port PG2 Pull-Down set

Definition at line 7208 of file stm32g431xx.h.

◆ PWR_PDCRG_PG2_Msk

#define PWR_PDCRG_PG2_Msk (0x1UL << PWR_PDCRG_PG2_Pos)

0x00000004

Definition at line 7207 of file stm32g431xx.h.

◆ PWR_PDCRG_PG2_Pos

#define PWR_PDCRG_PG2_Pos (2U)

Definition at line 7206 of file stm32g431xx.h.

◆ PWR_PDCRG_PG3

#define PWR_PDCRG_PG3 PWR_PDCRG_PG3_Msk

Port PG3 Pull-Down set

Definition at line 7205 of file stm32g431xx.h.

◆ PWR_PDCRG_PG3_Msk

#define PWR_PDCRG_PG3_Msk (0x1UL << PWR_PDCRG_PG3_Pos)

0x00000008

Definition at line 7204 of file stm32g431xx.h.

◆ PWR_PDCRG_PG3_Pos

#define PWR_PDCRG_PG3_Pos (3U)

Definition at line 7203 of file stm32g431xx.h.

◆ PWR_PDCRG_PG4

#define PWR_PDCRG_PG4 PWR_PDCRG_PG4_Msk

Port PG4 Pull-Down set

Definition at line 7202 of file stm32g431xx.h.

◆ PWR_PDCRG_PG4_Msk

#define PWR_PDCRG_PG4_Msk (0x1UL << PWR_PDCRG_PG4_Pos)

0x00000010

Definition at line 7201 of file stm32g431xx.h.

◆ PWR_PDCRG_PG4_Pos

#define PWR_PDCRG_PG4_Pos (4U)

Definition at line 7200 of file stm32g431xx.h.

◆ PWR_PDCRG_PG5

#define PWR_PDCRG_PG5 PWR_PDCRG_PG5_Msk

Port PG5 Pull-Down set

Definition at line 7199 of file stm32g431xx.h.

◆ PWR_PDCRG_PG5_Msk

#define PWR_PDCRG_PG5_Msk (0x1UL << PWR_PDCRG_PG5_Pos)

0x00000020

Definition at line 7198 of file stm32g431xx.h.

◆ PWR_PDCRG_PG5_Pos

#define PWR_PDCRG_PG5_Pos (5U)

Definition at line 7197 of file stm32g431xx.h.

◆ PWR_PDCRG_PG6

#define PWR_PDCRG_PG6 PWR_PDCRG_PG6_Msk

Port PG6 Pull-Down set

Definition at line 7196 of file stm32g431xx.h.

◆ PWR_PDCRG_PG6_Msk

#define PWR_PDCRG_PG6_Msk (0x1UL << PWR_PDCRG_PG6_Pos)

0x00000040

Definition at line 7195 of file stm32g431xx.h.

◆ PWR_PDCRG_PG6_Pos

#define PWR_PDCRG_PG6_Pos (6U)

Definition at line 7194 of file stm32g431xx.h.

◆ PWR_PDCRG_PG7

#define PWR_PDCRG_PG7 PWR_PDCRG_PG7_Msk

Port PG7 Pull-Down set

Definition at line 7193 of file stm32g431xx.h.

◆ PWR_PDCRG_PG7_Msk

#define PWR_PDCRG_PG7_Msk (0x1UL << PWR_PDCRG_PG7_Pos)

0x00000080

Definition at line 7192 of file stm32g431xx.h.

◆ PWR_PDCRG_PG7_Pos

#define PWR_PDCRG_PG7_Pos (7U)

Definition at line 7191 of file stm32g431xx.h.

◆ PWR_PDCRG_PG8

#define PWR_PDCRG_PG8 PWR_PDCRG_PG8_Msk

Port PG8 Pull-Down set

Definition at line 7190 of file stm32g431xx.h.

◆ PWR_PDCRG_PG8_Msk

#define PWR_PDCRG_PG8_Msk (0x1UL << PWR_PDCRG_PG8_Pos)

0x00000100

Definition at line 7189 of file stm32g431xx.h.

◆ PWR_PDCRG_PG8_Pos

#define PWR_PDCRG_PG8_Pos (8U)

Definition at line 7188 of file stm32g431xx.h.

◆ PWR_PDCRG_PG9

#define PWR_PDCRG_PG9 PWR_PDCRG_PG9_Msk

Port PG9 Pull-Down set

Definition at line 7187 of file stm32g431xx.h.

◆ PWR_PDCRG_PG9_Msk

#define PWR_PDCRG_PG9_Msk (0x1UL << PWR_PDCRG_PG9_Pos)

0x00000200

Definition at line 7186 of file stm32g431xx.h.

◆ PWR_PDCRG_PG9_Pos

#define PWR_PDCRG_PG9_Pos (9U)

Definition at line 7185 of file stm32g431xx.h.

◆ PWR_PUCRA_PA0

#define PWR_PUCRA_PA0 PWR_PUCRA_PA0_Msk

Port PA0 Pull-Up set

Definition at line 6665 of file stm32g431xx.h.

◆ PWR_PUCRA_PA0_Msk

#define PWR_PUCRA_PA0_Msk (0x1UL << PWR_PUCRA_PA0_Pos)

0x00000001

Definition at line 6664 of file stm32g431xx.h.

◆ PWR_PUCRA_PA0_Pos

#define PWR_PUCRA_PA0_Pos (0U)

Definition at line 6663 of file stm32g431xx.h.

◆ PWR_PUCRA_PA1

#define PWR_PUCRA_PA1 PWR_PUCRA_PA1_Msk

Port PA1 Pull-Up set

Definition at line 6662 of file stm32g431xx.h.

◆ PWR_PUCRA_PA10

#define PWR_PUCRA_PA10 PWR_PUCRA_PA10_Msk

Port PA10 Pull-Up set

Definition at line 6635 of file stm32g431xx.h.

◆ PWR_PUCRA_PA10_Msk

#define PWR_PUCRA_PA10_Msk (0x1UL << PWR_PUCRA_PA10_Pos)

0x00000400

Definition at line 6634 of file stm32g431xx.h.

◆ PWR_PUCRA_PA10_Pos

#define PWR_PUCRA_PA10_Pos (10U)

Definition at line 6633 of file stm32g431xx.h.

◆ PWR_PUCRA_PA11

#define PWR_PUCRA_PA11 PWR_PUCRA_PA11_Msk

Port PA11 Pull-Up set

Definition at line 6632 of file stm32g431xx.h.

◆ PWR_PUCRA_PA11_Msk

#define PWR_PUCRA_PA11_Msk (0x1UL << PWR_PUCRA_PA11_Pos)

0x00000800

Definition at line 6631 of file stm32g431xx.h.

◆ PWR_PUCRA_PA11_Pos

#define PWR_PUCRA_PA11_Pos (11U)

Definition at line 6630 of file stm32g431xx.h.

◆ PWR_PUCRA_PA12

#define PWR_PUCRA_PA12 PWR_PUCRA_PA12_Msk

Port PA12 Pull-Up set

Definition at line 6629 of file stm32g431xx.h.

◆ PWR_PUCRA_PA12_Msk

#define PWR_PUCRA_PA12_Msk (0x1UL << PWR_PUCRA_PA12_Pos)

0x00001000

Definition at line 6628 of file stm32g431xx.h.

◆ PWR_PUCRA_PA12_Pos

#define PWR_PUCRA_PA12_Pos (12U)

Definition at line 6627 of file stm32g431xx.h.

◆ PWR_PUCRA_PA13

#define PWR_PUCRA_PA13 PWR_PUCRA_PA13_Msk

Port PA13 Pull-Up set

Definition at line 6626 of file stm32g431xx.h.

◆ PWR_PUCRA_PA13_Msk

#define PWR_PUCRA_PA13_Msk (0x1UL << PWR_PUCRA_PA13_Pos)

0x00002000

Definition at line 6625 of file stm32g431xx.h.

◆ PWR_PUCRA_PA13_Pos

#define PWR_PUCRA_PA13_Pos (13U)

Definition at line 6624 of file stm32g431xx.h.

◆ PWR_PUCRA_PA15

#define PWR_PUCRA_PA15 PWR_PUCRA_PA15_Msk

Port PA15 Pull-Up set

Definition at line 6623 of file stm32g431xx.h.

◆ PWR_PUCRA_PA15_Msk

#define PWR_PUCRA_PA15_Msk (0x1UL << PWR_PUCRA_PA15_Pos)

0x00008000

Definition at line 6622 of file stm32g431xx.h.

◆ PWR_PUCRA_PA15_Pos

#define PWR_PUCRA_PA15_Pos (15U)

Definition at line 6621 of file stm32g431xx.h.

◆ PWR_PUCRA_PA1_Msk

#define PWR_PUCRA_PA1_Msk (0x1UL << PWR_PUCRA_PA1_Pos)

0x00000002

Definition at line 6661 of file stm32g431xx.h.

◆ PWR_PUCRA_PA1_Pos

#define PWR_PUCRA_PA1_Pos (1U)

Definition at line 6660 of file stm32g431xx.h.

◆ PWR_PUCRA_PA2

#define PWR_PUCRA_PA2 PWR_PUCRA_PA2_Msk

Port PA2 Pull-Up set

Definition at line 6659 of file stm32g431xx.h.

◆ PWR_PUCRA_PA2_Msk

#define PWR_PUCRA_PA2_Msk (0x1UL << PWR_PUCRA_PA2_Pos)

0x00000004

Definition at line 6658 of file stm32g431xx.h.

◆ PWR_PUCRA_PA2_Pos

#define PWR_PUCRA_PA2_Pos (2U)

Definition at line 6657 of file stm32g431xx.h.

◆ PWR_PUCRA_PA3

#define PWR_PUCRA_PA3 PWR_PUCRA_PA3_Msk

Port PA3 Pull-Up set

Definition at line 6656 of file stm32g431xx.h.

◆ PWR_PUCRA_PA3_Msk

#define PWR_PUCRA_PA3_Msk (0x1UL << PWR_PUCRA_PA3_Pos)

0x00000008

Definition at line 6655 of file stm32g431xx.h.

◆ PWR_PUCRA_PA3_Pos

#define PWR_PUCRA_PA3_Pos (3U)

Definition at line 6654 of file stm32g431xx.h.

◆ PWR_PUCRA_PA4

#define PWR_PUCRA_PA4 PWR_PUCRA_PA4_Msk

Port PA4 Pull-Up set

Definition at line 6653 of file stm32g431xx.h.

◆ PWR_PUCRA_PA4_Msk

#define PWR_PUCRA_PA4_Msk (0x1UL << PWR_PUCRA_PA4_Pos)

0x00000010

Definition at line 6652 of file stm32g431xx.h.

◆ PWR_PUCRA_PA4_Pos

#define PWR_PUCRA_PA4_Pos (4U)

Definition at line 6651 of file stm32g431xx.h.

◆ PWR_PUCRA_PA5

#define PWR_PUCRA_PA5 PWR_PUCRA_PA5_Msk

Port PA5 Pull-Up set

Definition at line 6650 of file stm32g431xx.h.

◆ PWR_PUCRA_PA5_Msk

#define PWR_PUCRA_PA5_Msk (0x1UL << PWR_PUCRA_PA5_Pos)

0x00000020

Definition at line 6649 of file stm32g431xx.h.

◆ PWR_PUCRA_PA5_Pos

#define PWR_PUCRA_PA5_Pos (5U)

Definition at line 6648 of file stm32g431xx.h.

◆ PWR_PUCRA_PA6

#define PWR_PUCRA_PA6 PWR_PUCRA_PA6_Msk

Port PA6 Pull-Up set

Definition at line 6647 of file stm32g431xx.h.

◆ PWR_PUCRA_PA6_Msk

#define PWR_PUCRA_PA6_Msk (0x1UL << PWR_PUCRA_PA6_Pos)

0x00000040

Definition at line 6646 of file stm32g431xx.h.

◆ PWR_PUCRA_PA6_Pos

#define PWR_PUCRA_PA6_Pos (6U)

Definition at line 6645 of file stm32g431xx.h.

◆ PWR_PUCRA_PA7

#define PWR_PUCRA_PA7 PWR_PUCRA_PA7_Msk

Port PA7 Pull-Up set

Definition at line 6644 of file stm32g431xx.h.

◆ PWR_PUCRA_PA7_Msk

#define PWR_PUCRA_PA7_Msk (0x1UL << PWR_PUCRA_PA7_Pos)

0x00000080

Definition at line 6643 of file stm32g431xx.h.

◆ PWR_PUCRA_PA7_Pos

#define PWR_PUCRA_PA7_Pos (7U)

Definition at line 6642 of file stm32g431xx.h.

◆ PWR_PUCRA_PA8

#define PWR_PUCRA_PA8 PWR_PUCRA_PA8_Msk

Port PA8 Pull-Up set

Definition at line 6641 of file stm32g431xx.h.

◆ PWR_PUCRA_PA8_Msk

#define PWR_PUCRA_PA8_Msk (0x1UL << PWR_PUCRA_PA8_Pos)

0x00000100

Definition at line 6640 of file stm32g431xx.h.

◆ PWR_PUCRA_PA8_Pos

#define PWR_PUCRA_PA8_Pos (8U)

Definition at line 6639 of file stm32g431xx.h.

◆ PWR_PUCRA_PA9

#define PWR_PUCRA_PA9 PWR_PUCRA_PA9_Msk

Port PA9 Pull-Up set

Definition at line 6638 of file stm32g431xx.h.

◆ PWR_PUCRA_PA9_Msk

#define PWR_PUCRA_PA9_Msk (0x1UL << PWR_PUCRA_PA9_Pos)

0x00000200

Definition at line 6637 of file stm32g431xx.h.

◆ PWR_PUCRA_PA9_Pos

#define PWR_PUCRA_PA9_Pos (9U)

Definition at line 6636 of file stm32g431xx.h.

◆ PWR_PUCRB_PB0

#define PWR_PUCRB_PB0 PWR_PUCRB_PB0_Msk

Port PB0 Pull-Up set

Definition at line 6760 of file stm32g431xx.h.

◆ PWR_PUCRB_PB0_Msk

#define PWR_PUCRB_PB0_Msk (0x1UL << PWR_PUCRB_PB0_Pos)

0x00000001

Definition at line 6759 of file stm32g431xx.h.

◆ PWR_PUCRB_PB0_Pos

#define PWR_PUCRB_PB0_Pos (0U)

Definition at line 6758 of file stm32g431xx.h.

◆ PWR_PUCRB_PB1

#define PWR_PUCRB_PB1 PWR_PUCRB_PB1_Msk

Port PB1 Pull-Up set

Definition at line 6757 of file stm32g431xx.h.

◆ PWR_PUCRB_PB10

#define PWR_PUCRB_PB10 PWR_PUCRB_PB10_Msk

Port PB10 Pull-Up set

Definition at line 6730 of file stm32g431xx.h.

◆ PWR_PUCRB_PB10_Msk

#define PWR_PUCRB_PB10_Msk (0x1UL << PWR_PUCRB_PB10_Pos)

0x00000400

Definition at line 6729 of file stm32g431xx.h.

◆ PWR_PUCRB_PB10_Pos

#define PWR_PUCRB_PB10_Pos (10U)

Definition at line 6728 of file stm32g431xx.h.

◆ PWR_PUCRB_PB11

#define PWR_PUCRB_PB11 PWR_PUCRB_PB11_Msk

Port PB11 Pull-Up set

Definition at line 6727 of file stm32g431xx.h.

◆ PWR_PUCRB_PB11_Msk

#define PWR_PUCRB_PB11_Msk (0x1UL << PWR_PUCRB_PB11_Pos)

0x00000800

Definition at line 6726 of file stm32g431xx.h.

◆ PWR_PUCRB_PB11_Pos

#define PWR_PUCRB_PB11_Pos (11U)

Definition at line 6725 of file stm32g431xx.h.

◆ PWR_PUCRB_PB12

#define PWR_PUCRB_PB12 PWR_PUCRB_PB12_Msk

Port PB12 Pull-Up set

Definition at line 6724 of file stm32g431xx.h.

◆ PWR_PUCRB_PB12_Msk

#define PWR_PUCRB_PB12_Msk (0x1UL << PWR_PUCRB_PB12_Pos)

0x00001000

Definition at line 6723 of file stm32g431xx.h.

◆ PWR_PUCRB_PB12_Pos

#define PWR_PUCRB_PB12_Pos (12U)

Definition at line 6722 of file stm32g431xx.h.

◆ PWR_PUCRB_PB13

#define PWR_PUCRB_PB13 PWR_PUCRB_PB13_Msk

Port PB13 Pull-Up set

Definition at line 6721 of file stm32g431xx.h.

◆ PWR_PUCRB_PB13_Msk

#define PWR_PUCRB_PB13_Msk (0x1UL << PWR_PUCRB_PB13_Pos)

0x00002000

Definition at line 6720 of file stm32g431xx.h.

◆ PWR_PUCRB_PB13_Pos

#define PWR_PUCRB_PB13_Pos (13U)

Definition at line 6719 of file stm32g431xx.h.

◆ PWR_PUCRB_PB14

#define PWR_PUCRB_PB14 PWR_PUCRB_PB14_Msk

Port PB14 Pull-Up set

Definition at line 6718 of file stm32g431xx.h.

◆ PWR_PUCRB_PB14_Msk

#define PWR_PUCRB_PB14_Msk (0x1UL << PWR_PUCRB_PB14_Pos)

0x00004000

Definition at line 6717 of file stm32g431xx.h.

◆ PWR_PUCRB_PB14_Pos

#define PWR_PUCRB_PB14_Pos (14U)

Definition at line 6716 of file stm32g431xx.h.

◆ PWR_PUCRB_PB15

#define PWR_PUCRB_PB15 PWR_PUCRB_PB15_Msk

Port PB15 Pull-Up set

Definition at line 6715 of file stm32g431xx.h.

◆ PWR_PUCRB_PB15_Msk

#define PWR_PUCRB_PB15_Msk (0x1UL << PWR_PUCRB_PB15_Pos)

0x00008000

Definition at line 6714 of file stm32g431xx.h.

◆ PWR_PUCRB_PB15_Pos

#define PWR_PUCRB_PB15_Pos (15U)

Definition at line 6713 of file stm32g431xx.h.

◆ PWR_PUCRB_PB1_Msk

#define PWR_PUCRB_PB1_Msk (0x1UL << PWR_PUCRB_PB1_Pos)

0x00000002

Definition at line 6756 of file stm32g431xx.h.

◆ PWR_PUCRB_PB1_Pos

#define PWR_PUCRB_PB1_Pos (1U)

Definition at line 6755 of file stm32g431xx.h.

◆ PWR_PUCRB_PB2

#define PWR_PUCRB_PB2 PWR_PUCRB_PB2_Msk

Port PB2 Pull-Up set

Definition at line 6754 of file stm32g431xx.h.

◆ PWR_PUCRB_PB2_Msk

#define PWR_PUCRB_PB2_Msk (0x1UL << PWR_PUCRB_PB2_Pos)

0x00000004

Definition at line 6753 of file stm32g431xx.h.

◆ PWR_PUCRB_PB2_Pos

#define PWR_PUCRB_PB2_Pos (2U)

Definition at line 6752 of file stm32g431xx.h.

◆ PWR_PUCRB_PB3

#define PWR_PUCRB_PB3 PWR_PUCRB_PB3_Msk

Port PB3 Pull-Up set

Definition at line 6751 of file stm32g431xx.h.

◆ PWR_PUCRB_PB3_Msk

#define PWR_PUCRB_PB3_Msk (0x1UL << PWR_PUCRB_PB3_Pos)

0x00000008

Definition at line 6750 of file stm32g431xx.h.

◆ PWR_PUCRB_PB3_Pos

#define PWR_PUCRB_PB3_Pos (3U)

Definition at line 6749 of file stm32g431xx.h.

◆ PWR_PUCRB_PB4

#define PWR_PUCRB_PB4 PWR_PUCRB_PB4_Msk

Port PB4 Pull-Up set

Definition at line 6748 of file stm32g431xx.h.

◆ PWR_PUCRB_PB4_Msk

#define PWR_PUCRB_PB4_Msk (0x1UL << PWR_PUCRB_PB4_Pos)

0x00000010

Definition at line 6747 of file stm32g431xx.h.

◆ PWR_PUCRB_PB4_Pos

#define PWR_PUCRB_PB4_Pos (4U)

Definition at line 6746 of file stm32g431xx.h.

◆ PWR_PUCRB_PB5

#define PWR_PUCRB_PB5 PWR_PUCRB_PB5_Msk

Port PB5 Pull-Up set

Definition at line 6745 of file stm32g431xx.h.

◆ PWR_PUCRB_PB5_Msk

#define PWR_PUCRB_PB5_Msk (0x1UL << PWR_PUCRB_PB5_Pos)

0x00000020

Definition at line 6744 of file stm32g431xx.h.

◆ PWR_PUCRB_PB5_Pos

#define PWR_PUCRB_PB5_Pos (5U)

Definition at line 6743 of file stm32g431xx.h.

◆ PWR_PUCRB_PB6

#define PWR_PUCRB_PB6 PWR_PUCRB_PB6_Msk

Port PB6 Pull-Up set

Definition at line 6742 of file stm32g431xx.h.

◆ PWR_PUCRB_PB6_Msk

#define PWR_PUCRB_PB6_Msk (0x1UL << PWR_PUCRB_PB6_Pos)

0x00000040

Definition at line 6741 of file stm32g431xx.h.

◆ PWR_PUCRB_PB6_Pos

#define PWR_PUCRB_PB6_Pos (6U)

Definition at line 6740 of file stm32g431xx.h.

◆ PWR_PUCRB_PB7

#define PWR_PUCRB_PB7 PWR_PUCRB_PB7_Msk

Port PB7 Pull-Up set

Definition at line 6739 of file stm32g431xx.h.

◆ PWR_PUCRB_PB7_Msk

#define PWR_PUCRB_PB7_Msk (0x1UL << PWR_PUCRB_PB7_Pos)

0x00000080

Definition at line 6738 of file stm32g431xx.h.

◆ PWR_PUCRB_PB7_Pos

#define PWR_PUCRB_PB7_Pos (7U)

Definition at line 6737 of file stm32g431xx.h.

◆ PWR_PUCRB_PB8

#define PWR_PUCRB_PB8 PWR_PUCRB_PB8_Msk

Port PB8 Pull-Up set

Definition at line 6736 of file stm32g431xx.h.

◆ PWR_PUCRB_PB8_Msk

#define PWR_PUCRB_PB8_Msk (0x1UL << PWR_PUCRB_PB8_Pos)

0x00000100

Definition at line 6735 of file stm32g431xx.h.

◆ PWR_PUCRB_PB8_Pos

#define PWR_PUCRB_PB8_Pos (8U)

Definition at line 6734 of file stm32g431xx.h.

◆ PWR_PUCRB_PB9

#define PWR_PUCRB_PB9 PWR_PUCRB_PB9_Msk

Port PB9 Pull-Up set

Definition at line 6733 of file stm32g431xx.h.

◆ PWR_PUCRB_PB9_Msk

#define PWR_PUCRB_PB9_Msk (0x1UL << PWR_PUCRB_PB9_Pos)

0x00000200

Definition at line 6732 of file stm32g431xx.h.

◆ PWR_PUCRB_PB9_Pos

#define PWR_PUCRB_PB9_Pos (9U)

Definition at line 6731 of file stm32g431xx.h.

◆ PWR_PUCRC_PC0

#define PWR_PUCRC_PC0 PWR_PUCRC_PC0_Msk

Port PC0 Pull-Up set

Definition at line 6857 of file stm32g431xx.h.

◆ PWR_PUCRC_PC0_Msk

#define PWR_PUCRC_PC0_Msk (0x1UL << PWR_PUCRC_PC0_Pos)

0x00000001

Definition at line 6856 of file stm32g431xx.h.

◆ PWR_PUCRC_PC0_Pos

#define PWR_PUCRC_PC0_Pos (0U)

Definition at line 6855 of file stm32g431xx.h.

◆ PWR_PUCRC_PC1

#define PWR_PUCRC_PC1 PWR_PUCRC_PC1_Msk

Port PC1 Pull-Up set

Definition at line 6854 of file stm32g431xx.h.

◆ PWR_PUCRC_PC10

#define PWR_PUCRC_PC10 PWR_PUCRC_PC10_Msk

Port PC10 Pull-Up set

Definition at line 6827 of file stm32g431xx.h.

◆ PWR_PUCRC_PC10_Msk

#define PWR_PUCRC_PC10_Msk (0x1UL << PWR_PUCRC_PC10_Pos)

0x00000400

Definition at line 6826 of file stm32g431xx.h.

◆ PWR_PUCRC_PC10_Pos

#define PWR_PUCRC_PC10_Pos (10U)

Definition at line 6825 of file stm32g431xx.h.

◆ PWR_PUCRC_PC11

#define PWR_PUCRC_PC11 PWR_PUCRC_PC11_Msk

Port PC11 Pull-Up set

Definition at line 6824 of file stm32g431xx.h.

◆ PWR_PUCRC_PC11_Msk

#define PWR_PUCRC_PC11_Msk (0x1UL << PWR_PUCRC_PC11_Pos)

0x00000800

Definition at line 6823 of file stm32g431xx.h.

◆ PWR_PUCRC_PC11_Pos

#define PWR_PUCRC_PC11_Pos (11U)

Definition at line 6822 of file stm32g431xx.h.

◆ PWR_PUCRC_PC12

#define PWR_PUCRC_PC12 PWR_PUCRC_PC12_Msk

Port PC12 Pull-Up set

Definition at line 6821 of file stm32g431xx.h.

◆ PWR_PUCRC_PC12_Msk

#define PWR_PUCRC_PC12_Msk (0x1UL << PWR_PUCRC_PC12_Pos)

0x00001000

Definition at line 6820 of file stm32g431xx.h.

◆ PWR_PUCRC_PC12_Pos

#define PWR_PUCRC_PC12_Pos (12U)

Definition at line 6819 of file stm32g431xx.h.

◆ PWR_PUCRC_PC13

#define PWR_PUCRC_PC13 PWR_PUCRC_PC13_Msk

Port PC13 Pull-Up set

Definition at line 6818 of file stm32g431xx.h.

◆ PWR_PUCRC_PC13_Msk

#define PWR_PUCRC_PC13_Msk (0x1UL << PWR_PUCRC_PC13_Pos)

0x00002000

Definition at line 6817 of file stm32g431xx.h.

◆ PWR_PUCRC_PC13_Pos

#define PWR_PUCRC_PC13_Pos (13U)

Definition at line 6816 of file stm32g431xx.h.

◆ PWR_PUCRC_PC14

#define PWR_PUCRC_PC14 PWR_PUCRC_PC14_Msk

Port PC14 Pull-Up set

Definition at line 6815 of file stm32g431xx.h.

◆ PWR_PUCRC_PC14_Msk

#define PWR_PUCRC_PC14_Msk (0x1UL << PWR_PUCRC_PC14_Pos)

0x00004000

Definition at line 6814 of file stm32g431xx.h.

◆ PWR_PUCRC_PC14_Pos

#define PWR_PUCRC_PC14_Pos (14U)

Definition at line 6813 of file stm32g431xx.h.

◆ PWR_PUCRC_PC15

#define PWR_PUCRC_PC15 PWR_PUCRC_PC15_Msk

Port PC15 Pull-Up set

Definition at line 6812 of file stm32g431xx.h.

◆ PWR_PUCRC_PC15_Msk

#define PWR_PUCRC_PC15_Msk (0x1UL << PWR_PUCRC_PC15_Pos)

0x00008000

Definition at line 6811 of file stm32g431xx.h.

◆ PWR_PUCRC_PC15_Pos

#define PWR_PUCRC_PC15_Pos (15U)

Definition at line 6810 of file stm32g431xx.h.

◆ PWR_PUCRC_PC1_Msk

#define PWR_PUCRC_PC1_Msk (0x1UL << PWR_PUCRC_PC1_Pos)

0x00000002

Definition at line 6853 of file stm32g431xx.h.

◆ PWR_PUCRC_PC1_Pos

#define PWR_PUCRC_PC1_Pos (1U)

Definition at line 6852 of file stm32g431xx.h.

◆ PWR_PUCRC_PC2

#define PWR_PUCRC_PC2 PWR_PUCRC_PC2_Msk

Port PC2 Pull-Up set

Definition at line 6851 of file stm32g431xx.h.

◆ PWR_PUCRC_PC2_Msk

#define PWR_PUCRC_PC2_Msk (0x1UL << PWR_PUCRC_PC2_Pos)

0x00000004

Definition at line 6850 of file stm32g431xx.h.

◆ PWR_PUCRC_PC2_Pos

#define PWR_PUCRC_PC2_Pos (2U)

Definition at line 6849 of file stm32g431xx.h.

◆ PWR_PUCRC_PC3

#define PWR_PUCRC_PC3 PWR_PUCRC_PC3_Msk

Port PC3 Pull-Up set

Definition at line 6848 of file stm32g431xx.h.

◆ PWR_PUCRC_PC3_Msk

#define PWR_PUCRC_PC3_Msk (0x1UL << PWR_PUCRC_PC3_Pos)

0x00000008

Definition at line 6847 of file stm32g431xx.h.

◆ PWR_PUCRC_PC3_Pos

#define PWR_PUCRC_PC3_Pos (3U)

Definition at line 6846 of file stm32g431xx.h.

◆ PWR_PUCRC_PC4

#define PWR_PUCRC_PC4 PWR_PUCRC_PC4_Msk

Port PC4 Pull-Up set

Definition at line 6845 of file stm32g431xx.h.

◆ PWR_PUCRC_PC4_Msk

#define PWR_PUCRC_PC4_Msk (0x1UL << PWR_PUCRC_PC4_Pos)

0x00000010

Definition at line 6844 of file stm32g431xx.h.

◆ PWR_PUCRC_PC4_Pos

#define PWR_PUCRC_PC4_Pos (4U)

Definition at line 6843 of file stm32g431xx.h.

◆ PWR_PUCRC_PC5

#define PWR_PUCRC_PC5 PWR_PUCRC_PC5_Msk

Port PC5 Pull-Up set

Definition at line 6842 of file stm32g431xx.h.

◆ PWR_PUCRC_PC5_Msk

#define PWR_PUCRC_PC5_Msk (0x1UL << PWR_PUCRC_PC5_Pos)

0x00000020

Definition at line 6841 of file stm32g431xx.h.

◆ PWR_PUCRC_PC5_Pos

#define PWR_PUCRC_PC5_Pos (5U)

Definition at line 6840 of file stm32g431xx.h.

◆ PWR_PUCRC_PC6

#define PWR_PUCRC_PC6 PWR_PUCRC_PC6_Msk

Port PC6 Pull-Up set

Definition at line 6839 of file stm32g431xx.h.

◆ PWR_PUCRC_PC6_Msk

#define PWR_PUCRC_PC6_Msk (0x1UL << PWR_PUCRC_PC6_Pos)

0x00000040

Definition at line 6838 of file stm32g431xx.h.

◆ PWR_PUCRC_PC6_Pos

#define PWR_PUCRC_PC6_Pos (6U)

Definition at line 6837 of file stm32g431xx.h.

◆ PWR_PUCRC_PC7

#define PWR_PUCRC_PC7 PWR_PUCRC_PC7_Msk

Port PC7 Pull-Up set

Definition at line 6836 of file stm32g431xx.h.

◆ PWR_PUCRC_PC7_Msk

#define PWR_PUCRC_PC7_Msk (0x1UL << PWR_PUCRC_PC7_Pos)

0x00000080

Definition at line 6835 of file stm32g431xx.h.

◆ PWR_PUCRC_PC7_Pos

#define PWR_PUCRC_PC7_Pos (7U)

Definition at line 6834 of file stm32g431xx.h.

◆ PWR_PUCRC_PC8

#define PWR_PUCRC_PC8 PWR_PUCRC_PC8_Msk

Port PC8 Pull-Up set

Definition at line 6833 of file stm32g431xx.h.

◆ PWR_PUCRC_PC8_Msk

#define PWR_PUCRC_PC8_Msk (0x1UL << PWR_PUCRC_PC8_Pos)

0x00000100

Definition at line 6832 of file stm32g431xx.h.

◆ PWR_PUCRC_PC8_Pos

#define PWR_PUCRC_PC8_Pos (8U)

Definition at line 6831 of file stm32g431xx.h.

◆ PWR_PUCRC_PC9

#define PWR_PUCRC_PC9 PWR_PUCRC_PC9_Msk

Port PC9 Pull-Up set

Definition at line 6830 of file stm32g431xx.h.

◆ PWR_PUCRC_PC9_Msk

#define PWR_PUCRC_PC9_Msk (0x1UL << PWR_PUCRC_PC9_Pos)

0x00000200

Definition at line 6829 of file stm32g431xx.h.

◆ PWR_PUCRC_PC9_Pos

#define PWR_PUCRC_PC9_Pos (9U)

Definition at line 6828 of file stm32g431xx.h.

◆ PWR_PUCRD_PD0

#define PWR_PUCRD_PD0 PWR_PUCRD_PD0_Msk

Port PD0 Pull-Up set

Definition at line 6957 of file stm32g431xx.h.

◆ PWR_PUCRD_PD0_Msk

#define PWR_PUCRD_PD0_Msk (0x1UL << PWR_PUCRD_PD0_Pos)

0x00000001

Definition at line 6956 of file stm32g431xx.h.

◆ PWR_PUCRD_PD0_Pos

#define PWR_PUCRD_PD0_Pos (0U)

Definition at line 6955 of file stm32g431xx.h.

◆ PWR_PUCRD_PD1

#define PWR_PUCRD_PD1 PWR_PUCRD_PD1_Msk

Port PD1 Pull-Up set

Definition at line 6954 of file stm32g431xx.h.

◆ PWR_PUCRD_PD10

#define PWR_PUCRD_PD10 PWR_PUCRD_PD10_Msk

Port PD10 Pull-Up set

Definition at line 6927 of file stm32g431xx.h.

◆ PWR_PUCRD_PD10_Msk

#define PWR_PUCRD_PD10_Msk (0x1UL << PWR_PUCRD_PD10_Pos)

0x00000400

Definition at line 6926 of file stm32g431xx.h.

◆ PWR_PUCRD_PD10_Pos

#define PWR_PUCRD_PD10_Pos (10U)

Definition at line 6925 of file stm32g431xx.h.

◆ PWR_PUCRD_PD11

#define PWR_PUCRD_PD11 PWR_PUCRD_PD11_Msk

Port PD11 Pull-Up set

Definition at line 6924 of file stm32g431xx.h.

◆ PWR_PUCRD_PD11_Msk

#define PWR_PUCRD_PD11_Msk (0x1UL << PWR_PUCRD_PD11_Pos)

0x00000800

Definition at line 6923 of file stm32g431xx.h.

◆ PWR_PUCRD_PD11_Pos

#define PWR_PUCRD_PD11_Pos (11U)

Definition at line 6922 of file stm32g431xx.h.

◆ PWR_PUCRD_PD12

#define PWR_PUCRD_PD12 PWR_PUCRD_PD12_Msk

Port PD12 Pull-Up set

Definition at line 6921 of file stm32g431xx.h.

◆ PWR_PUCRD_PD12_Msk

#define PWR_PUCRD_PD12_Msk (0x1UL << PWR_PUCRD_PD12_Pos)

0x00001000

Definition at line 6920 of file stm32g431xx.h.

◆ PWR_PUCRD_PD12_Pos

#define PWR_PUCRD_PD12_Pos (12U)

Definition at line 6919 of file stm32g431xx.h.

◆ PWR_PUCRD_PD13

#define PWR_PUCRD_PD13 PWR_PUCRD_PD13_Msk

Port PD13 Pull-Up set

Definition at line 6918 of file stm32g431xx.h.

◆ PWR_PUCRD_PD13_Msk

#define PWR_PUCRD_PD13_Msk (0x1UL << PWR_PUCRD_PD13_Pos)

0x00002000

Definition at line 6917 of file stm32g431xx.h.

◆ PWR_PUCRD_PD13_Pos

#define PWR_PUCRD_PD13_Pos (13U)

Definition at line 6916 of file stm32g431xx.h.

◆ PWR_PUCRD_PD14

#define PWR_PUCRD_PD14 PWR_PUCRD_PD14_Msk

Port PD14 Pull-Up set

Definition at line 6915 of file stm32g431xx.h.

◆ PWR_PUCRD_PD14_Msk

#define PWR_PUCRD_PD14_Msk (0x1UL << PWR_PUCRD_PD14_Pos)

0x00004000

Definition at line 6914 of file stm32g431xx.h.

◆ PWR_PUCRD_PD14_Pos

#define PWR_PUCRD_PD14_Pos (14U)

Definition at line 6913 of file stm32g431xx.h.

◆ PWR_PUCRD_PD15

#define PWR_PUCRD_PD15 PWR_PUCRD_PD15_Msk

Port PD15 Pull-Up set

Definition at line 6912 of file stm32g431xx.h.

◆ PWR_PUCRD_PD15_Msk

#define PWR_PUCRD_PD15_Msk (0x1UL << PWR_PUCRD_PD15_Pos)

0x00008000

Definition at line 6911 of file stm32g431xx.h.

◆ PWR_PUCRD_PD15_Pos

#define PWR_PUCRD_PD15_Pos (15U)

Definition at line 6910 of file stm32g431xx.h.

◆ PWR_PUCRD_PD1_Msk

#define PWR_PUCRD_PD1_Msk (0x1UL << PWR_PUCRD_PD1_Pos)

0x00000002

Definition at line 6953 of file stm32g431xx.h.

◆ PWR_PUCRD_PD1_Pos

#define PWR_PUCRD_PD1_Pos (1U)

Definition at line 6952 of file stm32g431xx.h.

◆ PWR_PUCRD_PD2

#define PWR_PUCRD_PD2 PWR_PUCRD_PD2_Msk

Port PD2 Pull-Up set

Definition at line 6951 of file stm32g431xx.h.

◆ PWR_PUCRD_PD2_Msk

#define PWR_PUCRD_PD2_Msk (0x1UL << PWR_PUCRD_PD2_Pos)

0x00000004

Definition at line 6950 of file stm32g431xx.h.

◆ PWR_PUCRD_PD2_Pos

#define PWR_PUCRD_PD2_Pos (2U)

Definition at line 6949 of file stm32g431xx.h.

◆ PWR_PUCRD_PD3

#define PWR_PUCRD_PD3 PWR_PUCRD_PD3_Msk

Port PD3 Pull-Up set

Definition at line 6948 of file stm32g431xx.h.

◆ PWR_PUCRD_PD3_Msk

#define PWR_PUCRD_PD3_Msk (0x1UL << PWR_PUCRD_PD3_Pos)

0x00000008

Definition at line 6947 of file stm32g431xx.h.

◆ PWR_PUCRD_PD3_Pos

#define PWR_PUCRD_PD3_Pos (3U)

Definition at line 6946 of file stm32g431xx.h.

◆ PWR_PUCRD_PD4

#define PWR_PUCRD_PD4 PWR_PUCRD_PD4_Msk

Port PD4 Pull-Up set

Definition at line 6945 of file stm32g431xx.h.

◆ PWR_PUCRD_PD4_Msk

#define PWR_PUCRD_PD4_Msk (0x1UL << PWR_PUCRD_PD4_Pos)

0x00000010

Definition at line 6944 of file stm32g431xx.h.

◆ PWR_PUCRD_PD4_Pos

#define PWR_PUCRD_PD4_Pos (4U)

Definition at line 6943 of file stm32g431xx.h.

◆ PWR_PUCRD_PD5

#define PWR_PUCRD_PD5 PWR_PUCRD_PD5_Msk

Port PD5 Pull-Up set

Definition at line 6942 of file stm32g431xx.h.

◆ PWR_PUCRD_PD5_Msk

#define PWR_PUCRD_PD5_Msk (0x1UL << PWR_PUCRD_PD5_Pos)

0x00000020

Definition at line 6941 of file stm32g431xx.h.

◆ PWR_PUCRD_PD5_Pos

#define PWR_PUCRD_PD5_Pos (5U)

Definition at line 6940 of file stm32g431xx.h.

◆ PWR_PUCRD_PD6

#define PWR_PUCRD_PD6 PWR_PUCRD_PD6_Msk

Port PD6 Pull-Up set

Definition at line 6939 of file stm32g431xx.h.

◆ PWR_PUCRD_PD6_Msk

#define PWR_PUCRD_PD6_Msk (0x1UL << PWR_PUCRD_PD6_Pos)

0x00000040

Definition at line 6938 of file stm32g431xx.h.

◆ PWR_PUCRD_PD6_Pos

#define PWR_PUCRD_PD6_Pos (6U)

Definition at line 6937 of file stm32g431xx.h.

◆ PWR_PUCRD_PD7

#define PWR_PUCRD_PD7 PWR_PUCRD_PD7_Msk

Port PD7 Pull-Up set

Definition at line 6936 of file stm32g431xx.h.

◆ PWR_PUCRD_PD7_Msk

#define PWR_PUCRD_PD7_Msk (0x1UL << PWR_PUCRD_PD7_Pos)

0x00000080

Definition at line 6935 of file stm32g431xx.h.

◆ PWR_PUCRD_PD7_Pos

#define PWR_PUCRD_PD7_Pos (7U)

Definition at line 6934 of file stm32g431xx.h.

◆ PWR_PUCRD_PD8

#define PWR_PUCRD_PD8 PWR_PUCRD_PD8_Msk

Port PD8 Pull-Up set

Definition at line 6933 of file stm32g431xx.h.

◆ PWR_PUCRD_PD8_Msk

#define PWR_PUCRD_PD8_Msk (0x1UL << PWR_PUCRD_PD8_Pos)

0x00000100

Definition at line 6932 of file stm32g431xx.h.

◆ PWR_PUCRD_PD8_Pos

#define PWR_PUCRD_PD8_Pos (8U)

Definition at line 6931 of file stm32g431xx.h.

◆ PWR_PUCRD_PD9

#define PWR_PUCRD_PD9 PWR_PUCRD_PD9_Msk

Port PD9 Pull-Up set

Definition at line 6930 of file stm32g431xx.h.

◆ PWR_PUCRD_PD9_Msk

#define PWR_PUCRD_PD9_Msk (0x1UL << PWR_PUCRD_PD9_Pos)

0x00000200

Definition at line 6929 of file stm32g431xx.h.

◆ PWR_PUCRD_PD9_Pos

#define PWR_PUCRD_PD9_Pos (9U)

Definition at line 6928 of file stm32g431xx.h.

◆ PWR_PUCRE_PE0

#define PWR_PUCRE_PE0 PWR_PUCRE_PE0_Msk

Port PE0 Pull-Up set

Definition at line 7057 of file stm32g431xx.h.

◆ PWR_PUCRE_PE0_Msk

#define PWR_PUCRE_PE0_Msk (0x1UL << PWR_PUCRE_PE0_Pos)

0x00000001

Definition at line 7056 of file stm32g431xx.h.

◆ PWR_PUCRE_PE0_Pos

#define PWR_PUCRE_PE0_Pos (0U)

Definition at line 7055 of file stm32g431xx.h.

◆ PWR_PUCRE_PE1

#define PWR_PUCRE_PE1 PWR_PUCRE_PE1_Msk

Port PE1 Pull-Up set

Definition at line 7054 of file stm32g431xx.h.

◆ PWR_PUCRE_PE10

#define PWR_PUCRE_PE10 PWR_PUCRE_PE10_Msk

Port PE10 Pull-Up set

Definition at line 7027 of file stm32g431xx.h.

◆ PWR_PUCRE_PE10_Msk

#define PWR_PUCRE_PE10_Msk (0x1UL << PWR_PUCRE_PE10_Pos)

0x00000400

Definition at line 7026 of file stm32g431xx.h.

◆ PWR_PUCRE_PE10_Pos

#define PWR_PUCRE_PE10_Pos (10U)

Definition at line 7025 of file stm32g431xx.h.

◆ PWR_PUCRE_PE11

#define PWR_PUCRE_PE11 PWR_PUCRE_PE11_Msk

Port PE11 Pull-Up set

Definition at line 7024 of file stm32g431xx.h.

◆ PWR_PUCRE_PE11_Msk

#define PWR_PUCRE_PE11_Msk (0x1UL << PWR_PUCRE_PE11_Pos)

0x00000800

Definition at line 7023 of file stm32g431xx.h.

◆ PWR_PUCRE_PE11_Pos

#define PWR_PUCRE_PE11_Pos (11U)

Definition at line 7022 of file stm32g431xx.h.

◆ PWR_PUCRE_PE12

#define PWR_PUCRE_PE12 PWR_PUCRE_PE12_Msk

Port PE12 Pull-Up set

Definition at line 7021 of file stm32g431xx.h.

◆ PWR_PUCRE_PE12_Msk

#define PWR_PUCRE_PE12_Msk (0x1UL << PWR_PUCRE_PE12_Pos)

0x00001000

Definition at line 7020 of file stm32g431xx.h.

◆ PWR_PUCRE_PE12_Pos

#define PWR_PUCRE_PE12_Pos (12U)

Definition at line 7019 of file stm32g431xx.h.

◆ PWR_PUCRE_PE13

#define PWR_PUCRE_PE13 PWR_PUCRE_PE13_Msk

Port PE13 Pull-Up set

Definition at line 7018 of file stm32g431xx.h.

◆ PWR_PUCRE_PE13_Msk

#define PWR_PUCRE_PE13_Msk (0x1UL << PWR_PUCRE_PE13_Pos)

0x00002000

Definition at line 7017 of file stm32g431xx.h.

◆ PWR_PUCRE_PE13_Pos

#define PWR_PUCRE_PE13_Pos (13U)

Definition at line 7016 of file stm32g431xx.h.

◆ PWR_PUCRE_PE14

#define PWR_PUCRE_PE14 PWR_PUCRE_PE14_Msk

Port PE14 Pull-Up set

Definition at line 7015 of file stm32g431xx.h.

◆ PWR_PUCRE_PE14_Msk

#define PWR_PUCRE_PE14_Msk (0x1UL << PWR_PUCRE_PE14_Pos)

0x00004000

Definition at line 7014 of file stm32g431xx.h.

◆ PWR_PUCRE_PE14_Pos

#define PWR_PUCRE_PE14_Pos (14U)

Definition at line 7013 of file stm32g431xx.h.

◆ PWR_PUCRE_PE15

#define PWR_PUCRE_PE15 PWR_PUCRE_PE15_Msk

Port PE15 Pull-Up set

Definition at line 7012 of file stm32g431xx.h.

◆ PWR_PUCRE_PE15_Msk

#define PWR_PUCRE_PE15_Msk (0x1UL << PWR_PUCRE_PE15_Pos)

0x00008000

Definition at line 7011 of file stm32g431xx.h.

◆ PWR_PUCRE_PE15_Pos

#define PWR_PUCRE_PE15_Pos (15U)

Definition at line 7010 of file stm32g431xx.h.

◆ PWR_PUCRE_PE1_Msk

#define PWR_PUCRE_PE1_Msk (0x1UL << PWR_PUCRE_PE1_Pos)

0x00000002

Definition at line 7053 of file stm32g431xx.h.

◆ PWR_PUCRE_PE1_Pos

#define PWR_PUCRE_PE1_Pos (1U)

Definition at line 7052 of file stm32g431xx.h.

◆ PWR_PUCRE_PE2

#define PWR_PUCRE_PE2 PWR_PUCRE_PE2_Msk

Port PE2 Pull-Up set

Definition at line 7051 of file stm32g431xx.h.

◆ PWR_PUCRE_PE2_Msk

#define PWR_PUCRE_PE2_Msk (0x1UL << PWR_PUCRE_PE2_Pos)

0x00000004

Definition at line 7050 of file stm32g431xx.h.

◆ PWR_PUCRE_PE2_Pos

#define PWR_PUCRE_PE2_Pos (2U)

Definition at line 7049 of file stm32g431xx.h.

◆ PWR_PUCRE_PE3

#define PWR_PUCRE_PE3 PWR_PUCRE_PE3_Msk

Port PE3 Pull-Up set

Definition at line 7048 of file stm32g431xx.h.

◆ PWR_PUCRE_PE3_Msk

#define PWR_PUCRE_PE3_Msk (0x1UL << PWR_PUCRE_PE3_Pos)

0x00000008

Definition at line 7047 of file stm32g431xx.h.

◆ PWR_PUCRE_PE3_Pos

#define PWR_PUCRE_PE3_Pos (3U)

Definition at line 7046 of file stm32g431xx.h.

◆ PWR_PUCRE_PE4

#define PWR_PUCRE_PE4 PWR_PUCRE_PE4_Msk

Port PE4 Pull-Up set

Definition at line 7045 of file stm32g431xx.h.

◆ PWR_PUCRE_PE4_Msk

#define PWR_PUCRE_PE4_Msk (0x1UL << PWR_PUCRE_PE4_Pos)

0x00000010

Definition at line 7044 of file stm32g431xx.h.

◆ PWR_PUCRE_PE4_Pos

#define PWR_PUCRE_PE4_Pos (4U)

Definition at line 7043 of file stm32g431xx.h.

◆ PWR_PUCRE_PE5

#define PWR_PUCRE_PE5 PWR_PUCRE_PE5_Msk

Port PE5 Pull-Up set

Definition at line 7042 of file stm32g431xx.h.

◆ PWR_PUCRE_PE5_Msk

#define PWR_PUCRE_PE5_Msk (0x1UL << PWR_PUCRE_PE5_Pos)

0x00000020

Definition at line 7041 of file stm32g431xx.h.

◆ PWR_PUCRE_PE5_Pos

#define PWR_PUCRE_PE5_Pos (5U)

Definition at line 7040 of file stm32g431xx.h.

◆ PWR_PUCRE_PE6

#define PWR_PUCRE_PE6 PWR_PUCRE_PE6_Msk

Port PE6 Pull-Up set

Definition at line 7039 of file stm32g431xx.h.

◆ PWR_PUCRE_PE6_Msk

#define PWR_PUCRE_PE6_Msk (0x1UL << PWR_PUCRE_PE6_Pos)

0x00000040

Definition at line 7038 of file stm32g431xx.h.

◆ PWR_PUCRE_PE6_Pos

#define PWR_PUCRE_PE6_Pos (6U)

Definition at line 7037 of file stm32g431xx.h.

◆ PWR_PUCRE_PE7

#define PWR_PUCRE_PE7 PWR_PUCRE_PE7_Msk

Port PE7 Pull-Up set

Definition at line 7036 of file stm32g431xx.h.

◆ PWR_PUCRE_PE7_Msk

#define PWR_PUCRE_PE7_Msk (0x1UL << PWR_PUCRE_PE7_Pos)

0x00000080

Definition at line 7035 of file stm32g431xx.h.

◆ PWR_PUCRE_PE7_Pos

#define PWR_PUCRE_PE7_Pos (7U)

Definition at line 7034 of file stm32g431xx.h.

◆ PWR_PUCRE_PE8

#define PWR_PUCRE_PE8 PWR_PUCRE_PE8_Msk

Port PE8 Pull-Up set

Definition at line 7033 of file stm32g431xx.h.

◆ PWR_PUCRE_PE8_Msk

#define PWR_PUCRE_PE8_Msk (0x1UL << PWR_PUCRE_PE8_Pos)

0x00000100

Definition at line 7032 of file stm32g431xx.h.

◆ PWR_PUCRE_PE8_Pos

#define PWR_PUCRE_PE8_Pos (8U)

Definition at line 7031 of file stm32g431xx.h.

◆ PWR_PUCRE_PE9

#define PWR_PUCRE_PE9 PWR_PUCRE_PE9_Msk

Port PE9 Pull-Up set

Definition at line 7030 of file stm32g431xx.h.

◆ PWR_PUCRE_PE9_Msk

#define PWR_PUCRE_PE9_Msk (0x1UL << PWR_PUCRE_PE9_Pos)

0x00000200

Definition at line 7029 of file stm32g431xx.h.

◆ PWR_PUCRE_PE9_Pos

#define PWR_PUCRE_PE9_Pos (9U)

Definition at line 7028 of file stm32g431xx.h.

◆ PWR_PUCRF_PF0

#define PWR_PUCRF_PF0 PWR_PUCRF_PF0_Msk

Port PF0 Pull-Up set

Definition at line 7157 of file stm32g431xx.h.

◆ PWR_PUCRF_PF0_Msk

#define PWR_PUCRF_PF0_Msk (0x1UL << PWR_PUCRF_PF0_Pos)

0x00000001

Definition at line 7156 of file stm32g431xx.h.

◆ PWR_PUCRF_PF0_Pos

#define PWR_PUCRF_PF0_Pos (0U)

Definition at line 7155 of file stm32g431xx.h.

◆ PWR_PUCRF_PF1

#define PWR_PUCRF_PF1 PWR_PUCRF_PF1_Msk

Port PF1 Pull-Up set

Definition at line 7154 of file stm32g431xx.h.

◆ PWR_PUCRF_PF10

#define PWR_PUCRF_PF10 PWR_PUCRF_PF10_Msk

Port PF10 Pull-Up set

Definition at line 7127 of file stm32g431xx.h.

◆ PWR_PUCRF_PF10_Msk

#define PWR_PUCRF_PF10_Msk (0x1UL << PWR_PUCRF_PF10_Pos)

0x00000400

Definition at line 7126 of file stm32g431xx.h.

◆ PWR_PUCRF_PF10_Pos

#define PWR_PUCRF_PF10_Pos (10U)

Definition at line 7125 of file stm32g431xx.h.

◆ PWR_PUCRF_PF11

#define PWR_PUCRF_PF11 PWR_PUCRF_PF11_Msk

Port PF11 Pull-Up set

Definition at line 7124 of file stm32g431xx.h.

◆ PWR_PUCRF_PF11_Msk

#define PWR_PUCRF_PF11_Msk (0x1UL << PWR_PUCRF_PF11_Pos)

0x00000800

Definition at line 7123 of file stm32g431xx.h.

◆ PWR_PUCRF_PF11_Pos

#define PWR_PUCRF_PF11_Pos (11U)

Definition at line 7122 of file stm32g431xx.h.

◆ PWR_PUCRF_PF12

#define PWR_PUCRF_PF12 PWR_PUCRF_PF12_Msk

Port PF12 Pull-Up set

Definition at line 7121 of file stm32g431xx.h.

◆ PWR_PUCRF_PF12_Msk

#define PWR_PUCRF_PF12_Msk (0x1UL << PWR_PUCRF_PF12_Pos)

0x00001000

Definition at line 7120 of file stm32g431xx.h.

◆ PWR_PUCRF_PF12_Pos

#define PWR_PUCRF_PF12_Pos (12U)

Definition at line 7119 of file stm32g431xx.h.

◆ PWR_PUCRF_PF13

#define PWR_PUCRF_PF13 PWR_PUCRF_PF13_Msk

Port PF13 Pull-Up set

Definition at line 7118 of file stm32g431xx.h.

◆ PWR_PUCRF_PF13_Msk

#define PWR_PUCRF_PF13_Msk (0x1UL << PWR_PUCRF_PF13_Pos)

0x00002000

Definition at line 7117 of file stm32g431xx.h.

◆ PWR_PUCRF_PF13_Pos

#define PWR_PUCRF_PF13_Pos (13U)

Definition at line 7116 of file stm32g431xx.h.

◆ PWR_PUCRF_PF14

#define PWR_PUCRF_PF14 PWR_PUCRF_PF14_Msk

Port PF14 Pull-Up set

Definition at line 7115 of file stm32g431xx.h.

◆ PWR_PUCRF_PF14_Msk

#define PWR_PUCRF_PF14_Msk (0x1UL << PWR_PUCRF_PF14_Pos)

0x00004000

Definition at line 7114 of file stm32g431xx.h.

◆ PWR_PUCRF_PF14_Pos

#define PWR_PUCRF_PF14_Pos (14U)

Definition at line 7113 of file stm32g431xx.h.

◆ PWR_PUCRF_PF15

#define PWR_PUCRF_PF15 PWR_PUCRF_PF15_Msk

Port PF15 Pull-Up set

Definition at line 7112 of file stm32g431xx.h.

◆ PWR_PUCRF_PF15_Msk

#define PWR_PUCRF_PF15_Msk (0x1UL << PWR_PUCRF_PF15_Pos)

0x00008000

Definition at line 7111 of file stm32g431xx.h.

◆ PWR_PUCRF_PF15_Pos

#define PWR_PUCRF_PF15_Pos (15U)

Definition at line 7110 of file stm32g431xx.h.

◆ PWR_PUCRF_PF1_Msk

#define PWR_PUCRF_PF1_Msk (0x1UL << PWR_PUCRF_PF1_Pos)

0x00000002

Definition at line 7153 of file stm32g431xx.h.

◆ PWR_PUCRF_PF1_Pos

#define PWR_PUCRF_PF1_Pos (1U)

Definition at line 7152 of file stm32g431xx.h.

◆ PWR_PUCRF_PF2

#define PWR_PUCRF_PF2 PWR_PUCRF_PF2_Msk

Port PF2 Pull-Up set

Definition at line 7151 of file stm32g431xx.h.

◆ PWR_PUCRF_PF2_Msk

#define PWR_PUCRF_PF2_Msk (0x1UL << PWR_PUCRF_PF2_Pos)

0x00000004

Definition at line 7150 of file stm32g431xx.h.

◆ PWR_PUCRF_PF2_Pos

#define PWR_PUCRF_PF2_Pos (2U)

Definition at line 7149 of file stm32g431xx.h.

◆ PWR_PUCRF_PF3

#define PWR_PUCRF_PF3 PWR_PUCRF_PF3_Msk

Port PF3 Pull-Up set

Definition at line 7148 of file stm32g431xx.h.

◆ PWR_PUCRF_PF3_Msk

#define PWR_PUCRF_PF3_Msk (0x1UL << PWR_PUCRF_PF3_Pos)

0x00000008

Definition at line 7147 of file stm32g431xx.h.

◆ PWR_PUCRF_PF3_Pos

#define PWR_PUCRF_PF3_Pos (3U)

Definition at line 7146 of file stm32g431xx.h.

◆ PWR_PUCRF_PF4

#define PWR_PUCRF_PF4 PWR_PUCRF_PF4_Msk

Port PF4 Pull-Up set

Definition at line 7145 of file stm32g431xx.h.

◆ PWR_PUCRF_PF4_Msk

#define PWR_PUCRF_PF4_Msk (0x1UL << PWR_PUCRF_PF4_Pos)

0x00000010

Definition at line 7144 of file stm32g431xx.h.

◆ PWR_PUCRF_PF4_Pos

#define PWR_PUCRF_PF4_Pos (4U)

Definition at line 7143 of file stm32g431xx.h.

◆ PWR_PUCRF_PF5

#define PWR_PUCRF_PF5 PWR_PUCRF_PF5_Msk

Port PF5 Pull-Up set

Definition at line 7142 of file stm32g431xx.h.

◆ PWR_PUCRF_PF5_Msk

#define PWR_PUCRF_PF5_Msk (0x1UL << PWR_PUCRF_PF5_Pos)

0x00000020

Definition at line 7141 of file stm32g431xx.h.

◆ PWR_PUCRF_PF5_Pos

#define PWR_PUCRF_PF5_Pos (5U)

Definition at line 7140 of file stm32g431xx.h.

◆ PWR_PUCRF_PF6

#define PWR_PUCRF_PF6 PWR_PUCRF_PF6_Msk

Port PF6 Pull-Up set

Definition at line 7139 of file stm32g431xx.h.

◆ PWR_PUCRF_PF6_Msk

#define PWR_PUCRF_PF6_Msk (0x1UL << PWR_PUCRF_PF6_Pos)

0x00000040

Definition at line 7138 of file stm32g431xx.h.

◆ PWR_PUCRF_PF6_Pos

#define PWR_PUCRF_PF6_Pos (6U)

Definition at line 7137 of file stm32g431xx.h.

◆ PWR_PUCRF_PF7

#define PWR_PUCRF_PF7 PWR_PUCRF_PF7_Msk

Port PF7 Pull-Up set

Definition at line 7136 of file stm32g431xx.h.

◆ PWR_PUCRF_PF7_Msk

#define PWR_PUCRF_PF7_Msk (0x1UL << PWR_PUCRF_PF7_Pos)

0x00000080

Definition at line 7135 of file stm32g431xx.h.

◆ PWR_PUCRF_PF7_Pos

#define PWR_PUCRF_PF7_Pos (7U)

Definition at line 7134 of file stm32g431xx.h.

◆ PWR_PUCRF_PF8

#define PWR_PUCRF_PF8 PWR_PUCRF_PF8_Msk

Port PF8 Pull-Up set

Definition at line 7133 of file stm32g431xx.h.

◆ PWR_PUCRF_PF8_Msk

#define PWR_PUCRF_PF8_Msk (0x1UL << PWR_PUCRF_PF8_Pos)

0x00000100

Definition at line 7132 of file stm32g431xx.h.

◆ PWR_PUCRF_PF8_Pos

#define PWR_PUCRF_PF8_Pos (8U)

Definition at line 7131 of file stm32g431xx.h.

◆ PWR_PUCRF_PF9

#define PWR_PUCRF_PF9 PWR_PUCRF_PF9_Msk

Port PF9 Pull-Up set

Definition at line 7130 of file stm32g431xx.h.

◆ PWR_PUCRF_PF9_Msk

#define PWR_PUCRF_PF9_Msk (0x1UL << PWR_PUCRF_PF9_Pos)

0x00000200

Definition at line 7129 of file stm32g431xx.h.

◆ PWR_PUCRF_PF9_Pos

#define PWR_PUCRF_PF9_Pos (9U)

Definition at line 7128 of file stm32g431xx.h.

◆ PWR_PUCRG_PG10

#define PWR_PUCRG_PG10 PWR_PUCRG_PG10_Msk

Port PG10 Pull-Up set

Definition at line 7179 of file stm32g431xx.h.

◆ PWR_PUCRG_PG10_Msk

#define PWR_PUCRG_PG10_Msk (0x1UL << PWR_PUCRG_PG10_Pos)

0x00000400

Definition at line 7178 of file stm32g431xx.h.

◆ PWR_PUCRG_PG10_Pos

#define PWR_PUCRG_PG10_Pos (10U)

Definition at line 7177 of file stm32g431xx.h.

◆ PWR_SCR_CSBF

#define PWR_SCR_CSBF PWR_SCR_CSBF_Msk

Clear Stand-By Flag

Definition at line 6600 of file stm32g431xx.h.

◆ PWR_SCR_CSBF_Msk

#define PWR_SCR_CSBF_Msk (0x1UL << PWR_SCR_CSBF_Pos)

0x00000100

Definition at line 6599 of file stm32g431xx.h.

◆ PWR_SCR_CSBF_Pos

#define PWR_SCR_CSBF_Pos (8U)

Definition at line 6598 of file stm32g431xx.h.

◆ PWR_SCR_CWUF

#define PWR_SCR_CWUF PWR_SCR_CWUF_Msk

Clear Wake-up Flags

Definition at line 6603 of file stm32g431xx.h.

◆ PWR_SCR_CWUF1

#define PWR_SCR_CWUF1 PWR_SCR_CWUF1_Msk

Clear Wake-up Flag 1

Definition at line 6618 of file stm32g431xx.h.

◆ PWR_SCR_CWUF1_Msk

#define PWR_SCR_CWUF1_Msk (0x1UL << PWR_SCR_CWUF1_Pos)

0x00000001

Definition at line 6617 of file stm32g431xx.h.

◆ PWR_SCR_CWUF1_Pos

#define PWR_SCR_CWUF1_Pos (0U)

Definition at line 6616 of file stm32g431xx.h.

◆ PWR_SCR_CWUF2

#define PWR_SCR_CWUF2 PWR_SCR_CWUF2_Msk

Clear Wake-up Flag 2

Definition at line 6615 of file stm32g431xx.h.

◆ PWR_SCR_CWUF2_Msk

#define PWR_SCR_CWUF2_Msk (0x1UL << PWR_SCR_CWUF2_Pos)

0x00000002

Definition at line 6614 of file stm32g431xx.h.

◆ PWR_SCR_CWUF2_Pos

#define PWR_SCR_CWUF2_Pos (1U)

Definition at line 6613 of file stm32g431xx.h.

◆ PWR_SCR_CWUF3

#define PWR_SCR_CWUF3 PWR_SCR_CWUF3_Msk

Clear Wake-up Flag 3

Definition at line 6612 of file stm32g431xx.h.

◆ PWR_SCR_CWUF3_Msk

#define PWR_SCR_CWUF3_Msk (0x1UL << PWR_SCR_CWUF3_Pos)

0x00000004

Definition at line 6611 of file stm32g431xx.h.

◆ PWR_SCR_CWUF3_Pos

#define PWR_SCR_CWUF3_Pos (2U)

Definition at line 6610 of file stm32g431xx.h.

◆ PWR_SCR_CWUF4

#define PWR_SCR_CWUF4 PWR_SCR_CWUF4_Msk

Clear Wake-up Flag 4

Definition at line 6609 of file stm32g431xx.h.

◆ PWR_SCR_CWUF4_Msk

#define PWR_SCR_CWUF4_Msk (0x1UL << PWR_SCR_CWUF4_Pos)

0x00000008

Definition at line 6608 of file stm32g431xx.h.

◆ PWR_SCR_CWUF4_Pos

#define PWR_SCR_CWUF4_Pos (3U)

Definition at line 6607 of file stm32g431xx.h.

◆ PWR_SCR_CWUF5

#define PWR_SCR_CWUF5 PWR_SCR_CWUF5_Msk

Clear Wake-up Flag 5

Definition at line 6606 of file stm32g431xx.h.

◆ PWR_SCR_CWUF5_Msk

#define PWR_SCR_CWUF5_Msk (0x1UL << PWR_SCR_CWUF5_Pos)

0x00000010

Definition at line 6605 of file stm32g431xx.h.

◆ PWR_SCR_CWUF5_Pos

#define PWR_SCR_CWUF5_Pos (4U)

Definition at line 6604 of file stm32g431xx.h.

◆ PWR_SCR_CWUF_Msk

#define PWR_SCR_CWUF_Msk (0x1FUL << PWR_SCR_CWUF_Pos)

0x0000001F

Definition at line 6602 of file stm32g431xx.h.

◆ PWR_SCR_CWUF_Pos

#define PWR_SCR_CWUF_Pos (0U)

Definition at line 6601 of file stm32g431xx.h.

◆ PWR_SR1_SBF

#define PWR_SR1_SBF PWR_SR1_SBF_Msk

Stand-By Flag

Definition at line 6551 of file stm32g431xx.h.

◆ PWR_SR1_SBF_Msk

#define PWR_SR1_SBF_Msk (0x1UL << PWR_SR1_SBF_Pos)

0x00000100

Definition at line 6550 of file stm32g431xx.h.

◆ PWR_SR1_SBF_Pos

#define PWR_SR1_SBF_Pos (8U)

Definition at line 6549 of file stm32g431xx.h.

◆ PWR_SR1_WUF

#define PWR_SR1_WUF PWR_SR1_WUF_Msk

Wake-up Flags

Definition at line 6554 of file stm32g431xx.h.

◆ PWR_SR1_WUF1

#define PWR_SR1_WUF1 PWR_SR1_WUF1_Msk

Wake-up Flag 1

Definition at line 6569 of file stm32g431xx.h.

◆ PWR_SR1_WUF1_Msk

#define PWR_SR1_WUF1_Msk (0x1UL << PWR_SR1_WUF1_Pos)

0x00000001

Definition at line 6568 of file stm32g431xx.h.

◆ PWR_SR1_WUF1_Pos

#define PWR_SR1_WUF1_Pos (0U)

Definition at line 6567 of file stm32g431xx.h.

◆ PWR_SR1_WUF2

#define PWR_SR1_WUF2 PWR_SR1_WUF2_Msk

Wake-up Flag 2

Definition at line 6566 of file stm32g431xx.h.

◆ PWR_SR1_WUF2_Msk

#define PWR_SR1_WUF2_Msk (0x1UL << PWR_SR1_WUF2_Pos)

0x00000002

Definition at line 6565 of file stm32g431xx.h.

◆ PWR_SR1_WUF2_Pos

#define PWR_SR1_WUF2_Pos (1U)

Definition at line 6564 of file stm32g431xx.h.

◆ PWR_SR1_WUF3

#define PWR_SR1_WUF3 PWR_SR1_WUF3_Msk

Wake-up Flag 3

Definition at line 6563 of file stm32g431xx.h.

◆ PWR_SR1_WUF3_Msk

#define PWR_SR1_WUF3_Msk (0x1UL << PWR_SR1_WUF3_Pos)

0x00000004

Definition at line 6562 of file stm32g431xx.h.

◆ PWR_SR1_WUF3_Pos

#define PWR_SR1_WUF3_Pos (2U)

Definition at line 6561 of file stm32g431xx.h.

◆ PWR_SR1_WUF4

#define PWR_SR1_WUF4 PWR_SR1_WUF4_Msk

Wake-up Flag 4

Definition at line 6560 of file stm32g431xx.h.

◆ PWR_SR1_WUF4_Msk

#define PWR_SR1_WUF4_Msk (0x1UL << PWR_SR1_WUF4_Pos)

0x00000008

Definition at line 6559 of file stm32g431xx.h.

◆ PWR_SR1_WUF4_Pos

#define PWR_SR1_WUF4_Pos (3U)

Definition at line 6558 of file stm32g431xx.h.

◆ PWR_SR1_WUF5

#define PWR_SR1_WUF5 PWR_SR1_WUF5_Msk

Wake-up Flag 5

Definition at line 6557 of file stm32g431xx.h.

◆ PWR_SR1_WUF5_Msk

#define PWR_SR1_WUF5_Msk (0x1UL << PWR_SR1_WUF5_Pos)

0x00000010

Definition at line 6556 of file stm32g431xx.h.

◆ PWR_SR1_WUF5_Pos

#define PWR_SR1_WUF5_Pos (4U)

Definition at line 6555 of file stm32g431xx.h.

◆ PWR_SR1_WUF_Msk

#define PWR_SR1_WUF_Msk (0x1FUL << PWR_SR1_WUF_Pos)

0x0000001F

Definition at line 6553 of file stm32g431xx.h.

◆ PWR_SR1_WUF_Pos

#define PWR_SR1_WUF_Pos (0U)

Definition at line 6552 of file stm32g431xx.h.

◆ PWR_SR1_WUFI

#define PWR_SR1_WUFI PWR_SR1_WUFI_Msk

Wake-Up Flag Internal

Definition at line 6548 of file stm32g431xx.h.

◆ PWR_SR1_WUFI_Msk

#define PWR_SR1_WUFI_Msk (0x1UL << PWR_SR1_WUFI_Pos)

0x00008000

Definition at line 6547 of file stm32g431xx.h.

◆ PWR_SR1_WUFI_Pos

#define PWR_SR1_WUFI_Pos (15U)

Definition at line 6546 of file stm32g431xx.h.

◆ PWR_SR2_PVDO

#define PWR_SR2_PVDO PWR_SR2_PVDO_Msk

Power Voltage Detector Output

Definition at line 6586 of file stm32g431xx.h.

◆ PWR_SR2_PVDO_Msk

#define PWR_SR2_PVDO_Msk (0x1UL << PWR_SR2_PVDO_Pos)

0x00000800

Definition at line 6585 of file stm32g431xx.h.

◆ PWR_SR2_PVDO_Pos

#define PWR_SR2_PVDO_Pos (11U)

Definition at line 6584 of file stm32g431xx.h.

◆ PWR_SR2_PVMO1

#define PWR_SR2_PVMO1 PWR_SR2_PVMO1_Msk

Peripheral Voltage Monitoring Output 1

Definition at line 6583 of file stm32g431xx.h.

◆ PWR_SR2_PVMO1_Msk

#define PWR_SR2_PVMO1_Msk (0x1UL << PWR_SR2_PVMO1_Pos)

0x00001000

Definition at line 6582 of file stm32g431xx.h.

◆ PWR_SR2_PVMO1_Pos

#define PWR_SR2_PVMO1_Pos (12U)

Definition at line 6581 of file stm32g431xx.h.

◆ PWR_SR2_PVMO2

#define PWR_SR2_PVMO2 PWR_SR2_PVMO2_Msk

Peripheral Voltage Monitoring Output 2

Definition at line 6580 of file stm32g431xx.h.

◆ PWR_SR2_PVMO2_Msk

#define PWR_SR2_PVMO2_Msk (0x1UL << PWR_SR2_PVMO2_Pos)

0x00002000

Definition at line 6579 of file stm32g431xx.h.

◆ PWR_SR2_PVMO2_Pos

#define PWR_SR2_PVMO2_Pos (13U)

Definition at line 6578 of file stm32g431xx.h.

◆ PWR_SR2_PVMO3

#define PWR_SR2_PVMO3 PWR_SR2_PVMO3_Msk

Peripheral Voltage Monitoring Output 3

Definition at line 6577 of file stm32g431xx.h.

◆ PWR_SR2_PVMO3_Msk

#define PWR_SR2_PVMO3_Msk (0x1UL << PWR_SR2_PVMO3_Pos)

0x00004000

Definition at line 6576 of file stm32g431xx.h.

◆ PWR_SR2_PVMO3_Pos

#define PWR_SR2_PVMO3_Pos (14U)

Definition at line 6575 of file stm32g431xx.h.

◆ PWR_SR2_PVMO4

#define PWR_SR2_PVMO4 PWR_SR2_PVMO4_Msk

Peripheral Voltage Monitoring Output 4

Definition at line 6574 of file stm32g431xx.h.

◆ PWR_SR2_PVMO4_Msk

#define PWR_SR2_PVMO4_Msk (0x1UL << PWR_SR2_PVMO4_Pos)

0x00008000

Definition at line 6573 of file stm32g431xx.h.

◆ PWR_SR2_PVMO4_Pos

#define PWR_SR2_PVMO4_Pos (15U)

Definition at line 6572 of file stm32g431xx.h.

◆ PWR_SR2_REGLPF

#define PWR_SR2_REGLPF PWR_SR2_REGLPF_Msk

Low-power Regulator Flag

Definition at line 6592 of file stm32g431xx.h.

◆ PWR_SR2_REGLPF_Msk

#define PWR_SR2_REGLPF_Msk (0x1UL << PWR_SR2_REGLPF_Pos)

0x00000200

Definition at line 6591 of file stm32g431xx.h.

◆ PWR_SR2_REGLPF_Pos

#define PWR_SR2_REGLPF_Pos (9U)

Definition at line 6590 of file stm32g431xx.h.

◆ PWR_SR2_REGLPS

#define PWR_SR2_REGLPS PWR_SR2_REGLPS_Msk

Low-power Regulator Started

Definition at line 6595 of file stm32g431xx.h.

◆ PWR_SR2_REGLPS_Msk

#define PWR_SR2_REGLPS_Msk (0x1UL << PWR_SR2_REGLPS_Pos)

0x00000100

Definition at line 6594 of file stm32g431xx.h.

◆ PWR_SR2_REGLPS_Pos

#define PWR_SR2_REGLPS_Pos (8U)

Definition at line 6593 of file stm32g431xx.h.

◆ PWR_SR2_VOSF

#define PWR_SR2_VOSF PWR_SR2_VOSF_Msk

Voltage Scaling Flag

Definition at line 6589 of file stm32g431xx.h.

◆ PWR_SR2_VOSF_Msk

#define PWR_SR2_VOSF_Msk (0x1UL << PWR_SR2_VOSF_Pos)

0x00000400

Definition at line 6588 of file stm32g431xx.h.

◆ PWR_SR2_VOSF_Pos

#define PWR_SR2_VOSF_Pos (10U)

Definition at line 6587 of file stm32g431xx.h.

◆ RCC_AHB1ENR_CORDICEN

#define RCC_AHB1ENR_CORDICEN RCC_AHB1ENR_CORDICEN_Msk

Definition at line 7698 of file stm32g431xx.h.

◆ RCC_AHB1ENR_CORDICEN_Msk

#define RCC_AHB1ENR_CORDICEN_Msk (0x1UL << RCC_AHB1ENR_CORDICEN_Pos)

0x00000008

Definition at line 7697 of file stm32g431xx.h.

◆ RCC_AHB1ENR_CORDICEN_Pos

#define RCC_AHB1ENR_CORDICEN_Pos (3U)

Definition at line 7696 of file stm32g431xx.h.

◆ RCC_AHB1ENR_CRCEN

#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk

Definition at line 7707 of file stm32g431xx.h.

◆ RCC_AHB1ENR_CRCEN_Msk

#define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos)

0x00001000

Definition at line 7706 of file stm32g431xx.h.

◆ RCC_AHB1ENR_CRCEN_Pos

#define RCC_AHB1ENR_CRCEN_Pos (12U)

Definition at line 7705 of file stm32g431xx.h.

◆ RCC_AHB1ENR_DMA1EN

#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk

Definition at line 7689 of file stm32g431xx.h.

◆ RCC_AHB1ENR_DMA1EN_Msk

#define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)

0x00000001

Definition at line 7688 of file stm32g431xx.h.

◆ RCC_AHB1ENR_DMA1EN_Pos

#define RCC_AHB1ENR_DMA1EN_Pos (0U)

Definition at line 7687 of file stm32g431xx.h.

◆ RCC_AHB1ENR_DMA2EN

#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk

Definition at line 7692 of file stm32g431xx.h.

◆ RCC_AHB1ENR_DMA2EN_Msk

#define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)

0x00000002

Definition at line 7691 of file stm32g431xx.h.

◆ RCC_AHB1ENR_DMA2EN_Pos

#define RCC_AHB1ENR_DMA2EN_Pos (1U)

Definition at line 7690 of file stm32g431xx.h.

◆ RCC_AHB1ENR_DMAMUX1EN

#define RCC_AHB1ENR_DMAMUX1EN RCC_AHB1ENR_DMAMUX1EN_Msk

Definition at line 7695 of file stm32g431xx.h.

◆ RCC_AHB1ENR_DMAMUX1EN_Msk

#define RCC_AHB1ENR_DMAMUX1EN_Msk (0x1UL << RCC_AHB1ENR_DMAMUX1EN_Pos)

0x00000004

Definition at line 7694 of file stm32g431xx.h.

◆ RCC_AHB1ENR_DMAMUX1EN_Pos

#define RCC_AHB1ENR_DMAMUX1EN_Pos (2U)

Definition at line 7693 of file stm32g431xx.h.

◆ RCC_AHB1ENR_FLASHEN

#define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk

Definition at line 7704 of file stm32g431xx.h.

◆ RCC_AHB1ENR_FLASHEN_Msk

#define RCC_AHB1ENR_FLASHEN_Msk (0x1UL << RCC_AHB1ENR_FLASHEN_Pos)

0x00000100

Definition at line 7703 of file stm32g431xx.h.

◆ RCC_AHB1ENR_FLASHEN_Pos

#define RCC_AHB1ENR_FLASHEN_Pos (8U)

Definition at line 7702 of file stm32g431xx.h.

◆ RCC_AHB1ENR_FMACEN

#define RCC_AHB1ENR_FMACEN RCC_AHB1ENR_FMACEN_Msk

Definition at line 7701 of file stm32g431xx.h.

◆ RCC_AHB1ENR_FMACEN_Msk

#define RCC_AHB1ENR_FMACEN_Msk (0x1UL << RCC_AHB1ENR_FMACEN_Pos)

0x00000010

Definition at line 7700 of file stm32g431xx.h.

◆ RCC_AHB1ENR_FMACEN_Pos

#define RCC_AHB1ENR_FMACEN_Pos (4U)

Definition at line 7699 of file stm32g431xx.h.

◆ RCC_AHB1RSTR_CORDICRST

#define RCC_AHB1RSTR_CORDICRST RCC_AHB1RSTR_CORDICRST_Msk

Definition at line 7545 of file stm32g431xx.h.

◆ RCC_AHB1RSTR_CORDICRST_Msk

#define RCC_AHB1RSTR_CORDICRST_Msk (0x1UL << RCC_AHB1RSTR_CORDICRST_Pos)

0x00000008

Definition at line 7544 of file stm32g431xx.h.

◆ RCC_AHB1RSTR_CORDICRST_Pos

#define RCC_AHB1RSTR_CORDICRST_Pos (3U)

Definition at line 7543 of file stm32g431xx.h.

◆ RCC_AHB1RSTR_CRCRST

#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk

Definition at line 7554 of file stm32g431xx.h.

◆ RCC_AHB1RSTR_CRCRST_Msk

#define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)

0x00001000

Definition at line 7553 of file stm32g431xx.h.

◆ RCC_AHB1RSTR_CRCRST_Pos

#define RCC_AHB1RSTR_CRCRST_Pos (12U)

Definition at line 7552 of file stm32g431xx.h.

◆ RCC_AHB1RSTR_DMA1RST

#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk

Definition at line 7536 of file stm32g431xx.h.

◆ RCC_AHB1RSTR_DMA1RST_Msk

#define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)

0x00000001

Definition at line 7535 of file stm32g431xx.h.

◆ RCC_AHB1RSTR_DMA1RST_Pos

#define RCC_AHB1RSTR_DMA1RST_Pos (0U)

Definition at line 7534 of file stm32g431xx.h.

◆ RCC_AHB1RSTR_DMA2RST

#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk

Definition at line 7539 of file stm32g431xx.h.

◆ RCC_AHB1RSTR_DMA2RST_Msk

#define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)

0x00000002

Definition at line 7538 of file stm32g431xx.h.

◆ RCC_AHB1RSTR_DMA2RST_Pos

#define RCC_AHB1RSTR_DMA2RST_Pos (1U)

Definition at line 7537 of file stm32g431xx.h.

◆ RCC_AHB1RSTR_DMAMUX1RST

#define RCC_AHB1RSTR_DMAMUX1RST RCC_AHB1RSTR_DMAMUX1RST_Msk

Definition at line 7542 of file stm32g431xx.h.

◆ RCC_AHB1RSTR_DMAMUX1RST_Msk

#define RCC_AHB1RSTR_DMAMUX1RST_Msk (0x1UL << RCC_AHB1RSTR_DMAMUX1RST_Pos)

0x00000004

Definition at line 7541 of file stm32g431xx.h.

◆ RCC_AHB1RSTR_DMAMUX1RST_Pos

#define RCC_AHB1RSTR_DMAMUX1RST_Pos (2U)

Definition at line 7540 of file stm32g431xx.h.

◆ RCC_AHB1RSTR_FLASHRST

#define RCC_AHB1RSTR_FLASHRST RCC_AHB1RSTR_FLASHRST_Msk

Definition at line 7551 of file stm32g431xx.h.

◆ RCC_AHB1RSTR_FLASHRST_Msk

#define RCC_AHB1RSTR_FLASHRST_Msk (0x1UL << RCC_AHB1RSTR_FLASHRST_Pos)

0x00000100

Definition at line 7550 of file stm32g431xx.h.

◆ RCC_AHB1RSTR_FLASHRST_Pos

#define RCC_AHB1RSTR_FLASHRST_Pos (8U)

Definition at line 7549 of file stm32g431xx.h.

◆ RCC_AHB1RSTR_FMACRST

#define RCC_AHB1RSTR_FMACRST RCC_AHB1RSTR_FMACRST_Msk

Definition at line 7548 of file stm32g431xx.h.

◆ RCC_AHB1RSTR_FMACRST_Msk

#define RCC_AHB1RSTR_FMACRST_Msk (0x1UL << RCC_AHB1RSTR_FMACRST_Pos)

0x00000010

Definition at line 7547 of file stm32g431xx.h.

◆ RCC_AHB1RSTR_FMACRST_Pos

#define RCC_AHB1RSTR_FMACRST_Pos (4U)

Definition at line 7546 of file stm32g431xx.h.

◆ RCC_AHB1SMENR_CORDICSMEN

#define RCC_AHB1SMENR_CORDICSMEN RCC_AHB1SMENR_CORDICSMEN_Msk

Definition at line 7857 of file stm32g431xx.h.

◆ RCC_AHB1SMENR_CORDICSMEN_Msk

#define RCC_AHB1SMENR_CORDICSMEN_Msk (0x1UL << RCC_AHB1SMENR_CORDICSMEN_Pos)

0x00000008

Definition at line 7856 of file stm32g431xx.h.

◆ RCC_AHB1SMENR_CORDICSMEN_Pos

#define RCC_AHB1SMENR_CORDICSMEN_Pos (3U)

Definition at line 7855 of file stm32g431xx.h.

◆ RCC_AHB1SMENR_CRCSMEN

#define RCC_AHB1SMENR_CRCSMEN RCC_AHB1SMENR_CRCSMEN_Msk

Definition at line 7869 of file stm32g431xx.h.

◆ RCC_AHB1SMENR_CRCSMEN_Msk

#define RCC_AHB1SMENR_CRCSMEN_Msk (0x1UL << RCC_AHB1SMENR_CRCSMEN_Pos)

0x00001000

Definition at line 7868 of file stm32g431xx.h.

◆ RCC_AHB1SMENR_CRCSMEN_Pos

#define RCC_AHB1SMENR_CRCSMEN_Pos (12U)

Definition at line 7867 of file stm32g431xx.h.

◆ RCC_AHB1SMENR_DMA1SMEN

#define RCC_AHB1SMENR_DMA1SMEN RCC_AHB1SMENR_DMA1SMEN_Msk

Definition at line 7848 of file stm32g431xx.h.

◆ RCC_AHB1SMENR_DMA1SMEN_Msk

#define RCC_AHB1SMENR_DMA1SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMA1SMEN_Pos)

0x00000001

Definition at line 7847 of file stm32g431xx.h.

◆ RCC_AHB1SMENR_DMA1SMEN_Pos

#define RCC_AHB1SMENR_DMA1SMEN_Pos (0U)

Definition at line 7846 of file stm32g431xx.h.

◆ RCC_AHB1SMENR_DMA2SMEN

#define RCC_AHB1SMENR_DMA2SMEN RCC_AHB1SMENR_DMA2SMEN_Msk

Definition at line 7851 of file stm32g431xx.h.

◆ RCC_AHB1SMENR_DMA2SMEN_Msk

#define RCC_AHB1SMENR_DMA2SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMA2SMEN_Pos)

0x00000002

Definition at line 7850 of file stm32g431xx.h.

◆ RCC_AHB1SMENR_DMA2SMEN_Pos

#define RCC_AHB1SMENR_DMA2SMEN_Pos (1U)

Definition at line 7849 of file stm32g431xx.h.

◆ RCC_AHB1SMENR_DMAMUX1SMEN

#define RCC_AHB1SMENR_DMAMUX1SMEN RCC_AHB1SMENR_DMAMUX1SMEN_Msk

Definition at line 7854 of file stm32g431xx.h.

◆ RCC_AHB1SMENR_DMAMUX1SMEN_Msk

#define RCC_AHB1SMENR_DMAMUX1SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMAMUX1SMEN_Pos)

0x00000004

Definition at line 7853 of file stm32g431xx.h.

◆ RCC_AHB1SMENR_DMAMUX1SMEN_Pos

#define RCC_AHB1SMENR_DMAMUX1SMEN_Pos (2U)

Definition at line 7852 of file stm32g431xx.h.

◆ RCC_AHB1SMENR_FLASHSMEN

#define RCC_AHB1SMENR_FLASHSMEN RCC_AHB1SMENR_FLASHSMEN_Msk

Definition at line 7863 of file stm32g431xx.h.

◆ RCC_AHB1SMENR_FLASHSMEN_Msk

#define RCC_AHB1SMENR_FLASHSMEN_Msk (0x1UL << RCC_AHB1SMENR_FLASHSMEN_Pos)

0x00000100

Definition at line 7862 of file stm32g431xx.h.

◆ RCC_AHB1SMENR_FLASHSMEN_Pos

#define RCC_AHB1SMENR_FLASHSMEN_Pos (8U)

Definition at line 7861 of file stm32g431xx.h.

◆ RCC_AHB1SMENR_FMACSMEN

#define RCC_AHB1SMENR_FMACSMEN RCC_AHB1SMENR_FMACSMEN_Msk

Definition at line 7860 of file stm32g431xx.h.

◆ RCC_AHB1SMENR_FMACSMEN_Msk

#define RCC_AHB1SMENR_FMACSMEN_Msk (0x1UL << RCC_AHB1SMENR_FMACSMEN_Pos)

0x00000010

Definition at line 7859 of file stm32g431xx.h.

◆ RCC_AHB1SMENR_FMACSMEN_Pos

#define RCC_AHB1SMENR_FMACSMEN_Pos (4U)

Definition at line 7858 of file stm32g431xx.h.

◆ RCC_AHB1SMENR_SRAM1SMEN

#define RCC_AHB1SMENR_SRAM1SMEN RCC_AHB1SMENR_SRAM1SMEN_Msk

Definition at line 7866 of file stm32g431xx.h.

◆ RCC_AHB1SMENR_SRAM1SMEN_Msk

#define RCC_AHB1SMENR_SRAM1SMEN_Msk (0x1UL << RCC_AHB1SMENR_SRAM1SMEN_Pos)

0x00000200

Definition at line 7865 of file stm32g431xx.h.

◆ RCC_AHB1SMENR_SRAM1SMEN_Pos

#define RCC_AHB1SMENR_SRAM1SMEN_Pos (9U)

Definition at line 7864 of file stm32g431xx.h.

◆ RCC_AHB2ENR_ADC12EN

#define RCC_AHB2ENR_ADC12EN RCC_AHB2ENR_ADC12EN_Msk

Definition at line 7733 of file stm32g431xx.h.

◆ RCC_AHB2ENR_ADC12EN_Msk

#define RCC_AHB2ENR_ADC12EN_Msk (0x1UL << RCC_AHB2ENR_ADC12EN_Pos)

0x00002000

Definition at line 7732 of file stm32g431xx.h.

◆ RCC_AHB2ENR_ADC12EN_Pos

#define RCC_AHB2ENR_ADC12EN_Pos (13U)

Definition at line 7731 of file stm32g431xx.h.

◆ RCC_AHB2ENR_DAC1EN

#define RCC_AHB2ENR_DAC1EN RCC_AHB2ENR_DAC1EN_Msk

Definition at line 7736 of file stm32g431xx.h.

◆ RCC_AHB2ENR_DAC1EN_Msk

#define RCC_AHB2ENR_DAC1EN_Msk (0x1UL << RCC_AHB2ENR_DAC1EN_Pos)

0x00010000

Definition at line 7735 of file stm32g431xx.h.

◆ RCC_AHB2ENR_DAC1EN_Pos

#define RCC_AHB2ENR_DAC1EN_Pos (16U)

Definition at line 7734 of file stm32g431xx.h.

◆ RCC_AHB2ENR_DAC3EN

#define RCC_AHB2ENR_DAC3EN RCC_AHB2ENR_DAC3EN_Msk

Definition at line 7739 of file stm32g431xx.h.

◆ RCC_AHB2ENR_DAC3EN_Msk

#define RCC_AHB2ENR_DAC3EN_Msk (0x1UL << RCC_AHB2ENR_DAC3EN_Pos)

0x00040000

Definition at line 7738 of file stm32g431xx.h.

◆ RCC_AHB2ENR_DAC3EN_Pos

#define RCC_AHB2ENR_DAC3EN_Pos (18U)

Definition at line 7737 of file stm32g431xx.h.

◆ RCC_AHB2ENR_GPIOAEN

#define RCC_AHB2ENR_GPIOAEN RCC_AHB2ENR_GPIOAEN_Msk

Definition at line 7712 of file stm32g431xx.h.

◆ RCC_AHB2ENR_GPIOAEN_Msk

#define RCC_AHB2ENR_GPIOAEN_Msk (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos)

0x00000001

Definition at line 7711 of file stm32g431xx.h.

◆ RCC_AHB2ENR_GPIOAEN_Pos

#define RCC_AHB2ENR_GPIOAEN_Pos (0U)

Definition at line 7710 of file stm32g431xx.h.

◆ RCC_AHB2ENR_GPIOBEN

#define RCC_AHB2ENR_GPIOBEN RCC_AHB2ENR_GPIOBEN_Msk

Definition at line 7715 of file stm32g431xx.h.

◆ RCC_AHB2ENR_GPIOBEN_Msk

#define RCC_AHB2ENR_GPIOBEN_Msk (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos)

0x00000002

Definition at line 7714 of file stm32g431xx.h.

◆ RCC_AHB2ENR_GPIOBEN_Pos

#define RCC_AHB2ENR_GPIOBEN_Pos (1U)

Definition at line 7713 of file stm32g431xx.h.

◆ RCC_AHB2ENR_GPIOCEN

#define RCC_AHB2ENR_GPIOCEN RCC_AHB2ENR_GPIOCEN_Msk

Definition at line 7718 of file stm32g431xx.h.

◆ RCC_AHB2ENR_GPIOCEN_Msk

#define RCC_AHB2ENR_GPIOCEN_Msk (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos)

0x00000004

Definition at line 7717 of file stm32g431xx.h.

◆ RCC_AHB2ENR_GPIOCEN_Pos

#define RCC_AHB2ENR_GPIOCEN_Pos (2U)

Definition at line 7716 of file stm32g431xx.h.

◆ RCC_AHB2ENR_GPIODEN

#define RCC_AHB2ENR_GPIODEN RCC_AHB2ENR_GPIODEN_Msk

Definition at line 7721 of file stm32g431xx.h.

◆ RCC_AHB2ENR_GPIODEN_Msk

#define RCC_AHB2ENR_GPIODEN_Msk (0x1UL << RCC_AHB2ENR_GPIODEN_Pos)

0x00000008

Definition at line 7720 of file stm32g431xx.h.

◆ RCC_AHB2ENR_GPIODEN_Pos

#define RCC_AHB2ENR_GPIODEN_Pos (3U)

Definition at line 7719 of file stm32g431xx.h.

◆ RCC_AHB2ENR_GPIOEEN

#define RCC_AHB2ENR_GPIOEEN RCC_AHB2ENR_GPIOEEN_Msk

Definition at line 7724 of file stm32g431xx.h.

◆ RCC_AHB2ENR_GPIOEEN_Msk

#define RCC_AHB2ENR_GPIOEEN_Msk (0x1UL << RCC_AHB2ENR_GPIOEEN_Pos)

0x00000010

Definition at line 7723 of file stm32g431xx.h.

◆ RCC_AHB2ENR_GPIOEEN_Pos

#define RCC_AHB2ENR_GPIOEEN_Pos (4U)

Definition at line 7722 of file stm32g431xx.h.

◆ RCC_AHB2ENR_GPIOFEN

#define RCC_AHB2ENR_GPIOFEN RCC_AHB2ENR_GPIOFEN_Msk

Definition at line 7727 of file stm32g431xx.h.

◆ RCC_AHB2ENR_GPIOFEN_Msk

#define RCC_AHB2ENR_GPIOFEN_Msk (0x1UL << RCC_AHB2ENR_GPIOFEN_Pos)

0x00000020

Definition at line 7726 of file stm32g431xx.h.

◆ RCC_AHB2ENR_GPIOFEN_Pos

#define RCC_AHB2ENR_GPIOFEN_Pos (5U)

Definition at line 7725 of file stm32g431xx.h.

◆ RCC_AHB2ENR_GPIOGEN

#define RCC_AHB2ENR_GPIOGEN RCC_AHB2ENR_GPIOGEN_Msk

Definition at line 7730 of file stm32g431xx.h.

◆ RCC_AHB2ENR_GPIOGEN_Msk

#define RCC_AHB2ENR_GPIOGEN_Msk (0x1UL << RCC_AHB2ENR_GPIOGEN_Pos)

0x00000040

Definition at line 7729 of file stm32g431xx.h.

◆ RCC_AHB2ENR_GPIOGEN_Pos

#define RCC_AHB2ENR_GPIOGEN_Pos (6U)

Definition at line 7728 of file stm32g431xx.h.

◆ RCC_AHB2ENR_RNGEN

#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk

Definition at line 7742 of file stm32g431xx.h.

◆ RCC_AHB2ENR_RNGEN_Msk

#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos)

0x04000000

Definition at line 7741 of file stm32g431xx.h.

◆ RCC_AHB2ENR_RNGEN_Pos

#define RCC_AHB2ENR_RNGEN_Pos (26U)

Definition at line 7740 of file stm32g431xx.h.

◆ RCC_AHB2RSTR_ADC12RST

#define RCC_AHB2RSTR_ADC12RST RCC_AHB2RSTR_ADC12RST_Msk

Definition at line 7580 of file stm32g431xx.h.

◆ RCC_AHB2RSTR_ADC12RST_Msk

#define RCC_AHB2RSTR_ADC12RST_Msk (0x1UL << RCC_AHB2RSTR_ADC12RST_Pos)

0x00002000

Definition at line 7579 of file stm32g431xx.h.

◆ RCC_AHB2RSTR_ADC12RST_Pos

#define RCC_AHB2RSTR_ADC12RST_Pos (13U)

Definition at line 7578 of file stm32g431xx.h.

◆ RCC_AHB2RSTR_DAC1RST

#define RCC_AHB2RSTR_DAC1RST RCC_AHB2RSTR_DAC1RST_Msk

Definition at line 7583 of file stm32g431xx.h.

◆ RCC_AHB2RSTR_DAC1RST_Msk

#define RCC_AHB2RSTR_DAC1RST_Msk (0x1UL << RCC_AHB2RSTR_DAC1RST_Pos)

0x00010000

Definition at line 7582 of file stm32g431xx.h.

◆ RCC_AHB2RSTR_DAC1RST_Pos

#define RCC_AHB2RSTR_DAC1RST_Pos (16U)

Definition at line 7581 of file stm32g431xx.h.

◆ RCC_AHB2RSTR_DAC3RST

#define RCC_AHB2RSTR_DAC3RST RCC_AHB2RSTR_DAC3RST_Msk

Definition at line 7586 of file stm32g431xx.h.

◆ RCC_AHB2RSTR_DAC3RST_Msk

#define RCC_AHB2RSTR_DAC3RST_Msk (0x1UL << RCC_AHB2RSTR_DAC3RST_Pos)

0x00040000

Definition at line 7585 of file stm32g431xx.h.

◆ RCC_AHB2RSTR_DAC3RST_Pos

#define RCC_AHB2RSTR_DAC3RST_Pos (18U)

Definition at line 7584 of file stm32g431xx.h.

◆ RCC_AHB2RSTR_GPIOARST

#define RCC_AHB2RSTR_GPIOARST RCC_AHB2RSTR_GPIOARST_Msk

Definition at line 7559 of file stm32g431xx.h.

◆ RCC_AHB2RSTR_GPIOARST_Msk

#define RCC_AHB2RSTR_GPIOARST_Msk (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos)

0x00000001

Definition at line 7558 of file stm32g431xx.h.

◆ RCC_AHB2RSTR_GPIOARST_Pos

#define RCC_AHB2RSTR_GPIOARST_Pos (0U)

Definition at line 7557 of file stm32g431xx.h.

◆ RCC_AHB2RSTR_GPIOBRST

#define RCC_AHB2RSTR_GPIOBRST RCC_AHB2RSTR_GPIOBRST_Msk

Definition at line 7562 of file stm32g431xx.h.

◆ RCC_AHB2RSTR_GPIOBRST_Msk

#define RCC_AHB2RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos)

0x00000002

Definition at line 7561 of file stm32g431xx.h.

◆ RCC_AHB2RSTR_GPIOBRST_Pos

#define RCC_AHB2RSTR_GPIOBRST_Pos (1U)

Definition at line 7560 of file stm32g431xx.h.

◆ RCC_AHB2RSTR_GPIOCRST

#define RCC_AHB2RSTR_GPIOCRST RCC_AHB2RSTR_GPIOCRST_Msk

Definition at line 7565 of file stm32g431xx.h.

◆ RCC_AHB2RSTR_GPIOCRST_Msk

#define RCC_AHB2RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos)

0x00000004

Definition at line 7564 of file stm32g431xx.h.

◆ RCC_AHB2RSTR_GPIOCRST_Pos

#define RCC_AHB2RSTR_GPIOCRST_Pos (2U)

Definition at line 7563 of file stm32g431xx.h.

◆ RCC_AHB2RSTR_GPIODRST

#define RCC_AHB2RSTR_GPIODRST RCC_AHB2RSTR_GPIODRST_Msk

Definition at line 7568 of file stm32g431xx.h.

◆ RCC_AHB2RSTR_GPIODRST_Msk

#define RCC_AHB2RSTR_GPIODRST_Msk (0x1UL << RCC_AHB2RSTR_GPIODRST_Pos)

0x00000008

Definition at line 7567 of file stm32g431xx.h.

◆ RCC_AHB2RSTR_GPIODRST_Pos

#define RCC_AHB2RSTR_GPIODRST_Pos (3U)

Definition at line 7566 of file stm32g431xx.h.

◆ RCC_AHB2RSTR_GPIOERST

#define RCC_AHB2RSTR_GPIOERST RCC_AHB2RSTR_GPIOERST_Msk

Definition at line 7571 of file stm32g431xx.h.

◆ RCC_AHB2RSTR_GPIOERST_Msk

#define RCC_AHB2RSTR_GPIOERST_Msk (0x1UL << RCC_AHB2RSTR_GPIOERST_Pos)

0x00000010

Definition at line 7570 of file stm32g431xx.h.

◆ RCC_AHB2RSTR_GPIOERST_Pos

#define RCC_AHB2RSTR_GPIOERST_Pos (4U)

Definition at line 7569 of file stm32g431xx.h.

◆ RCC_AHB2RSTR_GPIOFRST

#define RCC_AHB2RSTR_GPIOFRST RCC_AHB2RSTR_GPIOFRST_Msk

Definition at line 7574 of file stm32g431xx.h.

◆ RCC_AHB2RSTR_GPIOFRST_Msk

#define RCC_AHB2RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOFRST_Pos)

0x00000020

Definition at line 7573 of file stm32g431xx.h.

◆ RCC_AHB2RSTR_GPIOFRST_Pos

#define RCC_AHB2RSTR_GPIOFRST_Pos (5U)

Definition at line 7572 of file stm32g431xx.h.

◆ RCC_AHB2RSTR_GPIOGRST

#define RCC_AHB2RSTR_GPIOGRST RCC_AHB2RSTR_GPIOGRST_Msk

Definition at line 7577 of file stm32g431xx.h.

◆ RCC_AHB2RSTR_GPIOGRST_Msk

#define RCC_AHB2RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOGRST_Pos)

0x00000040

Definition at line 7576 of file stm32g431xx.h.

◆ RCC_AHB2RSTR_GPIOGRST_Pos

#define RCC_AHB2RSTR_GPIOGRST_Pos (6U)

Definition at line 7575 of file stm32g431xx.h.

◆ RCC_AHB2RSTR_RNGRST

#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk

Definition at line 7589 of file stm32g431xx.h.

◆ RCC_AHB2RSTR_RNGRST_Msk

#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)

0x04000000

Definition at line 7588 of file stm32g431xx.h.

◆ RCC_AHB2RSTR_RNGRST_Pos

#define RCC_AHB2RSTR_RNGRST_Pos (26U)

Definition at line 7587 of file stm32g431xx.h.

◆ RCC_AHB2SMENR_ADC12SMEN

#define RCC_AHB2SMENR_ADC12SMEN RCC_AHB2SMENR_ADC12SMEN_Msk

Definition at line 7901 of file stm32g431xx.h.

◆ RCC_AHB2SMENR_ADC12SMEN_Msk

#define RCC_AHB2SMENR_ADC12SMEN_Msk (0x1UL << RCC_AHB2SMENR_ADC12SMEN_Pos)

0x00002000

Definition at line 7900 of file stm32g431xx.h.

◆ RCC_AHB2SMENR_ADC12SMEN_Pos

#define RCC_AHB2SMENR_ADC12SMEN_Pos (13U)

Definition at line 7899 of file stm32g431xx.h.

◆ RCC_AHB2SMENR_CCMSRAMSMEN

#define RCC_AHB2SMENR_CCMSRAMSMEN RCC_AHB2SMENR_CCMSRAMSMEN_Msk

Definition at line 7895 of file stm32g431xx.h.

◆ RCC_AHB2SMENR_CCMSRAMSMEN_Msk

#define RCC_AHB2SMENR_CCMSRAMSMEN_Msk (0x1UL << RCC_AHB2SMENR_CCMSRAMSMEN_Pos)

0x00000200

Definition at line 7894 of file stm32g431xx.h.

◆ RCC_AHB2SMENR_CCMSRAMSMEN_Pos

#define RCC_AHB2SMENR_CCMSRAMSMEN_Pos (9U)

Definition at line 7893 of file stm32g431xx.h.

◆ RCC_AHB2SMENR_DAC1SMEN

#define RCC_AHB2SMENR_DAC1SMEN RCC_AHB2SMENR_DAC1SMEN_Msk

Definition at line 7904 of file stm32g431xx.h.

◆ RCC_AHB2SMENR_DAC1SMEN_Msk

#define RCC_AHB2SMENR_DAC1SMEN_Msk (0x1UL << RCC_AHB2SMENR_DAC1SMEN_Pos)

0x00010000

Definition at line 7903 of file stm32g431xx.h.

◆ RCC_AHB2SMENR_DAC1SMEN_Pos

#define RCC_AHB2SMENR_DAC1SMEN_Pos (16U)

Definition at line 7902 of file stm32g431xx.h.

◆ RCC_AHB2SMENR_DAC3SMEN

#define RCC_AHB2SMENR_DAC3SMEN RCC_AHB2SMENR_DAC3SMEN_Msk

Definition at line 7907 of file stm32g431xx.h.

◆ RCC_AHB2SMENR_DAC3SMEN_Msk

#define RCC_AHB2SMENR_DAC3SMEN_Msk (0x1UL << RCC_AHB2SMENR_DAC3SMEN_Pos)

0x00040000

Definition at line 7906 of file stm32g431xx.h.

◆ RCC_AHB2SMENR_DAC3SMEN_Pos

#define RCC_AHB2SMENR_DAC3SMEN_Pos (18U)

Definition at line 7905 of file stm32g431xx.h.

◆ RCC_AHB2SMENR_GPIOASMEN

#define RCC_AHB2SMENR_GPIOASMEN RCC_AHB2SMENR_GPIOASMEN_Msk

Definition at line 7874 of file stm32g431xx.h.

◆ RCC_AHB2SMENR_GPIOASMEN_Msk

#define RCC_AHB2SMENR_GPIOASMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOASMEN_Pos)

0x00000001

Definition at line 7873 of file stm32g431xx.h.

◆ RCC_AHB2SMENR_GPIOASMEN_Pos

#define RCC_AHB2SMENR_GPIOASMEN_Pos (0U)

Definition at line 7872 of file stm32g431xx.h.

◆ RCC_AHB2SMENR_GPIOBSMEN

#define RCC_AHB2SMENR_GPIOBSMEN RCC_AHB2SMENR_GPIOBSMEN_Msk

Definition at line 7877 of file stm32g431xx.h.

◆ RCC_AHB2SMENR_GPIOBSMEN_Msk

#define RCC_AHB2SMENR_GPIOBSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOBSMEN_Pos)

0x00000002

Definition at line 7876 of file stm32g431xx.h.

◆ RCC_AHB2SMENR_GPIOBSMEN_Pos

#define RCC_AHB2SMENR_GPIOBSMEN_Pos (1U)

Definition at line 7875 of file stm32g431xx.h.

◆ RCC_AHB2SMENR_GPIOCSMEN

#define RCC_AHB2SMENR_GPIOCSMEN RCC_AHB2SMENR_GPIOCSMEN_Msk

Definition at line 7880 of file stm32g431xx.h.

◆ RCC_AHB2SMENR_GPIOCSMEN_Msk

#define RCC_AHB2SMENR_GPIOCSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOCSMEN_Pos)

0x00000004

Definition at line 7879 of file stm32g431xx.h.

◆ RCC_AHB2SMENR_GPIOCSMEN_Pos

#define RCC_AHB2SMENR_GPIOCSMEN_Pos (2U)

Definition at line 7878 of file stm32g431xx.h.

◆ RCC_AHB2SMENR_GPIODSMEN

#define RCC_AHB2SMENR_GPIODSMEN RCC_AHB2SMENR_GPIODSMEN_Msk

Definition at line 7883 of file stm32g431xx.h.

◆ RCC_AHB2SMENR_GPIODSMEN_Msk

#define RCC_AHB2SMENR_GPIODSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIODSMEN_Pos)

0x00000008

Definition at line 7882 of file stm32g431xx.h.

◆ RCC_AHB2SMENR_GPIODSMEN_Pos

#define RCC_AHB2SMENR_GPIODSMEN_Pos (3U)

Definition at line 7881 of file stm32g431xx.h.

◆ RCC_AHB2SMENR_GPIOESMEN

#define RCC_AHB2SMENR_GPIOESMEN RCC_AHB2SMENR_GPIOESMEN_Msk

Definition at line 7886 of file stm32g431xx.h.

◆ RCC_AHB2SMENR_GPIOESMEN_Msk

#define RCC_AHB2SMENR_GPIOESMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOESMEN_Pos)

0x00000010

Definition at line 7885 of file stm32g431xx.h.

◆ RCC_AHB2SMENR_GPIOESMEN_Pos

#define RCC_AHB2SMENR_GPIOESMEN_Pos (4U)

Definition at line 7884 of file stm32g431xx.h.

◆ RCC_AHB2SMENR_GPIOFSMEN

#define RCC_AHB2SMENR_GPIOFSMEN RCC_AHB2SMENR_GPIOFSMEN_Msk

Definition at line 7889 of file stm32g431xx.h.

◆ RCC_AHB2SMENR_GPIOFSMEN_Msk

#define RCC_AHB2SMENR_GPIOFSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOFSMEN_Pos)

0x00000020

Definition at line 7888 of file stm32g431xx.h.

◆ RCC_AHB2SMENR_GPIOFSMEN_Pos

#define RCC_AHB2SMENR_GPIOFSMEN_Pos (5U)

Definition at line 7887 of file stm32g431xx.h.

◆ RCC_AHB2SMENR_GPIOGSMEN

#define RCC_AHB2SMENR_GPIOGSMEN RCC_AHB2SMENR_GPIOGSMEN_Msk

Definition at line 7892 of file stm32g431xx.h.

◆ RCC_AHB2SMENR_GPIOGSMEN_Msk

#define RCC_AHB2SMENR_GPIOGSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOGSMEN_Pos)

0x00000040

Definition at line 7891 of file stm32g431xx.h.

◆ RCC_AHB2SMENR_GPIOGSMEN_Pos

#define RCC_AHB2SMENR_GPIOGSMEN_Pos (6U)

Definition at line 7890 of file stm32g431xx.h.

◆ RCC_AHB2SMENR_RNGSMEN

#define RCC_AHB2SMENR_RNGSMEN RCC_AHB2SMENR_RNGSMEN_Msk

Definition at line 7910 of file stm32g431xx.h.

◆ RCC_AHB2SMENR_RNGSMEN_Msk

#define RCC_AHB2SMENR_RNGSMEN_Msk (0x1UL << RCC_AHB2SMENR_RNGSMEN_Pos)

0x04000000

Definition at line 7909 of file stm32g431xx.h.

◆ RCC_AHB2SMENR_RNGSMEN_Pos

#define RCC_AHB2SMENR_RNGSMEN_Pos (26U)

Definition at line 7908 of file stm32g431xx.h.

◆ RCC_AHB2SMENR_SRAM2SMEN

#define RCC_AHB2SMENR_SRAM2SMEN RCC_AHB2SMENR_SRAM2SMEN_Msk

Definition at line 7898 of file stm32g431xx.h.

◆ RCC_AHB2SMENR_SRAM2SMEN_Msk

#define RCC_AHB2SMENR_SRAM2SMEN_Msk (0x1UL << RCC_AHB2SMENR_SRAM2SMEN_Pos)

0x00000400

Definition at line 7897 of file stm32g431xx.h.

◆ RCC_AHB2SMENR_SRAM2SMEN_Pos

#define RCC_AHB2SMENR_SRAM2SMEN_Pos (10U)

Definition at line 7896 of file stm32g431xx.h.

◆ RCC_APB1ENR1_CRSEN

#define RCC_APB1ENR1_CRSEN RCC_APB1ENR1_CRSEN_Msk

Definition at line 7764 of file stm32g431xx.h.

◆ RCC_APB1ENR1_CRSEN_Msk

#define RCC_APB1ENR1_CRSEN_Msk (0x1UL << RCC_APB1ENR1_CRSEN_Pos)

0x00000100

Definition at line 7763 of file stm32g431xx.h.

◆ RCC_APB1ENR1_CRSEN_Pos

#define RCC_APB1ENR1_CRSEN_Pos (8U)

Definition at line 7762 of file stm32g431xx.h.

◆ RCC_APB1ENR1_FDCANEN

#define RCC_APB1ENR1_FDCANEN RCC_APB1ENR1_FDCANEN_Msk

Definition at line 7797 of file stm32g431xx.h.

◆ RCC_APB1ENR1_FDCANEN_Msk

#define RCC_APB1ENR1_FDCANEN_Msk (0x1UL << RCC_APB1ENR1_FDCANEN_Pos)

0x02000000

Definition at line 7796 of file stm32g431xx.h.

◆ RCC_APB1ENR1_FDCANEN_Pos

#define RCC_APB1ENR1_FDCANEN_Pos (25U)

Definition at line 7795 of file stm32g431xx.h.

◆ RCC_APB1ENR1_I2C1EN

#define RCC_APB1ENR1_I2C1EN RCC_APB1ENR1_I2C1EN_Msk

Definition at line 7788 of file stm32g431xx.h.

◆ RCC_APB1ENR1_I2C1EN_Msk

#define RCC_APB1ENR1_I2C1EN_Msk (0x1UL << RCC_APB1ENR1_I2C1EN_Pos)

0x00200000

Definition at line 7787 of file stm32g431xx.h.

◆ RCC_APB1ENR1_I2C1EN_Pos

#define RCC_APB1ENR1_I2C1EN_Pos (21U)

Definition at line 7786 of file stm32g431xx.h.

◆ RCC_APB1ENR1_I2C2EN

#define RCC_APB1ENR1_I2C2EN RCC_APB1ENR1_I2C2EN_Msk

Definition at line 7791 of file stm32g431xx.h.

◆ RCC_APB1ENR1_I2C2EN_Msk

#define RCC_APB1ENR1_I2C2EN_Msk (0x1UL << RCC_APB1ENR1_I2C2EN_Pos)

0x00400000

Definition at line 7790 of file stm32g431xx.h.

◆ RCC_APB1ENR1_I2C2EN_Pos

#define RCC_APB1ENR1_I2C2EN_Pos (22U)

Definition at line 7789 of file stm32g431xx.h.

◆ RCC_APB1ENR1_I2C3EN

#define RCC_APB1ENR1_I2C3EN RCC_APB1ENR1_I2C3EN_Msk

Definition at line 7803 of file stm32g431xx.h.

◆ RCC_APB1ENR1_I2C3EN_Msk

#define RCC_APB1ENR1_I2C3EN_Msk (0x1UL << RCC_APB1ENR1_I2C3EN_Pos)

0x40000000

Definition at line 7802 of file stm32g431xx.h.

◆ RCC_APB1ENR1_I2C3EN_Pos

#define RCC_APB1ENR1_I2C3EN_Pos (30U)

Definition at line 7801 of file stm32g431xx.h.

◆ RCC_APB1ENR1_LPTIM1EN

#define RCC_APB1ENR1_LPTIM1EN RCC_APB1ENR1_LPTIM1EN_Msk

Definition at line 7806 of file stm32g431xx.h.

◆ RCC_APB1ENR1_LPTIM1EN_Msk

#define RCC_APB1ENR1_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos)

0x80000000

Definition at line 7805 of file stm32g431xx.h.

◆ RCC_APB1ENR1_LPTIM1EN_Pos

#define RCC_APB1ENR1_LPTIM1EN_Pos (31U)

Definition at line 7804 of file stm32g431xx.h.

◆ RCC_APB1ENR1_PWREN

#define RCC_APB1ENR1_PWREN RCC_APB1ENR1_PWREN_Msk

Definition at line 7800 of file stm32g431xx.h.

◆ RCC_APB1ENR1_PWREN_Msk

#define RCC_APB1ENR1_PWREN_Msk (0x1UL << RCC_APB1ENR1_PWREN_Pos)

0x10000000

Definition at line 7799 of file stm32g431xx.h.

◆ RCC_APB1ENR1_PWREN_Pos

#define RCC_APB1ENR1_PWREN_Pos (28U)

Definition at line 7798 of file stm32g431xx.h.

◆ RCC_APB1ENR1_RTCAPBEN

#define RCC_APB1ENR1_RTCAPBEN RCC_APB1ENR1_RTCAPBEN_Msk

Definition at line 7767 of file stm32g431xx.h.

◆ RCC_APB1ENR1_RTCAPBEN_Msk

#define RCC_APB1ENR1_RTCAPBEN_Msk (0x1UL << RCC_APB1ENR1_RTCAPBEN_Pos)

0x00000400

Definition at line 7766 of file stm32g431xx.h.

◆ RCC_APB1ENR1_RTCAPBEN_Pos

#define RCC_APB1ENR1_RTCAPBEN_Pos (10U)

Definition at line 7765 of file stm32g431xx.h.

◆ RCC_APB1ENR1_SPI2EN

#define RCC_APB1ENR1_SPI2EN RCC_APB1ENR1_SPI2EN_Msk

Definition at line 7773 of file stm32g431xx.h.

◆ RCC_APB1ENR1_SPI2EN_Msk

#define RCC_APB1ENR1_SPI2EN_Msk (0x1UL << RCC_APB1ENR1_SPI2EN_Pos)

0x00004000

Definition at line 7772 of file stm32g431xx.h.

◆ RCC_APB1ENR1_SPI2EN_Pos

#define RCC_APB1ENR1_SPI2EN_Pos (14U)

Definition at line 7771 of file stm32g431xx.h.

◆ RCC_APB1ENR1_SPI3EN

#define RCC_APB1ENR1_SPI3EN RCC_APB1ENR1_SPI3EN_Msk

Definition at line 7776 of file stm32g431xx.h.

◆ RCC_APB1ENR1_SPI3EN_Msk

#define RCC_APB1ENR1_SPI3EN_Msk (0x1UL << RCC_APB1ENR1_SPI3EN_Pos)

0x00008000

Definition at line 7775 of file stm32g431xx.h.

◆ RCC_APB1ENR1_SPI3EN_Pos

#define RCC_APB1ENR1_SPI3EN_Pos (15U)

Definition at line 7774 of file stm32g431xx.h.

◆ RCC_APB1ENR1_TIM2EN

#define RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk

Definition at line 7749 of file stm32g431xx.h.

◆ RCC_APB1ENR1_TIM2EN_Msk

#define RCC_APB1ENR1_TIM2EN_Msk (0x1UL << RCC_APB1ENR1_TIM2EN_Pos)

0x00000001

Definition at line 7748 of file stm32g431xx.h.

◆ RCC_APB1ENR1_TIM2EN_Pos

#define RCC_APB1ENR1_TIM2EN_Pos (0U)

Definition at line 7747 of file stm32g431xx.h.

◆ RCC_APB1ENR1_TIM3EN

#define RCC_APB1ENR1_TIM3EN RCC_APB1ENR1_TIM3EN_Msk

Definition at line 7752 of file stm32g431xx.h.

◆ RCC_APB1ENR1_TIM3EN_Msk

#define RCC_APB1ENR1_TIM3EN_Msk (0x1UL << RCC_APB1ENR1_TIM3EN_Pos)

0x00000002

Definition at line 7751 of file stm32g431xx.h.

◆ RCC_APB1ENR1_TIM3EN_Pos

#define RCC_APB1ENR1_TIM3EN_Pos (1U)

Definition at line 7750 of file stm32g431xx.h.

◆ RCC_APB1ENR1_TIM4EN

#define RCC_APB1ENR1_TIM4EN RCC_APB1ENR1_TIM4EN_Msk

Definition at line 7755 of file stm32g431xx.h.

◆ RCC_APB1ENR1_TIM4EN_Msk

#define RCC_APB1ENR1_TIM4EN_Msk (0x1UL << RCC_APB1ENR1_TIM4EN_Pos)

0x00000004

Definition at line 7754 of file stm32g431xx.h.

◆ RCC_APB1ENR1_TIM4EN_Pos

#define RCC_APB1ENR1_TIM4EN_Pos (2U)

Definition at line 7753 of file stm32g431xx.h.

◆ RCC_APB1ENR1_TIM6EN

#define RCC_APB1ENR1_TIM6EN RCC_APB1ENR1_TIM6EN_Msk

Definition at line 7758 of file stm32g431xx.h.

◆ RCC_APB1ENR1_TIM6EN_Msk

#define RCC_APB1ENR1_TIM6EN_Msk (0x1UL << RCC_APB1ENR1_TIM6EN_Pos)

0x00000010

Definition at line 7757 of file stm32g431xx.h.

◆ RCC_APB1ENR1_TIM6EN_Pos

#define RCC_APB1ENR1_TIM6EN_Pos (4U)

Definition at line 7756 of file stm32g431xx.h.

◆ RCC_APB1ENR1_TIM7EN

#define RCC_APB1ENR1_TIM7EN RCC_APB1ENR1_TIM7EN_Msk

Definition at line 7761 of file stm32g431xx.h.

◆ RCC_APB1ENR1_TIM7EN_Msk

#define RCC_APB1ENR1_TIM7EN_Msk (0x1UL << RCC_APB1ENR1_TIM7EN_Pos)

0x00000020

Definition at line 7760 of file stm32g431xx.h.

◆ RCC_APB1ENR1_TIM7EN_Pos

#define RCC_APB1ENR1_TIM7EN_Pos (5U)

Definition at line 7759 of file stm32g431xx.h.

◆ RCC_APB1ENR1_UART4EN

#define RCC_APB1ENR1_UART4EN RCC_APB1ENR1_UART4EN_Msk

Definition at line 7785 of file stm32g431xx.h.

◆ RCC_APB1ENR1_UART4EN_Msk

#define RCC_APB1ENR1_UART4EN_Msk (0x1UL << RCC_APB1ENR1_UART4EN_Pos)

0x00080000

Definition at line 7784 of file stm32g431xx.h.

◆ RCC_APB1ENR1_UART4EN_Pos

#define RCC_APB1ENR1_UART4EN_Pos (19U)

Definition at line 7783 of file stm32g431xx.h.

◆ RCC_APB1ENR1_USART2EN

#define RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk

Definition at line 7779 of file stm32g431xx.h.

◆ RCC_APB1ENR1_USART2EN_Msk

#define RCC_APB1ENR1_USART2EN_Msk (0x1UL << RCC_APB1ENR1_USART2EN_Pos)

0x00020000

Definition at line 7778 of file stm32g431xx.h.

◆ RCC_APB1ENR1_USART2EN_Pos

#define RCC_APB1ENR1_USART2EN_Pos (17U)

Definition at line 7777 of file stm32g431xx.h.

◆ RCC_APB1ENR1_USART3EN

#define RCC_APB1ENR1_USART3EN RCC_APB1ENR1_USART3EN_Msk

Definition at line 7782 of file stm32g431xx.h.

◆ RCC_APB1ENR1_USART3EN_Msk

#define RCC_APB1ENR1_USART3EN_Msk (0x1UL << RCC_APB1ENR1_USART3EN_Pos)

0x00040000

Definition at line 7781 of file stm32g431xx.h.

◆ RCC_APB1ENR1_USART3EN_Pos

#define RCC_APB1ENR1_USART3EN_Pos (18U)

Definition at line 7780 of file stm32g431xx.h.

◆ RCC_APB1ENR1_USBEN

#define RCC_APB1ENR1_USBEN RCC_APB1ENR1_USBEN_Msk

Definition at line 7794 of file stm32g431xx.h.

◆ RCC_APB1ENR1_USBEN_Msk

#define RCC_APB1ENR1_USBEN_Msk (0x1UL << RCC_APB1ENR1_USBEN_Pos)

0x00800000

Definition at line 7793 of file stm32g431xx.h.

◆ RCC_APB1ENR1_USBEN_Pos

#define RCC_APB1ENR1_USBEN_Pos (23U)

Definition at line 7792 of file stm32g431xx.h.

◆ RCC_APB1ENR1_WWDGEN

#define RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk

Definition at line 7770 of file stm32g431xx.h.

◆ RCC_APB1ENR1_WWDGEN_Msk

#define RCC_APB1ENR1_WWDGEN_Msk (0x1UL << RCC_APB1ENR1_WWDGEN_Pos)

0x00000800

Definition at line 7769 of file stm32g431xx.h.

◆ RCC_APB1ENR1_WWDGEN_Pos

#define RCC_APB1ENR1_WWDGEN_Pos (11U)

Definition at line 7768 of file stm32g431xx.h.

◆ RCC_APB1ENR2_LPUART1EN

#define RCC_APB1ENR2_LPUART1EN RCC_APB1ENR2_LPUART1EN_Msk

Definition at line 7811 of file stm32g431xx.h.

◆ RCC_APB1ENR2_LPUART1EN_Msk

#define RCC_APB1ENR2_LPUART1EN_Msk (0x1UL << RCC_APB1ENR2_LPUART1EN_Pos)

0x00000001

Definition at line 7810 of file stm32g431xx.h.

◆ RCC_APB1ENR2_LPUART1EN_Pos

#define RCC_APB1ENR2_LPUART1EN_Pos (0U)

Definition at line 7809 of file stm32g431xx.h.

◆ RCC_APB1ENR2_UCPD1EN

#define RCC_APB1ENR2_UCPD1EN RCC_APB1ENR2_UCPD1EN_Msk

Definition at line 7814 of file stm32g431xx.h.

◆ RCC_APB1ENR2_UCPD1EN_Msk

#define RCC_APB1ENR2_UCPD1EN_Msk (0x1UL << RCC_APB1ENR2_UCPD1EN_Pos)

0x00000100

Definition at line 7813 of file stm32g431xx.h.

◆ RCC_APB1ENR2_UCPD1EN_Pos

#define RCC_APB1ENR2_UCPD1EN_Pos (8U)

Definition at line 7812 of file stm32g431xx.h.

◆ RCC_APB1RSTR1_CRSRST

#define RCC_APB1RSTR1_CRSRST RCC_APB1RSTR1_CRSRST_Msk

Definition at line 7611 of file stm32g431xx.h.

◆ RCC_APB1RSTR1_CRSRST_Msk

#define RCC_APB1RSTR1_CRSRST_Msk (0x1UL << RCC_APB1RSTR1_CRSRST_Pos)

0x00000100

Definition at line 7610 of file stm32g431xx.h.

◆ RCC_APB1RSTR1_CRSRST_Pos

#define RCC_APB1RSTR1_CRSRST_Pos (8U)

Definition at line 7609 of file stm32g431xx.h.

◆ RCC_APB1RSTR1_FDCANRST

#define RCC_APB1RSTR1_FDCANRST RCC_APB1RSTR1_FDCANRST_Msk

Definition at line 7638 of file stm32g431xx.h.

◆ RCC_APB1RSTR1_FDCANRST_Msk

#define RCC_APB1RSTR1_FDCANRST_Msk (0x1UL << RCC_APB1RSTR1_FDCANRST_Pos)

0x02000000

Definition at line 7637 of file stm32g431xx.h.

◆ RCC_APB1RSTR1_FDCANRST_Pos

#define RCC_APB1RSTR1_FDCANRST_Pos (25U)

Definition at line 7636 of file stm32g431xx.h.

◆ RCC_APB1RSTR1_I2C1RST

#define RCC_APB1RSTR1_I2C1RST RCC_APB1RSTR1_I2C1RST_Msk

Definition at line 7629 of file stm32g431xx.h.

◆ RCC_APB1RSTR1_I2C1RST_Msk

#define RCC_APB1RSTR1_I2C1RST_Msk (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos)

0x00200000

Definition at line 7628 of file stm32g431xx.h.

◆ RCC_APB1RSTR1_I2C1RST_Pos

#define RCC_APB1RSTR1_I2C1RST_Pos (21U)

Definition at line 7627 of file stm32g431xx.h.

◆ RCC_APB1RSTR1_I2C2RST

#define RCC_APB1RSTR1_I2C2RST RCC_APB1RSTR1_I2C2RST_Msk

Definition at line 7632 of file stm32g431xx.h.

◆ RCC_APB1RSTR1_I2C2RST_Msk

#define RCC_APB1RSTR1_I2C2RST_Msk (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos)

0x00400000

Definition at line 7631 of file stm32g431xx.h.

◆ RCC_APB1RSTR1_I2C2RST_Pos

#define RCC_APB1RSTR1_I2C2RST_Pos (22U)

Definition at line 7630 of file stm32g431xx.h.

◆ RCC_APB1RSTR1_I2C3RST

#define RCC_APB1RSTR1_I2C3RST RCC_APB1RSTR1_I2C3RST_Msk

Definition at line 7644 of file stm32g431xx.h.

◆ RCC_APB1RSTR1_I2C3RST_Msk

#define RCC_APB1RSTR1_I2C3RST_Msk (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos)

0x40000000

Definition at line 7643 of file stm32g431xx.h.

◆ RCC_APB1RSTR1_I2C3RST_Pos

#define RCC_APB1RSTR1_I2C3RST_Pos (30U)

Definition at line 7642 of file stm32g431xx.h.

◆ RCC_APB1RSTR1_LPTIM1RST

#define RCC_APB1RSTR1_LPTIM1RST RCC_APB1RSTR1_LPTIM1RST_Msk

Definition at line 7647 of file stm32g431xx.h.

◆ RCC_APB1RSTR1_LPTIM1RST_Msk

#define RCC_APB1RSTR1_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos)

0x80000000

Definition at line 7646 of file stm32g431xx.h.

◆ RCC_APB1RSTR1_LPTIM1RST_Pos

#define RCC_APB1RSTR1_LPTIM1RST_Pos (31U)

Definition at line 7645 of file stm32g431xx.h.

◆ RCC_APB1RSTR1_PWRRST

#define RCC_APB1RSTR1_PWRRST RCC_APB1RSTR1_PWRRST_Msk

Definition at line 7641 of file stm32g431xx.h.

◆ RCC_APB1RSTR1_PWRRST_Msk

#define RCC_APB1RSTR1_PWRRST_Msk (0x1UL << RCC_APB1RSTR1_PWRRST_Pos)

0x10000000

Definition at line 7640 of file stm32g431xx.h.

◆ RCC_APB1RSTR1_PWRRST_Pos

#define RCC_APB1RSTR1_PWRRST_Pos (28U)

Definition at line 7639 of file stm32g431xx.h.

◆ RCC_APB1RSTR1_SPI2RST

#define RCC_APB1RSTR1_SPI2RST RCC_APB1RSTR1_SPI2RST_Msk

Definition at line 7614 of file stm32g431xx.h.

◆ RCC_APB1RSTR1_SPI2RST_Msk

#define RCC_APB1RSTR1_SPI2RST_Msk (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos)

0x00004000

Definition at line 7613 of file stm32g431xx.h.

◆ RCC_APB1RSTR1_SPI2RST_Pos

#define RCC_APB1RSTR1_SPI2RST_Pos (14U)

Definition at line 7612 of file stm32g431xx.h.

◆ RCC_APB1RSTR1_SPI3RST

#define RCC_APB1RSTR1_SPI3RST RCC_APB1RSTR1_SPI3RST_Msk

Definition at line 7617 of file stm32g431xx.h.

◆ RCC_APB1RSTR1_SPI3RST_Msk

#define RCC_APB1RSTR1_SPI3RST_Msk (0x1UL << RCC_APB1RSTR1_SPI3RST_Pos)

0x00008000

Definition at line 7616 of file stm32g431xx.h.

◆ RCC_APB1RSTR1_SPI3RST_Pos

#define RCC_APB1RSTR1_SPI3RST_Pos (15U)

Definition at line 7615 of file stm32g431xx.h.

◆ RCC_APB1RSTR1_TIM2RST

#define RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk

Definition at line 7596 of file stm32g431xx.h.

◆ RCC_APB1RSTR1_TIM2RST_Msk

#define RCC_APB1RSTR1_TIM2RST_Msk (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos)

0x00000001

Definition at line 7595 of file stm32g431xx.h.

◆ RCC_APB1RSTR1_TIM2RST_Pos

#define RCC_APB1RSTR1_TIM2RST_Pos (0U)

Definition at line 7594 of file stm32g431xx.h.

◆ RCC_APB1RSTR1_TIM3RST

#define RCC_APB1RSTR1_TIM3RST RCC_APB1RSTR1_TIM3RST_Msk

Definition at line 7599 of file stm32g431xx.h.

◆ RCC_APB1RSTR1_TIM3RST_Msk

#define RCC_APB1RSTR1_TIM3RST_Msk (0x1UL << RCC_APB1RSTR1_TIM3RST_Pos)

0x00000002

Definition at line 7598 of file stm32g431xx.h.

◆ RCC_APB1RSTR1_TIM3RST_Pos

#define RCC_APB1RSTR1_TIM3RST_Pos (1U)

Definition at line 7597 of file stm32g431xx.h.

◆ RCC_APB1RSTR1_TIM4RST

#define RCC_APB1RSTR1_TIM4RST RCC_APB1RSTR1_TIM4RST_Msk

Definition at line 7602 of file stm32g431xx.h.

◆ RCC_APB1RSTR1_TIM4RST_Msk

#define RCC_APB1RSTR1_TIM4RST_Msk (0x1UL << RCC_APB1RSTR1_TIM4RST_Pos)

0x00000004

Definition at line 7601 of file stm32g431xx.h.

◆ RCC_APB1RSTR1_TIM4RST_Pos

#define RCC_APB1RSTR1_TIM4RST_Pos (2U)

Definition at line 7600 of file stm32g431xx.h.

◆ RCC_APB1RSTR1_TIM6RST

#define RCC_APB1RSTR1_TIM6RST RCC_APB1RSTR1_TIM6RST_Msk

Definition at line 7605 of file stm32g431xx.h.

◆ RCC_APB1RSTR1_TIM6RST_Msk

#define RCC_APB1RSTR1_TIM6RST_Msk (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos)

0x00000010

Definition at line 7604 of file stm32g431xx.h.

◆ RCC_APB1RSTR1_TIM6RST_Pos

#define RCC_APB1RSTR1_TIM6RST_Pos (4U)

Definition at line 7603 of file stm32g431xx.h.

◆ RCC_APB1RSTR1_TIM7RST

#define RCC_APB1RSTR1_TIM7RST RCC_APB1RSTR1_TIM7RST_Msk

Definition at line 7608 of file stm32g431xx.h.

◆ RCC_APB1RSTR1_TIM7RST_Msk

#define RCC_APB1RSTR1_TIM7RST_Msk (0x1UL << RCC_APB1RSTR1_TIM7RST_Pos)

0x00000020

Definition at line 7607 of file stm32g431xx.h.

◆ RCC_APB1RSTR1_TIM7RST_Pos

#define RCC_APB1RSTR1_TIM7RST_Pos (5U)

Definition at line 7606 of file stm32g431xx.h.

◆ RCC_APB1RSTR1_UART4RST

#define RCC_APB1RSTR1_UART4RST RCC_APB1RSTR1_UART4RST_Msk

Definition at line 7626 of file stm32g431xx.h.

◆ RCC_APB1RSTR1_UART4RST_Msk

#define RCC_APB1RSTR1_UART4RST_Msk (0x1UL << RCC_APB1RSTR1_UART4RST_Pos)

0x00080000

Definition at line 7625 of file stm32g431xx.h.

◆ RCC_APB1RSTR1_UART4RST_Pos

#define RCC_APB1RSTR1_UART4RST_Pos (19U)

Definition at line 7624 of file stm32g431xx.h.

◆ RCC_APB1RSTR1_USART2RST

#define RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk

Definition at line 7620 of file stm32g431xx.h.

◆ RCC_APB1RSTR1_USART2RST_Msk

#define RCC_APB1RSTR1_USART2RST_Msk (0x1UL << RCC_APB1RSTR1_USART2RST_Pos)

0x00020000

Definition at line 7619 of file stm32g431xx.h.

◆ RCC_APB1RSTR1_USART2RST_Pos

#define RCC_APB1RSTR1_USART2RST_Pos (17U)

Definition at line 7618 of file stm32g431xx.h.

◆ RCC_APB1RSTR1_USART3RST

#define RCC_APB1RSTR1_USART3RST RCC_APB1RSTR1_USART3RST_Msk

Definition at line 7623 of file stm32g431xx.h.

◆ RCC_APB1RSTR1_USART3RST_Msk

#define RCC_APB1RSTR1_USART3RST_Msk (0x1UL << RCC_APB1RSTR1_USART3RST_Pos)

0x00040000

Definition at line 7622 of file stm32g431xx.h.

◆ RCC_APB1RSTR1_USART3RST_Pos

#define RCC_APB1RSTR1_USART3RST_Pos (18U)

Definition at line 7621 of file stm32g431xx.h.

◆ RCC_APB1RSTR1_USBRST

#define RCC_APB1RSTR1_USBRST RCC_APB1RSTR1_USBRST_Msk

Definition at line 7635 of file stm32g431xx.h.

◆ RCC_APB1RSTR1_USBRST_Msk

#define RCC_APB1RSTR1_USBRST_Msk (0x1UL << RCC_APB1RSTR1_USBRST_Pos)

0x00800000

Definition at line 7634 of file stm32g431xx.h.

◆ RCC_APB1RSTR1_USBRST_Pos

#define RCC_APB1RSTR1_USBRST_Pos (23U)

Definition at line 7633 of file stm32g431xx.h.

◆ RCC_APB1RSTR2_LPUART1RST

#define RCC_APB1RSTR2_LPUART1RST RCC_APB1RSTR2_LPUART1RST_Msk

Definition at line 7652 of file stm32g431xx.h.

◆ RCC_APB1RSTR2_LPUART1RST_Msk

#define RCC_APB1RSTR2_LPUART1RST_Msk (0x1UL << RCC_APB1RSTR2_LPUART1RST_Pos)

0x00000001

Definition at line 7651 of file stm32g431xx.h.

◆ RCC_APB1RSTR2_LPUART1RST_Pos

#define RCC_APB1RSTR2_LPUART1RST_Pos (0U)

Definition at line 7650 of file stm32g431xx.h.

◆ RCC_APB1RSTR2_UCPD1RST

#define RCC_APB1RSTR2_UCPD1RST RCC_APB1RSTR2_UCPD1RST_Msk

Definition at line 7655 of file stm32g431xx.h.

◆ RCC_APB1RSTR2_UCPD1RST_Msk

#define RCC_APB1RSTR2_UCPD1RST_Msk (0x1UL << RCC_APB1RSTR2_UCPD1RST_Pos)

0x00000100

Definition at line 7654 of file stm32g431xx.h.

◆ RCC_APB1RSTR2_UCPD1RST_Pos

#define RCC_APB1RSTR2_UCPD1RST_Pos (8U)

Definition at line 7653 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_CRSSMEN

#define RCC_APB1SMENR1_CRSSMEN RCC_APB1SMENR1_CRSSMEN_Msk

Definition at line 7932 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_CRSSMEN_Msk

#define RCC_APB1SMENR1_CRSSMEN_Msk (0x1UL << RCC_APB1SMENR1_CRSSMEN_Pos)

0x00000100

Definition at line 7931 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_CRSSMEN_Pos

#define RCC_APB1SMENR1_CRSSMEN_Pos (8U)

Definition at line 7930 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_FDCANSMEN

#define RCC_APB1SMENR1_FDCANSMEN RCC_APB1SMENR1_FDCANSMEN_Msk

Definition at line 7965 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_FDCANSMEN_Msk

#define RCC_APB1SMENR1_FDCANSMEN_Msk (0x1UL << RCC_APB1SMENR1_FDCANSMEN_Pos)

0x02000000

Definition at line 7964 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_FDCANSMEN_Pos

#define RCC_APB1SMENR1_FDCANSMEN_Pos (25U)

Definition at line 7963 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_I2C1SMEN

#define RCC_APB1SMENR1_I2C1SMEN RCC_APB1SMENR1_I2C1SMEN_Msk

Definition at line 7956 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_I2C1SMEN_Msk

#define RCC_APB1SMENR1_I2C1SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C1SMEN_Pos)

0x00200000

Definition at line 7955 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_I2C1SMEN_Pos

#define RCC_APB1SMENR1_I2C1SMEN_Pos (21U)

Definition at line 7954 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_I2C2SMEN

#define RCC_APB1SMENR1_I2C2SMEN RCC_APB1SMENR1_I2C2SMEN_Msk

Definition at line 7959 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_I2C2SMEN_Msk

#define RCC_APB1SMENR1_I2C2SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C2SMEN_Pos)

0x00400000

Definition at line 7958 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_I2C2SMEN_Pos

#define RCC_APB1SMENR1_I2C2SMEN_Pos (22U)

Definition at line 7957 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_I2C3SMEN

#define RCC_APB1SMENR1_I2C3SMEN RCC_APB1SMENR1_I2C3SMEN_Msk

Definition at line 7971 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_I2C3SMEN_Msk

#define RCC_APB1SMENR1_I2C3SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C3SMEN_Pos)

0x40000000

Definition at line 7970 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_I2C3SMEN_Pos

#define RCC_APB1SMENR1_I2C3SMEN_Pos (30U)

Definition at line 7969 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_LPTIM1SMEN

#define RCC_APB1SMENR1_LPTIM1SMEN RCC_APB1SMENR1_LPTIM1SMEN_Msk

Definition at line 7974 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_LPTIM1SMEN_Msk

#define RCC_APB1SMENR1_LPTIM1SMEN_Msk (0x1UL << RCC_APB1SMENR1_LPTIM1SMEN_Pos)

0x80000000

Definition at line 7973 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_LPTIM1SMEN_Pos

#define RCC_APB1SMENR1_LPTIM1SMEN_Pos (31U)

Definition at line 7972 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_PWRSMEN

#define RCC_APB1SMENR1_PWRSMEN RCC_APB1SMENR1_PWRSMEN_Msk

Definition at line 7968 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_PWRSMEN_Msk

#define RCC_APB1SMENR1_PWRSMEN_Msk (0x1UL << RCC_APB1SMENR1_PWRSMEN_Pos)

0x10000000

Definition at line 7967 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_PWRSMEN_Pos

#define RCC_APB1SMENR1_PWRSMEN_Pos (28U)

Definition at line 7966 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_RTCAPBSMEN

#define RCC_APB1SMENR1_RTCAPBSMEN RCC_APB1SMENR1_RTCAPBSMEN_Msk

Definition at line 7935 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_RTCAPBSMEN_Msk

#define RCC_APB1SMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_APB1SMENR1_RTCAPBSMEN_Pos)

0x00000400

Definition at line 7934 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_RTCAPBSMEN_Pos

#define RCC_APB1SMENR1_RTCAPBSMEN_Pos (10U)

Definition at line 7933 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_SPI2SMEN

#define RCC_APB1SMENR1_SPI2SMEN RCC_APB1SMENR1_SPI2SMEN_Msk

Definition at line 7941 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_SPI2SMEN_Msk

#define RCC_APB1SMENR1_SPI2SMEN_Msk (0x1UL << RCC_APB1SMENR1_SPI2SMEN_Pos)

0x00004000

Definition at line 7940 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_SPI2SMEN_Pos

#define RCC_APB1SMENR1_SPI2SMEN_Pos (14U)

Definition at line 7939 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_SPI3SMEN

#define RCC_APB1SMENR1_SPI3SMEN RCC_APB1SMENR1_SPI3SMEN_Msk

Definition at line 7944 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_SPI3SMEN_Msk

#define RCC_APB1SMENR1_SPI3SMEN_Msk (0x1UL << RCC_APB1SMENR1_SPI3SMEN_Pos)

0x00008000

Definition at line 7943 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_SPI3SMEN_Pos

#define RCC_APB1SMENR1_SPI3SMEN_Pos (15U)

Definition at line 7942 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_TIM2SMEN

#define RCC_APB1SMENR1_TIM2SMEN RCC_APB1SMENR1_TIM2SMEN_Msk

Definition at line 7917 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_TIM2SMEN_Msk

#define RCC_APB1SMENR1_TIM2SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM2SMEN_Pos)

0x00000001

Definition at line 7916 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_TIM2SMEN_Pos

#define RCC_APB1SMENR1_TIM2SMEN_Pos (0U)

Definition at line 7915 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_TIM3SMEN

#define RCC_APB1SMENR1_TIM3SMEN RCC_APB1SMENR1_TIM3SMEN_Msk

Definition at line 7920 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_TIM3SMEN_Msk

#define RCC_APB1SMENR1_TIM3SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM3SMEN_Pos)

0x00000002

Definition at line 7919 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_TIM3SMEN_Pos

#define RCC_APB1SMENR1_TIM3SMEN_Pos (1U)

Definition at line 7918 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_TIM4SMEN

#define RCC_APB1SMENR1_TIM4SMEN RCC_APB1SMENR1_TIM4SMEN_Msk

Definition at line 7923 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_TIM4SMEN_Msk

#define RCC_APB1SMENR1_TIM4SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM4SMEN_Pos)

0x00000004

Definition at line 7922 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_TIM4SMEN_Pos

#define RCC_APB1SMENR1_TIM4SMEN_Pos (2U)

Definition at line 7921 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_TIM6SMEN

#define RCC_APB1SMENR1_TIM6SMEN RCC_APB1SMENR1_TIM6SMEN_Msk

Definition at line 7926 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_TIM6SMEN_Msk

#define RCC_APB1SMENR1_TIM6SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM6SMEN_Pos)

0x00000010

Definition at line 7925 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_TIM6SMEN_Pos

#define RCC_APB1SMENR1_TIM6SMEN_Pos (4U)

Definition at line 7924 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_TIM7SMEN

#define RCC_APB1SMENR1_TIM7SMEN RCC_APB1SMENR1_TIM7SMEN_Msk

Definition at line 7929 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_TIM7SMEN_Msk

#define RCC_APB1SMENR1_TIM7SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM7SMEN_Pos)

0x00000020

Definition at line 7928 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_TIM7SMEN_Pos

#define RCC_APB1SMENR1_TIM7SMEN_Pos (5U)

Definition at line 7927 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_UART4SMEN

#define RCC_APB1SMENR1_UART4SMEN RCC_APB1SMENR1_UART4SMEN_Msk

Definition at line 7953 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_UART4SMEN_Msk

#define RCC_APB1SMENR1_UART4SMEN_Msk (0x1UL << RCC_APB1SMENR1_UART4SMEN_Pos)

0x00080000

Definition at line 7952 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_UART4SMEN_Pos

#define RCC_APB1SMENR1_UART4SMEN_Pos (19U)

Definition at line 7951 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_USART2SMEN

#define RCC_APB1SMENR1_USART2SMEN RCC_APB1SMENR1_USART2SMEN_Msk

Definition at line 7947 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_USART2SMEN_Msk

#define RCC_APB1SMENR1_USART2SMEN_Msk (0x1UL << RCC_APB1SMENR1_USART2SMEN_Pos)

0x00020000

Definition at line 7946 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_USART2SMEN_Pos

#define RCC_APB1SMENR1_USART2SMEN_Pos (17U)

Definition at line 7945 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_USART3SMEN

#define RCC_APB1SMENR1_USART3SMEN RCC_APB1SMENR1_USART3SMEN_Msk

Definition at line 7950 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_USART3SMEN_Msk

#define RCC_APB1SMENR1_USART3SMEN_Msk (0x1UL << RCC_APB1SMENR1_USART3SMEN_Pos)

0x00040000

Definition at line 7949 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_USART3SMEN_Pos

#define RCC_APB1SMENR1_USART3SMEN_Pos (18U)

Definition at line 7948 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_USBSMEN

#define RCC_APB1SMENR1_USBSMEN RCC_APB1SMENR1_USBSMEN_Msk

Definition at line 7962 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_USBSMEN_Msk

#define RCC_APB1SMENR1_USBSMEN_Msk (0x1UL << RCC_APB1SMENR1_USBSMEN_Pos)

0x00800000

Definition at line 7961 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_USBSMEN_Pos

#define RCC_APB1SMENR1_USBSMEN_Pos (23U)

Definition at line 7960 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_WWDGSMEN

#define RCC_APB1SMENR1_WWDGSMEN RCC_APB1SMENR1_WWDGSMEN_Msk

Definition at line 7938 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_WWDGSMEN_Msk

#define RCC_APB1SMENR1_WWDGSMEN_Msk (0x1UL << RCC_APB1SMENR1_WWDGSMEN_Pos)

0x00000800

Definition at line 7937 of file stm32g431xx.h.

◆ RCC_APB1SMENR1_WWDGSMEN_Pos

#define RCC_APB1SMENR1_WWDGSMEN_Pos (11U)

Definition at line 7936 of file stm32g431xx.h.

◆ RCC_APB1SMENR2_LPUART1SMEN

#define RCC_APB1SMENR2_LPUART1SMEN RCC_APB1SMENR2_LPUART1SMEN_Msk

Definition at line 7979 of file stm32g431xx.h.

◆ RCC_APB1SMENR2_LPUART1SMEN_Msk

#define RCC_APB1SMENR2_LPUART1SMEN_Msk (0x1UL << RCC_APB1SMENR2_LPUART1SMEN_Pos)

0x00000001

Definition at line 7978 of file stm32g431xx.h.

◆ RCC_APB1SMENR2_LPUART1SMEN_Pos

#define RCC_APB1SMENR2_LPUART1SMEN_Pos (0U)

Definition at line 7977 of file stm32g431xx.h.

◆ RCC_APB1SMENR2_UCPD1SMEN

#define RCC_APB1SMENR2_UCPD1SMEN RCC_APB1SMENR2_UCPD1SMEN_Msk

Definition at line 7982 of file stm32g431xx.h.

◆ RCC_APB1SMENR2_UCPD1SMEN_Msk

#define RCC_APB1SMENR2_UCPD1SMEN_Msk (0x1UL << RCC_APB1SMENR2_UCPD1SMEN_Pos)

0x00000100

Definition at line 7981 of file stm32g431xx.h.

◆ RCC_APB1SMENR2_UCPD1SMEN_Pos

#define RCC_APB1SMENR2_UCPD1SMEN_Pos (8U)

Definition at line 7980 of file stm32g431xx.h.

◆ RCC_APB2ENR_SAI1EN

#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk

Definition at line 7843 of file stm32g431xx.h.

◆ RCC_APB2ENR_SAI1EN_Msk

#define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos)

0x00200000

Definition at line 7842 of file stm32g431xx.h.

◆ RCC_APB2ENR_SAI1EN_Pos

#define RCC_APB2ENR_SAI1EN_Pos (21U)

Definition at line 7841 of file stm32g431xx.h.

◆ RCC_APB2ENR_SPI1EN

#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk

Definition at line 7825 of file stm32g431xx.h.

◆ RCC_APB2ENR_SPI1EN_Msk

#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos)

0x00001000

Definition at line 7824 of file stm32g431xx.h.

◆ RCC_APB2ENR_SPI1EN_Pos

#define RCC_APB2ENR_SPI1EN_Pos (12U)

Definition at line 7823 of file stm32g431xx.h.

◆ RCC_APB2ENR_SYSCFGEN

#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk

Definition at line 7819 of file stm32g431xx.h.

◆ RCC_APB2ENR_SYSCFGEN_Msk

#define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)

0x00000001

Definition at line 7818 of file stm32g431xx.h.

◆ RCC_APB2ENR_SYSCFGEN_Pos

#define RCC_APB2ENR_SYSCFGEN_Pos (0U)

Definition at line 7817 of file stm32g431xx.h.

◆ RCC_APB2ENR_TIM15EN

#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk

Definition at line 7834 of file stm32g431xx.h.

◆ RCC_APB2ENR_TIM15EN_Msk

#define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos)

0x00010000

Definition at line 7833 of file stm32g431xx.h.

◆ RCC_APB2ENR_TIM15EN_Pos

#define RCC_APB2ENR_TIM15EN_Pos (16U)

Definition at line 7832 of file stm32g431xx.h.

◆ RCC_APB2ENR_TIM16EN

#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk

Definition at line 7837 of file stm32g431xx.h.

◆ RCC_APB2ENR_TIM16EN_Msk

#define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos)

0x00020000

Definition at line 7836 of file stm32g431xx.h.

◆ RCC_APB2ENR_TIM16EN_Pos

#define RCC_APB2ENR_TIM16EN_Pos (17U)

Definition at line 7835 of file stm32g431xx.h.

◆ RCC_APB2ENR_TIM17EN

#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk

Definition at line 7840 of file stm32g431xx.h.

◆ RCC_APB2ENR_TIM17EN_Msk

#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos)

0x00040000

Definition at line 7839 of file stm32g431xx.h.

◆ RCC_APB2ENR_TIM17EN_Pos

#define RCC_APB2ENR_TIM17EN_Pos (18U)

Definition at line 7838 of file stm32g431xx.h.

◆ RCC_APB2ENR_TIM1EN

#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk

Definition at line 7822 of file stm32g431xx.h.

◆ RCC_APB2ENR_TIM1EN_Msk

#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos)

0x00000800

Definition at line 7821 of file stm32g431xx.h.

◆ RCC_APB2ENR_TIM1EN_Pos

#define RCC_APB2ENR_TIM1EN_Pos (11U)

Definition at line 7820 of file stm32g431xx.h.

◆ RCC_APB2ENR_TIM8EN

#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk

Definition at line 7828 of file stm32g431xx.h.

◆ RCC_APB2ENR_TIM8EN_Msk

#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos)

0x00002000

Definition at line 7827 of file stm32g431xx.h.

◆ RCC_APB2ENR_TIM8EN_Pos

#define RCC_APB2ENR_TIM8EN_Pos (13U)

Definition at line 7826 of file stm32g431xx.h.

◆ RCC_APB2ENR_USART1EN

#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk

Definition at line 7831 of file stm32g431xx.h.

◆ RCC_APB2ENR_USART1EN_Msk

#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)

0x00004000

Definition at line 7830 of file stm32g431xx.h.

◆ RCC_APB2ENR_USART1EN_Pos

#define RCC_APB2ENR_USART1EN_Pos (14U)

Definition at line 7829 of file stm32g431xx.h.

◆ RCC_APB2RSTR_SAI1RST

#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk

Definition at line 7684 of file stm32g431xx.h.

◆ RCC_APB2RSTR_SAI1RST_Msk

#define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)

0x00200000

Definition at line 7683 of file stm32g431xx.h.

◆ RCC_APB2RSTR_SAI1RST_Pos

#define RCC_APB2RSTR_SAI1RST_Pos (21U)

Definition at line 7682 of file stm32g431xx.h.

◆ RCC_APB2RSTR_SPI1RST

#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk

Definition at line 7666 of file stm32g431xx.h.

◆ RCC_APB2RSTR_SPI1RST_Msk

#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)

0x00001000

Definition at line 7665 of file stm32g431xx.h.

◆ RCC_APB2RSTR_SPI1RST_Pos

#define RCC_APB2RSTR_SPI1RST_Pos (12U)

Definition at line 7664 of file stm32g431xx.h.

◆ RCC_APB2RSTR_SYSCFGRST

#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk

Definition at line 7660 of file stm32g431xx.h.

◆ RCC_APB2RSTR_SYSCFGRST_Msk

#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)

0x00000001

Definition at line 7659 of file stm32g431xx.h.

◆ RCC_APB2RSTR_SYSCFGRST_Pos

#define RCC_APB2RSTR_SYSCFGRST_Pos (0U)

Definition at line 7658 of file stm32g431xx.h.

◆ RCC_APB2RSTR_TIM15RST

#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk

Definition at line 7675 of file stm32g431xx.h.

◆ RCC_APB2RSTR_TIM15RST_Msk

#define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos)

0x00010000

Definition at line 7674 of file stm32g431xx.h.

◆ RCC_APB2RSTR_TIM15RST_Pos

#define RCC_APB2RSTR_TIM15RST_Pos (16U)

Definition at line 7673 of file stm32g431xx.h.

◆ RCC_APB2RSTR_TIM16RST

#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk

Definition at line 7678 of file stm32g431xx.h.

◆ RCC_APB2RSTR_TIM16RST_Msk

#define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos)

0x00020000

Definition at line 7677 of file stm32g431xx.h.

◆ RCC_APB2RSTR_TIM16RST_Pos

#define RCC_APB2RSTR_TIM16RST_Pos (17U)

Definition at line 7676 of file stm32g431xx.h.

◆ RCC_APB2RSTR_TIM17RST

#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk

Definition at line 7681 of file stm32g431xx.h.

◆ RCC_APB2RSTR_TIM17RST_Msk

#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)

0x00040000

Definition at line 7680 of file stm32g431xx.h.

◆ RCC_APB2RSTR_TIM17RST_Pos

#define RCC_APB2RSTR_TIM17RST_Pos (18U)

Definition at line 7679 of file stm32g431xx.h.

◆ RCC_APB2RSTR_TIM1RST

#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk

Definition at line 7663 of file stm32g431xx.h.

◆ RCC_APB2RSTR_TIM1RST_Msk

#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)

0x00000800

Definition at line 7662 of file stm32g431xx.h.

◆ RCC_APB2RSTR_TIM1RST_Pos

#define RCC_APB2RSTR_TIM1RST_Pos (11U)

Definition at line 7661 of file stm32g431xx.h.

◆ RCC_APB2RSTR_TIM8RST

#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk

Definition at line 7669 of file stm32g431xx.h.

◆ RCC_APB2RSTR_TIM8RST_Msk

#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)

0x00002000

Definition at line 7668 of file stm32g431xx.h.

◆ RCC_APB2RSTR_TIM8RST_Pos

#define RCC_APB2RSTR_TIM8RST_Pos (13U)

Definition at line 7667 of file stm32g431xx.h.

◆ RCC_APB2RSTR_USART1RST

#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk

Definition at line 7672 of file stm32g431xx.h.

◆ RCC_APB2RSTR_USART1RST_Msk

#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)

0x00004000

Definition at line 7671 of file stm32g431xx.h.

◆ RCC_APB2RSTR_USART1RST_Pos

#define RCC_APB2RSTR_USART1RST_Pos (14U)

Definition at line 7670 of file stm32g431xx.h.

◆ RCC_APB2SMENR_SAI1SMEN

#define RCC_APB2SMENR_SAI1SMEN RCC_APB2SMENR_SAI1SMEN_Msk

Definition at line 8011 of file stm32g431xx.h.

◆ RCC_APB2SMENR_SAI1SMEN_Msk

#define RCC_APB2SMENR_SAI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SAI1SMEN_Pos)

0x00200000

Definition at line 8010 of file stm32g431xx.h.

◆ RCC_APB2SMENR_SAI1SMEN_Pos

#define RCC_APB2SMENR_SAI1SMEN_Pos (21U)

Definition at line 8009 of file stm32g431xx.h.

◆ RCC_APB2SMENR_SPI1SMEN

#define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk

Definition at line 7993 of file stm32g431xx.h.

◆ RCC_APB2SMENR_SPI1SMEN_Msk

#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)

0x00001000

Definition at line 7992 of file stm32g431xx.h.

◆ RCC_APB2SMENR_SPI1SMEN_Pos

#define RCC_APB2SMENR_SPI1SMEN_Pos (12U)

Definition at line 7991 of file stm32g431xx.h.

◆ RCC_APB2SMENR_SYSCFGSMEN

#define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk

Definition at line 7987 of file stm32g431xx.h.

◆ RCC_APB2SMENR_SYSCFGSMEN_Msk

#define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos)

0x00000001

Definition at line 7986 of file stm32g431xx.h.

◆ RCC_APB2SMENR_SYSCFGSMEN_Pos

#define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U)

Definition at line 7985 of file stm32g431xx.h.

◆ RCC_APB2SMENR_TIM15SMEN

#define RCC_APB2SMENR_TIM15SMEN RCC_APB2SMENR_TIM15SMEN_Msk

Definition at line 8002 of file stm32g431xx.h.

◆ RCC_APB2SMENR_TIM15SMEN_Msk

#define RCC_APB2SMENR_TIM15SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM15SMEN_Pos)

0x00010000

Definition at line 8001 of file stm32g431xx.h.

◆ RCC_APB2SMENR_TIM15SMEN_Pos

#define RCC_APB2SMENR_TIM15SMEN_Pos (16U)

Definition at line 8000 of file stm32g431xx.h.

◆ RCC_APB2SMENR_TIM16SMEN

#define RCC_APB2SMENR_TIM16SMEN RCC_APB2SMENR_TIM16SMEN_Msk

Definition at line 8005 of file stm32g431xx.h.

◆ RCC_APB2SMENR_TIM16SMEN_Msk

#define RCC_APB2SMENR_TIM16SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos)

0x00020000

Definition at line 8004 of file stm32g431xx.h.

◆ RCC_APB2SMENR_TIM16SMEN_Pos

#define RCC_APB2SMENR_TIM16SMEN_Pos (17U)

Definition at line 8003 of file stm32g431xx.h.

◆ RCC_APB2SMENR_TIM17SMEN

#define RCC_APB2SMENR_TIM17SMEN RCC_APB2SMENR_TIM17SMEN_Msk

Definition at line 8008 of file stm32g431xx.h.

◆ RCC_APB2SMENR_TIM17SMEN_Msk

#define RCC_APB2SMENR_TIM17SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM17SMEN_Pos)

0x00040000

Definition at line 8007 of file stm32g431xx.h.

◆ RCC_APB2SMENR_TIM17SMEN_Pos

#define RCC_APB2SMENR_TIM17SMEN_Pos (18U)

Definition at line 8006 of file stm32g431xx.h.

◆ RCC_APB2SMENR_TIM1SMEN

#define RCC_APB2SMENR_TIM1SMEN RCC_APB2SMENR_TIM1SMEN_Msk

Definition at line 7990 of file stm32g431xx.h.

◆ RCC_APB2SMENR_TIM1SMEN_Msk

#define RCC_APB2SMENR_TIM1SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos)

0x00000800

Definition at line 7989 of file stm32g431xx.h.

◆ RCC_APB2SMENR_TIM1SMEN_Pos

#define RCC_APB2SMENR_TIM1SMEN_Pos (11U)

Definition at line 7988 of file stm32g431xx.h.

◆ RCC_APB2SMENR_TIM8SMEN

#define RCC_APB2SMENR_TIM8SMEN RCC_APB2SMENR_TIM8SMEN_Msk

Definition at line 7996 of file stm32g431xx.h.

◆ RCC_APB2SMENR_TIM8SMEN_Msk

#define RCC_APB2SMENR_TIM8SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM8SMEN_Pos)

0x00002000

Definition at line 7995 of file stm32g431xx.h.

◆ RCC_APB2SMENR_TIM8SMEN_Pos

#define RCC_APB2SMENR_TIM8SMEN_Pos (13U)

Definition at line 7994 of file stm32g431xx.h.

◆ RCC_APB2SMENR_USART1SMEN

#define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk

Definition at line 7999 of file stm32g431xx.h.

◆ RCC_APB2SMENR_USART1SMEN_Msk

#define RCC_APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos)

0x00004000

Definition at line 7998 of file stm32g431xx.h.

◆ RCC_APB2SMENR_USART1SMEN_Pos

#define RCC_APB2SMENR_USART1SMEN_Pos (14U)

Definition at line 7997 of file stm32g431xx.h.

◆ RCC_BDCR_BDRST

#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk

Definition at line 8135 of file stm32g431xx.h.

◆ RCC_BDCR_BDRST_Msk

#define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos)

0x00010000

Definition at line 8134 of file stm32g431xx.h.

◆ RCC_BDCR_BDRST_Pos

#define RCC_BDCR_BDRST_Pos (16U)

Definition at line 8133 of file stm32g431xx.h.

◆ RCC_BDCR_LSCOEN

#define RCC_BDCR_LSCOEN RCC_BDCR_LSCOEN_Msk

Definition at line 8138 of file stm32g431xx.h.

◆ RCC_BDCR_LSCOEN_Msk

#define RCC_BDCR_LSCOEN_Msk (0x1UL << RCC_BDCR_LSCOEN_Pos)

0x01000000

Definition at line 8137 of file stm32g431xx.h.

◆ RCC_BDCR_LSCOEN_Pos

#define RCC_BDCR_LSCOEN_Pos (24U)

Definition at line 8136 of file stm32g431xx.h.

◆ RCC_BDCR_LSCOSEL

#define RCC_BDCR_LSCOSEL RCC_BDCR_LSCOSEL_Msk

Definition at line 8141 of file stm32g431xx.h.

◆ RCC_BDCR_LSCOSEL_Msk

#define RCC_BDCR_LSCOSEL_Msk (0x1UL << RCC_BDCR_LSCOSEL_Pos)

0x02000000

Definition at line 8140 of file stm32g431xx.h.

◆ RCC_BDCR_LSCOSEL_Pos

#define RCC_BDCR_LSCOSEL_Pos (25U)

Definition at line 8139 of file stm32g431xx.h.

◆ RCC_BDCR_LSEBYP

#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk

Definition at line 8109 of file stm32g431xx.h.

◆ RCC_BDCR_LSEBYP_Msk

#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos)

0x00000004

Definition at line 8108 of file stm32g431xx.h.

◆ RCC_BDCR_LSEBYP_Pos

#define RCC_BDCR_LSEBYP_Pos (2U)

Definition at line 8107 of file stm32g431xx.h.

◆ RCC_BDCR_LSECSSD

#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk

Definition at line 8122 of file stm32g431xx.h.

◆ RCC_BDCR_LSECSSD_Msk

#define RCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos)

0x00000040

Definition at line 8121 of file stm32g431xx.h.

◆ RCC_BDCR_LSECSSD_Pos

#define RCC_BDCR_LSECSSD_Pos (6U)

Definition at line 8120 of file stm32g431xx.h.

◆ RCC_BDCR_LSECSSON

#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk

Definition at line 8119 of file stm32g431xx.h.

◆ RCC_BDCR_LSECSSON_Msk

#define RCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos)

0x00000020

Definition at line 8118 of file stm32g431xx.h.

◆ RCC_BDCR_LSECSSON_Pos

#define RCC_BDCR_LSECSSON_Pos (5U)

Definition at line 8117 of file stm32g431xx.h.

◆ RCC_BDCR_LSEDRV

#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk

Definition at line 8113 of file stm32g431xx.h.

◆ RCC_BDCR_LSEDRV_0

#define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos)

0x00000008

Definition at line 8114 of file stm32g431xx.h.

◆ RCC_BDCR_LSEDRV_1

#define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos)

0x00000010

Definition at line 8115 of file stm32g431xx.h.

◆ RCC_BDCR_LSEDRV_Msk

#define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos)

0x00000018

Definition at line 8112 of file stm32g431xx.h.

◆ RCC_BDCR_LSEDRV_Pos

#define RCC_BDCR_LSEDRV_Pos (3U)

Definition at line 8111 of file stm32g431xx.h.

◆ RCC_BDCR_LSEON

#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk

Definition at line 8103 of file stm32g431xx.h.

◆ RCC_BDCR_LSEON_Msk

#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos)

0x00000001

Definition at line 8102 of file stm32g431xx.h.

◆ RCC_BDCR_LSEON_Pos

#define RCC_BDCR_LSEON_Pos (0U)

Definition at line 8101 of file stm32g431xx.h.

◆ RCC_BDCR_LSERDY

#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk

Definition at line 8106 of file stm32g431xx.h.

◆ RCC_BDCR_LSERDY_Msk

#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos)

0x00000002

Definition at line 8105 of file stm32g431xx.h.

◆ RCC_BDCR_LSERDY_Pos

#define RCC_BDCR_LSERDY_Pos (1U)

Definition at line 8104 of file stm32g431xx.h.

◆ RCC_BDCR_RTCEN

#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk

Definition at line 8132 of file stm32g431xx.h.

◆ RCC_BDCR_RTCEN_Msk

#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos)

0x00008000

Definition at line 8131 of file stm32g431xx.h.

◆ RCC_BDCR_RTCEN_Pos

#define RCC_BDCR_RTCEN_Pos (15U)

Definition at line 8130 of file stm32g431xx.h.

◆ RCC_BDCR_RTCSEL

#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk

Definition at line 8126 of file stm32g431xx.h.

◆ RCC_BDCR_RTCSEL_0

#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos)

0x00000100

Definition at line 8127 of file stm32g431xx.h.

◆ RCC_BDCR_RTCSEL_1

#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos)

0x00000200

Definition at line 8128 of file stm32g431xx.h.

◆ RCC_BDCR_RTCSEL_Msk

#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos)

0x00000300

Definition at line 8125 of file stm32g431xx.h.

◆ RCC_BDCR_RTCSEL_Pos

#define RCC_BDCR_RTCSEL_Pos (8U)

Definition at line 8124 of file stm32g431xx.h.

◆ RCC_CCIPR_ADC12SEL

#define RCC_CCIPR_ADC12SEL RCC_CCIPR_ADC12SEL_Msk

Definition at line 8095 of file stm32g431xx.h.

◆ RCC_CCIPR_ADC12SEL_0

#define RCC_CCIPR_ADC12SEL_0 (0x1UL << RCC_CCIPR_ADC12SEL_Pos)

0x10000000

Definition at line 8096 of file stm32g431xx.h.

◆ RCC_CCIPR_ADC12SEL_1

#define RCC_CCIPR_ADC12SEL_1 (0x2UL << RCC_CCIPR_ADC12SEL_Pos)

0x20000000

Definition at line 8097 of file stm32g431xx.h.

◆ RCC_CCIPR_ADC12SEL_Msk

#define RCC_CCIPR_ADC12SEL_Msk (0x3UL << RCC_CCIPR_ADC12SEL_Pos)

0x30000000

Definition at line 8094 of file stm32g431xx.h.

◆ RCC_CCIPR_ADC12SEL_Pos

#define RCC_CCIPR_ADC12SEL_Pos (28U)

Definition at line 8093 of file stm32g431xx.h.

◆ RCC_CCIPR_CLK48SEL

#define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk

Definition at line 8089 of file stm32g431xx.h.

◆ RCC_CCIPR_CLK48SEL_0

#define RCC_CCIPR_CLK48SEL_0 (0x1UL << RCC_CCIPR_CLK48SEL_Pos)

0x04000000

Definition at line 8090 of file stm32g431xx.h.

◆ RCC_CCIPR_CLK48SEL_1

#define RCC_CCIPR_CLK48SEL_1 (0x2UL << RCC_CCIPR_CLK48SEL_Pos)

0x08000000

Definition at line 8091 of file stm32g431xx.h.

◆ RCC_CCIPR_CLK48SEL_Msk

#define RCC_CCIPR_CLK48SEL_Msk (0x3UL << RCC_CCIPR_CLK48SEL_Pos)

0x0C000000

Definition at line 8088 of file stm32g431xx.h.

◆ RCC_CCIPR_CLK48SEL_Pos

#define RCC_CCIPR_CLK48SEL_Pos (26U)

Definition at line 8087 of file stm32g431xx.h.

◆ RCC_CCIPR_FDCANSEL

#define RCC_CCIPR_FDCANSEL RCC_CCIPR_FDCANSEL_Msk

Definition at line 8083 of file stm32g431xx.h.

◆ RCC_CCIPR_FDCANSEL_0

#define RCC_CCIPR_FDCANSEL_0 (0x1UL << RCC_CCIPR_FDCANSEL_Pos)

0x01000000

Definition at line 8084 of file stm32g431xx.h.

◆ RCC_CCIPR_FDCANSEL_1

#define RCC_CCIPR_FDCANSEL_1 (0x2UL << RCC_CCIPR_FDCANSEL_Pos)

0x02000000

Definition at line 8085 of file stm32g431xx.h.

◆ RCC_CCIPR_FDCANSEL_Msk

#define RCC_CCIPR_FDCANSEL_Msk (0x3UL << RCC_CCIPR_FDCANSEL_Pos)

0x03000000

Definition at line 8082 of file stm32g431xx.h.

◆ RCC_CCIPR_FDCANSEL_Pos

#define RCC_CCIPR_FDCANSEL_Pos (24U)

Definition at line 8081 of file stm32g431xx.h.

◆ RCC_CCIPR_I2C1SEL

#define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk

Definition at line 8047 of file stm32g431xx.h.

◆ RCC_CCIPR_I2C1SEL_0

#define RCC_CCIPR_I2C1SEL_0 (0x1UL << RCC_CCIPR_I2C1SEL_Pos)

0x00001000

Definition at line 8048 of file stm32g431xx.h.

◆ RCC_CCIPR_I2C1SEL_1

#define RCC_CCIPR_I2C1SEL_1 (0x2UL << RCC_CCIPR_I2C1SEL_Pos)

0x00002000

Definition at line 8049 of file stm32g431xx.h.

◆ RCC_CCIPR_I2C1SEL_Msk

#define RCC_CCIPR_I2C1SEL_Msk (0x3UL << RCC_CCIPR_I2C1SEL_Pos)

0x00003000

Definition at line 8046 of file stm32g431xx.h.

◆ RCC_CCIPR_I2C1SEL_Pos

#define RCC_CCIPR_I2C1SEL_Pos (12U)

Definition at line 8045 of file stm32g431xx.h.

◆ RCC_CCIPR_I2C2SEL

#define RCC_CCIPR_I2C2SEL RCC_CCIPR_I2C2SEL_Msk

Definition at line 8053 of file stm32g431xx.h.

◆ RCC_CCIPR_I2C2SEL_0

#define RCC_CCIPR_I2C2SEL_0 (0x1UL << RCC_CCIPR_I2C2SEL_Pos)

0x00004000

Definition at line 8054 of file stm32g431xx.h.

◆ RCC_CCIPR_I2C2SEL_1

#define RCC_CCIPR_I2C2SEL_1 (0x2UL << RCC_CCIPR_I2C2SEL_Pos)

0x00008000

Definition at line 8055 of file stm32g431xx.h.

◆ RCC_CCIPR_I2C2SEL_Msk

#define RCC_CCIPR_I2C2SEL_Msk (0x3UL << RCC_CCIPR_I2C2SEL_Pos)

0x0000C000

Definition at line 8052 of file stm32g431xx.h.

◆ RCC_CCIPR_I2C2SEL_Pos

#define RCC_CCIPR_I2C2SEL_Pos (14U)

Definition at line 8051 of file stm32g431xx.h.

◆ RCC_CCIPR_I2C3SEL

#define RCC_CCIPR_I2C3SEL RCC_CCIPR_I2C3SEL_Msk

Definition at line 8059 of file stm32g431xx.h.

◆ RCC_CCIPR_I2C3SEL_0

#define RCC_CCIPR_I2C3SEL_0 (0x1UL << RCC_CCIPR_I2C3SEL_Pos)

0x00010000

Definition at line 8060 of file stm32g431xx.h.

◆ RCC_CCIPR_I2C3SEL_1

#define RCC_CCIPR_I2C3SEL_1 (0x2UL << RCC_CCIPR_I2C3SEL_Pos)

0x00020000

Definition at line 8061 of file stm32g431xx.h.

◆ RCC_CCIPR_I2C3SEL_Msk

#define RCC_CCIPR_I2C3SEL_Msk (0x3UL << RCC_CCIPR_I2C3SEL_Pos)

0x00030000

Definition at line 8058 of file stm32g431xx.h.

◆ RCC_CCIPR_I2C3SEL_Pos

#define RCC_CCIPR_I2C3SEL_Pos (16U)

Definition at line 8057 of file stm32g431xx.h.

◆ RCC_CCIPR_I2S23SEL

#define RCC_CCIPR_I2S23SEL RCC_CCIPR_I2S23SEL_Msk

Definition at line 8077 of file stm32g431xx.h.

◆ RCC_CCIPR_I2S23SEL_0

#define RCC_CCIPR_I2S23SEL_0 (0x1UL << RCC_CCIPR_I2S23SEL_Pos)

0x00400000

Definition at line 8078 of file stm32g431xx.h.

◆ RCC_CCIPR_I2S23SEL_1

#define RCC_CCIPR_I2S23SEL_1 (0x2UL << RCC_CCIPR_I2S23SEL_Pos)

0x00800000

Definition at line 8079 of file stm32g431xx.h.

◆ RCC_CCIPR_I2S23SEL_Msk

#define RCC_CCIPR_I2S23SEL_Msk (0x3UL << RCC_CCIPR_I2S23SEL_Pos)

0x00C00000

Definition at line 8076 of file stm32g431xx.h.

◆ RCC_CCIPR_I2S23SEL_Pos

#define RCC_CCIPR_I2S23SEL_Pos (22U)

Definition at line 8075 of file stm32g431xx.h.

◆ RCC_CCIPR_LPTIM1SEL

#define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk

Definition at line 8065 of file stm32g431xx.h.

◆ RCC_CCIPR_LPTIM1SEL_0

#define RCC_CCIPR_LPTIM1SEL_0 (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos)

0x00040000

Definition at line 8066 of file stm32g431xx.h.

◆ RCC_CCIPR_LPTIM1SEL_1

#define RCC_CCIPR_LPTIM1SEL_1 (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos)

0x00080000

Definition at line 8067 of file stm32g431xx.h.

◆ RCC_CCIPR_LPTIM1SEL_Msk

#define RCC_CCIPR_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos)

0x000C0000

Definition at line 8064 of file stm32g431xx.h.

◆ RCC_CCIPR_LPTIM1SEL_Pos

#define RCC_CCIPR_LPTIM1SEL_Pos (18U)

Definition at line 8063 of file stm32g431xx.h.

◆ RCC_CCIPR_LPUART1SEL

#define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk

Definition at line 8041 of file stm32g431xx.h.

◆ RCC_CCIPR_LPUART1SEL_0

#define RCC_CCIPR_LPUART1SEL_0 (0x1UL << RCC_CCIPR_LPUART1SEL_Pos)

0x00000400

Definition at line 8042 of file stm32g431xx.h.

◆ RCC_CCIPR_LPUART1SEL_1

#define RCC_CCIPR_LPUART1SEL_1 (0x2UL << RCC_CCIPR_LPUART1SEL_Pos)

0x00000800

Definition at line 8043 of file stm32g431xx.h.

◆ RCC_CCIPR_LPUART1SEL_Msk

#define RCC_CCIPR_LPUART1SEL_Msk (0x3UL << RCC_CCIPR_LPUART1SEL_Pos)

0x00000C00

Definition at line 8040 of file stm32g431xx.h.

◆ RCC_CCIPR_LPUART1SEL_Pos

#define RCC_CCIPR_LPUART1SEL_Pos (10U)

Definition at line 8039 of file stm32g431xx.h.

◆ RCC_CCIPR_SAI1SEL

#define RCC_CCIPR_SAI1SEL RCC_CCIPR_SAI1SEL_Msk

Definition at line 8071 of file stm32g431xx.h.

◆ RCC_CCIPR_SAI1SEL_0

#define RCC_CCIPR_SAI1SEL_0 (0x1UL << RCC_CCIPR_SAI1SEL_Pos)

0x00100000

Definition at line 8072 of file stm32g431xx.h.

◆ RCC_CCIPR_SAI1SEL_1

#define RCC_CCIPR_SAI1SEL_1 (0x2UL << RCC_CCIPR_SAI1SEL_Pos)

0x00200000

Definition at line 8073 of file stm32g431xx.h.

◆ RCC_CCIPR_SAI1SEL_Msk

#define RCC_CCIPR_SAI1SEL_Msk (0x3UL << RCC_CCIPR_SAI1SEL_Pos)

0x00300000

Definition at line 8070 of file stm32g431xx.h.

◆ RCC_CCIPR_SAI1SEL_Pos

#define RCC_CCIPR_SAI1SEL_Pos (20U)

Definition at line 8069 of file stm32g431xx.h.

◆ RCC_CCIPR_UART4SEL

#define RCC_CCIPR_UART4SEL RCC_CCIPR_UART4SEL_Msk

Definition at line 8034 of file stm32g431xx.h.

◆ RCC_CCIPR_UART4SEL_0

#define RCC_CCIPR_UART4SEL_0 (0x1UL << RCC_CCIPR_UART4SEL_Pos)

0x00000040

Definition at line 8035 of file stm32g431xx.h.

◆ RCC_CCIPR_UART4SEL_1

#define RCC_CCIPR_UART4SEL_1 (0x2UL << RCC_CCIPR_UART4SEL_Pos)

0x00000080

Definition at line 8036 of file stm32g431xx.h.

◆ RCC_CCIPR_UART4SEL_Msk

#define RCC_CCIPR_UART4SEL_Msk (0x3UL << RCC_CCIPR_UART4SEL_Pos)

0x000000C0

Definition at line 8033 of file stm32g431xx.h.

◆ RCC_CCIPR_UART4SEL_Pos

#define RCC_CCIPR_UART4SEL_Pos (6U)

Definition at line 8032 of file stm32g431xx.h.

◆ RCC_CCIPR_USART1SEL

#define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk

Definition at line 8016 of file stm32g431xx.h.

◆ RCC_CCIPR_USART1SEL_0

#define RCC_CCIPR_USART1SEL_0 (0x1UL << RCC_CCIPR_USART1SEL_Pos)

0x00000001

Definition at line 8017 of file stm32g431xx.h.

◆ RCC_CCIPR_USART1SEL_1

#define RCC_CCIPR_USART1SEL_1 (0x2UL << RCC_CCIPR_USART1SEL_Pos)

0x00000002

Definition at line 8018 of file stm32g431xx.h.

◆ RCC_CCIPR_USART1SEL_Msk

#define RCC_CCIPR_USART1SEL_Msk (0x3UL << RCC_CCIPR_USART1SEL_Pos)

0x00000003

Definition at line 8015 of file stm32g431xx.h.

◆ RCC_CCIPR_USART1SEL_Pos

#define RCC_CCIPR_USART1SEL_Pos (0U)

Definition at line 8014 of file stm32g431xx.h.

◆ RCC_CCIPR_USART2SEL

#define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk

Definition at line 8022 of file stm32g431xx.h.

◆ RCC_CCIPR_USART2SEL_0

#define RCC_CCIPR_USART2SEL_0 (0x1UL << RCC_CCIPR_USART2SEL_Pos)

0x00000004

Definition at line 8023 of file stm32g431xx.h.

◆ RCC_CCIPR_USART2SEL_1

#define RCC_CCIPR_USART2SEL_1 (0x2UL << RCC_CCIPR_USART2SEL_Pos)

0x00000008

Definition at line 8024 of file stm32g431xx.h.

◆ RCC_CCIPR_USART2SEL_Msk

#define RCC_CCIPR_USART2SEL_Msk (0x3UL << RCC_CCIPR_USART2SEL_Pos)

0x0000000C

Definition at line 8021 of file stm32g431xx.h.

◆ RCC_CCIPR_USART2SEL_Pos

#define RCC_CCIPR_USART2SEL_Pos (2U)

Definition at line 8020 of file stm32g431xx.h.

◆ RCC_CCIPR_USART3SEL

#define RCC_CCIPR_USART3SEL RCC_CCIPR_USART3SEL_Msk

Definition at line 8028 of file stm32g431xx.h.

◆ RCC_CCIPR_USART3SEL_0

#define RCC_CCIPR_USART3SEL_0 (0x1UL << RCC_CCIPR_USART3SEL_Pos)

0x00000010

Definition at line 8029 of file stm32g431xx.h.

◆ RCC_CCIPR_USART3SEL_1

#define RCC_CCIPR_USART3SEL_1 (0x2UL << RCC_CCIPR_USART3SEL_Pos)

0x00000020

Definition at line 8030 of file stm32g431xx.h.

◆ RCC_CCIPR_USART3SEL_Msk

#define RCC_CCIPR_USART3SEL_Msk (0x3UL << RCC_CCIPR_USART3SEL_Pos)

0x00000030

Definition at line 8027 of file stm32g431xx.h.

◆ RCC_CCIPR_USART3SEL_Pos

#define RCC_CCIPR_USART3SEL_Pos (4U)

Definition at line 8026 of file stm32g431xx.h.

◆ RCC_CFGR_HPRE

#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk

HPRE[3:0] bits (AHB prescaler)

Definition at line 7317 of file stm32g431xx.h.

◆ RCC_CFGR_HPRE_0

#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos)

0x00000010

Definition at line 7318 of file stm32g431xx.h.

◆ RCC_CFGR_HPRE_1

#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos)

0x00000020

Definition at line 7319 of file stm32g431xx.h.

◆ RCC_CFGR_HPRE_2

#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos)

0x00000040

Definition at line 7320 of file stm32g431xx.h.

◆ RCC_CFGR_HPRE_3

#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos)

0x00000080

Definition at line 7321 of file stm32g431xx.h.

◆ RCC_CFGR_HPRE_DIV1

#define RCC_CFGR_HPRE_DIV1 (0x00000000U)

SYSCLK not divided

Definition at line 7323 of file stm32g431xx.h.

◆ RCC_CFGR_HPRE_DIV128

#define RCC_CFGR_HPRE_DIV128 (0x000000D0U)

SYSCLK divided by 128

Definition at line 7329 of file stm32g431xx.h.

◆ RCC_CFGR_HPRE_DIV16

#define RCC_CFGR_HPRE_DIV16 (0x000000B0U)

SYSCLK divided by 16

Definition at line 7327 of file stm32g431xx.h.

◆ RCC_CFGR_HPRE_DIV2

#define RCC_CFGR_HPRE_DIV2 (0x00000080U)

SYSCLK divided by 2

Definition at line 7324 of file stm32g431xx.h.

◆ RCC_CFGR_HPRE_DIV256

#define RCC_CFGR_HPRE_DIV256 (0x000000E0U)

SYSCLK divided by 256

Definition at line 7330 of file stm32g431xx.h.

◆ RCC_CFGR_HPRE_DIV4

#define RCC_CFGR_HPRE_DIV4 (0x00000090U)

SYSCLK divided by 4

Definition at line 7325 of file stm32g431xx.h.

◆ RCC_CFGR_HPRE_DIV512

#define RCC_CFGR_HPRE_DIV512 (0x000000F0U)

SYSCLK divided by 512 PPRE1 configuration

Definition at line 7333 of file stm32g431xx.h.

◆ RCC_CFGR_HPRE_DIV64

#define RCC_CFGR_HPRE_DIV64 (0x000000C0U)

SYSCLK divided by 64

Definition at line 7328 of file stm32g431xx.h.

◆ RCC_CFGR_HPRE_DIV8

#define RCC_CFGR_HPRE_DIV8 (0x000000A0U)

SYSCLK divided by 8

Definition at line 7326 of file stm32g431xx.h.

◆ RCC_CFGR_HPRE_Msk

#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos)

0x000000F0

Definition at line 7316 of file stm32g431xx.h.

◆ RCC_CFGR_HPRE_Pos

#define RCC_CFGR_HPRE_Pos (4U)

Definition at line 7315 of file stm32g431xx.h.

◆ RCC_CFGR_MCO_PRE

#define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE

Definition at line 7384 of file stm32g431xx.h.

◆ RCC_CFGR_MCO_PRE_1

#define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1

Definition at line 7385 of file stm32g431xx.h.

◆ RCC_CFGR_MCO_PRE_16

#define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16

Definition at line 7389 of file stm32g431xx.h.

◆ RCC_CFGR_MCO_PRE_2

#define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2

Definition at line 7386 of file stm32g431xx.h.

◆ RCC_CFGR_MCO_PRE_4

#define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4

Definition at line 7387 of file stm32g431xx.h.

◆ RCC_CFGR_MCO_PRE_8

#define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8

Definition at line 7388 of file stm32g431xx.h.

◆ RCC_CFGR_MCOPRE

#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk

MCO prescaler

Definition at line 7372 of file stm32g431xx.h.

◆ RCC_CFGR_MCOPRE_0

#define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos)

0x10000000

Definition at line 7373 of file stm32g431xx.h.

◆ RCC_CFGR_MCOPRE_1

#define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos)

0x20000000

Definition at line 7374 of file stm32g431xx.h.

◆ RCC_CFGR_MCOPRE_2

#define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos)

0x40000000

Definition at line 7375 of file stm32g431xx.h.

◆ RCC_CFGR_MCOPRE_DIV1

#define RCC_CFGR_MCOPRE_DIV1 (0x00000000U)

MCO is divided by 1

Definition at line 7377 of file stm32g431xx.h.

◆ RCC_CFGR_MCOPRE_DIV16

#define RCC_CFGR_MCOPRE_DIV16 (0x40000000U)

MCO is divided by 16

Definition at line 7381 of file stm32g431xx.h.

◆ RCC_CFGR_MCOPRE_DIV2

#define RCC_CFGR_MCOPRE_DIV2 (0x10000000U)

MCO is divided by 2

Definition at line 7378 of file stm32g431xx.h.

◆ RCC_CFGR_MCOPRE_DIV4

#define RCC_CFGR_MCOPRE_DIV4 (0x20000000U)

MCO is divided by 4

Definition at line 7379 of file stm32g431xx.h.

◆ RCC_CFGR_MCOPRE_DIV8

#define RCC_CFGR_MCOPRE_DIV8 (0x30000000U)

MCO is divided by 8

Definition at line 7380 of file stm32g431xx.h.

◆ RCC_CFGR_MCOPRE_Msk

#define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos)

0x70000000

Definition at line 7371 of file stm32g431xx.h.

◆ RCC_CFGR_MCOPRE_Pos

#define RCC_CFGR_MCOPRE_Pos (28U)

Definition at line 7370 of file stm32g431xx.h.

◆ RCC_CFGR_MCOSEL

#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk

MCOSEL [3:0] bits (Clock output selection)

Definition at line 7364 of file stm32g431xx.h.

◆ RCC_CFGR_MCOSEL_0

#define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos)

0x01000000

Definition at line 7365 of file stm32g431xx.h.

◆ RCC_CFGR_MCOSEL_1

#define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos)

0x02000000

Definition at line 7366 of file stm32g431xx.h.

◆ RCC_CFGR_MCOSEL_2

#define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos)

0x04000000

Definition at line 7367 of file stm32g431xx.h.

◆ RCC_CFGR_MCOSEL_3

#define RCC_CFGR_MCOSEL_3 (0x8UL << RCC_CFGR_MCOSEL_Pos)

0x08000000

Definition at line 7368 of file stm32g431xx.h.

◆ RCC_CFGR_MCOSEL_Msk

#define RCC_CFGR_MCOSEL_Msk (0xFUL << RCC_CFGR_MCOSEL_Pos)

0x0F000000

Definition at line 7363 of file stm32g431xx.h.

◆ RCC_CFGR_MCOSEL_Pos

#define RCC_CFGR_MCOSEL_Pos (24U)

Definition at line 7362 of file stm32g431xx.h.

◆ RCC_CFGR_PPRE1

#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk

PRE1[2:0] bits (APB2 prescaler)

Definition at line 7336 of file stm32g431xx.h.

◆ RCC_CFGR_PPRE1_0

#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos)

0x00000100

Definition at line 7337 of file stm32g431xx.h.

◆ RCC_CFGR_PPRE1_1

#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos)

0x00000200

Definition at line 7338 of file stm32g431xx.h.

◆ RCC_CFGR_PPRE1_2

#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos)

0x00000400

Definition at line 7339 of file stm32g431xx.h.

◆ RCC_CFGR_PPRE1_DIV1

#define RCC_CFGR_PPRE1_DIV1 (0x00000000U)

HCLK not divided

Definition at line 7341 of file stm32g431xx.h.

◆ RCC_CFGR_PPRE1_DIV16

#define RCC_CFGR_PPRE1_DIV16 (0x00000700U)

HCLK divided by 16 PPRE2 configuration

Definition at line 7347 of file stm32g431xx.h.

◆ RCC_CFGR_PPRE1_DIV2

#define RCC_CFGR_PPRE1_DIV2 (0x00000400U)

HCLK divided by 2

Definition at line 7342 of file stm32g431xx.h.

◆ RCC_CFGR_PPRE1_DIV4

#define RCC_CFGR_PPRE1_DIV4 (0x00000500U)

HCLK divided by 4

Definition at line 7343 of file stm32g431xx.h.

◆ RCC_CFGR_PPRE1_DIV8

#define RCC_CFGR_PPRE1_DIV8 (0x00000600U)

HCLK divided by 8

Definition at line 7344 of file stm32g431xx.h.

◆ RCC_CFGR_PPRE1_Msk

#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos)

0x00000700

Definition at line 7335 of file stm32g431xx.h.

◆ RCC_CFGR_PPRE1_Pos

#define RCC_CFGR_PPRE1_Pos (8U)

Definition at line 7334 of file stm32g431xx.h.

◆ RCC_CFGR_PPRE2

#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk

PRE2[2:0] bits (APB2 prescaler)

Definition at line 7350 of file stm32g431xx.h.

◆ RCC_CFGR_PPRE2_0

#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos)

0x00000800

Definition at line 7351 of file stm32g431xx.h.

◆ RCC_CFGR_PPRE2_1

#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos)

0x00001000

Definition at line 7352 of file stm32g431xx.h.

◆ RCC_CFGR_PPRE2_2

#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos)

0x00002000

Definition at line 7353 of file stm32g431xx.h.

◆ RCC_CFGR_PPRE2_DIV1

#define RCC_CFGR_PPRE2_DIV1 (0x00000000U)

HCLK not divided

Definition at line 7355 of file stm32g431xx.h.

◆ RCC_CFGR_PPRE2_DIV16

#define RCC_CFGR_PPRE2_DIV16 (0x00003800U)

HCLK divided by 16 MCOSEL configuration

Definition at line 7361 of file stm32g431xx.h.

◆ RCC_CFGR_PPRE2_DIV2

#define RCC_CFGR_PPRE2_DIV2 (0x00002000U)

HCLK divided by 2

Definition at line 7356 of file stm32g431xx.h.

◆ RCC_CFGR_PPRE2_DIV4

#define RCC_CFGR_PPRE2_DIV4 (0x00002800U)

HCLK divided by 4

Definition at line 7357 of file stm32g431xx.h.

◆ RCC_CFGR_PPRE2_DIV8

#define RCC_CFGR_PPRE2_DIV8 (0x00003000U)

HCLK divided by 8

Definition at line 7358 of file stm32g431xx.h.

◆ RCC_CFGR_PPRE2_Msk

#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos)

0x00003800

Definition at line 7349 of file stm32g431xx.h.

◆ RCC_CFGR_PPRE2_Pos

#define RCC_CFGR_PPRE2_Pos (11U)

Definition at line 7348 of file stm32g431xx.h.

◆ RCC_CFGR_SW

#define RCC_CFGR_SW RCC_CFGR_SW_Msk

SW[1:0] bits (System clock Switch)

Definition at line 7295 of file stm32g431xx.h.

◆ RCC_CFGR_SW_0

#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos)

0x00000001

Definition at line 7296 of file stm32g431xx.h.

◆ RCC_CFGR_SW_1

#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos)

0x00000002

Definition at line 7297 of file stm32g431xx.h.

◆ RCC_CFGR_SW_HSE

#define RCC_CFGR_SW_HSE (0x00000002U)

HSE oscillator selection as system clock

Definition at line 7300 of file stm32g431xx.h.

◆ RCC_CFGR_SW_HSI

#define RCC_CFGR_SW_HSI (0x00000001U)

HSI16 oscillator selection as system clock

Definition at line 7299 of file stm32g431xx.h.

◆ RCC_CFGR_SW_Msk

#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos)

0x00000003

Definition at line 7294 of file stm32g431xx.h.

◆ RCC_CFGR_SW_PLL

#define RCC_CFGR_SW_PLL (0x00000003U)

PLL selection as system clock SWS configuration

Definition at line 7303 of file stm32g431xx.h.

◆ RCC_CFGR_SW_Pos

#define RCC_CFGR_SW_Pos (0U)

< SW configuration

Definition at line 7293 of file stm32g431xx.h.

◆ RCC_CFGR_SWS

#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk

SWS[1:0] bits (System Clock Switch Status)

Definition at line 7306 of file stm32g431xx.h.

◆ RCC_CFGR_SWS_0

#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos)

0x00000004

Definition at line 7307 of file stm32g431xx.h.

◆ RCC_CFGR_SWS_1

#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos)

0x00000008

Definition at line 7308 of file stm32g431xx.h.

◆ RCC_CFGR_SWS_HSE

#define RCC_CFGR_SWS_HSE (0x00000008U)

HSE oscillator used as system clock

Definition at line 7311 of file stm32g431xx.h.

◆ RCC_CFGR_SWS_HSI

#define RCC_CFGR_SWS_HSI (0x00000004U)

HSI16 oscillator used as system clock

Definition at line 7310 of file stm32g431xx.h.

◆ RCC_CFGR_SWS_Msk

#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos)

0x0000000C

Definition at line 7305 of file stm32g431xx.h.

◆ RCC_CFGR_SWS_PLL

#define RCC_CFGR_SWS_PLL (0x0000000CU)

PLL used as system clock HPRE configuration

Definition at line 7314 of file stm32g431xx.h.

◆ RCC_CFGR_SWS_Pos

#define RCC_CFGR_SWS_Pos (2U)

Definition at line 7304 of file stm32g431xx.h.

◆ RCC_CICR_CSSC

#define RCC_CICR_CSSC RCC_CICR_CSSC_Msk

Definition at line 7525 of file stm32g431xx.h.

◆ RCC_CICR_CSSC_Msk

#define RCC_CICR_CSSC_Msk (0x1UL << RCC_CICR_CSSC_Pos)

0x00000100

Definition at line 7524 of file stm32g431xx.h.

◆ RCC_CICR_CSSC_Pos

#define RCC_CICR_CSSC_Pos (8U)

Definition at line 7523 of file stm32g431xx.h.

◆ RCC_CICR_HSERDYC

#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk

Definition at line 7519 of file stm32g431xx.h.

◆ RCC_CICR_HSERDYC_Msk

#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos)

0x00000010

Definition at line 7518 of file stm32g431xx.h.

◆ RCC_CICR_HSERDYC_Pos

#define RCC_CICR_HSERDYC_Pos (4U)

Definition at line 7517 of file stm32g431xx.h.

◆ RCC_CICR_HSI48RDYC

#define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk

Definition at line 7531 of file stm32g431xx.h.

◆ RCC_CICR_HSI48RDYC_Msk

#define RCC_CICR_HSI48RDYC_Msk (0x1UL << RCC_CICR_HSI48RDYC_Pos)

0x00000400

Definition at line 7530 of file stm32g431xx.h.

◆ RCC_CICR_HSI48RDYC_Pos

#define RCC_CICR_HSI48RDYC_Pos (10U)

Definition at line 7529 of file stm32g431xx.h.

◆ RCC_CICR_HSIRDYC

#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk

Definition at line 7516 of file stm32g431xx.h.

◆ RCC_CICR_HSIRDYC_Msk

#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos)

0x00000008

Definition at line 7515 of file stm32g431xx.h.

◆ RCC_CICR_HSIRDYC_Pos

#define RCC_CICR_HSIRDYC_Pos (3U)

Definition at line 7514 of file stm32g431xx.h.

◆ RCC_CICR_LSECSSC

#define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk

Definition at line 7528 of file stm32g431xx.h.

◆ RCC_CICR_LSECSSC_Msk

#define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos)

0x00000200

Definition at line 7527 of file stm32g431xx.h.

◆ RCC_CICR_LSECSSC_Pos

#define RCC_CICR_LSECSSC_Pos (9U)

Definition at line 7526 of file stm32g431xx.h.

◆ RCC_CICR_LSERDYC

#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk

Definition at line 7513 of file stm32g431xx.h.

◆ RCC_CICR_LSERDYC_Msk

#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos)

0x00000002

Definition at line 7512 of file stm32g431xx.h.

◆ RCC_CICR_LSERDYC_Pos

#define RCC_CICR_LSERDYC_Pos (1U)

Definition at line 7511 of file stm32g431xx.h.

◆ RCC_CICR_LSIRDYC

#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk

Definition at line 7510 of file stm32g431xx.h.

◆ RCC_CICR_LSIRDYC_Msk

#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos)

0x00000001

Definition at line 7509 of file stm32g431xx.h.

◆ RCC_CICR_LSIRDYC_Pos

#define RCC_CICR_LSIRDYC_Pos (0U)

Definition at line 7508 of file stm32g431xx.h.

◆ RCC_CICR_PLLRDYC

#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk

Definition at line 7522 of file stm32g431xx.h.

◆ RCC_CICR_PLLRDYC_Msk

#define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos)

0x00000020

Definition at line 7521 of file stm32g431xx.h.

◆ RCC_CICR_PLLRDYC_Pos

#define RCC_CICR_PLLRDYC_Pos (5U)

Definition at line 7520 of file stm32g431xx.h.

◆ RCC_CIER_HSERDYIE

#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk

Definition at line 7470 of file stm32g431xx.h.

◆ RCC_CIER_HSERDYIE_Msk

#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos)

0x00000010

Definition at line 7469 of file stm32g431xx.h.

◆ RCC_CIER_HSERDYIE_Pos

#define RCC_CIER_HSERDYIE_Pos (4U)

Definition at line 7468 of file stm32g431xx.h.

◆ RCC_CIER_HSI48RDYIE

#define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk

Definition at line 7479 of file stm32g431xx.h.

◆ RCC_CIER_HSI48RDYIE_Msk

#define RCC_CIER_HSI48RDYIE_Msk (0x1UL << RCC_CIER_HSI48RDYIE_Pos)

0x00000400

Definition at line 7478 of file stm32g431xx.h.

◆ RCC_CIER_HSI48RDYIE_Pos

#define RCC_CIER_HSI48RDYIE_Pos (10U)

Definition at line 7477 of file stm32g431xx.h.

◆ RCC_CIER_HSIRDYIE

#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk

Definition at line 7467 of file stm32g431xx.h.

◆ RCC_CIER_HSIRDYIE_Msk

#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos)

0x00000008

Definition at line 7466 of file stm32g431xx.h.

◆ RCC_CIER_HSIRDYIE_Pos

#define RCC_CIER_HSIRDYIE_Pos (3U)

Definition at line 7465 of file stm32g431xx.h.

◆ RCC_CIER_LSECSSIE

#define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk

Definition at line 7476 of file stm32g431xx.h.

◆ RCC_CIER_LSECSSIE_Msk

#define RCC_CIER_LSECSSIE_Msk (0x1UL << RCC_CIER_LSECSSIE_Pos)

0x00000200

Definition at line 7475 of file stm32g431xx.h.

◆ RCC_CIER_LSECSSIE_Pos

#define RCC_CIER_LSECSSIE_Pos (9U)

Definition at line 7474 of file stm32g431xx.h.

◆ RCC_CIER_LSERDYIE

#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk

Definition at line 7464 of file stm32g431xx.h.

◆ RCC_CIER_LSERDYIE_Msk

#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos)

0x00000002

Definition at line 7463 of file stm32g431xx.h.

◆ RCC_CIER_LSERDYIE_Pos

#define RCC_CIER_LSERDYIE_Pos (1U)

Definition at line 7462 of file stm32g431xx.h.

◆ RCC_CIER_LSIRDYIE

#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk

Definition at line 7461 of file stm32g431xx.h.

◆ RCC_CIER_LSIRDYIE_Msk

#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos)

0x00000001

Definition at line 7460 of file stm32g431xx.h.

◆ RCC_CIER_LSIRDYIE_Pos

#define RCC_CIER_LSIRDYIE_Pos (0U)

Definition at line 7459 of file stm32g431xx.h.

◆ RCC_CIER_PLLRDYIE

#define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk

Definition at line 7473 of file stm32g431xx.h.

◆ RCC_CIER_PLLRDYIE_Msk

#define RCC_CIER_PLLRDYIE_Msk (0x1UL << RCC_CIER_PLLRDYIE_Pos)

0x00000020

Definition at line 7472 of file stm32g431xx.h.

◆ RCC_CIER_PLLRDYIE_Pos

#define RCC_CIER_PLLRDYIE_Pos (5U)

Definition at line 7471 of file stm32g431xx.h.

◆ RCC_CIFR_CSSF

#define RCC_CIFR_CSSF RCC_CIFR_CSSF_Msk

Definition at line 7499 of file stm32g431xx.h.

◆ RCC_CIFR_CSSF_Msk

#define RCC_CIFR_CSSF_Msk (0x1UL << RCC_CIFR_CSSF_Pos)

0x00000100

Definition at line 7498 of file stm32g431xx.h.

◆ RCC_CIFR_CSSF_Pos

#define RCC_CIFR_CSSF_Pos (8U)

Definition at line 7497 of file stm32g431xx.h.

◆ RCC_CIFR_HSERDYF

#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk

Definition at line 7493 of file stm32g431xx.h.

◆ RCC_CIFR_HSERDYF_Msk

#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos)

0x00000010

Definition at line 7492 of file stm32g431xx.h.

◆ RCC_CIFR_HSERDYF_Pos

#define RCC_CIFR_HSERDYF_Pos (4U)

Definition at line 7491 of file stm32g431xx.h.

◆ RCC_CIFR_HSI48RDYF

#define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk

Definition at line 7505 of file stm32g431xx.h.

◆ RCC_CIFR_HSI48RDYF_Msk

#define RCC_CIFR_HSI48RDYF_Msk (0x1UL << RCC_CIFR_HSI48RDYF_Pos)

0x00000400

Definition at line 7504 of file stm32g431xx.h.

◆ RCC_CIFR_HSI48RDYF_Pos

#define RCC_CIFR_HSI48RDYF_Pos (10U)

Definition at line 7503 of file stm32g431xx.h.

◆ RCC_CIFR_HSIRDYF

#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk

Definition at line 7490 of file stm32g431xx.h.

◆ RCC_CIFR_HSIRDYF_Msk

#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos)

0x00000008

Definition at line 7489 of file stm32g431xx.h.

◆ RCC_CIFR_HSIRDYF_Pos

#define RCC_CIFR_HSIRDYF_Pos (3U)

Definition at line 7488 of file stm32g431xx.h.

◆ RCC_CIFR_LSECSSF

#define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk

Definition at line 7502 of file stm32g431xx.h.

◆ RCC_CIFR_LSECSSF_Msk

#define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos)

0x00000200

Definition at line 7501 of file stm32g431xx.h.

◆ RCC_CIFR_LSECSSF_Pos

#define RCC_CIFR_LSECSSF_Pos (9U)

Definition at line 7500 of file stm32g431xx.h.

◆ RCC_CIFR_LSERDYF

#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk

Definition at line 7487 of file stm32g431xx.h.

◆ RCC_CIFR_LSERDYF_Msk

#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos)

0x00000002

Definition at line 7486 of file stm32g431xx.h.

◆ RCC_CIFR_LSERDYF_Pos

#define RCC_CIFR_LSERDYF_Pos (1U)

Definition at line 7485 of file stm32g431xx.h.

◆ RCC_CIFR_LSIRDYF

#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk

Definition at line 7484 of file stm32g431xx.h.

◆ RCC_CIFR_LSIRDYF_Msk

#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos)

0x00000001

Definition at line 7483 of file stm32g431xx.h.

◆ RCC_CIFR_LSIRDYF_Pos

#define RCC_CIFR_LSIRDYF_Pos (0U)

Definition at line 7482 of file stm32g431xx.h.

◆ RCC_CIFR_PLLRDYF

#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk

Definition at line 7496 of file stm32g431xx.h.

◆ RCC_CIFR_PLLRDYF_Msk

#define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos)

0x00000020

Definition at line 7495 of file stm32g431xx.h.

◆ RCC_CIFR_PLLRDYF_Pos

#define RCC_CIFR_PLLRDYF_Pos (5U)

Definition at line 7494 of file stm32g431xx.h.

◆ RCC_CR_CSSON

#define RCC_CR_CSSON RCC_CR_CSSON_Msk

HSE Clock Security System enable

Definition at line 7256 of file stm32g431xx.h.

◆ RCC_CR_CSSON_Msk

#define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos)

0x00080000

Definition at line 7255 of file stm32g431xx.h.

◆ RCC_CR_CSSON_Pos

#define RCC_CR_CSSON_Pos (19U)

Definition at line 7254 of file stm32g431xx.h.

◆ RCC_CR_HSEBYP

#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk

External High Speed oscillator (HSE) clock bypass

Definition at line 7253 of file stm32g431xx.h.

◆ RCC_CR_HSEBYP_Msk

#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos)

0x00040000

Definition at line 7252 of file stm32g431xx.h.

◆ RCC_CR_HSEBYP_Pos

#define RCC_CR_HSEBYP_Pos (18U)

Definition at line 7251 of file stm32g431xx.h.

◆ RCC_CR_HSEON

#define RCC_CR_HSEON RCC_CR_HSEON_Msk

External High Speed oscillator (HSE) clock enable

Definition at line 7247 of file stm32g431xx.h.

◆ RCC_CR_HSEON_Msk

#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos)

0x00010000

Definition at line 7246 of file stm32g431xx.h.

◆ RCC_CR_HSEON_Pos

#define RCC_CR_HSEON_Pos (16U)

Definition at line 7245 of file stm32g431xx.h.

◆ RCC_CR_HSERDY

#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk

External High Speed oscillator (HSE) clock ready

Definition at line 7250 of file stm32g431xx.h.

◆ RCC_CR_HSERDY_Msk

#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos)

0x00020000

Definition at line 7249 of file stm32g431xx.h.

◆ RCC_CR_HSERDY_Pos

#define RCC_CR_HSERDY_Pos (17U)

Definition at line 7248 of file stm32g431xx.h.

◆ RCC_CR_HSIKERON

#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk

Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel

Definition at line 7240 of file stm32g431xx.h.

◆ RCC_CR_HSIKERON_Msk

#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos)

0x00000200

Definition at line 7239 of file stm32g431xx.h.

◆ RCC_CR_HSIKERON_Pos

#define RCC_CR_HSIKERON_Pos (9U)

Definition at line 7238 of file stm32g431xx.h.

◆ RCC_CR_HSION

#define RCC_CR_HSION RCC_CR_HSION_Msk

Internal High Speed oscillator (HSI16) clock enable

Definition at line 7237 of file stm32g431xx.h.

◆ RCC_CR_HSION_Msk

#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos)

0x00000100

Definition at line 7236 of file stm32g431xx.h.

◆ RCC_CR_HSION_Pos

#define RCC_CR_HSION_Pos (8U)

Definition at line 7235 of file stm32g431xx.h.

◆ RCC_CR_HSIRDY

#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk

Internal High Speed oscillator (HSI16) clock ready flag

Definition at line 7243 of file stm32g431xx.h.

◆ RCC_CR_HSIRDY_Msk

#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos)

0x00000400

Definition at line 7242 of file stm32g431xx.h.

◆ RCC_CR_HSIRDY_Pos

#define RCC_CR_HSIRDY_Pos (10U)

Definition at line 7241 of file stm32g431xx.h.

◆ RCC_CR_PLLON

#define RCC_CR_PLLON RCC_CR_PLLON_Msk

System PLL clock enable

Definition at line 7260 of file stm32g431xx.h.

◆ RCC_CR_PLLON_Msk

#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos)

0x01000000

Definition at line 7259 of file stm32g431xx.h.

◆ RCC_CR_PLLON_Pos

#define RCC_CR_PLLON_Pos (24U)

Definition at line 7258 of file stm32g431xx.h.

◆ RCC_CR_PLLRDY

#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk

System PLL clock ready

Definition at line 7263 of file stm32g431xx.h.

◆ RCC_CR_PLLRDY_Msk

#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos)

0x02000000

Definition at line 7262 of file stm32g431xx.h.

◆ RCC_CR_PLLRDY_Pos

#define RCC_CR_PLLRDY_Pos (25U)

Definition at line 7261 of file stm32g431xx.h.

◆ RCC_CRRCR_HSI48CAL

#define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk

HSI48CAL[8:0] bits

Definition at line 8187 of file stm32g431xx.h.

◆ RCC_CRRCR_HSI48CAL_0

#define RCC_CRRCR_HSI48CAL_0 (0x001UL << RCC_CRRCR_HSI48CAL_Pos)

0x00000080

Definition at line 8188 of file stm32g431xx.h.

◆ RCC_CRRCR_HSI48CAL_1

#define RCC_CRRCR_HSI48CAL_1 (0x002UL << RCC_CRRCR_HSI48CAL_Pos)

0x00000100

Definition at line 8189 of file stm32g431xx.h.

◆ RCC_CRRCR_HSI48CAL_2

#define RCC_CRRCR_HSI48CAL_2 (0x004UL << RCC_CRRCR_HSI48CAL_Pos)

0x00000200

Definition at line 8190 of file stm32g431xx.h.

◆ RCC_CRRCR_HSI48CAL_3

#define RCC_CRRCR_HSI48CAL_3 (0x008UL << RCC_CRRCR_HSI48CAL_Pos)

0x00000400

Definition at line 8191 of file stm32g431xx.h.

◆ RCC_CRRCR_HSI48CAL_4

#define RCC_CRRCR_HSI48CAL_4 (0x010UL << RCC_CRRCR_HSI48CAL_Pos)

0x00000800

Definition at line 8192 of file stm32g431xx.h.

◆ RCC_CRRCR_HSI48CAL_5

#define RCC_CRRCR_HSI48CAL_5 (0x020UL << RCC_CRRCR_HSI48CAL_Pos)

0x00001000

Definition at line 8193 of file stm32g431xx.h.

◆ RCC_CRRCR_HSI48CAL_6

#define RCC_CRRCR_HSI48CAL_6 (0x040UL << RCC_CRRCR_HSI48CAL_Pos)

0x00002000

Definition at line 8194 of file stm32g431xx.h.

◆ RCC_CRRCR_HSI48CAL_7

#define RCC_CRRCR_HSI48CAL_7 (0x080UL << RCC_CRRCR_HSI48CAL_Pos)

0x00004000

Definition at line 8195 of file stm32g431xx.h.

◆ RCC_CRRCR_HSI48CAL_8

#define RCC_CRRCR_HSI48CAL_8 (0x100UL << RCC_CRRCR_HSI48CAL_Pos)

0x00008000

Definition at line 8196 of file stm32g431xx.h.

◆ RCC_CRRCR_HSI48CAL_Msk

#define RCC_CRRCR_HSI48CAL_Msk (0x1FFUL << RCC_CRRCR_HSI48CAL_Pos)

0x0000FF80

Definition at line 8186 of file stm32g431xx.h.

◆ RCC_CRRCR_HSI48CAL_Pos

#define RCC_CRRCR_HSI48CAL_Pos (7U)

Definition at line 8185 of file stm32g431xx.h.

◆ RCC_CRRCR_HSI48ON

#define RCC_CRRCR_HSI48ON RCC_CRRCR_HSI48ON_Msk

Definition at line 8179 of file stm32g431xx.h.

◆ RCC_CRRCR_HSI48ON_Msk

#define RCC_CRRCR_HSI48ON_Msk (0x1UL << RCC_CRRCR_HSI48ON_Pos)

0x00000001

Definition at line 8178 of file stm32g431xx.h.

◆ RCC_CRRCR_HSI48ON_Pos

#define RCC_CRRCR_HSI48ON_Pos (0U)

Definition at line 8177 of file stm32g431xx.h.

◆ RCC_CRRCR_HSI48RDY

#define RCC_CRRCR_HSI48RDY RCC_CRRCR_HSI48RDY_Msk

HSI48CAL configuration

Definition at line 8184 of file stm32g431xx.h.

◆ RCC_CRRCR_HSI48RDY_Msk

#define RCC_CRRCR_HSI48RDY_Msk (0x1UL << RCC_CRRCR_HSI48RDY_Pos)

0x00000002

Definition at line 8181 of file stm32g431xx.h.

◆ RCC_CRRCR_HSI48RDY_Pos

#define RCC_CRRCR_HSI48RDY_Pos (1U)

Definition at line 8180 of file stm32g431xx.h.

◆ RCC_CSR_BORRSTF

#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk

Definition at line 8162 of file stm32g431xx.h.

◆ RCC_CSR_BORRSTF_Msk

#define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos)

0x08000000

Definition at line 8161 of file stm32g431xx.h.

◆ RCC_CSR_BORRSTF_Pos

#define RCC_CSR_BORRSTF_Pos (27U)

Definition at line 8160 of file stm32g431xx.h.

◆ RCC_CSR_IWDGRSTF

#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk

Definition at line 8168 of file stm32g431xx.h.

◆ RCC_CSR_IWDGRSTF_Msk

#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos)

0x20000000

Definition at line 8167 of file stm32g431xx.h.

◆ RCC_CSR_IWDGRSTF_Pos

#define RCC_CSR_IWDGRSTF_Pos (29U)

Definition at line 8166 of file stm32g431xx.h.

◆ RCC_CSR_LPWRRSTF

#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk

Definition at line 8174 of file stm32g431xx.h.

◆ RCC_CSR_LPWRRSTF_Msk

#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos)

0x80000000

Definition at line 8173 of file stm32g431xx.h.

◆ RCC_CSR_LPWRRSTF_Pos

#define RCC_CSR_LPWRRSTF_Pos (31U)

Definition at line 8172 of file stm32g431xx.h.

◆ RCC_CSR_LSION

#define RCC_CSR_LSION RCC_CSR_LSION_Msk

Definition at line 8146 of file stm32g431xx.h.

◆ RCC_CSR_LSION_Msk

#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos)

0x00000001

Definition at line 8145 of file stm32g431xx.h.

◆ RCC_CSR_LSION_Pos

#define RCC_CSR_LSION_Pos (0U)

Definition at line 8144 of file stm32g431xx.h.

◆ RCC_CSR_LSIRDY

#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk

Definition at line 8149 of file stm32g431xx.h.

◆ RCC_CSR_LSIRDY_Msk

#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos)

0x00000002

Definition at line 8148 of file stm32g431xx.h.

◆ RCC_CSR_LSIRDY_Pos

#define RCC_CSR_LSIRDY_Pos (1U)

Definition at line 8147 of file stm32g431xx.h.

◆ RCC_CSR_OBLRSTF

#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk

Definition at line 8156 of file stm32g431xx.h.

◆ RCC_CSR_OBLRSTF_Msk

#define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos)

0x02000000

Definition at line 8155 of file stm32g431xx.h.

◆ RCC_CSR_OBLRSTF_Pos

#define RCC_CSR_OBLRSTF_Pos (25U)

Definition at line 8154 of file stm32g431xx.h.

◆ RCC_CSR_PINRSTF

#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk

Definition at line 8159 of file stm32g431xx.h.

◆ RCC_CSR_PINRSTF_Msk

#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos)

0x04000000

Definition at line 8158 of file stm32g431xx.h.

◆ RCC_CSR_PINRSTF_Pos

#define RCC_CSR_PINRSTF_Pos (26U)

Definition at line 8157 of file stm32g431xx.h.

◆ RCC_CSR_RMVF

#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk

Definition at line 8153 of file stm32g431xx.h.

◆ RCC_CSR_RMVF_Msk

#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos)

0x00800000

Definition at line 8152 of file stm32g431xx.h.

◆ RCC_CSR_RMVF_Pos

#define RCC_CSR_RMVF_Pos (23U)

Definition at line 8151 of file stm32g431xx.h.

◆ RCC_CSR_SFTRSTF

#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk

Definition at line 8165 of file stm32g431xx.h.

◆ RCC_CSR_SFTRSTF_Msk

#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos)

0x10000000

Definition at line 8164 of file stm32g431xx.h.

◆ RCC_CSR_SFTRSTF_Pos

#define RCC_CSR_SFTRSTF_Pos (28U)

Definition at line 8163 of file stm32g431xx.h.

◆ RCC_CSR_WWDGRSTF

#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk

Definition at line 8171 of file stm32g431xx.h.

◆ RCC_CSR_WWDGRSTF_Msk

#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos)

0x40000000

Definition at line 8170 of file stm32g431xx.h.

◆ RCC_CSR_WWDGRSTF_Pos

#define RCC_CSR_WWDGRSTF_Pos (30U)

Definition at line 8169 of file stm32g431xx.h.

◆ RCC_HSI48_SUPPORT

#define RCC_HSI48_SUPPORT

Definition at line 7231 of file stm32g431xx.h.

◆ RCC_ICSCR_HSICAL

#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk

HSICAL[7:0] bits

Definition at line 7269 of file stm32g431xx.h.

◆ RCC_ICSCR_HSICAL_0

#define RCC_ICSCR_HSICAL_0 (0x01UL << RCC_ICSCR_HSICAL_Pos)

0x00010000

Definition at line 7270 of file stm32g431xx.h.

◆ RCC_ICSCR_HSICAL_1

#define RCC_ICSCR_HSICAL_1 (0x02UL << RCC_ICSCR_HSICAL_Pos)

0x00020000

Definition at line 7271 of file stm32g431xx.h.

◆ RCC_ICSCR_HSICAL_2

#define RCC_ICSCR_HSICAL_2 (0x04UL << RCC_ICSCR_HSICAL_Pos)

0x00040000

Definition at line 7272 of file stm32g431xx.h.

◆ RCC_ICSCR_HSICAL_3

#define RCC_ICSCR_HSICAL_3 (0x08UL << RCC_ICSCR_HSICAL_Pos)

0x00080000

Definition at line 7273 of file stm32g431xx.h.

◆ RCC_ICSCR_HSICAL_4

#define RCC_ICSCR_HSICAL_4 (0x10UL << RCC_ICSCR_HSICAL_Pos)

0x00100000

Definition at line 7274 of file stm32g431xx.h.

◆ RCC_ICSCR_HSICAL_5

#define RCC_ICSCR_HSICAL_5 (0x20UL << RCC_ICSCR_HSICAL_Pos)

0x00200000

Definition at line 7275 of file stm32g431xx.h.

◆ RCC_ICSCR_HSICAL_6

#define RCC_ICSCR_HSICAL_6 (0x40UL << RCC_ICSCR_HSICAL_Pos)

0x00400000

Definition at line 7276 of file stm32g431xx.h.

◆ RCC_ICSCR_HSICAL_7

#define RCC_ICSCR_HSICAL_7 (0x80UL << RCC_ICSCR_HSICAL_Pos)

0x00800000 HSITRIM configuration

Definition at line 7279 of file stm32g431xx.h.

◆ RCC_ICSCR_HSICAL_Msk

#define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos)

0x00FF0000

Definition at line 7268 of file stm32g431xx.h.

◆ RCC_ICSCR_HSICAL_Pos

#define RCC_ICSCR_HSICAL_Pos (16U)

< HSICAL configuration

Definition at line 7267 of file stm32g431xx.h.

◆ RCC_ICSCR_HSITRIM

#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk

HSITRIM[6:0] bits

Definition at line 7282 of file stm32g431xx.h.

◆ RCC_ICSCR_HSITRIM_0

#define RCC_ICSCR_HSITRIM_0 (0x01UL << RCC_ICSCR_HSITRIM_Pos)

0x01000000

Definition at line 7283 of file stm32g431xx.h.

◆ RCC_ICSCR_HSITRIM_1

#define RCC_ICSCR_HSITRIM_1 (0x02UL << RCC_ICSCR_HSITRIM_Pos)

0x02000000

Definition at line 7284 of file stm32g431xx.h.

◆ RCC_ICSCR_HSITRIM_2

#define RCC_ICSCR_HSITRIM_2 (0x04UL << RCC_ICSCR_HSITRIM_Pos)

0x04000000

Definition at line 7285 of file stm32g431xx.h.

◆ RCC_ICSCR_HSITRIM_3

#define RCC_ICSCR_HSITRIM_3 (0x08UL << RCC_ICSCR_HSITRIM_Pos)

0x08000000

Definition at line 7286 of file stm32g431xx.h.

◆ RCC_ICSCR_HSITRIM_4

#define RCC_ICSCR_HSITRIM_4 (0x10UL << RCC_ICSCR_HSITRIM_Pos)

0x10000000

Definition at line 7287 of file stm32g431xx.h.

◆ RCC_ICSCR_HSITRIM_5

#define RCC_ICSCR_HSITRIM_5 (0x20UL << RCC_ICSCR_HSITRIM_Pos)

0x20000000

Definition at line 7288 of file stm32g431xx.h.

◆ RCC_ICSCR_HSITRIM_6

#define RCC_ICSCR_HSITRIM_6 (0x40UL << RCC_ICSCR_HSITRIM_Pos)

0x40000000

Definition at line 7289 of file stm32g431xx.h.

◆ RCC_ICSCR_HSITRIM_Msk

#define RCC_ICSCR_HSITRIM_Msk (0x7FUL << RCC_ICSCR_HSITRIM_Pos)

0x7F000000

Definition at line 7281 of file stm32g431xx.h.

◆ RCC_ICSCR_HSITRIM_Pos

#define RCC_ICSCR_HSITRIM_Pos (24U)

Definition at line 7280 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLM

#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk

Definition at line 7407 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLM_0

#define RCC_PLLCFGR_PLLM_0 (0x1UL << RCC_PLLCFGR_PLLM_Pos)

0x00000010

Definition at line 7408 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLM_1

#define RCC_PLLCFGR_PLLM_1 (0x2UL << RCC_PLLCFGR_PLLM_Pos)

0x00000020

Definition at line 7409 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLM_2

#define RCC_PLLCFGR_PLLM_2 (0x4UL << RCC_PLLCFGR_PLLM_Pos)

0x00000040

Definition at line 7410 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLM_3

#define RCC_PLLCFGR_PLLM_3 (0x8UL << RCC_PLLCFGR_PLLM_Pos)

0x00000080

Definition at line 7411 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLM_Msk

#define RCC_PLLCFGR_PLLM_Msk (0xFUL << RCC_PLLCFGR_PLLM_Pos)

0x000000F0

Definition at line 7406 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLM_Pos

#define RCC_PLLCFGR_PLLM_Pos (4U)

Definition at line 7405 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLN

#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk

Definition at line 7415 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLN_0

#define RCC_PLLCFGR_PLLN_0 (0x01UL << RCC_PLLCFGR_PLLN_Pos)

0x00000100

Definition at line 7416 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLN_1

#define RCC_PLLCFGR_PLLN_1 (0x02UL << RCC_PLLCFGR_PLLN_Pos)

0x00000200

Definition at line 7417 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLN_2

#define RCC_PLLCFGR_PLLN_2 (0x04UL << RCC_PLLCFGR_PLLN_Pos)

0x00000400

Definition at line 7418 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLN_3

#define RCC_PLLCFGR_PLLN_3 (0x08UL << RCC_PLLCFGR_PLLN_Pos)

0x00000800

Definition at line 7419 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLN_4

#define RCC_PLLCFGR_PLLN_4 (0x10UL << RCC_PLLCFGR_PLLN_Pos)

0x00001000

Definition at line 7420 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLN_5

#define RCC_PLLCFGR_PLLN_5 (0x20UL << RCC_PLLCFGR_PLLN_Pos)

0x00002000

Definition at line 7421 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLN_6

#define RCC_PLLCFGR_PLLN_6 (0x40UL << RCC_PLLCFGR_PLLN_Pos)

0x00004000

Definition at line 7422 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLN_Msk

#define RCC_PLLCFGR_PLLN_Msk (0x7FUL << RCC_PLLCFGR_PLLN_Pos)

0x00007F00

Definition at line 7414 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLN_Pos

#define RCC_PLLCFGR_PLLN_Pos (8U)

Definition at line 7413 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLP

#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk

Definition at line 7429 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLP_Msk

#define RCC_PLLCFGR_PLLP_Msk (0x1UL << RCC_PLLCFGR_PLLP_Pos)

0x00020000

Definition at line 7428 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLP_Pos

#define RCC_PLLCFGR_PLLP_Pos (17U)

Definition at line 7427 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLPDIV

#define RCC_PLLCFGR_PLLPDIV RCC_PLLCFGR_PLLPDIV_Msk

Definition at line 7451 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLPDIV_0

#define RCC_PLLCFGR_PLLPDIV_0 (0x01UL << RCC_PLLCFGR_PLLPDIV_Pos)

0x08000000

Definition at line 7452 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLPDIV_1

#define RCC_PLLCFGR_PLLPDIV_1 (0x02UL << RCC_PLLCFGR_PLLPDIV_Pos)

0x10000000

Definition at line 7453 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLPDIV_2

#define RCC_PLLCFGR_PLLPDIV_2 (0x04UL << RCC_PLLCFGR_PLLPDIV_Pos)

0x20000000

Definition at line 7454 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLPDIV_3

#define RCC_PLLCFGR_PLLPDIV_3 (0x08UL << RCC_PLLCFGR_PLLPDIV_Pos)

0x40000000

Definition at line 7455 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLPDIV_4

#define RCC_PLLCFGR_PLLPDIV_4 (0x10UL << RCC_PLLCFGR_PLLPDIV_Pos)

0x80000000

Definition at line 7456 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLPDIV_Msk

#define RCC_PLLCFGR_PLLPDIV_Msk (0x1FUL << RCC_PLLCFGR_PLLPDIV_Pos)

0xF8000000

Definition at line 7450 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLPDIV_Pos

#define RCC_PLLCFGR_PLLPDIV_Pos (27U)

Definition at line 7449 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLPEN

#define RCC_PLLCFGR_PLLPEN RCC_PLLCFGR_PLLPEN_Msk

Definition at line 7426 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLPEN_Msk

#define RCC_PLLCFGR_PLLPEN_Msk (0x1UL << RCC_PLLCFGR_PLLPEN_Pos)

0x00010000

Definition at line 7425 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLPEN_Pos

#define RCC_PLLCFGR_PLLPEN_Pos (16U)

Definition at line 7424 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLQ

#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk

Definition at line 7436 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLQ_0

#define RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos)

0x00200000

Definition at line 7437 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLQ_1

#define RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos)

0x00400000

Definition at line 7438 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLQ_Msk

#define RCC_PLLCFGR_PLLQ_Msk (0x3UL << RCC_PLLCFGR_PLLQ_Pos)

0x00600000

Definition at line 7435 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLQ_Pos

#define RCC_PLLCFGR_PLLQ_Pos (21U)

Definition at line 7434 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLQEN

#define RCC_PLLCFGR_PLLQEN RCC_PLLCFGR_PLLQEN_Msk

Definition at line 7432 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLQEN_Msk

#define RCC_PLLCFGR_PLLQEN_Msk (0x1UL << RCC_PLLCFGR_PLLQEN_Pos)

0x00100000

Definition at line 7431 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLQEN_Pos

#define RCC_PLLCFGR_PLLQEN_Pos (20U)

Definition at line 7430 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLR

#define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk

Definition at line 7445 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLR_0

#define RCC_PLLCFGR_PLLR_0 (0x1UL << RCC_PLLCFGR_PLLR_Pos)

0x02000000

Definition at line 7446 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLR_1

#define RCC_PLLCFGR_PLLR_1 (0x2UL << RCC_PLLCFGR_PLLR_Pos)

0x04000000

Definition at line 7447 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLR_Msk

#define RCC_PLLCFGR_PLLR_Msk (0x3UL << RCC_PLLCFGR_PLLR_Pos)

0x06000000

Definition at line 7444 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLR_Pos

#define RCC_PLLCFGR_PLLR_Pos (25U)

Definition at line 7443 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLREN

#define RCC_PLLCFGR_PLLREN RCC_PLLCFGR_PLLREN_Msk

Definition at line 7442 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLREN_Msk

#define RCC_PLLCFGR_PLLREN_Msk (0x1UL << RCC_PLLCFGR_PLLREN_Pos)

0x01000000

Definition at line 7441 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLREN_Pos

#define RCC_PLLCFGR_PLLREN_Pos (24U)

Definition at line 7440 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLSRC

#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk

Definition at line 7394 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLSRC_0

#define RCC_PLLCFGR_PLLSRC_0 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)

0x00000001

Definition at line 7395 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLSRC_1

#define RCC_PLLCFGR_PLLSRC_1 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos)

0x00000002

Definition at line 7396 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLSRC_HSE

#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk

HSE oscillator source clock selected

Definition at line 7403 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLSRC_HSE_Msk

#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_HSE_Pos)

0x00000003

Definition at line 7402 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLSRC_HSE_Pos

#define RCC_PLLCFGR_PLLSRC_HSE_Pos (0U)

Definition at line 7401 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLSRC_HSI

#define RCC_PLLCFGR_PLLSRC_HSI RCC_PLLCFGR_PLLSRC_HSI_Msk

HSI16 oscillator source clock selected

Definition at line 7400 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLSRC_HSI_Msk

#define RCC_PLLCFGR_PLLSRC_HSI_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSI_Pos)

0x00000002

Definition at line 7399 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLSRC_HSI_Pos

#define RCC_PLLCFGR_PLLSRC_HSI_Pos (1U)

Definition at line 7398 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLSRC_Msk

#define RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos)

0x00000003

Definition at line 7393 of file stm32g431xx.h.

◆ RCC_PLLCFGR_PLLSRC_Pos

#define RCC_PLLCFGR_PLLSRC_Pos (0U)

Definition at line 7392 of file stm32g431xx.h.

◆ RCC_PLLP_DIV_2_31_SUPPORT

#define RCC_PLLP_DIV_2_31_SUPPORT

Definition at line 7232 of file stm32g431xx.h.

◆ RNG_CR_CED

#define RNG_CR_CED RNG_CR_IE_Msk

Definition at line 8215 of file stm32g431xx.h.

◆ RNG_CR_CED_Msk

#define RNG_CR_CED_Msk (0x1UL << RNG_CR_IE_Pos)

0x00000020

Definition at line 8214 of file stm32g431xx.h.

◆ RNG_CR_CED_Pos

#define RNG_CR_CED_Pos (5U)

Definition at line 8213 of file stm32g431xx.h.

◆ RNG_CR_IE

#define RNG_CR_IE RNG_CR_IE_Msk

Definition at line 8212 of file stm32g431xx.h.

◆ RNG_CR_IE_Msk

#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos)

0x00000008

Definition at line 8211 of file stm32g431xx.h.

◆ RNG_CR_IE_Pos

#define RNG_CR_IE_Pos (3U)

Definition at line 8210 of file stm32g431xx.h.

◆ RNG_CR_RNGEN

#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk

Definition at line 8209 of file stm32g431xx.h.

◆ RNG_CR_RNGEN_Msk

#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos)

0x00000004

Definition at line 8208 of file stm32g431xx.h.

◆ RNG_CR_RNGEN_Pos

#define RNG_CR_RNGEN_Pos (2U)

Definition at line 8207 of file stm32g431xx.h.

◆ RNG_SR_CECS

#define RNG_SR_CECS RNG_SR_CECS_Msk

Definition at line 8223 of file stm32g431xx.h.

◆ RNG_SR_CECS_Msk

#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos)

0x00000002

Definition at line 8222 of file stm32g431xx.h.

◆ RNG_SR_CECS_Pos

#define RNG_SR_CECS_Pos (1U)

Definition at line 8221 of file stm32g431xx.h.

◆ RNG_SR_CEIS

#define RNG_SR_CEIS RNG_SR_CEIS_Msk

Definition at line 8229 of file stm32g431xx.h.

◆ RNG_SR_CEIS_Msk

#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos)

0x00000020

Definition at line 8228 of file stm32g431xx.h.

◆ RNG_SR_CEIS_Pos

#define RNG_SR_CEIS_Pos (5U)

Definition at line 8227 of file stm32g431xx.h.

◆ RNG_SR_DRDY

#define RNG_SR_DRDY RNG_SR_DRDY_Msk

Definition at line 8220 of file stm32g431xx.h.

◆ RNG_SR_DRDY_Msk

#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos)

0x00000001

Definition at line 8219 of file stm32g431xx.h.

◆ RNG_SR_DRDY_Pos

#define RNG_SR_DRDY_Pos (0U)

Definition at line 8218 of file stm32g431xx.h.

◆ RNG_SR_SECS

#define RNG_SR_SECS RNG_SR_SECS_Msk

Definition at line 8226 of file stm32g431xx.h.

◆ RNG_SR_SECS_Msk

#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos)

0x00000004

Definition at line 8225 of file stm32g431xx.h.

◆ RNG_SR_SECS_Pos

#define RNG_SR_SECS_Pos (2U)

Definition at line 8224 of file stm32g431xx.h.

◆ RNG_SR_SEIS

#define RNG_SR_SEIS RNG_SR_SEIS_Msk

Definition at line 8232 of file stm32g431xx.h.

◆ RNG_SR_SEIS_Msk

#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos)

0x00000040

Definition at line 8231 of file stm32g431xx.h.

◆ RNG_SR_SEIS_Pos

#define RNG_SR_SEIS_Pos (6U)

Definition at line 8230 of file stm32g431xx.h.

◆ RTC_ALRMAR_DT

#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk

Definition at line 8582 of file stm32g431xx.h.

◆ RTC_ALRMAR_DT_0

#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos)

0x10000000

Definition at line 8583 of file stm32g431xx.h.

◆ RTC_ALRMAR_DT_1

#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos)

0x20000000

Definition at line 8584 of file stm32g431xx.h.

◆ RTC_ALRMAR_DT_Msk

#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos)

0x30000000

Definition at line 8581 of file stm32g431xx.h.

◆ RTC_ALRMAR_DT_Pos

#define RTC_ALRMAR_DT_Pos (28U)

Definition at line 8580 of file stm32g431xx.h.

◆ RTC_ALRMAR_DU

#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk

Definition at line 8587 of file stm32g431xx.h.

◆ RTC_ALRMAR_DU_0

#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos)

0x01000000

Definition at line 8588 of file stm32g431xx.h.

◆ RTC_ALRMAR_DU_1

#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos)

0x02000000

Definition at line 8589 of file stm32g431xx.h.

◆ RTC_ALRMAR_DU_2

#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos)

0x04000000

Definition at line 8590 of file stm32g431xx.h.

◆ RTC_ALRMAR_DU_3

#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos)

0x08000000

Definition at line 8591 of file stm32g431xx.h.

◆ RTC_ALRMAR_DU_Msk

#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos)

0x0F000000

Definition at line 8586 of file stm32g431xx.h.

◆ RTC_ALRMAR_DU_Pos

#define RTC_ALRMAR_DU_Pos (24U)

Definition at line 8585 of file stm32g431xx.h.

◆ RTC_ALRMAR_HT

#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk

Definition at line 8600 of file stm32g431xx.h.

◆ RTC_ALRMAR_HT_0

#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos)

0x00100000

Definition at line 8601 of file stm32g431xx.h.

◆ RTC_ALRMAR_HT_1

#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos)

0x00200000

Definition at line 8602 of file stm32g431xx.h.

◆ RTC_ALRMAR_HT_Msk

#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos)

0x00300000

Definition at line 8599 of file stm32g431xx.h.

◆ RTC_ALRMAR_HT_Pos

#define RTC_ALRMAR_HT_Pos (20U)

Definition at line 8598 of file stm32g431xx.h.

◆ RTC_ALRMAR_HU

#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk

Definition at line 8605 of file stm32g431xx.h.

◆ RTC_ALRMAR_HU_0

#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos)

0x00010000

Definition at line 8606 of file stm32g431xx.h.

◆ RTC_ALRMAR_HU_1

#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos)

0x00020000

Definition at line 8607 of file stm32g431xx.h.

◆ RTC_ALRMAR_HU_2

#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos)

0x00040000

Definition at line 8608 of file stm32g431xx.h.

◆ RTC_ALRMAR_HU_3

#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos)

0x00080000

Definition at line 8609 of file stm32g431xx.h.

◆ RTC_ALRMAR_HU_Msk

#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos)

0x000F0000

Definition at line 8604 of file stm32g431xx.h.

◆ RTC_ALRMAR_HU_Pos

#define RTC_ALRMAR_HU_Pos (16U)

Definition at line 8603 of file stm32g431xx.h.

◆ RTC_ALRMAR_MNT

#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk

Definition at line 8615 of file stm32g431xx.h.

◆ RTC_ALRMAR_MNT_0

#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos)

0x00001000

Definition at line 8616 of file stm32g431xx.h.

◆ RTC_ALRMAR_MNT_1

#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos)

0x00002000

Definition at line 8617 of file stm32g431xx.h.

◆ RTC_ALRMAR_MNT_2

#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos)

0x00004000

Definition at line 8618 of file stm32g431xx.h.

◆ RTC_ALRMAR_MNT_Msk

#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos)

0x00007000

Definition at line 8614 of file stm32g431xx.h.

◆ RTC_ALRMAR_MNT_Pos

#define RTC_ALRMAR_MNT_Pos (12U)

Definition at line 8613 of file stm32g431xx.h.

◆ RTC_ALRMAR_MNU

#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk

Definition at line 8621 of file stm32g431xx.h.

◆ RTC_ALRMAR_MNU_0

#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos)

0x00000100

Definition at line 8622 of file stm32g431xx.h.

◆ RTC_ALRMAR_MNU_1

#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos)

0x00000200

Definition at line 8623 of file stm32g431xx.h.

◆ RTC_ALRMAR_MNU_2

#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos)

0x00000400

Definition at line 8624 of file stm32g431xx.h.

◆ RTC_ALRMAR_MNU_3

#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos)

0x00000800

Definition at line 8625 of file stm32g431xx.h.

◆ RTC_ALRMAR_MNU_Msk

#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos)

0x00000F00

Definition at line 8620 of file stm32g431xx.h.

◆ RTC_ALRMAR_MNU_Pos

#define RTC_ALRMAR_MNU_Pos (8U)

Definition at line 8619 of file stm32g431xx.h.

◆ RTC_ALRMAR_MSK1

#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk

Definition at line 8628 of file stm32g431xx.h.

◆ RTC_ALRMAR_MSK1_Msk

#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos)

0x00000080

Definition at line 8627 of file stm32g431xx.h.

◆ RTC_ALRMAR_MSK1_Pos

#define RTC_ALRMAR_MSK1_Pos (7U)

Definition at line 8626 of file stm32g431xx.h.

◆ RTC_ALRMAR_MSK2

#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk

Definition at line 8612 of file stm32g431xx.h.

◆ RTC_ALRMAR_MSK2_Msk

#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos)

0x00008000

Definition at line 8611 of file stm32g431xx.h.

◆ RTC_ALRMAR_MSK2_Pos

#define RTC_ALRMAR_MSK2_Pos (15U)

Definition at line 8610 of file stm32g431xx.h.

◆ RTC_ALRMAR_MSK3

#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk

Definition at line 8594 of file stm32g431xx.h.

◆ RTC_ALRMAR_MSK3_Msk

#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos)

0x00800000

Definition at line 8593 of file stm32g431xx.h.

◆ RTC_ALRMAR_MSK3_Pos

#define RTC_ALRMAR_MSK3_Pos (23U)

Definition at line 8592 of file stm32g431xx.h.

◆ RTC_ALRMAR_MSK4

#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk

Definition at line 8576 of file stm32g431xx.h.

◆ RTC_ALRMAR_MSK4_Msk

#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos)

0x80000000

Definition at line 8575 of file stm32g431xx.h.

◆ RTC_ALRMAR_MSK4_Pos

#define RTC_ALRMAR_MSK4_Pos (31U)

Definition at line 8574 of file stm32g431xx.h.

◆ RTC_ALRMAR_PM

#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk

Definition at line 8597 of file stm32g431xx.h.

◆ RTC_ALRMAR_PM_Msk

#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos)

0x00400000

Definition at line 8596 of file stm32g431xx.h.

◆ RTC_ALRMAR_PM_Pos

#define RTC_ALRMAR_PM_Pos (22U)

Definition at line 8595 of file stm32g431xx.h.

◆ RTC_ALRMAR_ST

#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk

Definition at line 8631 of file stm32g431xx.h.

◆ RTC_ALRMAR_ST_0

#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos)

0x00000010

Definition at line 8632 of file stm32g431xx.h.

◆ RTC_ALRMAR_ST_1

#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos)

0x00000020

Definition at line 8633 of file stm32g431xx.h.

◆ RTC_ALRMAR_ST_2

#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos)

0x00000040

Definition at line 8634 of file stm32g431xx.h.

◆ RTC_ALRMAR_ST_Msk

#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos)

0x00000070

Definition at line 8630 of file stm32g431xx.h.

◆ RTC_ALRMAR_ST_Pos

#define RTC_ALRMAR_ST_Pos (4U)

Definition at line 8629 of file stm32g431xx.h.

◆ RTC_ALRMAR_SU

#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk

Definition at line 8637 of file stm32g431xx.h.

◆ RTC_ALRMAR_SU_0

#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos)

0x00000001

Definition at line 8638 of file stm32g431xx.h.

◆ RTC_ALRMAR_SU_1

#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos)

0x00000002

Definition at line 8639 of file stm32g431xx.h.

◆ RTC_ALRMAR_SU_2

#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos)

0x00000004

Definition at line 8640 of file stm32g431xx.h.

◆ RTC_ALRMAR_SU_3

#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos)

0x00000008

Definition at line 8641 of file stm32g431xx.h.

◆ RTC_ALRMAR_SU_Msk

#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos)

0x0000000F

Definition at line 8636 of file stm32g431xx.h.

◆ RTC_ALRMAR_SU_Pos

#define RTC_ALRMAR_SU_Pos (0U)

Definition at line 8635 of file stm32g431xx.h.

◆ RTC_ALRMAR_WDSEL

#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk

Definition at line 8579 of file stm32g431xx.h.

◆ RTC_ALRMAR_WDSEL_Msk

#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos)

0x40000000

Definition at line 8578 of file stm32g431xx.h.

◆ RTC_ALRMAR_WDSEL_Pos

#define RTC_ALRMAR_WDSEL_Pos (30U)

Definition at line 8577 of file stm32g431xx.h.

◆ RTC_ALRMASSR_MASKSS

#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk

Definition at line 8646 of file stm32g431xx.h.

◆ RTC_ALRMASSR_MASKSS_0

#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos)

0x01000000

Definition at line 8647 of file stm32g431xx.h.

◆ RTC_ALRMASSR_MASKSS_1

#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos)

0x02000000

Definition at line 8648 of file stm32g431xx.h.

◆ RTC_ALRMASSR_MASKSS_2

#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos)

0x04000000

Definition at line 8649 of file stm32g431xx.h.

◆ RTC_ALRMASSR_MASKSS_3

#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos)

0x08000000

Definition at line 8650 of file stm32g431xx.h.

◆ RTC_ALRMASSR_MASKSS_Msk

#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos)

0x0F000000

Definition at line 8645 of file stm32g431xx.h.

◆ RTC_ALRMASSR_MASKSS_Pos

#define RTC_ALRMASSR_MASKSS_Pos (24U)

Definition at line 8644 of file stm32g431xx.h.

◆ RTC_ALRMASSR_SS

#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk

Definition at line 8653 of file stm32g431xx.h.

◆ RTC_ALRMASSR_SS_Msk

#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos)

0x00007FFF

Definition at line 8652 of file stm32g431xx.h.

◆ RTC_ALRMASSR_SS_Pos

#define RTC_ALRMASSR_SS_Pos (0U)

Definition at line 8651 of file stm32g431xx.h.

◆ RTC_ALRMBR_DT

#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk

Definition at line 8664 of file stm32g431xx.h.

◆ RTC_ALRMBR_DT_0

#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos)

0x10000000

Definition at line 8665 of file stm32g431xx.h.

◆ RTC_ALRMBR_DT_1

#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos)

0x20000000

Definition at line 8666 of file stm32g431xx.h.

◆ RTC_ALRMBR_DT_Msk

#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos)

0x30000000

Definition at line 8663 of file stm32g431xx.h.

◆ RTC_ALRMBR_DT_Pos

#define RTC_ALRMBR_DT_Pos (28U)

Definition at line 8662 of file stm32g431xx.h.

◆ RTC_ALRMBR_DU

#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk

Definition at line 8669 of file stm32g431xx.h.

◆ RTC_ALRMBR_DU_0

#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos)

0x01000000

Definition at line 8670 of file stm32g431xx.h.

◆ RTC_ALRMBR_DU_1

#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos)

0x02000000

Definition at line 8671 of file stm32g431xx.h.

◆ RTC_ALRMBR_DU_2

#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos)

0x04000000

Definition at line 8672 of file stm32g431xx.h.

◆ RTC_ALRMBR_DU_3

#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos)

0x08000000

Definition at line 8673 of file stm32g431xx.h.

◆ RTC_ALRMBR_DU_Msk

#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos)

0x0F000000

Definition at line 8668 of file stm32g431xx.h.

◆ RTC_ALRMBR_DU_Pos

#define RTC_ALRMBR_DU_Pos (24U)

Definition at line 8667 of file stm32g431xx.h.

◆ RTC_ALRMBR_HT

#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk

Definition at line 8682 of file stm32g431xx.h.

◆ RTC_ALRMBR_HT_0

#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos)

0x00100000

Definition at line 8683 of file stm32g431xx.h.

◆ RTC_ALRMBR_HT_1

#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos)

0x00200000

Definition at line 8684 of file stm32g431xx.h.

◆ RTC_ALRMBR_HT_Msk

#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos)

0x00300000

Definition at line 8681 of file stm32g431xx.h.

◆ RTC_ALRMBR_HT_Pos

#define RTC_ALRMBR_HT_Pos (20U)

Definition at line 8680 of file stm32g431xx.h.

◆ RTC_ALRMBR_HU

#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk

Definition at line 8687 of file stm32g431xx.h.

◆ RTC_ALRMBR_HU_0

#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos)

0x00010000

Definition at line 8688 of file stm32g431xx.h.

◆ RTC_ALRMBR_HU_1

#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos)

0x00020000

Definition at line 8689 of file stm32g431xx.h.

◆ RTC_ALRMBR_HU_2

#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos)

0x00040000

Definition at line 8690 of file stm32g431xx.h.

◆ RTC_ALRMBR_HU_3

#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos)

0x00080000

Definition at line 8691 of file stm32g431xx.h.

◆ RTC_ALRMBR_HU_Msk

#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos)

0x000F0000

Definition at line 8686 of file stm32g431xx.h.

◆ RTC_ALRMBR_HU_Pos

#define RTC_ALRMBR_HU_Pos (16U)

Definition at line 8685 of file stm32g431xx.h.

◆ RTC_ALRMBR_MNT

#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk

Definition at line 8697 of file stm32g431xx.h.

◆ RTC_ALRMBR_MNT_0

#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos)

0x00001000

Definition at line 8698 of file stm32g431xx.h.

◆ RTC_ALRMBR_MNT_1

#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos)

0x00002000

Definition at line 8699 of file stm32g431xx.h.

◆ RTC_ALRMBR_MNT_2

#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos)

0x00004000

Definition at line 8700 of file stm32g431xx.h.

◆ RTC_ALRMBR_MNT_Msk

#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos)

0x00007000

Definition at line 8696 of file stm32g431xx.h.

◆ RTC_ALRMBR_MNT_Pos

#define RTC_ALRMBR_MNT_Pos (12U)

Definition at line 8695 of file stm32g431xx.h.

◆ RTC_ALRMBR_MNU

#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk

Definition at line 8703 of file stm32g431xx.h.

◆ RTC_ALRMBR_MNU_0

#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos)

0x00000100

Definition at line 8704 of file stm32g431xx.h.

◆ RTC_ALRMBR_MNU_1

#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos)

0x00000200

Definition at line 8705 of file stm32g431xx.h.

◆ RTC_ALRMBR_MNU_2

#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos)

0x00000400

Definition at line 8706 of file stm32g431xx.h.

◆ RTC_ALRMBR_MNU_3

#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos)

0x00000800

Definition at line 8707 of file stm32g431xx.h.

◆ RTC_ALRMBR_MNU_Msk

#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos)

0x00000F00

Definition at line 8702 of file stm32g431xx.h.

◆ RTC_ALRMBR_MNU_Pos

#define RTC_ALRMBR_MNU_Pos (8U)

Definition at line 8701 of file stm32g431xx.h.

◆ RTC_ALRMBR_MSK1

#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk

Definition at line 8710 of file stm32g431xx.h.

◆ RTC_ALRMBR_MSK1_Msk

#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos)

0x00000080

Definition at line 8709 of file stm32g431xx.h.

◆ RTC_ALRMBR_MSK1_Pos

#define RTC_ALRMBR_MSK1_Pos (7U)

Definition at line 8708 of file stm32g431xx.h.

◆ RTC_ALRMBR_MSK2

#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk

Definition at line 8694 of file stm32g431xx.h.

◆ RTC_ALRMBR_MSK2_Msk

#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos)

0x00008000

Definition at line 8693 of file stm32g431xx.h.

◆ RTC_ALRMBR_MSK2_Pos

#define RTC_ALRMBR_MSK2_Pos (15U)

Definition at line 8692 of file stm32g431xx.h.

◆ RTC_ALRMBR_MSK3

#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk

Definition at line 8676 of file stm32g431xx.h.

◆ RTC_ALRMBR_MSK3_Msk

#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos)

0x00800000

Definition at line 8675 of file stm32g431xx.h.

◆ RTC_ALRMBR_MSK3_Pos

#define RTC_ALRMBR_MSK3_Pos (23U)

Definition at line 8674 of file stm32g431xx.h.

◆ RTC_ALRMBR_MSK4

#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk

Definition at line 8658 of file stm32g431xx.h.

◆ RTC_ALRMBR_MSK4_Msk

#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos)

0x80000000

Definition at line 8657 of file stm32g431xx.h.

◆ RTC_ALRMBR_MSK4_Pos

#define RTC_ALRMBR_MSK4_Pos (31U)

Definition at line 8656 of file stm32g431xx.h.

◆ RTC_ALRMBR_PM

#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk

Definition at line 8679 of file stm32g431xx.h.

◆ RTC_ALRMBR_PM_Msk

#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos)

0x00400000

Definition at line 8678 of file stm32g431xx.h.

◆ RTC_ALRMBR_PM_Pos

#define RTC_ALRMBR_PM_Pos (22U)

Definition at line 8677 of file stm32g431xx.h.

◆ RTC_ALRMBR_ST

#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk

Definition at line 8713 of file stm32g431xx.h.

◆ RTC_ALRMBR_ST_0

#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos)

0x00000010

Definition at line 8714 of file stm32g431xx.h.

◆ RTC_ALRMBR_ST_1

#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos)

0x00000020

Definition at line 8715 of file stm32g431xx.h.

◆ RTC_ALRMBR_ST_2

#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos)

0x00000040

Definition at line 8716 of file stm32g431xx.h.

◆ RTC_ALRMBR_ST_Msk

#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos)

0x00000070

Definition at line 8712 of file stm32g431xx.h.

◆ RTC_ALRMBR_ST_Pos

#define RTC_ALRMBR_ST_Pos (4U)

Definition at line 8711 of file stm32g431xx.h.

◆ RTC_ALRMBR_SU

#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk

Definition at line 8719 of file stm32g431xx.h.

◆ RTC_ALRMBR_SU_0

#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos)

0x00000001

Definition at line 8720 of file stm32g431xx.h.

◆ RTC_ALRMBR_SU_1

#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos)

0x00000002

Definition at line 8721 of file stm32g431xx.h.

◆ RTC_ALRMBR_SU_2

#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos)

0x00000004

Definition at line 8722 of file stm32g431xx.h.

◆ RTC_ALRMBR_SU_3

#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos)

0x00000008

Definition at line 8723 of file stm32g431xx.h.

◆ RTC_ALRMBR_SU_Msk

#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos)

0x0000000F

Definition at line 8718 of file stm32g431xx.h.

◆ RTC_ALRMBR_SU_Pos

#define RTC_ALRMBR_SU_Pos (0U)

Definition at line 8717 of file stm32g431xx.h.

◆ RTC_ALRMBR_WDSEL

#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk

Definition at line 8661 of file stm32g431xx.h.

◆ RTC_ALRMBR_WDSEL_Msk

#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos)

0x40000000

Definition at line 8660 of file stm32g431xx.h.

◆ RTC_ALRMBR_WDSEL_Pos

#define RTC_ALRMBR_WDSEL_Pos (30U)

Definition at line 8659 of file stm32g431xx.h.

◆ RTC_ALRMBSSR_MASKSS

#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk

Definition at line 8728 of file stm32g431xx.h.

◆ RTC_ALRMBSSR_MASKSS_0

#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)

0x01000000

Definition at line 8729 of file stm32g431xx.h.

◆ RTC_ALRMBSSR_MASKSS_1

#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)

0x02000000

Definition at line 8730 of file stm32g431xx.h.

◆ RTC_ALRMBSSR_MASKSS_2

#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)

0x04000000

Definition at line 8731 of file stm32g431xx.h.

◆ RTC_ALRMBSSR_MASKSS_3

#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)

0x08000000

Definition at line 8732 of file stm32g431xx.h.

◆ RTC_ALRMBSSR_MASKSS_Msk

#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)

0x0F000000

Definition at line 8727 of file stm32g431xx.h.

◆ RTC_ALRMBSSR_MASKSS_Pos

#define RTC_ALRMBSSR_MASKSS_Pos (24U)

Definition at line 8726 of file stm32g431xx.h.

◆ RTC_ALRMBSSR_SS

#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk

Definition at line 8735 of file stm32g431xx.h.

◆ RTC_ALRMBSSR_SS_Msk

#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)

0x00007FFF

Definition at line 8734 of file stm32g431xx.h.

◆ RTC_ALRMBSSR_SS_Pos

#define RTC_ALRMBSSR_SS_Pos (0U)

Definition at line 8733 of file stm32g431xx.h.

◆ RTC_CALR_CALM

#define RTC_CALR_CALM RTC_CALR_CALM_Msk

Definition at line 8476 of file stm32g431xx.h.

◆ RTC_CALR_CALM_0

#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos)

0x00000001

Definition at line 8477 of file stm32g431xx.h.

◆ RTC_CALR_CALM_1

#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos)

0x00000002

Definition at line 8478 of file stm32g431xx.h.

◆ RTC_CALR_CALM_2

#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos)

0x00000004

Definition at line 8479 of file stm32g431xx.h.

◆ RTC_CALR_CALM_3

#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos)

0x00000008

Definition at line 8480 of file stm32g431xx.h.

◆ RTC_CALR_CALM_4

#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos)

0x00000010

Definition at line 8481 of file stm32g431xx.h.

◆ RTC_CALR_CALM_5

#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos)

0x00000020

Definition at line 8482 of file stm32g431xx.h.

◆ RTC_CALR_CALM_6

#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos)

0x00000040

Definition at line 8483 of file stm32g431xx.h.

◆ RTC_CALR_CALM_7

#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos)

0x00000080

Definition at line 8484 of file stm32g431xx.h.

◆ RTC_CALR_CALM_8

#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos)

0x00000100

Definition at line 8485 of file stm32g431xx.h.

◆ RTC_CALR_CALM_Msk

#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos)

0x000001FF

Definition at line 8475 of file stm32g431xx.h.

◆ RTC_CALR_CALM_Pos

#define RTC_CALR_CALM_Pos (0U)

Definition at line 8474 of file stm32g431xx.h.

◆ RTC_CALR_CALP

#define RTC_CALR_CALP RTC_CALR_CALP_Msk

Definition at line 8467 of file stm32g431xx.h.

◆ RTC_CALR_CALP_Msk

#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos)

0x00008000

Definition at line 8466 of file stm32g431xx.h.

◆ RTC_CALR_CALP_Pos

#define RTC_CALR_CALP_Pos (15U)

Definition at line 8465 of file stm32g431xx.h.

◆ RTC_CALR_CALW16

#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk

Definition at line 8473 of file stm32g431xx.h.

◆ RTC_CALR_CALW16_Msk

#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos)

0x00002000

Definition at line 8472 of file stm32g431xx.h.

◆ RTC_CALR_CALW16_Pos

#define RTC_CALR_CALW16_Pos (13U)

Definition at line 8471 of file stm32g431xx.h.

◆ RTC_CALR_CALW8

#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk

Definition at line 8470 of file stm32g431xx.h.

◆ RTC_CALR_CALW8_Msk

#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos)

0x00004000

Definition at line 8469 of file stm32g431xx.h.

◆ RTC_CALR_CALW8_Pos

#define RTC_CALR_CALW8_Pos (14U)

Definition at line 8468 of file stm32g431xx.h.

◆ RTC_CR_ADD1H

#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk

Definition at line 8415 of file stm32g431xx.h.

◆ RTC_CR_ADD1H_Msk

#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos)

0x00010000

Definition at line 8414 of file stm32g431xx.h.

◆ RTC_CR_ADD1H_Pos

#define RTC_CR_ADD1H_Pos (16U)

Definition at line 8413 of file stm32g431xx.h.

◆ RTC_CR_ALRAE

#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk

Definition at line 8439 of file stm32g431xx.h.

◆ RTC_CR_ALRAE_Msk

#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos)

0x00000100

Definition at line 8438 of file stm32g431xx.h.

◆ RTC_CR_ALRAE_Pos

#define RTC_CR_ALRAE_Pos (8U)

Definition at line 8437 of file stm32g431xx.h.

◆ RTC_CR_ALRAIE

#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk

Definition at line 8427 of file stm32g431xx.h.

◆ RTC_CR_ALRAIE_Msk

#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos)

0x00001000

Definition at line 8426 of file stm32g431xx.h.

◆ RTC_CR_ALRAIE_Pos

#define RTC_CR_ALRAIE_Pos (12U)

Definition at line 8425 of file stm32g431xx.h.

◆ RTC_CR_ALRBE

#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk

Definition at line 8436 of file stm32g431xx.h.

◆ RTC_CR_ALRBE_Msk

#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos)

0x00000200

Definition at line 8435 of file stm32g431xx.h.

◆ RTC_CR_ALRBE_Pos

#define RTC_CR_ALRBE_Pos (9U)

Definition at line 8434 of file stm32g431xx.h.

◆ RTC_CR_ALRBIE

#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk

Definition at line 8424 of file stm32g431xx.h.

◆ RTC_CR_ALRBIE_Msk

#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos)

0x00002000

Definition at line 8423 of file stm32g431xx.h.

◆ RTC_CR_ALRBIE_Pos

#define RTC_CR_ALRBIE_Pos (13U)

Definition at line 8422 of file stm32g431xx.h.

◆ RTC_CR_BKP

#define RTC_CR_BKP RTC_CR_BKP_Msk

Definition at line 8409 of file stm32g431xx.h.

◆ RTC_CR_BKP_Msk

#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos)

0x00040000

Definition at line 8408 of file stm32g431xx.h.

◆ RTC_CR_BKP_Pos

#define RTC_CR_BKP_Pos (18U)

Definition at line 8407 of file stm32g431xx.h.

◆ RTC_CR_BYPSHAD

#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk

Definition at line 8445 of file stm32g431xx.h.

◆ RTC_CR_BYPSHAD_Msk

#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos)

0x00000020

Definition at line 8444 of file stm32g431xx.h.

◆ RTC_CR_BYPSHAD_Pos

#define RTC_CR_BYPSHAD_Pos (5U)

Definition at line 8443 of file stm32g431xx.h.

◆ RTC_CR_COE

#define RTC_CR_COE RTC_CR_COE_Msk

Definition at line 8395 of file stm32g431xx.h.

◆ RTC_CR_COE_Msk

#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos)

0x00800000

Definition at line 8394 of file stm32g431xx.h.

◆ RTC_CR_COE_Pos

#define RTC_CR_COE_Pos (23U)

Definition at line 8393 of file stm32g431xx.h.

◆ RTC_CR_COSEL

#define RTC_CR_COSEL RTC_CR_COSEL_Msk

Definition at line 8406 of file stm32g431xx.h.

◆ RTC_CR_COSEL_Msk

#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos)

0x00080000

Definition at line 8405 of file stm32g431xx.h.

◆ RTC_CR_COSEL_Pos

#define RTC_CR_COSEL_Pos (19U)

Definition at line 8404 of file stm32g431xx.h.

◆ RTC_CR_FMT

#define RTC_CR_FMT RTC_CR_FMT_Msk

Definition at line 8442 of file stm32g431xx.h.

◆ RTC_CR_FMT_Msk

#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos)

0x00000040

Definition at line 8441 of file stm32g431xx.h.

◆ RTC_CR_FMT_Pos

#define RTC_CR_FMT_Pos (6U)

Definition at line 8440 of file stm32g431xx.h.

◆ RTC_CR_ITSE

#define RTC_CR_ITSE RTC_CR_ITSE_Msk

Timestamp on internal event enable

Definition at line 8392 of file stm32g431xx.h.

◆ RTC_CR_ITSE_Msk

#define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos)

0x01000000

Definition at line 8391 of file stm32g431xx.h.

◆ RTC_CR_ITSE_Pos

#define RTC_CR_ITSE_Pos (24U)

Definition at line 8390 of file stm32g431xx.h.

◆ RTC_CR_OSEL

#define RTC_CR_OSEL RTC_CR_OSEL_Msk

Definition at line 8398 of file stm32g431xx.h.

◆ RTC_CR_OSEL_0

#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos)

0x00200000

Definition at line 8399 of file stm32g431xx.h.

◆ RTC_CR_OSEL_1

#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos)

0x00400000

Definition at line 8400 of file stm32g431xx.h.

◆ RTC_CR_OSEL_Msk

#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos)

0x00600000

Definition at line 8397 of file stm32g431xx.h.

◆ RTC_CR_OSEL_Pos

#define RTC_CR_OSEL_Pos (21U)

Definition at line 8396 of file stm32g431xx.h.

◆ RTC_CR_OUT2EN

#define RTC_CR_OUT2EN RTC_CR_OUT2EN_Msk

RTC_OUT2 output enable

Definition at line 8377 of file stm32g431xx.h.

◆ RTC_CR_OUT2EN_Msk

#define RTC_CR_OUT2EN_Msk (0x1UL << RTC_CR_OUT2EN_Pos)

0x80000000

Definition at line 8376 of file stm32g431xx.h.

◆ RTC_CR_OUT2EN_Pos

#define RTC_CR_OUT2EN_Pos (31U)

Definition at line 8375 of file stm32g431xx.h.

◆ RTC_CR_POL

#define RTC_CR_POL RTC_CR_POL_Msk

Definition at line 8403 of file stm32g431xx.h.

◆ RTC_CR_POL_Msk

#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos)

0x00100000

Definition at line 8402 of file stm32g431xx.h.

◆ RTC_CR_POL_Pos

#define RTC_CR_POL_Pos (20U)

Definition at line 8401 of file stm32g431xx.h.

◆ RTC_CR_REFCKON

#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk

Definition at line 8448 of file stm32g431xx.h.

◆ RTC_CR_REFCKON_Msk

#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos)

0x00000010

Definition at line 8447 of file stm32g431xx.h.

◆ RTC_CR_REFCKON_Pos

#define RTC_CR_REFCKON_Pos (4U)

Definition at line 8446 of file stm32g431xx.h.

◆ RTC_CR_SUB1H

#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk

Definition at line 8412 of file stm32g431xx.h.

◆ RTC_CR_SUB1H_Msk

#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos)

0x00020000

Definition at line 8411 of file stm32g431xx.h.

◆ RTC_CR_SUB1H_Pos

#define RTC_CR_SUB1H_Pos (17U)

Definition at line 8410 of file stm32g431xx.h.

◆ RTC_CR_TAMPALRM_PU

#define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk

TAMPALARM output pull-up config

Definition at line 8383 of file stm32g431xx.h.

◆ RTC_CR_TAMPALRM_PU_Msk

#define RTC_CR_TAMPALRM_PU_Msk (0x1UL << RTC_CR_TAMPALRM_PU_Pos)

0x20000000

Definition at line 8382 of file stm32g431xx.h.

◆ RTC_CR_TAMPALRM_PU_Pos

#define RTC_CR_TAMPALRM_PU_Pos (29U)

Definition at line 8381 of file stm32g431xx.h.

◆ RTC_CR_TAMPALRM_TYPE

#define RTC_CR_TAMPALRM_TYPE RTC_CR_TAMPALRM_TYPE_Msk

TAMPALARM output type

Definition at line 8380 of file stm32g431xx.h.

◆ RTC_CR_TAMPALRM_TYPE_Msk

#define RTC_CR_TAMPALRM_TYPE_Msk (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos)

0x40000000

Definition at line 8379 of file stm32g431xx.h.

◆ RTC_CR_TAMPALRM_TYPE_Pos

#define RTC_CR_TAMPALRM_TYPE_Pos (30U)

Definition at line 8378 of file stm32g431xx.h.

◆ RTC_CR_TAMPOE

#define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk

Tamper detection output enable on TAMPALARM

Definition at line 8386 of file stm32g431xx.h.

◆ RTC_CR_TAMPOE_Msk

#define RTC_CR_TAMPOE_Msk (0x1UL << RTC_CR_TAMPOE_Pos)

0x04000000

Definition at line 8385 of file stm32g431xx.h.

◆ RTC_CR_TAMPOE_Pos

#define RTC_CR_TAMPOE_Pos (26U)

Definition at line 8384 of file stm32g431xx.h.

◆ RTC_CR_TAMPTS

#define RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk

Activate timestamp on tamper detection event

Definition at line 8389 of file stm32g431xx.h.

◆ RTC_CR_TAMPTS_Msk

#define RTC_CR_TAMPTS_Msk (0x1UL << RTC_CR_TAMPTS_Pos)

0x02000000

Definition at line 8388 of file stm32g431xx.h.

◆ RTC_CR_TAMPTS_Pos

#define RTC_CR_TAMPTS_Pos (25U)

Definition at line 8387 of file stm32g431xx.h.

◆ RTC_CR_TSE

#define RTC_CR_TSE RTC_CR_TSE_Msk

Definition at line 8430 of file stm32g431xx.h.

◆ RTC_CR_TSE_Msk

#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos)

0x00000800

Definition at line 8429 of file stm32g431xx.h.

◆ RTC_CR_TSE_Pos

#define RTC_CR_TSE_Pos (11U)

Definition at line 8428 of file stm32g431xx.h.

◆ RTC_CR_TSEDGE

#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk

Definition at line 8451 of file stm32g431xx.h.

◆ RTC_CR_TSEDGE_Msk

#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos)

0x00000008

Definition at line 8450 of file stm32g431xx.h.

◆ RTC_CR_TSEDGE_Pos

#define RTC_CR_TSEDGE_Pos (3U)

Definition at line 8449 of file stm32g431xx.h.

◆ RTC_CR_TSIE

#define RTC_CR_TSIE RTC_CR_TSIE_Msk

Definition at line 8418 of file stm32g431xx.h.

◆ RTC_CR_TSIE_Msk

#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos)

0x00008000

Definition at line 8417 of file stm32g431xx.h.

◆ RTC_CR_TSIE_Pos

#define RTC_CR_TSIE_Pos (15U)

Definition at line 8416 of file stm32g431xx.h.

◆ RTC_CR_WUCKSEL

#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk

Definition at line 8454 of file stm32g431xx.h.

◆ RTC_CR_WUCKSEL_0

#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos)

0x00000001

Definition at line 8455 of file stm32g431xx.h.

◆ RTC_CR_WUCKSEL_1

#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos)

0x00000002

Definition at line 8456 of file stm32g431xx.h.

◆ RTC_CR_WUCKSEL_2

#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos)

0x00000004

Definition at line 8457 of file stm32g431xx.h.

◆ RTC_CR_WUCKSEL_Msk

#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos)

0x00000007

Definition at line 8453 of file stm32g431xx.h.

◆ RTC_CR_WUCKSEL_Pos

#define RTC_CR_WUCKSEL_Pos (0U)

Definition at line 8452 of file stm32g431xx.h.

◆ RTC_CR_WUTE

#define RTC_CR_WUTE RTC_CR_WUTE_Msk

Definition at line 8433 of file stm32g431xx.h.

◆ RTC_CR_WUTE_Msk

#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos)

0x00000400

Definition at line 8432 of file stm32g431xx.h.

◆ RTC_CR_WUTE_Pos

#define RTC_CR_WUTE_Pos (10U)

Definition at line 8431 of file stm32g431xx.h.

◆ RTC_CR_WUTIE

#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk

Definition at line 8421 of file stm32g431xx.h.

◆ RTC_CR_WUTIE_Msk

#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos)

0x00004000

Definition at line 8420 of file stm32g431xx.h.

◆ RTC_CR_WUTIE_Pos

#define RTC_CR_WUTIE_Pos (14U)

Definition at line 8419 of file stm32g431xx.h.

◆ RTC_DR_DT

#define RTC_DR_DT RTC_DR_DT_Msk

Definition at line 8316 of file stm32g431xx.h.

◆ RTC_DR_DT_0

#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos)

0x00000010

Definition at line 8317 of file stm32g431xx.h.

◆ RTC_DR_DT_1

#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos)

0x00000020

Definition at line 8318 of file stm32g431xx.h.

◆ RTC_DR_DT_Msk

#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos)

0x00000030

Definition at line 8315 of file stm32g431xx.h.

◆ RTC_DR_DT_Pos

#define RTC_DR_DT_Pos (4U)

Definition at line 8314 of file stm32g431xx.h.

◆ RTC_DR_DU

#define RTC_DR_DU RTC_DR_DU_Msk

Definition at line 8321 of file stm32g431xx.h.

◆ RTC_DR_DU_0

#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos)

0x00000001

Definition at line 8322 of file stm32g431xx.h.

◆ RTC_DR_DU_1

#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos)

0x00000002

Definition at line 8323 of file stm32g431xx.h.

◆ RTC_DR_DU_2

#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos)

0x00000004

Definition at line 8324 of file stm32g431xx.h.

◆ RTC_DR_DU_3

#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos)

0x00000008

Definition at line 8325 of file stm32g431xx.h.

◆ RTC_DR_DU_Msk

#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos)

0x0000000F

Definition at line 8320 of file stm32g431xx.h.

◆ RTC_DR_DU_Pos

#define RTC_DR_DU_Pos (0U)

Definition at line 8319 of file stm32g431xx.h.

◆ RTC_DR_MT

#define RTC_DR_MT RTC_DR_MT_Msk

Definition at line 8306 of file stm32g431xx.h.

◆ RTC_DR_MT_Msk

#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos)

0x00001000

Definition at line 8305 of file stm32g431xx.h.

◆ RTC_DR_MT_Pos

#define RTC_DR_MT_Pos (12U)

Definition at line 8304 of file stm32g431xx.h.

◆ RTC_DR_MU

#define RTC_DR_MU RTC_DR_MU_Msk

Definition at line 8309 of file stm32g431xx.h.

◆ RTC_DR_MU_0

#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos)

0x00000100

Definition at line 8310 of file stm32g431xx.h.

◆ RTC_DR_MU_1

#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos)

0x00000200

Definition at line 8311 of file stm32g431xx.h.

◆ RTC_DR_MU_2

#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos)

0x00000400

Definition at line 8312 of file stm32g431xx.h.

◆ RTC_DR_MU_3

#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos)

0x00000800

Definition at line 8313 of file stm32g431xx.h.

◆ RTC_DR_MU_Msk

#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos)

0x00000F00

Definition at line 8308 of file stm32g431xx.h.

◆ RTC_DR_MU_Pos

#define RTC_DR_MU_Pos (8U)

Definition at line 8307 of file stm32g431xx.h.

◆ RTC_DR_WDU

#define RTC_DR_WDU RTC_DR_WDU_Msk

Definition at line 8300 of file stm32g431xx.h.

◆ RTC_DR_WDU_0

#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos)

0x00002000

Definition at line 8301 of file stm32g431xx.h.

◆ RTC_DR_WDU_1

#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos)

0x00004000

Definition at line 8302 of file stm32g431xx.h.

◆ RTC_DR_WDU_2

#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos)

0x00008000

Definition at line 8303 of file stm32g431xx.h.

◆ RTC_DR_WDU_Msk

#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos)

0x0000E000

Definition at line 8299 of file stm32g431xx.h.

◆ RTC_DR_WDU_Pos

#define RTC_DR_WDU_Pos (13U)

Definition at line 8298 of file stm32g431xx.h.

◆ RTC_DR_YT

#define RTC_DR_YT RTC_DR_YT_Msk

Definition at line 8286 of file stm32g431xx.h.

◆ RTC_DR_YT_0

#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos)

0x00100000

Definition at line 8287 of file stm32g431xx.h.

◆ RTC_DR_YT_1

#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos)

0x00200000

Definition at line 8288 of file stm32g431xx.h.

◆ RTC_DR_YT_2

#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos)

0x00400000

Definition at line 8289 of file stm32g431xx.h.

◆ RTC_DR_YT_3

#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos)

0x00800000

Definition at line 8290 of file stm32g431xx.h.

◆ RTC_DR_YT_Msk

#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos)

0x00F00000

Definition at line 8285 of file stm32g431xx.h.

◆ RTC_DR_YT_Pos

#define RTC_DR_YT_Pos (20U)

Definition at line 8284 of file stm32g431xx.h.

◆ RTC_DR_YU

#define RTC_DR_YU RTC_DR_YU_Msk

Definition at line 8293 of file stm32g431xx.h.

◆ RTC_DR_YU_0

#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos)

0x00010000

Definition at line 8294 of file stm32g431xx.h.

◆ RTC_DR_YU_1

#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos)

0x00020000

Definition at line 8295 of file stm32g431xx.h.

◆ RTC_DR_YU_2

#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos)

0x00040000

Definition at line 8296 of file stm32g431xx.h.

◆ RTC_DR_YU_3

#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos)

0x00080000

Definition at line 8297 of file stm32g431xx.h.

◆ RTC_DR_YU_Msk

#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos)

0x000F0000

Definition at line 8292 of file stm32g431xx.h.

◆ RTC_DR_YU_Pos

#define RTC_DR_YU_Pos (16U)

Definition at line 8291 of file stm32g431xx.h.

◆ RTC_ICSR_ALRAWF

#define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk

Definition at line 8359 of file stm32g431xx.h.

◆ RTC_ICSR_ALRAWF_Msk

#define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos)

0x00000001

Definition at line 8358 of file stm32g431xx.h.

◆ RTC_ICSR_ALRAWF_Pos

#define RTC_ICSR_ALRAWF_Pos (0U)

Definition at line 8357 of file stm32g431xx.h.

◆ RTC_ICSR_ALRBWF

#define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk

Definition at line 8356 of file stm32g431xx.h.

◆ RTC_ICSR_ALRBWF_Msk

#define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos)

0x00000002

Definition at line 8355 of file stm32g431xx.h.

◆ RTC_ICSR_ALRBWF_Pos

#define RTC_ICSR_ALRBWF_Pos (1U)

Definition at line 8354 of file stm32g431xx.h.

◆ RTC_ICSR_INIT

#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk

Definition at line 8338 of file stm32g431xx.h.

◆ RTC_ICSR_INIT_Msk

#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos)

0x00000080

Definition at line 8337 of file stm32g431xx.h.

◆ RTC_ICSR_INIT_Pos

#define RTC_ICSR_INIT_Pos (7U)

Definition at line 8336 of file stm32g431xx.h.

◆ RTC_ICSR_INITF

#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk

Definition at line 8341 of file stm32g431xx.h.

◆ RTC_ICSR_INITF_Msk

#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos)

0x00000040

Definition at line 8340 of file stm32g431xx.h.

◆ RTC_ICSR_INITF_Pos

#define RTC_ICSR_INITF_Pos (6U)

Definition at line 8339 of file stm32g431xx.h.

◆ RTC_ICSR_INITS

#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk

Definition at line 8347 of file stm32g431xx.h.

◆ RTC_ICSR_INITS_Msk

#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos)

0x00000010

Definition at line 8346 of file stm32g431xx.h.

◆ RTC_ICSR_INITS_Pos

#define RTC_ICSR_INITS_Pos (4U)

Definition at line 8345 of file stm32g431xx.h.

◆ RTC_ICSR_RECALPF

#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk

Definition at line 8335 of file stm32g431xx.h.

◆ RTC_ICSR_RECALPF_Msk

#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos)

0x00010000

Definition at line 8334 of file stm32g431xx.h.

◆ RTC_ICSR_RECALPF_Pos

#define RTC_ICSR_RECALPF_Pos (16U)

Definition at line 8333 of file stm32g431xx.h.

◆ RTC_ICSR_RSF

#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk

Definition at line 8344 of file stm32g431xx.h.

◆ RTC_ICSR_RSF_Msk

#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos)

0x00000020

Definition at line 8343 of file stm32g431xx.h.

◆ RTC_ICSR_RSF_Pos

#define RTC_ICSR_RSF_Pos (5U)

Definition at line 8342 of file stm32g431xx.h.

◆ RTC_ICSR_SHPF

#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk

Definition at line 8350 of file stm32g431xx.h.

◆ RTC_ICSR_SHPF_Msk

#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos)

0x00000008

Definition at line 8349 of file stm32g431xx.h.

◆ RTC_ICSR_SHPF_Pos

#define RTC_ICSR_SHPF_Pos (3U)

Definition at line 8348 of file stm32g431xx.h.

◆ RTC_ICSR_WUTWF

#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk

Definition at line 8353 of file stm32g431xx.h.

◆ RTC_ICSR_WUTWF_Msk

#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos)

0x00000004

Definition at line 8352 of file stm32g431xx.h.

◆ RTC_ICSR_WUTWF_Pos

#define RTC_ICSR_WUTWF_Pos (2U)

Definition at line 8351 of file stm32g431xx.h.

◆ RTC_MISR_ALRAMF

#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk

Definition at line 8775 of file stm32g431xx.h.

◆ RTC_MISR_ALRAMF_Msk

#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos)

0x00000001

Definition at line 8774 of file stm32g431xx.h.

◆ RTC_MISR_ALRAMF_Pos

#define RTC_MISR_ALRAMF_Pos (0U)

Definition at line 8773 of file stm32g431xx.h.

◆ RTC_MISR_ALRBMF

#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk

Definition at line 8772 of file stm32g431xx.h.

◆ RTC_MISR_ALRBMF_Msk

#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos)

0x00000002

Definition at line 8771 of file stm32g431xx.h.

◆ RTC_MISR_ALRBMF_Pos

#define RTC_MISR_ALRBMF_Pos (1U)

Definition at line 8770 of file stm32g431xx.h.

◆ RTC_MISR_ITSMF

#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk

Definition at line 8760 of file stm32g431xx.h.

◆ RTC_MISR_ITSMF_Msk

#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos)

0x00000020

Definition at line 8759 of file stm32g431xx.h.

◆ RTC_MISR_ITSMF_Pos

#define RTC_MISR_ITSMF_Pos (5U)

Definition at line 8758 of file stm32g431xx.h.

◆ RTC_MISR_TSMF

#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk

Definition at line 8766 of file stm32g431xx.h.

◆ RTC_MISR_TSMF_Msk

#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos)

0x00000008

Definition at line 8765 of file stm32g431xx.h.

◆ RTC_MISR_TSMF_Pos

#define RTC_MISR_TSMF_Pos (3U)

Definition at line 8764 of file stm32g431xx.h.

◆ RTC_MISR_TSOVMF

#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk

Definition at line 8763 of file stm32g431xx.h.

◆ RTC_MISR_TSOVMF_Msk

#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos)

0x00000010

Definition at line 8762 of file stm32g431xx.h.

◆ RTC_MISR_TSOVMF_Pos

#define RTC_MISR_TSOVMF_Pos (4U)

Definition at line 8761 of file stm32g431xx.h.

◆ RTC_MISR_WUTMF

#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk

Definition at line 8769 of file stm32g431xx.h.

◆ RTC_MISR_WUTMF_Msk

#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos)

0x00000004

Definition at line 8768 of file stm32g431xx.h.

◆ RTC_MISR_WUTMF_Pos

#define RTC_MISR_WUTMF_Pos (2U)

Definition at line 8767 of file stm32g431xx.h.

◆ RTC_PRER_PREDIV_A

#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk

Definition at line 8364 of file stm32g431xx.h.

◆ RTC_PRER_PREDIV_A_Msk

#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos)

0x007F0000

Definition at line 8363 of file stm32g431xx.h.

◆ RTC_PRER_PREDIV_A_Pos

#define RTC_PRER_PREDIV_A_Pos (16U)

Definition at line 8362 of file stm32g431xx.h.

◆ RTC_PRER_PREDIV_S

#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk

Definition at line 8367 of file stm32g431xx.h.

◆ RTC_PRER_PREDIV_S_Msk

#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)

0x00007FFF

Definition at line 8366 of file stm32g431xx.h.

◆ RTC_PRER_PREDIV_S_Pos

#define RTC_PRER_PREDIV_S_Pos (0U)

Definition at line 8365 of file stm32g431xx.h.

◆ RTC_SCR_CALRAF

#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk

Definition at line 8795 of file stm32g431xx.h.

◆ RTC_SCR_CALRAF_Msk

#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos)

0x00000001

Definition at line 8794 of file stm32g431xx.h.

◆ RTC_SCR_CALRAF_Pos

#define RTC_SCR_CALRAF_Pos (0U)

Definition at line 8793 of file stm32g431xx.h.

◆ RTC_SCR_CALRBF

#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk

Definition at line 8792 of file stm32g431xx.h.

◆ RTC_SCR_CALRBF_Msk

#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos)

0x00000002

Definition at line 8791 of file stm32g431xx.h.

◆ RTC_SCR_CALRBF_Pos

#define RTC_SCR_CALRBF_Pos (1U)

Definition at line 8790 of file stm32g431xx.h.

◆ RTC_SCR_CITSF

#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk

Definition at line 8780 of file stm32g431xx.h.

◆ RTC_SCR_CITSF_Msk

#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos)

0x00000020

Definition at line 8779 of file stm32g431xx.h.

◆ RTC_SCR_CITSF_Pos

#define RTC_SCR_CITSF_Pos (5U)

Definition at line 8778 of file stm32g431xx.h.

◆ RTC_SCR_CTSF

#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk

Definition at line 8786 of file stm32g431xx.h.

◆ RTC_SCR_CTSF_Msk

#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos)

0x00000008

Definition at line 8785 of file stm32g431xx.h.

◆ RTC_SCR_CTSF_Pos

#define RTC_SCR_CTSF_Pos (3U)

Definition at line 8784 of file stm32g431xx.h.

◆ RTC_SCR_CTSOVF

#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk

Definition at line 8783 of file stm32g431xx.h.

◆ RTC_SCR_CTSOVF_Msk

#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos)

0x00000010

Definition at line 8782 of file stm32g431xx.h.

◆ RTC_SCR_CTSOVF_Pos

#define RTC_SCR_CTSOVF_Pos (4U)

Definition at line 8781 of file stm32g431xx.h.

◆ RTC_SCR_CWUTF

#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk

Definition at line 8789 of file stm32g431xx.h.

◆ RTC_SCR_CWUTF_Msk

#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos)

0x00000004

Definition at line 8788 of file stm32g431xx.h.

◆ RTC_SCR_CWUTF_Pos

#define RTC_SCR_CWUTF_Pos (2U)

Definition at line 8787 of file stm32g431xx.h.

◆ RTC_SHIFTR_ADD1S

#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk

Definition at line 8493 of file stm32g431xx.h.

◆ RTC_SHIFTR_ADD1S_Msk

#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos)

0x80000000

Definition at line 8492 of file stm32g431xx.h.

◆ RTC_SHIFTR_ADD1S_Pos

#define RTC_SHIFTR_ADD1S_Pos (31U)

Definition at line 8491 of file stm32g431xx.h.

◆ RTC_SHIFTR_SUBFS

#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk

Definition at line 8490 of file stm32g431xx.h.

◆ RTC_SHIFTR_SUBFS_Msk

#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)

0x00007FFF

Definition at line 8489 of file stm32g431xx.h.

◆ RTC_SHIFTR_SUBFS_Pos

#define RTC_SHIFTR_SUBFS_Pos (0U)

Definition at line 8488 of file stm32g431xx.h.

◆ RTC_SR_ALRAF

#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk

Definition at line 8755 of file stm32g431xx.h.

◆ RTC_SR_ALRAF_Msk

#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos)

0x00000001

Definition at line 8754 of file stm32g431xx.h.

◆ RTC_SR_ALRAF_Pos

#define RTC_SR_ALRAF_Pos (0U)

Definition at line 8753 of file stm32g431xx.h.

◆ RTC_SR_ALRBF

#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk

Definition at line 8752 of file stm32g431xx.h.

◆ RTC_SR_ALRBF_Msk

#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos)

0x00000002

Definition at line 8751 of file stm32g431xx.h.

◆ RTC_SR_ALRBF_Pos

#define RTC_SR_ALRBF_Pos (1U)

Definition at line 8750 of file stm32g431xx.h.

◆ RTC_SR_ITSF

#define RTC_SR_ITSF RTC_SR_ITSF_Msk

Definition at line 8740 of file stm32g431xx.h.

◆ RTC_SR_ITSF_Msk

#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos)

0x00000020

Definition at line 8739 of file stm32g431xx.h.

◆ RTC_SR_ITSF_Pos

#define RTC_SR_ITSF_Pos (5U)

Definition at line 8738 of file stm32g431xx.h.

◆ RTC_SR_TSF

#define RTC_SR_TSF RTC_SR_TSF_Msk

Definition at line 8746 of file stm32g431xx.h.

◆ RTC_SR_TSF_Msk

#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos)

0x00000008

Definition at line 8745 of file stm32g431xx.h.

◆ RTC_SR_TSF_Pos

#define RTC_SR_TSF_Pos (3U)

Definition at line 8744 of file stm32g431xx.h.

◆ RTC_SR_TSOVF

#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk

Definition at line 8743 of file stm32g431xx.h.

◆ RTC_SR_TSOVF_Msk

#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos)

0x00000010

Definition at line 8742 of file stm32g431xx.h.

◆ RTC_SR_TSOVF_Pos

#define RTC_SR_TSOVF_Pos (4U)

Definition at line 8741 of file stm32g431xx.h.

◆ RTC_SR_WUTF

#define RTC_SR_WUTF RTC_SR_WUTF_Msk

Definition at line 8749 of file stm32g431xx.h.

◆ RTC_SR_WUTF_Msk

#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos)

0x00000004

Definition at line 8748 of file stm32g431xx.h.

◆ RTC_SR_WUTF_Pos

#define RTC_SR_WUTF_Pos (2U)

Definition at line 8747 of file stm32g431xx.h.

◆ RTC_SSR_SS

#define RTC_SSR_SS RTC_SSR_SS_Msk

Definition at line 8330 of file stm32g431xx.h.

◆ RTC_SSR_SS_Msk

#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos)

0x0000FFFF

Definition at line 8329 of file stm32g431xx.h.

◆ RTC_SSR_SS_Pos

#define RTC_SSR_SS_Pos (0U)

Definition at line 8328 of file stm32g431xx.h.

◆ RTC_TR_HT

#define RTC_TR_HT RTC_TR_HT_Msk

Definition at line 8246 of file stm32g431xx.h.

◆ RTC_TR_HT_0

#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos)

0x00100000

Definition at line 8247 of file stm32g431xx.h.

◆ RTC_TR_HT_1

#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos)

0x00200000

Definition at line 8248 of file stm32g431xx.h.

◆ RTC_TR_HT_Msk

#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos)

0x00300000

Definition at line 8245 of file stm32g431xx.h.

◆ RTC_TR_HT_Pos

#define RTC_TR_HT_Pos (20U)

Definition at line 8244 of file stm32g431xx.h.

◆ RTC_TR_HU

#define RTC_TR_HU RTC_TR_HU_Msk

Definition at line 8251 of file stm32g431xx.h.

◆ RTC_TR_HU_0

#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos)

0x00010000

Definition at line 8252 of file stm32g431xx.h.

◆ RTC_TR_HU_1

#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos)

0x00020000

Definition at line 8253 of file stm32g431xx.h.

◆ RTC_TR_HU_2

#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos)

0x00040000

Definition at line 8254 of file stm32g431xx.h.

◆ RTC_TR_HU_3

#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos)

0x00080000

Definition at line 8255 of file stm32g431xx.h.

◆ RTC_TR_HU_Msk

#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos)

0x000F0000

Definition at line 8250 of file stm32g431xx.h.

◆ RTC_TR_HU_Pos

#define RTC_TR_HU_Pos (16U)

Definition at line 8249 of file stm32g431xx.h.

◆ RTC_TR_MNT

#define RTC_TR_MNT RTC_TR_MNT_Msk

Definition at line 8258 of file stm32g431xx.h.

◆ RTC_TR_MNT_0

#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos)

0x00001000

Definition at line 8259 of file stm32g431xx.h.

◆ RTC_TR_MNT_1

#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos)

0x00002000

Definition at line 8260 of file stm32g431xx.h.

◆ RTC_TR_MNT_2

#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos)

0x00004000

Definition at line 8261 of file stm32g431xx.h.

◆ RTC_TR_MNT_Msk

#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos)

0x00007000

Definition at line 8257 of file stm32g431xx.h.

◆ RTC_TR_MNT_Pos

#define RTC_TR_MNT_Pos (12U)

Definition at line 8256 of file stm32g431xx.h.

◆ RTC_TR_MNU

#define RTC_TR_MNU RTC_TR_MNU_Msk

Definition at line 8264 of file stm32g431xx.h.

◆ RTC_TR_MNU_0

#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos)

0x00000100

Definition at line 8265 of file stm32g431xx.h.

◆ RTC_TR_MNU_1

#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos)

0x00000200

Definition at line 8266 of file stm32g431xx.h.

◆ RTC_TR_MNU_2

#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos)

0x00000400

Definition at line 8267 of file stm32g431xx.h.

◆ RTC_TR_MNU_3

#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos)

0x00000800

Definition at line 8268 of file stm32g431xx.h.

◆ RTC_TR_MNU_Msk

#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos)

0x00000F00

Definition at line 8263 of file stm32g431xx.h.

◆ RTC_TR_MNU_Pos

#define RTC_TR_MNU_Pos (8U)

Definition at line 8262 of file stm32g431xx.h.

◆ RTC_TR_PM

#define RTC_TR_PM RTC_TR_PM_Msk

Definition at line 8243 of file stm32g431xx.h.

◆ RTC_TR_PM_Msk

#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos)

0x00400000

Definition at line 8242 of file stm32g431xx.h.

◆ RTC_TR_PM_Pos

#define RTC_TR_PM_Pos (22U)

Definition at line 8241 of file stm32g431xx.h.

◆ RTC_TR_ST

#define RTC_TR_ST RTC_TR_ST_Msk

Definition at line 8271 of file stm32g431xx.h.

◆ RTC_TR_ST_0

#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos)

0x00000010

Definition at line 8272 of file stm32g431xx.h.

◆ RTC_TR_ST_1

#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos)

0x00000020

Definition at line 8273 of file stm32g431xx.h.

◆ RTC_TR_ST_2

#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos)

0x00000040

Definition at line 8274 of file stm32g431xx.h.

◆ RTC_TR_ST_Msk

#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos)

0x00000070

Definition at line 8270 of file stm32g431xx.h.

◆ RTC_TR_ST_Pos

#define RTC_TR_ST_Pos (4U)

Definition at line 8269 of file stm32g431xx.h.

◆ RTC_TR_SU

#define RTC_TR_SU RTC_TR_SU_Msk

Definition at line 8277 of file stm32g431xx.h.

◆ RTC_TR_SU_0

#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos)

0x00000001

Definition at line 8278 of file stm32g431xx.h.

◆ RTC_TR_SU_1

#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos)

0x00000002

Definition at line 8279 of file stm32g431xx.h.

◆ RTC_TR_SU_2

#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos)

0x00000004

Definition at line 8280 of file stm32g431xx.h.

◆ RTC_TR_SU_3

#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos)

0x00000008

Definition at line 8281 of file stm32g431xx.h.

◆ RTC_TR_SU_Msk

#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos)

0x0000000F

Definition at line 8276 of file stm32g431xx.h.

◆ RTC_TR_SU_Pos

#define RTC_TR_SU_Pos (0U)

Definition at line 8275 of file stm32g431xx.h.

◆ RTC_TSDR_DT

#define RTC_TSDR_DT RTC_TSDR_DT_Msk

Definition at line 8557 of file stm32g431xx.h.

◆ RTC_TSDR_DT_0

#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos)

0x00000010

Definition at line 8558 of file stm32g431xx.h.

◆ RTC_TSDR_DT_1

#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos)

0x00000020

Definition at line 8559 of file stm32g431xx.h.

◆ RTC_TSDR_DT_Msk

#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos)

0x00000030

Definition at line 8556 of file stm32g431xx.h.

◆ RTC_TSDR_DT_Pos

#define RTC_TSDR_DT_Pos (4U)

Definition at line 8555 of file stm32g431xx.h.

◆ RTC_TSDR_DU

#define RTC_TSDR_DU RTC_TSDR_DU_Msk

Definition at line 8562 of file stm32g431xx.h.

◆ RTC_TSDR_DU_0

#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos)

0x00000001

Definition at line 8563 of file stm32g431xx.h.

◆ RTC_TSDR_DU_1

#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos)

0x00000002

Definition at line 8564 of file stm32g431xx.h.

◆ RTC_TSDR_DU_2

#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos)

0x00000004

Definition at line 8565 of file stm32g431xx.h.

◆ RTC_TSDR_DU_3

#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos)

0x00000008

Definition at line 8566 of file stm32g431xx.h.

◆ RTC_TSDR_DU_Msk

#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos)

0x0000000F

Definition at line 8561 of file stm32g431xx.h.

◆ RTC_TSDR_DU_Pos

#define RTC_TSDR_DU_Pos (0U)

Definition at line 8560 of file stm32g431xx.h.

◆ RTC_TSDR_MT

#define RTC_TSDR_MT RTC_TSDR_MT_Msk

Definition at line 8547 of file stm32g431xx.h.

◆ RTC_TSDR_MT_Msk

#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos)

0x00001000

Definition at line 8546 of file stm32g431xx.h.

◆ RTC_TSDR_MT_Pos

#define RTC_TSDR_MT_Pos (12U)

Definition at line 8545 of file stm32g431xx.h.

◆ RTC_TSDR_MU

#define RTC_TSDR_MU RTC_TSDR_MU_Msk

Definition at line 8550 of file stm32g431xx.h.

◆ RTC_TSDR_MU_0

#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos)

0x00000100

Definition at line 8551 of file stm32g431xx.h.

◆ RTC_TSDR_MU_1

#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos)

0x00000200

Definition at line 8552 of file stm32g431xx.h.

◆ RTC_TSDR_MU_2

#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos)

0x00000400

Definition at line 8553 of file stm32g431xx.h.

◆ RTC_TSDR_MU_3

#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos)

0x00000800

Definition at line 8554 of file stm32g431xx.h.

◆ RTC_TSDR_MU_Msk

#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos)

0x00000F00

Definition at line 8549 of file stm32g431xx.h.

◆ RTC_TSDR_MU_Pos

#define RTC_TSDR_MU_Pos (8U)

Definition at line 8548 of file stm32g431xx.h.

◆ RTC_TSDR_WDU

#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk

Definition at line 8541 of file stm32g431xx.h.

◆ RTC_TSDR_WDU_0

#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos)

0x00002000

Definition at line 8542 of file stm32g431xx.h.

◆ RTC_TSDR_WDU_1

#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos)

0x00004000

Definition at line 8543 of file stm32g431xx.h.

◆ RTC_TSDR_WDU_2

#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos)

0x00008000

Definition at line 8544 of file stm32g431xx.h.

◆ RTC_TSDR_WDU_Msk

#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos)

0x0000E000

Definition at line 8540 of file stm32g431xx.h.

◆ RTC_TSDR_WDU_Pos

#define RTC_TSDR_WDU_Pos (13U)

Definition at line 8539 of file stm32g431xx.h.

◆ RTC_TSSSR_SS

#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk

Definition at line 8571 of file stm32g431xx.h.

◆ RTC_TSSSR_SS_Msk

#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos)

0x0000FFFF

Definition at line 8570 of file stm32g431xx.h.

◆ RTC_TSSSR_SS_Pos

#define RTC_TSSSR_SS_Pos (0U)

Definition at line 8569 of file stm32g431xx.h.

◆ RTC_TSTR_HT

#define RTC_TSTR_HT RTC_TSTR_HT_Msk

Definition at line 8501 of file stm32g431xx.h.

◆ RTC_TSTR_HT_0

#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos)

0x00100000

Definition at line 8502 of file stm32g431xx.h.

◆ RTC_TSTR_HT_1

#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos)

0x00200000

Definition at line 8503 of file stm32g431xx.h.

◆ RTC_TSTR_HT_Msk

#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos)

0x00300000

Definition at line 8500 of file stm32g431xx.h.

◆ RTC_TSTR_HT_Pos

#define RTC_TSTR_HT_Pos (20U)

Definition at line 8499 of file stm32g431xx.h.

◆ RTC_TSTR_HU

#define RTC_TSTR_HU RTC_TSTR_HU_Msk

Definition at line 8506 of file stm32g431xx.h.

◆ RTC_TSTR_HU_0

#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos)

0x00010000

Definition at line 8507 of file stm32g431xx.h.

◆ RTC_TSTR_HU_1

#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos)

0x00020000

Definition at line 8508 of file stm32g431xx.h.

◆ RTC_TSTR_HU_2

#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos)

0x00040000

Definition at line 8509 of file stm32g431xx.h.

◆ RTC_TSTR_HU_3

#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos)

0x00080000

Definition at line 8510 of file stm32g431xx.h.

◆ RTC_TSTR_HU_Msk

#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos)

0x000F0000

Definition at line 8505 of file stm32g431xx.h.

◆ RTC_TSTR_HU_Pos

#define RTC_TSTR_HU_Pos (16U)

Definition at line 8504 of file stm32g431xx.h.

◆ RTC_TSTR_MNT

#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk

Definition at line 8513 of file stm32g431xx.h.

◆ RTC_TSTR_MNT_0

#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos)

0x00001000

Definition at line 8514 of file stm32g431xx.h.

◆ RTC_TSTR_MNT_1

#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos)

0x00002000

Definition at line 8515 of file stm32g431xx.h.

◆ RTC_TSTR_MNT_2

#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos)

0x00004000

Definition at line 8516 of file stm32g431xx.h.

◆ RTC_TSTR_MNT_Msk

#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos)

0x00007000

Definition at line 8512 of file stm32g431xx.h.

◆ RTC_TSTR_MNT_Pos

#define RTC_TSTR_MNT_Pos (12U)

Definition at line 8511 of file stm32g431xx.h.

◆ RTC_TSTR_MNU

#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk

Definition at line 8519 of file stm32g431xx.h.

◆ RTC_TSTR_MNU_0

#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos)

0x00000100

Definition at line 8520 of file stm32g431xx.h.

◆ RTC_TSTR_MNU_1

#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos)

0x00000200

Definition at line 8521 of file stm32g431xx.h.

◆ RTC_TSTR_MNU_2

#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos)

0x00000400

Definition at line 8522 of file stm32g431xx.h.

◆ RTC_TSTR_MNU_3

#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos)

0x00000800

Definition at line 8523 of file stm32g431xx.h.

◆ RTC_TSTR_MNU_Msk

#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos)

0x00000F00

Definition at line 8518 of file stm32g431xx.h.

◆ RTC_TSTR_MNU_Pos

#define RTC_TSTR_MNU_Pos (8U)

Definition at line 8517 of file stm32g431xx.h.

◆ RTC_TSTR_PM

#define RTC_TSTR_PM RTC_TSTR_PM_Msk

Definition at line 8498 of file stm32g431xx.h.

◆ RTC_TSTR_PM_Msk

#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos)

0x00400000

Definition at line 8497 of file stm32g431xx.h.

◆ RTC_TSTR_PM_Pos

#define RTC_TSTR_PM_Pos (22U)

Definition at line 8496 of file stm32g431xx.h.

◆ RTC_TSTR_ST

#define RTC_TSTR_ST RTC_TSTR_ST_Msk

Definition at line 8526 of file stm32g431xx.h.

◆ RTC_TSTR_ST_0

#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos)

0x00000010

Definition at line 8527 of file stm32g431xx.h.

◆ RTC_TSTR_ST_1

#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos)

0x00000020

Definition at line 8528 of file stm32g431xx.h.

◆ RTC_TSTR_ST_2

#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos)

0x00000040

Definition at line 8529 of file stm32g431xx.h.

◆ RTC_TSTR_ST_Msk

#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos)

0x00000070

Definition at line 8525 of file stm32g431xx.h.

◆ RTC_TSTR_ST_Pos

#define RTC_TSTR_ST_Pos (4U)

Definition at line 8524 of file stm32g431xx.h.

◆ RTC_TSTR_SU

#define RTC_TSTR_SU RTC_TSTR_SU_Msk

Definition at line 8532 of file stm32g431xx.h.

◆ RTC_TSTR_SU_0

#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos)

0x00000001

Definition at line 8533 of file stm32g431xx.h.

◆ RTC_TSTR_SU_1

#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos)

0x00000002

Definition at line 8534 of file stm32g431xx.h.

◆ RTC_TSTR_SU_2

#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos)

0x00000004

Definition at line 8535 of file stm32g431xx.h.

◆ RTC_TSTR_SU_3

#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos)

0x00000008

Definition at line 8536 of file stm32g431xx.h.

◆ RTC_TSTR_SU_Msk

#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos)

0x0000000F

Definition at line 8531 of file stm32g431xx.h.

◆ RTC_TSTR_SU_Pos

#define RTC_TSTR_SU_Pos (0U)

Definition at line 8530 of file stm32g431xx.h.

◆ RTC_WPR_KEY

#define RTC_WPR_KEY RTC_WPR_KEY_Msk

Definition at line 8462 of file stm32g431xx.h.

◆ RTC_WPR_KEY_Msk

#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos)

0x000000FF

Definition at line 8461 of file stm32g431xx.h.

◆ RTC_WPR_KEY_Pos

#define RTC_WPR_KEY_Pos (0U)

Definition at line 8460 of file stm32g431xx.h.

◆ RTC_WUTR_WUT

#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk

Definition at line 8372 of file stm32g431xx.h.

◆ RTC_WUTR_WUT_Msk

#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos)

0x0000FFFF

Definition at line 8371 of file stm32g431xx.h.

◆ RTC_WUTR_WUT_Pos

#define RTC_WUTR_WUT_Pos (0U)

Definition at line 8370 of file stm32g431xx.h.

◆ SAI_GCR_SYNCIN

#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk

SYNCIN[1:0] bits (Synchronization Inputs)

Definition at line 9056 of file stm32g431xx.h.

◆ SAI_GCR_SYNCIN_0

#define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos)

0x00000001

Definition at line 9057 of file stm32g431xx.h.

◆ SAI_GCR_SYNCIN_1

#define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos)

0x00000002

Definition at line 9058 of file stm32g431xx.h.

◆ SAI_GCR_SYNCIN_Msk

#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos)

0x00000003

Definition at line 9055 of file stm32g431xx.h.

◆ SAI_GCR_SYNCIN_Pos

#define SAI_GCR_SYNCIN_Pos (0U)

Definition at line 9054 of file stm32g431xx.h.

◆ SAI_GCR_SYNCOUT

#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk

SYNCOUT[1:0] bits (Synchronization Outputs)

Definition at line 9062 of file stm32g431xx.h.

◆ SAI_GCR_SYNCOUT_0

#define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos)

0x00000010

Definition at line 9063 of file stm32g431xx.h.

◆ SAI_GCR_SYNCOUT_1

#define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos)

0x00000020

Definition at line 9064 of file stm32g431xx.h.

◆ SAI_GCR_SYNCOUT_Msk

#define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos)

0x00000030

Definition at line 9061 of file stm32g431xx.h.

◆ SAI_GCR_SYNCOUT_Pos

#define SAI_GCR_SYNCOUT_Pos (4U)

Definition at line 9060 of file stm32g431xx.h.

◆ SAI_PDMCR_CKEN1

#define SAI_PDMCR_CKEN1 SAI_PDMCR_CKEN1_Msk

Clock 1 enable

Definition at line 9331 of file stm32g431xx.h.

◆ SAI_PDMCR_CKEN1_Msk

#define SAI_PDMCR_CKEN1_Msk (0x1UL << SAI_PDMCR_CKEN1_Pos)

0x00000100

Definition at line 9330 of file stm32g431xx.h.

◆ SAI_PDMCR_CKEN1_Pos

#define SAI_PDMCR_CKEN1_Pos (8U)

Definition at line 9329 of file stm32g431xx.h.

◆ SAI_PDMCR_CKEN2

#define SAI_PDMCR_CKEN2 SAI_PDMCR_CKEN2_Msk

Clock 2 enable

Definition at line 9334 of file stm32g431xx.h.

◆ SAI_PDMCR_CKEN2_Msk

#define SAI_PDMCR_CKEN2_Msk (0x1UL << SAI_PDMCR_CKEN2_Pos)

0x00000200

Definition at line 9333 of file stm32g431xx.h.

◆ SAI_PDMCR_CKEN2_Pos

#define SAI_PDMCR_CKEN2_Pos (9U)

Definition at line 9332 of file stm32g431xx.h.

◆ SAI_PDMCR_CKEN3

#define SAI_PDMCR_CKEN3 SAI_PDMCR_CKEN3_Msk

Clock 3 enable

Definition at line 9337 of file stm32g431xx.h.

◆ SAI_PDMCR_CKEN3_Msk

#define SAI_PDMCR_CKEN3_Msk (0x1UL << SAI_PDMCR_CKEN3_Pos)

0x00000400

Definition at line 9336 of file stm32g431xx.h.

◆ SAI_PDMCR_CKEN3_Pos

#define SAI_PDMCR_CKEN3_Pos (10U)

Definition at line 9335 of file stm32g431xx.h.

◆ SAI_PDMCR_CKEN4

#define SAI_PDMCR_CKEN4 SAI_PDMCR_CKEN4_Msk

Clock 4 enable

Definition at line 9340 of file stm32g431xx.h.

◆ SAI_PDMCR_CKEN4_Msk

#define SAI_PDMCR_CKEN4_Msk (0x1UL << SAI_PDMCR_CKEN4_Pos)

0x00000800

Definition at line 9339 of file stm32g431xx.h.

◆ SAI_PDMCR_CKEN4_Pos

#define SAI_PDMCR_CKEN4_Pos (11U)

Definition at line 9338 of file stm32g431xx.h.

◆ SAI_PDMCR_MICNBR

#define SAI_PDMCR_MICNBR SAI_PDMCR_MICNBR_Msk

MICNBR[1:0] (Number of microphones)

Definition at line 9325 of file stm32g431xx.h.

◆ SAI_PDMCR_MICNBR_0

#define SAI_PDMCR_MICNBR_0 (0x1UL << SAI_PDMCR_MICNBR_Pos)

0x00000010

Definition at line 9326 of file stm32g431xx.h.

◆ SAI_PDMCR_MICNBR_1

#define SAI_PDMCR_MICNBR_1 (0x2UL << SAI_PDMCR_MICNBR_Pos)

0x00000020

Definition at line 9327 of file stm32g431xx.h.

◆ SAI_PDMCR_MICNBR_Msk

#define SAI_PDMCR_MICNBR_Msk (0x3UL << SAI_PDMCR_MICNBR_Pos)

0x00000030

Definition at line 9324 of file stm32g431xx.h.

◆ SAI_PDMCR_MICNBR_Pos

#define SAI_PDMCR_MICNBR_Pos (4U)

Definition at line 9323 of file stm32g431xx.h.

◆ SAI_PDMCR_PDMEN

#define SAI_PDMCR_PDMEN SAI_PDMCR_PDMEN_Msk

PDM enable

Definition at line 9321 of file stm32g431xx.h.

◆ SAI_PDMCR_PDMEN_Msk

#define SAI_PDMCR_PDMEN_Msk (0x1UL << SAI_PDMCR_PDMEN_Pos)

0x00000001

Definition at line 9320 of file stm32g431xx.h.

◆ SAI_PDMCR_PDMEN_Pos

#define SAI_PDMCR_PDMEN_Pos (0U)

Definition at line 9319 of file stm32g431xx.h.

◆ SAI_PDMDLY_DLYM1L

#define SAI_PDMDLY_DLYM1L SAI_PDMDLY_DLYM1L_Msk

DLYM1L[2:0] (Delay line adjust for left microphone of pair 1)

Definition at line 9345 of file stm32g431xx.h.

◆ SAI_PDMDLY_DLYM1L_0

#define SAI_PDMDLY_DLYM1L_0 (0x1UL << SAI_PDMDLY_DLYM1L_Pos)

0x00000001

Definition at line 9346 of file stm32g431xx.h.

◆ SAI_PDMDLY_DLYM1L_1

#define SAI_PDMDLY_DLYM1L_1 (0x2UL << SAI_PDMDLY_DLYM1L_Pos)

0x00000002

Definition at line 9347 of file stm32g431xx.h.

◆ SAI_PDMDLY_DLYM1L_2

#define SAI_PDMDLY_DLYM1L_2 (0x4UL << SAI_PDMDLY_DLYM1L_Pos)

0x00000004

Definition at line 9348 of file stm32g431xx.h.

◆ SAI_PDMDLY_DLYM1L_Msk

#define SAI_PDMDLY_DLYM1L_Msk (0x7UL << SAI_PDMDLY_DLYM1L_Pos)

0x00000007

Definition at line 9344 of file stm32g431xx.h.

◆ SAI_PDMDLY_DLYM1L_Pos

#define SAI_PDMDLY_DLYM1L_Pos (0U)

Definition at line 9343 of file stm32g431xx.h.

◆ SAI_PDMDLY_DLYM1R

#define SAI_PDMDLY_DLYM1R SAI_PDMDLY_DLYM1R_Msk

DLYM1R[2:0] (Delay line adjust for right microphone of pair 1)

Definition at line 9352 of file stm32g431xx.h.

◆ SAI_PDMDLY_DLYM1R_0

#define SAI_PDMDLY_DLYM1R_0 (0x1UL << SAI_PDMDLY_DLYM1R_Pos)

0x00000010

Definition at line 9353 of file stm32g431xx.h.

◆ SAI_PDMDLY_DLYM1R_1

#define SAI_PDMDLY_DLYM1R_1 (0x2UL << SAI_PDMDLY_DLYM1R_Pos)

0x00000020

Definition at line 9354 of file stm32g431xx.h.

◆ SAI_PDMDLY_DLYM1R_2

#define SAI_PDMDLY_DLYM1R_2 (0x4UL << SAI_PDMDLY_DLYM1R_Pos)

0x00000040

Definition at line 9355 of file stm32g431xx.h.

◆ SAI_PDMDLY_DLYM1R_Msk

#define SAI_PDMDLY_DLYM1R_Msk (0x7UL << SAI_PDMDLY_DLYM1R_Pos)

0x00000070

Definition at line 9351 of file stm32g431xx.h.

◆ SAI_PDMDLY_DLYM1R_Pos

#define SAI_PDMDLY_DLYM1R_Pos (4U)

Definition at line 9350 of file stm32g431xx.h.

◆ SAI_PDMDLY_DLYM2L

#define SAI_PDMDLY_DLYM2L SAI_PDMDLY_DLYM2L_Msk

DLYM2L[2:0] (Delay line adjust for left microphone of pair 2)

Definition at line 9359 of file stm32g431xx.h.

◆ SAI_PDMDLY_DLYM2L_0

#define SAI_PDMDLY_DLYM2L_0 (0x1UL << SAI_PDMDLY_DLYM2L_Pos)

0x00000100

Definition at line 9360 of file stm32g431xx.h.

◆ SAI_PDMDLY_DLYM2L_1

#define SAI_PDMDLY_DLYM2L_1 (0x2UL << SAI_PDMDLY_DLYM2L_Pos)

0x00000200

Definition at line 9361 of file stm32g431xx.h.

◆ SAI_PDMDLY_DLYM2L_2

#define SAI_PDMDLY_DLYM2L_2 (0x4UL << SAI_PDMDLY_DLYM2L_Pos)

0x00000400

Definition at line 9362 of file stm32g431xx.h.

◆ SAI_PDMDLY_DLYM2L_Msk

#define SAI_PDMDLY_DLYM2L_Msk (0x7UL << SAI_PDMDLY_DLYM2L_Pos)

0x00000700

Definition at line 9358 of file stm32g431xx.h.

◆ SAI_PDMDLY_DLYM2L_Pos

#define SAI_PDMDLY_DLYM2L_Pos (8U)

Definition at line 9357 of file stm32g431xx.h.

◆ SAI_PDMDLY_DLYM2R

#define SAI_PDMDLY_DLYM2R SAI_PDMDLY_DLYM2R_Msk

DLYM2R[2:0] (Delay line adjust for right microphone of pair 2)

Definition at line 9366 of file stm32g431xx.h.

◆ SAI_PDMDLY_DLYM2R_0

#define SAI_PDMDLY_DLYM2R_0 (0x1UL << SAI_PDMDLY_DLYM2R_Pos)

0x00001000

Definition at line 9367 of file stm32g431xx.h.

◆ SAI_PDMDLY_DLYM2R_1

#define SAI_PDMDLY_DLYM2R_1 (0x2UL << SAI_PDMDLY_DLYM2R_Pos)

0x00002000

Definition at line 9368 of file stm32g431xx.h.

◆ SAI_PDMDLY_DLYM2R_2

#define SAI_PDMDLY_DLYM2R_2 (0x4UL << SAI_PDMDLY_DLYM2R_Pos)

0x00004000

Definition at line 9369 of file stm32g431xx.h.

◆ SAI_PDMDLY_DLYM2R_Msk

#define SAI_PDMDLY_DLYM2R_Msk (0x7UL << SAI_PDMDLY_DLYM2R_Pos)

0x00007000

Definition at line 9365 of file stm32g431xx.h.

◆ SAI_PDMDLY_DLYM2R_Pos

#define SAI_PDMDLY_DLYM2R_Pos (12U)

Definition at line 9364 of file stm32g431xx.h.

◆ SAI_PDMDLY_DLYM3L

#define SAI_PDMDLY_DLYM3L SAI_PDMDLY_DLYM3L_Msk

DLYM3L[2:0] (Delay line adjust for left microphone of pair 3)

Definition at line 9373 of file stm32g431xx.h.

◆ SAI_PDMDLY_DLYM3L_0

#define SAI_PDMDLY_DLYM3L_0 (0x1UL << SAI_PDMDLY_DLYM3L_Pos)

0x00010000

Definition at line 9374 of file stm32g431xx.h.

◆ SAI_PDMDLY_DLYM3L_1

#define SAI_PDMDLY_DLYM3L_1 (0x2UL << SAI_PDMDLY_DLYM3L_Pos)

0x00020000

Definition at line 9375 of file stm32g431xx.h.

◆ SAI_PDMDLY_DLYM3L_2

#define SAI_PDMDLY_DLYM3L_2 (0x4UL << SAI_PDMDLY_DLYM3L_Pos)

0x00040000

Definition at line 9376 of file stm32g431xx.h.

◆ SAI_PDMDLY_DLYM3L_Msk

#define SAI_PDMDLY_DLYM3L_Msk (0x7UL << SAI_PDMDLY_DLYM3L_Pos)

0x00070000

Definition at line 9372 of file stm32g431xx.h.

◆ SAI_PDMDLY_DLYM3L_Pos

#define SAI_PDMDLY_DLYM3L_Pos (16U)

Definition at line 9371 of file stm32g431xx.h.

◆ SAI_PDMDLY_DLYM3R

#define SAI_PDMDLY_DLYM3R SAI_PDMDLY_DLYM3R_Msk

DLYM3R[2:0] (Delay line adjust for right microphone of pair 3)

Definition at line 9380 of file stm32g431xx.h.

◆ SAI_PDMDLY_DLYM3R_0

#define SAI_PDMDLY_DLYM3R_0 (0x1UL << SAI_PDMDLY_DLYM3R_Pos)

0x00100000

Definition at line 9381 of file stm32g431xx.h.

◆ SAI_PDMDLY_DLYM3R_1

#define SAI_PDMDLY_DLYM3R_1 (0x2UL << SAI_PDMDLY_DLYM3R_Pos)

0x00200000

Definition at line 9382 of file stm32g431xx.h.

◆ SAI_PDMDLY_DLYM3R_2

#define SAI_PDMDLY_DLYM3R_2 (0x4UL << SAI_PDMDLY_DLYM3R_Pos)

0x00400000

Definition at line 9383 of file stm32g431xx.h.

◆ SAI_PDMDLY_DLYM3R_Msk

#define SAI_PDMDLY_DLYM3R_Msk (0x7UL << SAI_PDMDLY_DLYM3R_Pos)

0x00700000

Definition at line 9379 of file stm32g431xx.h.

◆ SAI_PDMDLY_DLYM3R_Pos

#define SAI_PDMDLY_DLYM3R_Pos (20U)

Definition at line 9378 of file stm32g431xx.h.

◆ SAI_PDMDLY_DLYM4L

#define SAI_PDMDLY_DLYM4L SAI_PDMDLY_DLYM4L_Msk

DLYM4L[2:0] (Delay line adjust for left microphone of pair 4)

Definition at line 9387 of file stm32g431xx.h.

◆ SAI_PDMDLY_DLYM4L_0

#define SAI_PDMDLY_DLYM4L_0 (0x1UL << SAI_PDMDLY_DLYM4L_Pos)

0x01000000

Definition at line 9388 of file stm32g431xx.h.

◆ SAI_PDMDLY_DLYM4L_1

#define SAI_PDMDLY_DLYM4L_1 (0x2UL << SAI_PDMDLY_DLYM4L_Pos)

0x02000000

Definition at line 9389 of file stm32g431xx.h.

◆ SAI_PDMDLY_DLYM4L_2

#define SAI_PDMDLY_DLYM4L_2 (0x4UL << SAI_PDMDLY_DLYM4L_Pos)

0x04000000

Definition at line 9390 of file stm32g431xx.h.

◆ SAI_PDMDLY_DLYM4L_Msk

#define SAI_PDMDLY_DLYM4L_Msk (0x7UL << SAI_PDMDLY_DLYM4L_Pos)

0x07000000

Definition at line 9386 of file stm32g431xx.h.

◆ SAI_PDMDLY_DLYM4L_Pos

#define SAI_PDMDLY_DLYM4L_Pos (24U)

Definition at line 9385 of file stm32g431xx.h.

◆ SAI_PDMDLY_DLYM4R

#define SAI_PDMDLY_DLYM4R SAI_PDMDLY_DLYM4R_Msk

DLYM4R[2:0] (Delay line adjust for right microphone of pair 4)

Definition at line 9394 of file stm32g431xx.h.

◆ SAI_PDMDLY_DLYM4R_0

#define SAI_PDMDLY_DLYM4R_0 (0x1UL << SAI_PDMDLY_DLYM4R_Pos)

0x10000000

Definition at line 9395 of file stm32g431xx.h.

◆ SAI_PDMDLY_DLYM4R_1

#define SAI_PDMDLY_DLYM4R_1 (0x2UL << SAI_PDMDLY_DLYM4R_Pos)

0x20000000

Definition at line 9396 of file stm32g431xx.h.

◆ SAI_PDMDLY_DLYM4R_2

#define SAI_PDMDLY_DLYM4R_2 (0x4UL << SAI_PDMDLY_DLYM4R_Pos)

0x40000000

Definition at line 9397 of file stm32g431xx.h.

◆ SAI_PDMDLY_DLYM4R_Msk

#define SAI_PDMDLY_DLYM4R_Msk (0x7UL << SAI_PDMDLY_DLYM4R_Pos)

0x70000000

Definition at line 9393 of file stm32g431xx.h.

◆ SAI_PDMDLY_DLYM4R_Pos

#define SAI_PDMDLY_DLYM4R_Pos (28U)

Definition at line 9392 of file stm32g431xx.h.

◆ SAI_xCLRFR_CAFSDET

#define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk

Clear Anticipated frame synchronization detection

Definition at line 9308 of file stm32g431xx.h.

◆ SAI_xCLRFR_CAFSDET_Msk

#define SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos)

0x00000020

Definition at line 9307 of file stm32g431xx.h.

◆ SAI_xCLRFR_CAFSDET_Pos

#define SAI_xCLRFR_CAFSDET_Pos (5U)

Definition at line 9306 of file stm32g431xx.h.

◆ SAI_xCLRFR_CCNRDY

#define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk

Clear Codec not ready

Definition at line 9305 of file stm32g431xx.h.

◆ SAI_xCLRFR_CCNRDY_Msk

#define SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos)

0x00000010

Definition at line 9304 of file stm32g431xx.h.

◆ SAI_xCLRFR_CCNRDY_Pos

#define SAI_xCLRFR_CCNRDY_Pos (4U)

Definition at line 9303 of file stm32g431xx.h.

◆ SAI_xCLRFR_CFREQ

#define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk

Clear FIFO request

Definition at line 9302 of file stm32g431xx.h.

◆ SAI_xCLRFR_CFREQ_Msk

#define SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos)

0x00000008

Definition at line 9301 of file stm32g431xx.h.

◆ SAI_xCLRFR_CFREQ_Pos

#define SAI_xCLRFR_CFREQ_Pos (3U)

Definition at line 9300 of file stm32g431xx.h.

◆ SAI_xCLRFR_CLFSDET

#define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk

Clear Late frame synchronization detection

Definition at line 9311 of file stm32g431xx.h.

◆ SAI_xCLRFR_CLFSDET_Msk

#define SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos)

0x00000040

Definition at line 9310 of file stm32g431xx.h.

◆ SAI_xCLRFR_CLFSDET_Pos

#define SAI_xCLRFR_CLFSDET_Pos (6U)

Definition at line 9309 of file stm32g431xx.h.

◆ SAI_xCLRFR_CMUTEDET

#define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk

Clear Mute detection

Definition at line 9296 of file stm32g431xx.h.

◆ SAI_xCLRFR_CMUTEDET_Msk

#define SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)

0x00000002

Definition at line 9295 of file stm32g431xx.h.

◆ SAI_xCLRFR_CMUTEDET_Pos

#define SAI_xCLRFR_CMUTEDET_Pos (1U)

Definition at line 9294 of file stm32g431xx.h.

◆ SAI_xCLRFR_COVRUDR

#define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk

Clear Overrun underrun

Definition at line 9293 of file stm32g431xx.h.

◆ SAI_xCLRFR_COVRUDR_Msk

#define SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos)

0x00000001

Definition at line 9292 of file stm32g431xx.h.

◆ SAI_xCLRFR_COVRUDR_Pos

#define SAI_xCLRFR_COVRUDR_Pos (0U)

Definition at line 9291 of file stm32g431xx.h.

◆ SAI_xCLRFR_CWCKCFG

#define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk

Clear Wrong Clock Configuration

Definition at line 9299 of file stm32g431xx.h.

◆ SAI_xCLRFR_CWCKCFG_Msk

#define SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)

0x00000004

Definition at line 9298 of file stm32g431xx.h.

◆ SAI_xCLRFR_CWCKCFG_Pos

#define SAI_xCLRFR_CWCKCFG_Pos (2U)

Definition at line 9297 of file stm32g431xx.h.

◆ SAI_xCR1_CKSTR

#define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk

ClocK STRobing edge

Definition at line 9091 of file stm32g431xx.h.

◆ SAI_xCR1_CKSTR_Msk

#define SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos)

0x00000200

Definition at line 9090 of file stm32g431xx.h.

◆ SAI_xCR1_CKSTR_Pos

#define SAI_xCR1_CKSTR_Pos (9U)

Definition at line 9089 of file stm32g431xx.h.

◆ SAI_xCR1_DMAEN

#define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk

DMA enable

Definition at line 9110 of file stm32g431xx.h.

◆ SAI_xCR1_DMAEN_Msk

#define SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos)

0x00020000

Definition at line 9109 of file stm32g431xx.h.

◆ SAI_xCR1_DMAEN_Pos

#define SAI_xCR1_DMAEN_Pos (17U)

Definition at line 9108 of file stm32g431xx.h.

◆ SAI_xCR1_DS

#define SAI_xCR1_DS SAI_xCR1_DS_Msk

DS[1:0] bits (Data Size)

Definition at line 9081 of file stm32g431xx.h.

◆ SAI_xCR1_DS_0

#define SAI_xCR1_DS_0 (0x1UL << SAI_xCR1_DS_Pos)

0x00000020

Definition at line 9082 of file stm32g431xx.h.

◆ SAI_xCR1_DS_1

#define SAI_xCR1_DS_1 (0x2UL << SAI_xCR1_DS_Pos)

0x00000040

Definition at line 9083 of file stm32g431xx.h.

◆ SAI_xCR1_DS_2

#define SAI_xCR1_DS_2 (0x4UL << SAI_xCR1_DS_Pos)

0x00000080

Definition at line 9084 of file stm32g431xx.h.

◆ SAI_xCR1_DS_Msk

#define SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos)

0x000000E0

Definition at line 9080 of file stm32g431xx.h.

◆ SAI_xCR1_DS_Pos

#define SAI_xCR1_DS_Pos (5U)

Definition at line 9079 of file stm32g431xx.h.

◆ SAI_xCR1_LSBFIRST

#define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk

LSB First Configuration

Definition at line 9088 of file stm32g431xx.h.

◆ SAI_xCR1_LSBFIRST_Msk

#define SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos)

0x00000100

Definition at line 9087 of file stm32g431xx.h.

◆ SAI_xCR1_LSBFIRST_Pos

#define SAI_xCR1_LSBFIRST_Pos (8U)

Definition at line 9086 of file stm32g431xx.h.

◆ SAI_xCR1_MCKDIV

#define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk

MCKDIV[5:0] (Master ClocK Divider)

Definition at line 9117 of file stm32g431xx.h.

◆ SAI_xCR1_MCKDIV_0

#define SAI_xCR1_MCKDIV_0 (0x00100000U)

Bit 0

Definition at line 9118 of file stm32g431xx.h.

◆ SAI_xCR1_MCKDIV_1

#define SAI_xCR1_MCKDIV_1 (0x00200000U)

Bit 1

Definition at line 9119 of file stm32g431xx.h.

◆ SAI_xCR1_MCKDIV_2

#define SAI_xCR1_MCKDIV_2 (0x00400000U)

Bit 2

Definition at line 9120 of file stm32g431xx.h.

◆ SAI_xCR1_MCKDIV_3

#define SAI_xCR1_MCKDIV_3 (0x00800000U)

Bit 3

Definition at line 9121 of file stm32g431xx.h.

◆ SAI_xCR1_MCKDIV_4

#define SAI_xCR1_MCKDIV_4 (0x01000000U)

Bit 4

Definition at line 9122 of file stm32g431xx.h.

◆ SAI_xCR1_MCKDIV_5

#define SAI_xCR1_MCKDIV_5 (0x02000000U)

Bit 5

Definition at line 9123 of file stm32g431xx.h.

◆ SAI_xCR1_MCKDIV_Msk

#define SAI_xCR1_MCKDIV_Msk (0x3FUL << SAI_xCR1_MCKDIV_Pos)

0x03F00000

Definition at line 9116 of file stm32g431xx.h.

◆ SAI_xCR1_MCKDIV_Pos

#define SAI_xCR1_MCKDIV_Pos (20U)

Definition at line 9115 of file stm32g431xx.h.

◆ SAI_xCR1_MCKEN

#define SAI_xCR1_MCKEN SAI_xCR1_MCKEN_Msk

Master clock generation enable

Definition at line 9131 of file stm32g431xx.h.

◆ SAI_xCR1_MCKEN_Msk

#define SAI_xCR1_MCKEN_Msk (0x1UL << SAI_xCR1_MCKEN_Pos)

0x08000000

Definition at line 9130 of file stm32g431xx.h.

◆ SAI_xCR1_MCKEN_Pos

#define SAI_xCR1_MCKEN_Pos (27U)

Definition at line 9129 of file stm32g431xx.h.

◆ SAI_xCR1_MODE

#define SAI_xCR1_MODE SAI_xCR1_MODE_Msk

MODE[1:0] bits (Audio Block Mode)

Definition at line 9069 of file stm32g431xx.h.

◆ SAI_xCR1_MODE_0

#define SAI_xCR1_MODE_0 (0x1UL << SAI_xCR1_MODE_Pos)

0x00000001

Definition at line 9070 of file stm32g431xx.h.

◆ SAI_xCR1_MODE_1

#define SAI_xCR1_MODE_1 (0x2UL << SAI_xCR1_MODE_Pos)

0x00000002

Definition at line 9071 of file stm32g431xx.h.

◆ SAI_xCR1_MODE_Msk

#define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos)

0x00000003

Definition at line 9068 of file stm32g431xx.h.

◆ SAI_xCR1_MODE_Pos

#define SAI_xCR1_MODE_Pos (0U)

Definition at line 9067 of file stm32g431xx.h.

◆ SAI_xCR1_MONO

#define SAI_xCR1_MONO SAI_xCR1_MONO_Msk

Mono mode

Definition at line 9101 of file stm32g431xx.h.

◆ SAI_xCR1_MONO_Msk

#define SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos)

0x00001000

Definition at line 9100 of file stm32g431xx.h.

◆ SAI_xCR1_MONO_Pos

#define SAI_xCR1_MONO_Pos (12U)

Definition at line 9099 of file stm32g431xx.h.

◆ SAI_xCR1_NODIV

#define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk

No Divider Configuration

Definition at line 9113 of file stm32g431xx.h.

◆ SAI_xCR1_NODIV_Msk

#define SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos)

0x00080000

Definition at line 9112 of file stm32g431xx.h.

◆ SAI_xCR1_NODIV_Pos

#define SAI_xCR1_NODIV_Pos (19U)

Definition at line 9111 of file stm32g431xx.h.

◆ SAI_xCR1_OSR

#define SAI_xCR1_OSR SAI_xCR1_OSR_Msk

Oversampling ratio for master clock

Definition at line 9127 of file stm32g431xx.h.

◆ SAI_xCR1_OSR_Msk

#define SAI_xCR1_OSR_Msk (0x1UL << SAI_xCR1_OSR_Pos)

0x04000000

Definition at line 9126 of file stm32g431xx.h.

◆ SAI_xCR1_OSR_Pos

#define SAI_xCR1_OSR_Pos (26U)

Definition at line 9125 of file stm32g431xx.h.

◆ SAI_xCR1_OUTDRIV

#define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk

Output Drive

Definition at line 9104 of file stm32g431xx.h.

◆ SAI_xCR1_OUTDRIV_Msk

#define SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos)

0x00002000

Definition at line 9103 of file stm32g431xx.h.

◆ SAI_xCR1_OUTDRIV_Pos

#define SAI_xCR1_OUTDRIV_Pos (13U)

Definition at line 9102 of file stm32g431xx.h.

◆ SAI_xCR1_PRTCFG

#define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk

PRTCFG[1:0] bits (Protocol Configuration)

Definition at line 9075 of file stm32g431xx.h.

◆ SAI_xCR1_PRTCFG_0

#define SAI_xCR1_PRTCFG_0 (0x1UL << SAI_xCR1_PRTCFG_Pos)

0x00000004

Definition at line 9076 of file stm32g431xx.h.

◆ SAI_xCR1_PRTCFG_1

#define SAI_xCR1_PRTCFG_1 (0x2UL << SAI_xCR1_PRTCFG_Pos)

0x00000008

Definition at line 9077 of file stm32g431xx.h.

◆ SAI_xCR1_PRTCFG_Msk

#define SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos)

0x0000000C

Definition at line 9074 of file stm32g431xx.h.

◆ SAI_xCR1_PRTCFG_Pos

#define SAI_xCR1_PRTCFG_Pos (2U)

Definition at line 9073 of file stm32g431xx.h.

◆ SAI_xCR1_SAIEN

#define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk

Audio Block enable

Definition at line 9107 of file stm32g431xx.h.

◆ SAI_xCR1_SAIEN_Msk

#define SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos)

0x00010000

Definition at line 9106 of file stm32g431xx.h.

◆ SAI_xCR1_SAIEN_Pos

#define SAI_xCR1_SAIEN_Pos (16U)

Definition at line 9105 of file stm32g431xx.h.

◆ SAI_xCR1_SYNCEN

#define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk

SYNCEN[1:0](SYNChronization ENable)

Definition at line 9095 of file stm32g431xx.h.

◆ SAI_xCR1_SYNCEN_0

#define SAI_xCR1_SYNCEN_0 (0x1UL << SAI_xCR1_SYNCEN_Pos)

0x00000400

Definition at line 9096 of file stm32g431xx.h.

◆ SAI_xCR1_SYNCEN_1

#define SAI_xCR1_SYNCEN_1 (0x2UL << SAI_xCR1_SYNCEN_Pos)

0x00000800

Definition at line 9097 of file stm32g431xx.h.

◆ SAI_xCR1_SYNCEN_Msk

#define SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos)

0x00000C00

Definition at line 9094 of file stm32g431xx.h.

◆ SAI_xCR1_SYNCEN_Pos

#define SAI_xCR1_SYNCEN_Pos (10U)

Definition at line 9093 of file stm32g431xx.h.

◆ SAI_xCR2_COMP

#define SAI_xCR2_COMP SAI_xCR2_COMP_Msk

COMP[1:0] (Companding mode)

Definition at line 9170 of file stm32g431xx.h.

◆ SAI_xCR2_COMP_0

#define SAI_xCR2_COMP_0 (0x1UL << SAI_xCR2_COMP_Pos)

0x00004000

Definition at line 9171 of file stm32g431xx.h.

◆ SAI_xCR2_COMP_1

#define SAI_xCR2_COMP_1 (0x2UL << SAI_xCR2_COMP_Pos)

0x00008000

Definition at line 9172 of file stm32g431xx.h.

◆ SAI_xCR2_COMP_Msk

#define SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos)

0x0000C000

Definition at line 9169 of file stm32g431xx.h.

◆ SAI_xCR2_COMP_Pos

#define SAI_xCR2_COMP_Pos (14U)

Definition at line 9168 of file stm32g431xx.h.

◆ SAI_xCR2_CPL

#define SAI_xCR2_CPL SAI_xCR2_CPL_Msk

CPL mode

Definition at line 9167 of file stm32g431xx.h.

◆ SAI_xCR2_CPL_Msk

#define SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos)

0x00002000

Definition at line 9166 of file stm32g431xx.h.

◆ SAI_xCR2_CPL_Pos

#define SAI_xCR2_CPL_Pos (13U)

Definition at line 9165 of file stm32g431xx.h.

◆ SAI_xCR2_FFLUSH

#define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk

Fifo FLUSH

Definition at line 9143 of file stm32g431xx.h.

◆ SAI_xCR2_FFLUSH_Msk

#define SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos)

0x00000008

Definition at line 9142 of file stm32g431xx.h.

◆ SAI_xCR2_FFLUSH_Pos

#define SAI_xCR2_FFLUSH_Pos (3U)

Definition at line 9141 of file stm32g431xx.h.

◆ SAI_xCR2_FTH

#define SAI_xCR2_FTH SAI_xCR2_FTH_Msk

FTH[2:0](Fifo THreshold)

Definition at line 9136 of file stm32g431xx.h.

◆ SAI_xCR2_FTH_0

#define SAI_xCR2_FTH_0 (0x1UL << SAI_xCR2_FTH_Pos)

0x00000001

Definition at line 9137 of file stm32g431xx.h.

◆ SAI_xCR2_FTH_1

#define SAI_xCR2_FTH_1 (0x2UL << SAI_xCR2_FTH_Pos)

0x00000002

Definition at line 9138 of file stm32g431xx.h.

◆ SAI_xCR2_FTH_2

#define SAI_xCR2_FTH_2 (0x4UL << SAI_xCR2_FTH_Pos)

0x00000004

Definition at line 9139 of file stm32g431xx.h.

◆ SAI_xCR2_FTH_Msk

#define SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos)

0x00000007

Definition at line 9135 of file stm32g431xx.h.

◆ SAI_xCR2_FTH_Pos

#define SAI_xCR2_FTH_Pos (0U)

Definition at line 9134 of file stm32g431xx.h.

◆ SAI_xCR2_MUTE

#define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk

Mute mode

Definition at line 9149 of file stm32g431xx.h.

◆ SAI_xCR2_MUTE_Msk

#define SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos)

0x00000020

Definition at line 9148 of file stm32g431xx.h.

◆ SAI_xCR2_MUTE_Pos

#define SAI_xCR2_MUTE_Pos (5U)

Definition at line 9147 of file stm32g431xx.h.

◆ SAI_xCR2_MUTECNT

#define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk

MUTECNT[5:0] (MUTE counter)

Definition at line 9157 of file stm32g431xx.h.

◆ SAI_xCR2_MUTECNT_0

#define SAI_xCR2_MUTECNT_0 (0x01UL << SAI_xCR2_MUTECNT_Pos)

0x00000080

Definition at line 9158 of file stm32g431xx.h.

◆ SAI_xCR2_MUTECNT_1

#define SAI_xCR2_MUTECNT_1 (0x02UL << SAI_xCR2_MUTECNT_Pos)

0x00000100

Definition at line 9159 of file stm32g431xx.h.

◆ SAI_xCR2_MUTECNT_2

#define SAI_xCR2_MUTECNT_2 (0x04UL << SAI_xCR2_MUTECNT_Pos)

0x00000200

Definition at line 9160 of file stm32g431xx.h.

◆ SAI_xCR2_MUTECNT_3

#define SAI_xCR2_MUTECNT_3 (0x08UL << SAI_xCR2_MUTECNT_Pos)

0x00000400

Definition at line 9161 of file stm32g431xx.h.

◆ SAI_xCR2_MUTECNT_4

#define SAI_xCR2_MUTECNT_4 (0x10UL << SAI_xCR2_MUTECNT_Pos)

0x00000800

Definition at line 9162 of file stm32g431xx.h.

◆ SAI_xCR2_MUTECNT_5

#define SAI_xCR2_MUTECNT_5 (0x20UL << SAI_xCR2_MUTECNT_Pos)

0x00001000

Definition at line 9163 of file stm32g431xx.h.

◆ SAI_xCR2_MUTECNT_Msk

#define SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos)

0x00001F80

Definition at line 9156 of file stm32g431xx.h.

◆ SAI_xCR2_MUTECNT_Pos

#define SAI_xCR2_MUTECNT_Pos (7U)

Definition at line 9155 of file stm32g431xx.h.

◆ SAI_xCR2_MUTEVAL

#define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk

Muate value

Definition at line 9152 of file stm32g431xx.h.

◆ SAI_xCR2_MUTEVAL_Msk

#define SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos)

0x00000040

Definition at line 9151 of file stm32g431xx.h.

◆ SAI_xCR2_MUTEVAL_Pos

#define SAI_xCR2_MUTEVAL_Pos (6U)

Definition at line 9150 of file stm32g431xx.h.

◆ SAI_xCR2_TRIS

#define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk

TRIState Management on data line

Definition at line 9146 of file stm32g431xx.h.

◆ SAI_xCR2_TRIS_Msk

#define SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos)

0x00000010

Definition at line 9145 of file stm32g431xx.h.

◆ SAI_xCR2_TRIS_Pos

#define SAI_xCR2_TRIS_Pos (4U)

Definition at line 9144 of file stm32g431xx.h.

◆ SAI_xDR_DATA

#define SAI_xDR_DATA SAI_xDR_DATA_Msk

Definition at line 9316 of file stm32g431xx.h.

◆ SAI_xDR_DATA_Msk

#define SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)

0xFFFFFFFF

Definition at line 9315 of file stm32g431xx.h.

◆ SAI_xDR_DATA_Pos

#define SAI_xDR_DATA_Pos (0U)

Definition at line 9314 of file stm32g431xx.h.

◆ SAI_xFRCR_FRL

#define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk

FRL[7:0](Frame length)

Definition at line 9178 of file stm32g431xx.h.

◆ SAI_xFRCR_FRL_0

#define SAI_xFRCR_FRL_0 (0x01UL << SAI_xFRCR_FRL_Pos)

0x00000001

Definition at line 9179 of file stm32g431xx.h.

◆ SAI_xFRCR_FRL_1

#define SAI_xFRCR_FRL_1 (0x02UL << SAI_xFRCR_FRL_Pos)

0x00000002

Definition at line 9180 of file stm32g431xx.h.

◆ SAI_xFRCR_FRL_2

#define SAI_xFRCR_FRL_2 (0x04UL << SAI_xFRCR_FRL_Pos)

0x00000004

Definition at line 9181 of file stm32g431xx.h.

◆ SAI_xFRCR_FRL_3

#define SAI_xFRCR_FRL_3 (0x08UL << SAI_xFRCR_FRL_Pos)

0x00000008

Definition at line 9182 of file stm32g431xx.h.

◆ SAI_xFRCR_FRL_4

#define SAI_xFRCR_FRL_4 (0x10UL << SAI_xFRCR_FRL_Pos)

0x00000010

Definition at line 9183 of file stm32g431xx.h.

◆ SAI_xFRCR_FRL_5

#define SAI_xFRCR_FRL_5 (0x20UL << SAI_xFRCR_FRL_Pos)

0x00000020

Definition at line 9184 of file stm32g431xx.h.

◆ SAI_xFRCR_FRL_6

#define SAI_xFRCR_FRL_6 (0x40UL << SAI_xFRCR_FRL_Pos)

0x00000040

Definition at line 9185 of file stm32g431xx.h.

◆ SAI_xFRCR_FRL_7

#define SAI_xFRCR_FRL_7 (0x80UL << SAI_xFRCR_FRL_Pos)

0x00000080

Definition at line 9186 of file stm32g431xx.h.

◆ SAI_xFRCR_FRL_Msk

#define SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos)

0x000000FF

Definition at line 9177 of file stm32g431xx.h.

◆ SAI_xFRCR_FRL_Pos

#define SAI_xFRCR_FRL_Pos (0U)

Definition at line 9176 of file stm32g431xx.h.

◆ SAI_xFRCR_FSALL

#define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk

FRL[6:0] (Frame synchronization active level length)

Definition at line 9190 of file stm32g431xx.h.

◆ SAI_xFRCR_FSALL_0

#define SAI_xFRCR_FSALL_0 (0x01UL << SAI_xFRCR_FSALL_Pos)

0x00000100

Definition at line 9191 of file stm32g431xx.h.

◆ SAI_xFRCR_FSALL_1

#define SAI_xFRCR_FSALL_1 (0x02UL << SAI_xFRCR_FSALL_Pos)

0x00000200

Definition at line 9192 of file stm32g431xx.h.

◆ SAI_xFRCR_FSALL_2

#define SAI_xFRCR_FSALL_2 (0x04UL << SAI_xFRCR_FSALL_Pos)

0x00000400

Definition at line 9193 of file stm32g431xx.h.

◆ SAI_xFRCR_FSALL_3

#define SAI_xFRCR_FSALL_3 (0x08UL << SAI_xFRCR_FSALL_Pos)

0x00000800

Definition at line 9194 of file stm32g431xx.h.

◆ SAI_xFRCR_FSALL_4

#define SAI_xFRCR_FSALL_4 (0x10UL << SAI_xFRCR_FSALL_Pos)

0x00001000

Definition at line 9195 of file stm32g431xx.h.

◆ SAI_xFRCR_FSALL_5

#define SAI_xFRCR_FSALL_5 (0x20UL << SAI_xFRCR_FSALL_Pos)

0x00002000

Definition at line 9196 of file stm32g431xx.h.

◆ SAI_xFRCR_FSALL_6

#define SAI_xFRCR_FSALL_6 (0x40UL << SAI_xFRCR_FSALL_Pos)

0x00004000

Definition at line 9197 of file stm32g431xx.h.

◆ SAI_xFRCR_FSALL_Msk

#define SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos)

0x00007F00

Definition at line 9189 of file stm32g431xx.h.

◆ SAI_xFRCR_FSALL_Pos

#define SAI_xFRCR_FSALL_Pos (8U)

Definition at line 9188 of file stm32g431xx.h.

◆ SAI_xFRCR_FSDEF

#define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk

Frame Synchronization Definition

Definition at line 9201 of file stm32g431xx.h.

◆ SAI_xFRCR_FSDEF_Msk

#define SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos)

0x00010000

Definition at line 9200 of file stm32g431xx.h.

◆ SAI_xFRCR_FSDEF_Pos

#define SAI_xFRCR_FSDEF_Pos (16U)

Definition at line 9199 of file stm32g431xx.h.

◆ SAI_xFRCR_FSOFF

#define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk

Frame Synchronization OFFset

Definition at line 9207 of file stm32g431xx.h.

◆ SAI_xFRCR_FSOFF_Msk

#define SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos)

0x00040000

Definition at line 9206 of file stm32g431xx.h.

◆ SAI_xFRCR_FSOFF_Pos

#define SAI_xFRCR_FSOFF_Pos (18U)

Definition at line 9205 of file stm32g431xx.h.

◆ SAI_xFRCR_FSPOL

#define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk

Frame Synchronization POLarity

Definition at line 9204 of file stm32g431xx.h.

◆ SAI_xFRCR_FSPOL_Msk

#define SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos)

0x00020000

Definition at line 9203 of file stm32g431xx.h.

◆ SAI_xFRCR_FSPOL_Pos

#define SAI_xFRCR_FSPOL_Pos (17U)

Definition at line 9202 of file stm32g431xx.h.

◆ SAI_xIMR_AFSDETIE

#define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk

Anticipated frame synchronization detection interrupt enable

Definition at line 9255 of file stm32g431xx.h.

◆ SAI_xIMR_AFSDETIE_Msk

#define SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos)

0x00000020

Definition at line 9254 of file stm32g431xx.h.

◆ SAI_xIMR_AFSDETIE_Pos

#define SAI_xIMR_AFSDETIE_Pos (5U)

Definition at line 9253 of file stm32g431xx.h.

◆ SAI_xIMR_CNRDYIE

#define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk

Codec not ready interrupt enable

Definition at line 9252 of file stm32g431xx.h.

◆ SAI_xIMR_CNRDYIE_Msk

#define SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos)

0x00000010

Definition at line 9251 of file stm32g431xx.h.

◆ SAI_xIMR_CNRDYIE_Pos

#define SAI_xIMR_CNRDYIE_Pos (4U)

Definition at line 9250 of file stm32g431xx.h.

◆ SAI_xIMR_FREQIE

#define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk

FIFO request interrupt enable

Definition at line 9249 of file stm32g431xx.h.

◆ SAI_xIMR_FREQIE_Msk

#define SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos)

0x00000008

Definition at line 9248 of file stm32g431xx.h.

◆ SAI_xIMR_FREQIE_Pos

#define SAI_xIMR_FREQIE_Pos (3U)

Definition at line 9247 of file stm32g431xx.h.

◆ SAI_xIMR_LFSDETIE

#define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk

Late frame synchronization detection interrupt enable

Definition at line 9258 of file stm32g431xx.h.

◆ SAI_xIMR_LFSDETIE_Msk

#define SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos)

0x00000040

Definition at line 9257 of file stm32g431xx.h.

◆ SAI_xIMR_LFSDETIE_Pos

#define SAI_xIMR_LFSDETIE_Pos (6U)

Definition at line 9256 of file stm32g431xx.h.

◆ SAI_xIMR_MUTEDETIE

#define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk

Mute detection interrupt enable

Definition at line 9243 of file stm32g431xx.h.

◆ SAI_xIMR_MUTEDETIE_Msk

#define SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos)

0x00000002

Definition at line 9242 of file stm32g431xx.h.

◆ SAI_xIMR_MUTEDETIE_Pos

#define SAI_xIMR_MUTEDETIE_Pos (1U)

Definition at line 9241 of file stm32g431xx.h.

◆ SAI_xIMR_OVRUDRIE

#define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk

Overrun underrun interrupt enable

Definition at line 9240 of file stm32g431xx.h.

◆ SAI_xIMR_OVRUDRIE_Msk

#define SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos)

0x00000001

Definition at line 9239 of file stm32g431xx.h.

◆ SAI_xIMR_OVRUDRIE_Pos

#define SAI_xIMR_OVRUDRIE_Pos (0U)

Definition at line 9238 of file stm32g431xx.h.

◆ SAI_xIMR_WCKCFGIE

#define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk

Wrong Clock Configuration interrupt enable

Definition at line 9246 of file stm32g431xx.h.

◆ SAI_xIMR_WCKCFGIE_Msk

#define SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos)

0x00000004

Definition at line 9245 of file stm32g431xx.h.

◆ SAI_xIMR_WCKCFGIE_Pos

#define SAI_xIMR_WCKCFGIE_Pos (2U)

Definition at line 9244 of file stm32g431xx.h.

◆ SAI_xSLOTR_FBOFF

#define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk

FRL[4:0](First Bit Offset)

Definition at line 9212 of file stm32g431xx.h.

◆ SAI_xSLOTR_FBOFF_0

#define SAI_xSLOTR_FBOFF_0 (0x01UL << SAI_xSLOTR_FBOFF_Pos)

0x00000001

Definition at line 9213 of file stm32g431xx.h.

◆ SAI_xSLOTR_FBOFF_1

#define SAI_xSLOTR_FBOFF_1 (0x02UL << SAI_xSLOTR_FBOFF_Pos)

0x00000002

Definition at line 9214 of file stm32g431xx.h.

◆ SAI_xSLOTR_FBOFF_2

#define SAI_xSLOTR_FBOFF_2 (0x04UL << SAI_xSLOTR_FBOFF_Pos)

0x00000004

Definition at line 9215 of file stm32g431xx.h.

◆ SAI_xSLOTR_FBOFF_3

#define SAI_xSLOTR_FBOFF_3 (0x08UL << SAI_xSLOTR_FBOFF_Pos)

0x00000008

Definition at line 9216 of file stm32g431xx.h.

◆ SAI_xSLOTR_FBOFF_4

#define SAI_xSLOTR_FBOFF_4 (0x10UL << SAI_xSLOTR_FBOFF_Pos)

0x00000010

Definition at line 9217 of file stm32g431xx.h.

◆ SAI_xSLOTR_FBOFF_Msk

#define SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos)

0x0000001F

Definition at line 9211 of file stm32g431xx.h.

◆ SAI_xSLOTR_FBOFF_Pos

#define SAI_xSLOTR_FBOFF_Pos (0U)

Definition at line 9210 of file stm32g431xx.h.

◆ SAI_xSLOTR_NBSLOT

#define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk

NBSLOT[3:0] (Number of Slot in audio Frame)

Definition at line 9227 of file stm32g431xx.h.

◆ SAI_xSLOTR_NBSLOT_0

#define SAI_xSLOTR_NBSLOT_0 (0x1UL << SAI_xSLOTR_NBSLOT_Pos)

0x00000100

Definition at line 9228 of file stm32g431xx.h.

◆ SAI_xSLOTR_NBSLOT_1

#define SAI_xSLOTR_NBSLOT_1 (0x2UL << SAI_xSLOTR_NBSLOT_Pos)

0x00000200

Definition at line 9229 of file stm32g431xx.h.

◆ SAI_xSLOTR_NBSLOT_2

#define SAI_xSLOTR_NBSLOT_2 (0x4UL << SAI_xSLOTR_NBSLOT_Pos)

0x00000400

Definition at line 9230 of file stm32g431xx.h.

◆ SAI_xSLOTR_NBSLOT_3

#define SAI_xSLOTR_NBSLOT_3 (0x8UL << SAI_xSLOTR_NBSLOT_Pos)

0x00000800

Definition at line 9231 of file stm32g431xx.h.

◆ SAI_xSLOTR_NBSLOT_Msk

#define SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos)

0x00000F00

Definition at line 9226 of file stm32g431xx.h.

◆ SAI_xSLOTR_NBSLOT_Pos

#define SAI_xSLOTR_NBSLOT_Pos (8U)

Definition at line 9225 of file stm32g431xx.h.

◆ SAI_xSLOTR_SLOTEN

#define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk

SLOTEN[15:0] (Slot Enable)

Definition at line 9235 of file stm32g431xx.h.

◆ SAI_xSLOTR_SLOTEN_Msk

#define SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)

0xFFFF0000

Definition at line 9234 of file stm32g431xx.h.

◆ SAI_xSLOTR_SLOTEN_Pos

#define SAI_xSLOTR_SLOTEN_Pos (16U)

Definition at line 9233 of file stm32g431xx.h.

◆ SAI_xSLOTR_SLOTSZ

#define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk

SLOTSZ[1:0] (Slot size)

Definition at line 9221 of file stm32g431xx.h.

◆ SAI_xSLOTR_SLOTSZ_0

#define SAI_xSLOTR_SLOTSZ_0 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)

0x00000040

Definition at line 9222 of file stm32g431xx.h.

◆ SAI_xSLOTR_SLOTSZ_1

#define SAI_xSLOTR_SLOTSZ_1 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)

0x00000080

Definition at line 9223 of file stm32g431xx.h.

◆ SAI_xSLOTR_SLOTSZ_Msk

#define SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)

0x000000C0

Definition at line 9220 of file stm32g431xx.h.

◆ SAI_xSLOTR_SLOTSZ_Pos

#define SAI_xSLOTR_SLOTSZ_Pos (6U)

Definition at line 9219 of file stm32g431xx.h.

◆ SAI_xSR_AFSDET

#define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk

Anticipated frame synchronization detection

Definition at line 9278 of file stm32g431xx.h.

◆ SAI_xSR_AFSDET_Msk

#define SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos)

0x00000020

Definition at line 9277 of file stm32g431xx.h.

◆ SAI_xSR_AFSDET_Pos

#define SAI_xSR_AFSDET_Pos (5U)

Definition at line 9276 of file stm32g431xx.h.

◆ SAI_xSR_CNRDY

#define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk

Codec not ready

Definition at line 9275 of file stm32g431xx.h.

◆ SAI_xSR_CNRDY_Msk

#define SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos)

0x00000010

Definition at line 9274 of file stm32g431xx.h.

◆ SAI_xSR_CNRDY_Pos

#define SAI_xSR_CNRDY_Pos (4U)

Definition at line 9273 of file stm32g431xx.h.

◆ SAI_xSR_FLVL

#define SAI_xSR_FLVL SAI_xSR_FLVL_Msk

FLVL[2:0] (FIFO Level Threshold)

Definition at line 9285 of file stm32g431xx.h.

◆ SAI_xSR_FLVL_0

#define SAI_xSR_FLVL_0 (0x1UL << SAI_xSR_FLVL_Pos)

0x00010000

Definition at line 9286 of file stm32g431xx.h.

◆ SAI_xSR_FLVL_1

#define SAI_xSR_FLVL_1 (0x2UL << SAI_xSR_FLVL_Pos)

0x00020000

Definition at line 9287 of file stm32g431xx.h.

◆ SAI_xSR_FLVL_2

#define SAI_xSR_FLVL_2 (0x4UL << SAI_xSR_FLVL_Pos)

0x00040000

Definition at line 9288 of file stm32g431xx.h.

◆ SAI_xSR_FLVL_Msk

#define SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos)

0x00070000

Definition at line 9284 of file stm32g431xx.h.

◆ SAI_xSR_FLVL_Pos

#define SAI_xSR_FLVL_Pos (16U)

Definition at line 9283 of file stm32g431xx.h.

◆ SAI_xSR_FREQ

#define SAI_xSR_FREQ SAI_xSR_FREQ_Msk

FIFO request

Definition at line 9272 of file stm32g431xx.h.

◆ SAI_xSR_FREQ_Msk

#define SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos)

0x00000008

Definition at line 9271 of file stm32g431xx.h.

◆ SAI_xSR_FREQ_Pos

#define SAI_xSR_FREQ_Pos (3U)

Definition at line 9270 of file stm32g431xx.h.

◆ SAI_xSR_LFSDET

#define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk

Late frame synchronization detection

Definition at line 9281 of file stm32g431xx.h.

◆ SAI_xSR_LFSDET_Msk

#define SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos)

0x00000040

Definition at line 9280 of file stm32g431xx.h.

◆ SAI_xSR_LFSDET_Pos

#define SAI_xSR_LFSDET_Pos (6U)

Definition at line 9279 of file stm32g431xx.h.

◆ SAI_xSR_MUTEDET

#define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk

Mute detection

Definition at line 9266 of file stm32g431xx.h.

◆ SAI_xSR_MUTEDET_Msk

#define SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos)

0x00000002

Definition at line 9265 of file stm32g431xx.h.

◆ SAI_xSR_MUTEDET_Pos

#define SAI_xSR_MUTEDET_Pos (1U)

Definition at line 9264 of file stm32g431xx.h.

◆ SAI_xSR_OVRUDR

#define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk

Overrun underrun

Definition at line 9263 of file stm32g431xx.h.

◆ SAI_xSR_OVRUDR_Msk

#define SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos)

0x00000001

Definition at line 9262 of file stm32g431xx.h.

◆ SAI_xSR_OVRUDR_Pos

#define SAI_xSR_OVRUDR_Pos (0U)

Definition at line 9261 of file stm32g431xx.h.

◆ SAI_xSR_WCKCFG

#define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk

Wrong Clock Configuration

Definition at line 9269 of file stm32g431xx.h.

◆ SAI_xSR_WCKCFG_Msk

#define SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos)

0x00000004

Definition at line 9268 of file stm32g431xx.h.

◆ SAI_xSR_WCKCFG_Pos

#define SAI_xSR_WCKCFG_Pos (2U)

Definition at line 9267 of file stm32g431xx.h.

◆ SPI_CR1_BIDIMODE

#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk

Bidirectional data mode enable

Definition at line 9457 of file stm32g431xx.h.

◆ SPI_CR1_BIDIMODE_Msk

#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos)

0x00008000

Definition at line 9456 of file stm32g431xx.h.

◆ SPI_CR1_BIDIMODE_Pos

#define SPI_CR1_BIDIMODE_Pos (15U)

Definition at line 9455 of file stm32g431xx.h.

◆ SPI_CR1_BIDIOE

#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk

Output enable in bidirectional mode

Definition at line 9454 of file stm32g431xx.h.

◆ SPI_CR1_BIDIOE_Msk

#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos)

0x00004000

Definition at line 9453 of file stm32g431xx.h.

◆ SPI_CR1_BIDIOE_Pos

#define SPI_CR1_BIDIOE_Pos (14U)

Definition at line 9452 of file stm32g431xx.h.

◆ SPI_CR1_BR

#define SPI_CR1_BR SPI_CR1_BR_Msk

BR[2:0] bits (Baud Rate Control)

Definition at line 9423 of file stm32g431xx.h.

◆ SPI_CR1_BR_0

#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos)

0x00000008

Definition at line 9424 of file stm32g431xx.h.

◆ SPI_CR1_BR_1

#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos)

0x00000010

Definition at line 9425 of file stm32g431xx.h.

◆ SPI_CR1_BR_2

#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos)

0x00000020

Definition at line 9426 of file stm32g431xx.h.

◆ SPI_CR1_BR_Msk

#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos)

0x00000038

Definition at line 9422 of file stm32g431xx.h.

◆ SPI_CR1_BR_Pos

#define SPI_CR1_BR_Pos (3U)

Definition at line 9421 of file stm32g431xx.h.

◆ SPI_CR1_CPHA

#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk

Clock Phase

Definition at line 9413 of file stm32g431xx.h.

◆ SPI_CR1_CPHA_Msk

#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos)

0x00000001

Definition at line 9412 of file stm32g431xx.h.

◆ SPI_CR1_CPHA_Pos

#define SPI_CR1_CPHA_Pos (0U)

Definition at line 9411 of file stm32g431xx.h.

◆ SPI_CR1_CPOL

#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk

Clock Polarity

Definition at line 9416 of file stm32g431xx.h.

◆ SPI_CR1_CPOL_Msk

#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos)

0x00000002

Definition at line 9415 of file stm32g431xx.h.

◆ SPI_CR1_CPOL_Pos

#define SPI_CR1_CPOL_Pos (1U)

Definition at line 9414 of file stm32g431xx.h.

◆ SPI_CR1_CRCEN

#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk

Hardware CRC calculation enable

Definition at line 9451 of file stm32g431xx.h.

◆ SPI_CR1_CRCEN_Msk

#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos)

0x00002000

Definition at line 9450 of file stm32g431xx.h.

◆ SPI_CR1_CRCEN_Pos

#define SPI_CR1_CRCEN_Pos (13U)

Definition at line 9449 of file stm32g431xx.h.

◆ SPI_CR1_CRCL

#define SPI_CR1_CRCL SPI_CR1_CRCL_Msk

CRC Length

Definition at line 9445 of file stm32g431xx.h.

◆ SPI_CR1_CRCL_Msk

#define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos)

0x00000800

Definition at line 9444 of file stm32g431xx.h.

◆ SPI_CR1_CRCL_Pos

#define SPI_CR1_CRCL_Pos (11U)

Definition at line 9443 of file stm32g431xx.h.

◆ SPI_CR1_CRCNEXT

#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk

Transmit CRC next

Definition at line 9448 of file stm32g431xx.h.

◆ SPI_CR1_CRCNEXT_Msk

#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos)

0x00001000

Definition at line 9447 of file stm32g431xx.h.

◆ SPI_CR1_CRCNEXT_Pos

#define SPI_CR1_CRCNEXT_Pos (12U)

Definition at line 9446 of file stm32g431xx.h.

◆ SPI_CR1_LSBFIRST

#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk

Frame Format

Definition at line 9433 of file stm32g431xx.h.

◆ SPI_CR1_LSBFIRST_Msk

#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos)

0x00000080

Definition at line 9432 of file stm32g431xx.h.

◆ SPI_CR1_LSBFIRST_Pos

#define SPI_CR1_LSBFIRST_Pos (7U)

Definition at line 9431 of file stm32g431xx.h.

◆ SPI_CR1_MSTR

#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk

Master Selection

Definition at line 9419 of file stm32g431xx.h.

◆ SPI_CR1_MSTR_Msk

#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos)

0x00000004

Definition at line 9418 of file stm32g431xx.h.

◆ SPI_CR1_MSTR_Pos

#define SPI_CR1_MSTR_Pos (2U)

Definition at line 9417 of file stm32g431xx.h.

◆ SPI_CR1_RXONLY

#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk

Receive only

Definition at line 9442 of file stm32g431xx.h.

◆ SPI_CR1_RXONLY_Msk

#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos)

0x00000400

Definition at line 9441 of file stm32g431xx.h.

◆ SPI_CR1_RXONLY_Pos

#define SPI_CR1_RXONLY_Pos (10U)

Definition at line 9440 of file stm32g431xx.h.

◆ SPI_CR1_SPE

#define SPI_CR1_SPE SPI_CR1_SPE_Msk

SPI Enable

Definition at line 9430 of file stm32g431xx.h.

◆ SPI_CR1_SPE_Msk

#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos)

0x00000040

Definition at line 9429 of file stm32g431xx.h.

◆ SPI_CR1_SPE_Pos

#define SPI_CR1_SPE_Pos (6U)

Definition at line 9428 of file stm32g431xx.h.

◆ SPI_CR1_SSI

#define SPI_CR1_SSI SPI_CR1_SSI_Msk

Internal slave select

Definition at line 9436 of file stm32g431xx.h.

◆ SPI_CR1_SSI_Msk

#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos)

0x00000100

Definition at line 9435 of file stm32g431xx.h.

◆ SPI_CR1_SSI_Pos

#define SPI_CR1_SSI_Pos (8U)

Definition at line 9434 of file stm32g431xx.h.

◆ SPI_CR1_SSM

#define SPI_CR1_SSM SPI_CR1_SSM_Msk

Software slave management

Definition at line 9439 of file stm32g431xx.h.

◆ SPI_CR1_SSM_Msk

#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos)

0x00000200

Definition at line 9438 of file stm32g431xx.h.

◆ SPI_CR1_SSM_Pos

#define SPI_CR1_SSM_Pos (9U)

Definition at line 9437 of file stm32g431xx.h.

◆ SPI_CR2_DS

#define SPI_CR2_DS SPI_CR2_DS_Msk

DS[3:0] Data Size

Definition at line 9486 of file stm32g431xx.h.

◆ SPI_CR2_DS_0

#define SPI_CR2_DS_0 (0x1UL << SPI_CR2_DS_Pos)

0x00000100

Definition at line 9487 of file stm32g431xx.h.

◆ SPI_CR2_DS_1

#define SPI_CR2_DS_1 (0x2UL << SPI_CR2_DS_Pos)

0x00000200

Definition at line 9488 of file stm32g431xx.h.

◆ SPI_CR2_DS_2

#define SPI_CR2_DS_2 (0x4UL << SPI_CR2_DS_Pos)

0x00000400

Definition at line 9489 of file stm32g431xx.h.

◆ SPI_CR2_DS_3

#define SPI_CR2_DS_3 (0x8UL << SPI_CR2_DS_Pos)

0x00000800

Definition at line 9490 of file stm32g431xx.h.

◆ SPI_CR2_DS_Msk

#define SPI_CR2_DS_Msk (0xFUL << SPI_CR2_DS_Pos)

0x00000F00

Definition at line 9485 of file stm32g431xx.h.

◆ SPI_CR2_DS_Pos

#define SPI_CR2_DS_Pos (8U)

Definition at line 9484 of file stm32g431xx.h.

◆ SPI_CR2_ERRIE

#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk

Error Interrupt Enable

Definition at line 9477 of file stm32g431xx.h.

◆ SPI_CR2_ERRIE_Msk

#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos)

0x00000020

Definition at line 9476 of file stm32g431xx.h.

◆ SPI_CR2_ERRIE_Pos

#define SPI_CR2_ERRIE_Pos (5U)

Definition at line 9475 of file stm32g431xx.h.

◆ SPI_CR2_FRF

#define SPI_CR2_FRF SPI_CR2_FRF_Msk

Frame Format Enable

Definition at line 9474 of file stm32g431xx.h.

◆ SPI_CR2_FRF_Msk

#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos)

0x00000010

Definition at line 9473 of file stm32g431xx.h.

◆ SPI_CR2_FRF_Pos

#define SPI_CR2_FRF_Pos (4U)

Definition at line 9472 of file stm32g431xx.h.

◆ SPI_CR2_FRXTH

#define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk

FIFO reception Threshold

Definition at line 9493 of file stm32g431xx.h.

◆ SPI_CR2_FRXTH_Msk

#define SPI_CR2_FRXTH_Msk (0x1UL << SPI_CR2_FRXTH_Pos)

0x00001000

Definition at line 9492 of file stm32g431xx.h.

◆ SPI_CR2_FRXTH_Pos

#define SPI_CR2_FRXTH_Pos (12U)

Definition at line 9491 of file stm32g431xx.h.

◆ SPI_CR2_LDMARX

#define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk

Last DMA transfer for reception

Definition at line 9496 of file stm32g431xx.h.

◆ SPI_CR2_LDMARX_Msk

#define SPI_CR2_LDMARX_Msk (0x1UL << SPI_CR2_LDMARX_Pos)

0x00002000

Definition at line 9495 of file stm32g431xx.h.

◆ SPI_CR2_LDMARX_Pos

#define SPI_CR2_LDMARX_Pos (13U)

Definition at line 9494 of file stm32g431xx.h.

◆ SPI_CR2_LDMATX

#define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk

Last DMA transfer for transmission

Definition at line 9499 of file stm32g431xx.h.

◆ SPI_CR2_LDMATX_Msk

#define SPI_CR2_LDMATX_Msk (0x1UL << SPI_CR2_LDMATX_Pos)

0x00004000

Definition at line 9498 of file stm32g431xx.h.

◆ SPI_CR2_LDMATX_Pos

#define SPI_CR2_LDMATX_Pos (14U)

Definition at line 9497 of file stm32g431xx.h.

◆ SPI_CR2_NSSP

#define SPI_CR2_NSSP SPI_CR2_NSSP_Msk

NSS pulse management Enable

Definition at line 9471 of file stm32g431xx.h.

◆ SPI_CR2_NSSP_Msk

#define SPI_CR2_NSSP_Msk (0x1UL << SPI_CR2_NSSP_Pos)

0x00000008

Definition at line 9470 of file stm32g431xx.h.

◆ SPI_CR2_NSSP_Pos

#define SPI_CR2_NSSP_Pos (3U)

Definition at line 9469 of file stm32g431xx.h.

◆ SPI_CR2_RXDMAEN

#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk

Rx Buffer DMA Enable

Definition at line 9462 of file stm32g431xx.h.

◆ SPI_CR2_RXDMAEN_Msk

#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos)

0x00000001

Definition at line 9461 of file stm32g431xx.h.

◆ SPI_CR2_RXDMAEN_Pos

#define SPI_CR2_RXDMAEN_Pos (0U)

Definition at line 9460 of file stm32g431xx.h.

◆ SPI_CR2_RXNEIE

#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk

RX buffer Not Empty Interrupt Enable

Definition at line 9480 of file stm32g431xx.h.

◆ SPI_CR2_RXNEIE_Msk

#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos)

0x00000040

Definition at line 9479 of file stm32g431xx.h.

◆ SPI_CR2_RXNEIE_Pos

#define SPI_CR2_RXNEIE_Pos (6U)

Definition at line 9478 of file stm32g431xx.h.

◆ SPI_CR2_SSOE

#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk

SS Output Enable

Definition at line 9468 of file stm32g431xx.h.

◆ SPI_CR2_SSOE_Msk

#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos)

0x00000004

Definition at line 9467 of file stm32g431xx.h.

◆ SPI_CR2_SSOE_Pos

#define SPI_CR2_SSOE_Pos (2U)

Definition at line 9466 of file stm32g431xx.h.

◆ SPI_CR2_TXDMAEN

#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk

Tx Buffer DMA Enable

Definition at line 9465 of file stm32g431xx.h.

◆ SPI_CR2_TXDMAEN_Msk

#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos)

0x00000002

Definition at line 9464 of file stm32g431xx.h.

◆ SPI_CR2_TXDMAEN_Pos

#define SPI_CR2_TXDMAEN_Pos (1U)

Definition at line 9463 of file stm32g431xx.h.

◆ SPI_CR2_TXEIE

#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk

Tx buffer Empty Interrupt Enable

Definition at line 9483 of file stm32g431xx.h.

◆ SPI_CR2_TXEIE_Msk

#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos)

0x00000080

Definition at line 9482 of file stm32g431xx.h.

◆ SPI_CR2_TXEIE_Pos

#define SPI_CR2_TXEIE_Pos (7U)

Definition at line 9481 of file stm32g431xx.h.

◆ SPI_CRCPR_CRCPOLY

#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk

CRC polynomial register

Definition at line 9548 of file stm32g431xx.h.

◆ SPI_CRCPR_CRCPOLY_Msk

#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)

0x0000FFFF

Definition at line 9547 of file stm32g431xx.h.

◆ SPI_CRCPR_CRCPOLY_Pos

#define SPI_CRCPR_CRCPOLY_Pos (0U)

Definition at line 9546 of file stm32g431xx.h.

◆ SPI_DR_DR

#define SPI_DR_DR SPI_DR_DR_Msk

Data Register

Definition at line 9543 of file stm32g431xx.h.

◆ SPI_DR_DR_Msk

#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos)

0x0000FFFF

Definition at line 9542 of file stm32g431xx.h.

◆ SPI_DR_DR_Pos

#define SPI_DR_DR_Pos (0U)

Definition at line 9541 of file stm32g431xx.h.

◆ SPI_I2S_SUPPORT

#define SPI_I2S_SUPPORT

I2S support

Definition at line 9408 of file stm32g431xx.h.

◆ SPI_I2SCFGR_ASTRTEN

#define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk

Asynchronous start enable

Definition at line 9593 of file stm32g431xx.h.

◆ SPI_I2SCFGR_ASTRTEN_Msk

#define SPI_I2SCFGR_ASTRTEN_Msk (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos)

0x00001000

Definition at line 9592 of file stm32g431xx.h.

◆ SPI_I2SCFGR_ASTRTEN_Pos

#define SPI_I2SCFGR_ASTRTEN_Pos (12U)

Definition at line 9591 of file stm32g431xx.h.

◆ SPI_I2SCFGR_CHLEN

#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk

Channel length (number of bits per audio channel)

Definition at line 9563 of file stm32g431xx.h.

◆ SPI_I2SCFGR_CHLEN_Msk

#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos)

0x00000001

Definition at line 9562 of file stm32g431xx.h.

◆ SPI_I2SCFGR_CHLEN_Pos

#define SPI_I2SCFGR_CHLEN_Pos (0U)

Definition at line 9561 of file stm32g431xx.h.

◆ SPI_I2SCFGR_CKPOL

#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk

steady state clock polarity

Definition at line 9571 of file stm32g431xx.h.

◆ SPI_I2SCFGR_CKPOL_Msk

#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos)

0x00000008

Definition at line 9570 of file stm32g431xx.h.

◆ SPI_I2SCFGR_CKPOL_Pos

#define SPI_I2SCFGR_CKPOL_Pos (3U)

Definition at line 9569 of file stm32g431xx.h.

◆ SPI_I2SCFGR_DATLEN

#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk

DATLEN[1:0] bits (Data length to be transferred)

Definition at line 9566 of file stm32g431xx.h.

◆ SPI_I2SCFGR_DATLEN_0

#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos)

0x00000002

Definition at line 9567 of file stm32g431xx.h.

◆ SPI_I2SCFGR_DATLEN_1

#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos)

0x00000004

Definition at line 9568 of file stm32g431xx.h.

◆ SPI_I2SCFGR_DATLEN_Msk

#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos)

0x00000006

Definition at line 9565 of file stm32g431xx.h.

◆ SPI_I2SCFGR_DATLEN_Pos

#define SPI_I2SCFGR_DATLEN_Pos (1U)

Definition at line 9564 of file stm32g431xx.h.

◆ SPI_I2SCFGR_I2SCFG

#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk

I2SCFG[1:0] bits (I2S configuration mode)

Definition at line 9582 of file stm32g431xx.h.

◆ SPI_I2SCFGR_I2SCFG_0

#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)

0x00000100

Definition at line 9583 of file stm32g431xx.h.

◆ SPI_I2SCFGR_I2SCFG_1

#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)

0x00000200

Definition at line 9584 of file stm32g431xx.h.

◆ SPI_I2SCFGR_I2SCFG_Msk

#define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)

0x00000300

Definition at line 9581 of file stm32g431xx.h.

◆ SPI_I2SCFGR_I2SCFG_Pos

#define SPI_I2SCFGR_I2SCFG_Pos (8U)

Definition at line 9580 of file stm32g431xx.h.

◆ SPI_I2SCFGR_I2SE

#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk

I2S Enable

Definition at line 9587 of file stm32g431xx.h.

◆ SPI_I2SCFGR_I2SE_Msk

#define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos)

0x00000400

Definition at line 9586 of file stm32g431xx.h.

◆ SPI_I2SCFGR_I2SE_Pos

#define SPI_I2SCFGR_I2SE_Pos (10U)

Definition at line 9585 of file stm32g431xx.h.

◆ SPI_I2SCFGR_I2SMOD

#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk

I2S mode selection

Definition at line 9590 of file stm32g431xx.h.

◆ SPI_I2SCFGR_I2SMOD_Msk

#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)

0x00000800

Definition at line 9589 of file stm32g431xx.h.

◆ SPI_I2SCFGR_I2SMOD_Pos

#define SPI_I2SCFGR_I2SMOD_Pos (11U)

Definition at line 9588 of file stm32g431xx.h.

◆ SPI_I2SCFGR_I2SSTD

#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk

I2SSTD[1:0] bits (I2S standard selection)

Definition at line 9574 of file stm32g431xx.h.

◆ SPI_I2SCFGR_I2SSTD_0

#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)

0x00000010

Definition at line 9575 of file stm32g431xx.h.

◆ SPI_I2SCFGR_I2SSTD_1

#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)

0x00000020

Definition at line 9576 of file stm32g431xx.h.

◆ SPI_I2SCFGR_I2SSTD_Msk

#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)

0x00000030

Definition at line 9573 of file stm32g431xx.h.

◆ SPI_I2SCFGR_I2SSTD_Pos

#define SPI_I2SCFGR_I2SSTD_Pos (4U)

Definition at line 9572 of file stm32g431xx.h.

◆ SPI_I2SCFGR_PCMSYNC

#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk

PCM frame synchronization

Definition at line 9579 of file stm32g431xx.h.

◆ SPI_I2SCFGR_PCMSYNC_Msk

#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)

0x00000080

Definition at line 9578 of file stm32g431xx.h.

◆ SPI_I2SCFGR_PCMSYNC_Pos

#define SPI_I2SCFGR_PCMSYNC_Pos (7U)

Definition at line 9577 of file stm32g431xx.h.

◆ SPI_I2SPR_I2SDIV

#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk

I2S Linear prescaler

Definition at line 9598 of file stm32g431xx.h.

◆ SPI_I2SPR_I2SDIV_Msk

#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos)

0x000000FF

Definition at line 9597 of file stm32g431xx.h.

◆ SPI_I2SPR_I2SDIV_Pos

#define SPI_I2SPR_I2SDIV_Pos (0U)

Definition at line 9596 of file stm32g431xx.h.

◆ SPI_I2SPR_MCKOE

#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk

Master Clock Output Enable

Definition at line 9604 of file stm32g431xx.h.

◆ SPI_I2SPR_MCKOE_Msk

#define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos)

0x00000200

Definition at line 9603 of file stm32g431xx.h.

◆ SPI_I2SPR_MCKOE_Pos

#define SPI_I2SPR_MCKOE_Pos (9U)

Definition at line 9602 of file stm32g431xx.h.

◆ SPI_I2SPR_ODD

#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk

Odd factor for the prescaler

Definition at line 9601 of file stm32g431xx.h.

◆ SPI_I2SPR_ODD_Msk

#define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos)

0x00000100

Definition at line 9600 of file stm32g431xx.h.

◆ SPI_I2SPR_ODD_Pos

#define SPI_I2SPR_ODD_Pos (8U)

Definition at line 9599 of file stm32g431xx.h.

◆ SPI_RXCRCR_RXCRC

#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk

Rx CRC Register

Definition at line 9553 of file stm32g431xx.h.

◆ SPI_RXCRCR_RXCRC_Msk

#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)

0x0000FFFF

Definition at line 9552 of file stm32g431xx.h.

◆ SPI_RXCRCR_RXCRC_Pos

#define SPI_RXCRCR_RXCRC_Pos (0U)

Definition at line 9551 of file stm32g431xx.h.

◆ SPI_SR_BSY

#define SPI_SR_BSY SPI_SR_BSY_Msk

Busy flag

Definition at line 9525 of file stm32g431xx.h.

◆ SPI_SR_BSY_Msk

#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos)

0x00000080

Definition at line 9524 of file stm32g431xx.h.

◆ SPI_SR_BSY_Pos

#define SPI_SR_BSY_Pos (7U)

Definition at line 9523 of file stm32g431xx.h.

◆ SPI_SR_CHSIDE

#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk

Channel side

Definition at line 9510 of file stm32g431xx.h.

◆ SPI_SR_CHSIDE_Msk

#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos)

0x00000004

Definition at line 9509 of file stm32g431xx.h.

◆ SPI_SR_CHSIDE_Pos

#define SPI_SR_CHSIDE_Pos (2U)

Definition at line 9508 of file stm32g431xx.h.

◆ SPI_SR_CRCERR

#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk

CRC Error flag

Definition at line 9516 of file stm32g431xx.h.

◆ SPI_SR_CRCERR_Msk

#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos)

0x00000010

Definition at line 9515 of file stm32g431xx.h.

◆ SPI_SR_CRCERR_Pos

#define SPI_SR_CRCERR_Pos (4U)

Definition at line 9514 of file stm32g431xx.h.

◆ SPI_SR_FRE

#define SPI_SR_FRE SPI_SR_FRE_Msk

TI frame format error

Definition at line 9528 of file stm32g431xx.h.

◆ SPI_SR_FRE_Msk

#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos)

0x00000100

Definition at line 9527 of file stm32g431xx.h.

◆ SPI_SR_FRE_Pos

#define SPI_SR_FRE_Pos (8U)

Definition at line 9526 of file stm32g431xx.h.

◆ SPI_SR_FRLVL

#define SPI_SR_FRLVL SPI_SR_FRLVL_Msk

FIFO Reception Level

Definition at line 9531 of file stm32g431xx.h.

◆ SPI_SR_FRLVL_0

#define SPI_SR_FRLVL_0 (0x1UL << SPI_SR_FRLVL_Pos)

0x00000200

Definition at line 9532 of file stm32g431xx.h.

◆ SPI_SR_FRLVL_1

#define SPI_SR_FRLVL_1 (0x2UL << SPI_SR_FRLVL_Pos)

0x00000400

Definition at line 9533 of file stm32g431xx.h.

◆ SPI_SR_FRLVL_Msk

#define SPI_SR_FRLVL_Msk (0x3UL << SPI_SR_FRLVL_Pos)

0x00000600

Definition at line 9530 of file stm32g431xx.h.

◆ SPI_SR_FRLVL_Pos

#define SPI_SR_FRLVL_Pos (9U)

Definition at line 9529 of file stm32g431xx.h.

◆ SPI_SR_FTLVL

#define SPI_SR_FTLVL SPI_SR_FTLVL_Msk

FIFO Transmission Level

Definition at line 9536 of file stm32g431xx.h.

◆ SPI_SR_FTLVL_0

#define SPI_SR_FTLVL_0 (0x1UL << SPI_SR_FTLVL_Pos)

0x00000800

Definition at line 9537 of file stm32g431xx.h.

◆ SPI_SR_FTLVL_1

#define SPI_SR_FTLVL_1 (0x2UL << SPI_SR_FTLVL_Pos)

0x00001000

Definition at line 9538 of file stm32g431xx.h.

◆ SPI_SR_FTLVL_Msk

#define SPI_SR_FTLVL_Msk (0x3UL << SPI_SR_FTLVL_Pos)

0x00001800

Definition at line 9535 of file stm32g431xx.h.

◆ SPI_SR_FTLVL_Pos

#define SPI_SR_FTLVL_Pos (11U)

Definition at line 9534 of file stm32g431xx.h.

◆ SPI_SR_MODF

#define SPI_SR_MODF SPI_SR_MODF_Msk

Mode fault

Definition at line 9519 of file stm32g431xx.h.

◆ SPI_SR_MODF_Msk

#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos)

0x00000020

Definition at line 9518 of file stm32g431xx.h.

◆ SPI_SR_MODF_Pos

#define SPI_SR_MODF_Pos (5U)

Definition at line 9517 of file stm32g431xx.h.

◆ SPI_SR_OVR

#define SPI_SR_OVR SPI_SR_OVR_Msk

Overrun flag

Definition at line 9522 of file stm32g431xx.h.

◆ SPI_SR_OVR_Msk

#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos)

0x00000040

Definition at line 9521 of file stm32g431xx.h.

◆ SPI_SR_OVR_Pos

#define SPI_SR_OVR_Pos (6U)

Definition at line 9520 of file stm32g431xx.h.

◆ SPI_SR_RXNE

#define SPI_SR_RXNE SPI_SR_RXNE_Msk

Receive buffer Not Empty

Definition at line 9504 of file stm32g431xx.h.

◆ SPI_SR_RXNE_Msk

#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos)

0x00000001

Definition at line 9503 of file stm32g431xx.h.

◆ SPI_SR_RXNE_Pos

#define SPI_SR_RXNE_Pos (0U)

Definition at line 9502 of file stm32g431xx.h.

◆ SPI_SR_TXE

#define SPI_SR_TXE SPI_SR_TXE_Msk

Transmit buffer Empty

Definition at line 9507 of file stm32g431xx.h.

◆ SPI_SR_TXE_Msk

#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos)

0x00000002

Definition at line 9506 of file stm32g431xx.h.

◆ SPI_SR_TXE_Pos

#define SPI_SR_TXE_Pos (1U)

Definition at line 9505 of file stm32g431xx.h.

◆ SPI_SR_UDR

#define SPI_SR_UDR SPI_SR_UDR_Msk

Underrun flag

Definition at line 9513 of file stm32g431xx.h.

◆ SPI_SR_UDR_Msk

#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos)

0x00000008

Definition at line 9512 of file stm32g431xx.h.

◆ SPI_SR_UDR_Pos

#define SPI_SR_UDR_Pos (3U)

Definition at line 9511 of file stm32g431xx.h.

◆ SPI_TXCRCR_TXCRC

#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk

Tx CRC Register

Definition at line 9558 of file stm32g431xx.h.

◆ SPI_TXCRCR_TXCRC_Msk

#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)

0x0000FFFF

Definition at line 9557 of file stm32g431xx.h.

◆ SPI_TXCRCR_TXCRC_Pos

#define SPI_TXCRCR_TXCRC_Pos (0U)

Definition at line 9556 of file stm32g431xx.h.

◆ SYSCFG_CFGR1_ANASWVDD

#define SYSCFG_CFGR1_ANASWVDD SYSCFG_CFGR1_ANASWVDD_Msk

GPIO analog switch control voltage selection

Definition at line 9629 of file stm32g431xx.h.

◆ SYSCFG_CFGR1_ANASWVDD_Msk

#define SYSCFG_CFGR1_ANASWVDD_Msk (0x1UL << SYSCFG_CFGR1_ANASWVDD_Pos)

0x00000200

Definition at line 9628 of file stm32g431xx.h.

◆ SYSCFG_CFGR1_ANASWVDD_Pos

#define SYSCFG_CFGR1_ANASWVDD_Pos (9U)

Definition at line 9627 of file stm32g431xx.h.

◆ SYSCFG_CFGR1_BOOSTEN

#define SYSCFG_CFGR1_BOOSTEN SYSCFG_CFGR1_BOOSTEN_Msk

I/O analog switch voltage booster enable

Definition at line 9626 of file stm32g431xx.h.

◆ SYSCFG_CFGR1_BOOSTEN_Msk

#define SYSCFG_CFGR1_BOOSTEN_Msk (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos)

0x00000100

Definition at line 9625 of file stm32g431xx.h.

◆ SYSCFG_CFGR1_BOOSTEN_Pos

#define SYSCFG_CFGR1_BOOSTEN_Pos (8U)

Definition at line 9624 of file stm32g431xx.h.

◆ SYSCFG_CFGR1_FPU_IE_0

#define SYSCFG_CFGR1_FPU_IE_0 (0x04000000U)

Invalid operation Interrupt enable

Definition at line 9651 of file stm32g431xx.h.

◆ SYSCFG_CFGR1_FPU_IE_1

#define SYSCFG_CFGR1_FPU_IE_1 (0x08000000U)

Divide-by-zero Interrupt enable

Definition at line 9652 of file stm32g431xx.h.

◆ SYSCFG_CFGR1_FPU_IE_2

#define SYSCFG_CFGR1_FPU_IE_2 (0x10000000U)

Underflow Interrupt enable

Definition at line 9653 of file stm32g431xx.h.

◆ SYSCFG_CFGR1_FPU_IE_3

#define SYSCFG_CFGR1_FPU_IE_3 (0x20000000U)

Overflow Interrupt enable

Definition at line 9654 of file stm32g431xx.h.

◆ SYSCFG_CFGR1_FPU_IE_4

#define SYSCFG_CFGR1_FPU_IE_4 (0x40000000U)

Input denormal Interrupt enable

Definition at line 9655 of file stm32g431xx.h.

◆ SYSCFG_CFGR1_FPU_IE_5

#define SYSCFG_CFGR1_FPU_IE_5 (0x80000000U)

Inexact Interrupt enable (interrupt disabled at reset)

Definition at line 9656 of file stm32g431xx.h.

◆ SYSCFG_CFGR1_I2C1_FMP

#define SYSCFG_CFGR1_I2C1_FMP SYSCFG_CFGR1_I2C1_FMP_Msk

I2C1 Fast mode plus

Definition at line 9644 of file stm32g431xx.h.

◆ SYSCFG_CFGR1_I2C1_FMP_Msk

#define SYSCFG_CFGR1_I2C1_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos)

0x00100000

Definition at line 9643 of file stm32g431xx.h.

◆ SYSCFG_CFGR1_I2C1_FMP_Pos

#define SYSCFG_CFGR1_I2C1_FMP_Pos (20U)

Definition at line 9642 of file stm32g431xx.h.

◆ SYSCFG_CFGR1_I2C2_FMP

#define SYSCFG_CFGR1_I2C2_FMP SYSCFG_CFGR1_I2C2_FMP_Msk

I2C2 Fast mode plus

Definition at line 9647 of file stm32g431xx.h.

◆ SYSCFG_CFGR1_I2C2_FMP_Msk

#define SYSCFG_CFGR1_I2C2_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C2_FMP_Pos)

0x00200000

Definition at line 9646 of file stm32g431xx.h.

◆ SYSCFG_CFGR1_I2C2_FMP_Pos

#define SYSCFG_CFGR1_I2C2_FMP_Pos (21U)

Definition at line 9645 of file stm32g431xx.h.

◆ SYSCFG_CFGR1_I2C3_FMP

#define SYSCFG_CFGR1_I2C3_FMP SYSCFG_CFGR1_I2C3_FMP_Msk

I2C3 Fast mode plus

Definition at line 9650 of file stm32g431xx.h.

◆ SYSCFG_CFGR1_I2C3_FMP_Msk

#define SYSCFG_CFGR1_I2C3_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C3_FMP_Pos)

0x00400000

Definition at line 9649 of file stm32g431xx.h.

◆ SYSCFG_CFGR1_I2C3_FMP_Pos

#define SYSCFG_CFGR1_I2C3_FMP_Pos (22U)

Definition at line 9648 of file stm32g431xx.h.

◆ SYSCFG_CFGR1_I2C_PB6_FMP

#define SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk

I2C PB6 Fast mode plus

Definition at line 9632 of file stm32g431xx.h.

◆ SYSCFG_CFGR1_I2C_PB6_FMP_Msk

#define SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos)

0x00010000

Definition at line 9631 of file stm32g431xx.h.

◆ SYSCFG_CFGR1_I2C_PB6_FMP_Pos

#define SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U)

Definition at line 9630 of file stm32g431xx.h.

◆ SYSCFG_CFGR1_I2C_PB7_FMP

#define SYSCFG_CFGR1_I2C_PB7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk

I2C PB7 Fast mode plus

Definition at line 9635 of file stm32g431xx.h.

◆ SYSCFG_CFGR1_I2C_PB7_FMP_Msk

#define SYSCFG_CFGR1_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos)

0x00020000

Definition at line 9634 of file stm32g431xx.h.

◆ SYSCFG_CFGR1_I2C_PB7_FMP_Pos

#define SYSCFG_CFGR1_I2C_PB7_FMP_Pos (17U)

Definition at line 9633 of file stm32g431xx.h.

◆ SYSCFG_CFGR1_I2C_PB8_FMP

#define SYSCFG_CFGR1_I2C_PB8_FMP SYSCFG_CFGR1_I2C_PB8_FMP_Msk

I2C PB8 Fast mode plus

Definition at line 9638 of file stm32g431xx.h.

◆ SYSCFG_CFGR1_I2C_PB8_FMP_Msk

#define SYSCFG_CFGR1_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos)

0x00040000

Definition at line 9637 of file stm32g431xx.h.

◆ SYSCFG_CFGR1_I2C_PB8_FMP_Pos

#define SYSCFG_CFGR1_I2C_PB8_FMP_Pos (18U)

Definition at line 9636 of file stm32g431xx.h.

◆ SYSCFG_CFGR1_I2C_PB9_FMP

#define SYSCFG_CFGR1_I2C_PB9_FMP SYSCFG_CFGR1_I2C_PB9_FMP_Msk

I2C PB9 Fast mode plus

Definition at line 9641 of file stm32g431xx.h.

◆ SYSCFG_CFGR1_I2C_PB9_FMP_Msk

#define SYSCFG_CFGR1_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos)

0x00080000

Definition at line 9640 of file stm32g431xx.h.

◆ SYSCFG_CFGR1_I2C_PB9_FMP_Pos

#define SYSCFG_CFGR1_I2C_PB9_FMP_Pos (19U)

Definition at line 9639 of file stm32g431xx.h.

◆ SYSCFG_CFGR2_CLL

#define SYSCFG_CFGR2_CLL SYSCFG_CFGR2_CLL_Msk

Core Lockup Lock

Definition at line 9895 of file stm32g431xx.h.

◆ SYSCFG_CFGR2_CLL_Msk

#define SYSCFG_CFGR2_CLL_Msk (0x1UL << SYSCFG_CFGR2_CLL_Pos)

0x00000001

Definition at line 9894 of file stm32g431xx.h.

◆ SYSCFG_CFGR2_CLL_Pos

#define SYSCFG_CFGR2_CLL_Pos (0U)

Definition at line 9893 of file stm32g431xx.h.

◆ SYSCFG_CFGR2_ECCL

#define SYSCFG_CFGR2_ECCL SYSCFG_CFGR2_ECCL_Msk

ECC Lock

Definition at line 9904 of file stm32g431xx.h.

◆ SYSCFG_CFGR2_ECCL_Msk

#define SYSCFG_CFGR2_ECCL_Msk (0x1UL << SYSCFG_CFGR2_ECCL_Pos)

0x00000008

Definition at line 9903 of file stm32g431xx.h.

◆ SYSCFG_CFGR2_ECCL_Pos

#define SYSCFG_CFGR2_ECCL_Pos (3U)

Definition at line 9902 of file stm32g431xx.h.

◆ SYSCFG_CFGR2_PVDL

#define SYSCFG_CFGR2_PVDL SYSCFG_CFGR2_PVDL_Msk

PVD Lock

Definition at line 9901 of file stm32g431xx.h.

◆ SYSCFG_CFGR2_PVDL_Msk

#define SYSCFG_CFGR2_PVDL_Msk (0x1UL << SYSCFG_CFGR2_PVDL_Pos)

0x00000004

Definition at line 9900 of file stm32g431xx.h.

◆ SYSCFG_CFGR2_PVDL_Pos

#define SYSCFG_CFGR2_PVDL_Pos (2U)

Definition at line 9899 of file stm32g431xx.h.

◆ SYSCFG_CFGR2_SPF

#define SYSCFG_CFGR2_SPF SYSCFG_CFGR2_SPF_Msk

SRAM Parity Flag

Definition at line 9907 of file stm32g431xx.h.

◆ SYSCFG_CFGR2_SPF_Msk

#define SYSCFG_CFGR2_SPF_Msk (0x1UL << SYSCFG_CFGR2_SPF_Pos)

0x00000100

Definition at line 9906 of file stm32g431xx.h.

◆ SYSCFG_CFGR2_SPF_Pos

#define SYSCFG_CFGR2_SPF_Pos (8U)

Definition at line 9905 of file stm32g431xx.h.

◆ SYSCFG_CFGR2_SPL

#define SYSCFG_CFGR2_SPL SYSCFG_CFGR2_SPL_Msk

SRAM Parity Lock

Definition at line 9898 of file stm32g431xx.h.

◆ SYSCFG_CFGR2_SPL_Msk

#define SYSCFG_CFGR2_SPL_Msk (0x1UL << SYSCFG_CFGR2_SPL_Pos)

0x00000002

Definition at line 9897 of file stm32g431xx.h.

◆ SYSCFG_CFGR2_SPL_Pos

#define SYSCFG_CFGR2_SPL_Pos (1U)

Definition at line 9896 of file stm32g431xx.h.

◆ SYSCFG_EXTICR1_EXTI0

#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk

EXTI 0 configuration

Definition at line 9661 of file stm32g431xx.h.

◆ SYSCFG_EXTICR1_EXTI0_Msk

#define SYSCFG_EXTICR1_EXTI0_Msk (0x7UL << SYSCFG_EXTICR1_EXTI0_Pos)

0x0000000F

Definition at line 9660 of file stm32g431xx.h.

◆ SYSCFG_EXTICR1_EXTI0_PA

#define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U)

EXTI0 configuration.

PA[0] pin

Definition at line 9675 of file stm32g431xx.h.

◆ SYSCFG_EXTICR1_EXTI0_PB

#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U)

PB[0] pin

Definition at line 9676 of file stm32g431xx.h.

◆ SYSCFG_EXTICR1_EXTI0_PC

#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U)

PC[0] pin

Definition at line 9677 of file stm32g431xx.h.

◆ SYSCFG_EXTICR1_EXTI0_PD

#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U)

PD[0] pin

Definition at line 9678 of file stm32g431xx.h.

◆ SYSCFG_EXTICR1_EXTI0_PE

#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U)

PE[0] pin

Definition at line 9679 of file stm32g431xx.h.

◆ SYSCFG_EXTICR1_EXTI0_PF

#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U)

PF[0] pin

Definition at line 9680 of file stm32g431xx.h.

◆ SYSCFG_EXTICR1_EXTI0_PG

#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U)

PG[0] pin

Definition at line 9681 of file stm32g431xx.h.

◆ SYSCFG_EXTICR1_EXTI0_Pos

#define SYSCFG_EXTICR1_EXTI0_Pos (0U)

Definition at line 9659 of file stm32g431xx.h.

◆ SYSCFG_EXTICR1_EXTI1

#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk

EXTI 1 configuration

Definition at line 9664 of file stm32g431xx.h.

◆ SYSCFG_EXTICR1_EXTI1_Msk

#define SYSCFG_EXTICR1_EXTI1_Msk (0x7UL << SYSCFG_EXTICR1_EXTI1_Pos)

0x000000F0

Definition at line 9663 of file stm32g431xx.h.

◆ SYSCFG_EXTICR1_EXTI1_PA

#define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U)

EXTI1 configuration.

PA[1] pin

Definition at line 9686 of file stm32g431xx.h.

◆ SYSCFG_EXTICR1_EXTI1_PB

#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U)

PB[1] pin

Definition at line 9687 of file stm32g431xx.h.

◆ SYSCFG_EXTICR1_EXTI1_PC

#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U)

PC[1] pin

Definition at line 9688 of file stm32g431xx.h.

◆ SYSCFG_EXTICR1_EXTI1_PD

#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U)

PD[1] pin

Definition at line 9689 of file stm32g431xx.h.

◆ SYSCFG_EXTICR1_EXTI1_PE

#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U)

PE[1] pin

Definition at line 9690 of file stm32g431xx.h.

◆ SYSCFG_EXTICR1_EXTI1_PF

#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U)

PF[1] pin

Definition at line 9691 of file stm32g431xx.h.

◆ SYSCFG_EXTICR1_EXTI1_PG

#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U)

PG[1] pin

Definition at line 9692 of file stm32g431xx.h.

◆ SYSCFG_EXTICR1_EXTI1_Pos

#define SYSCFG_EXTICR1_EXTI1_Pos (4U)

Definition at line 9662 of file stm32g431xx.h.

◆ SYSCFG_EXTICR1_EXTI2

#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk

EXTI 2 configuration

Definition at line 9667 of file stm32g431xx.h.

◆ SYSCFG_EXTICR1_EXTI2_Msk

#define SYSCFG_EXTICR1_EXTI2_Msk (0x7UL << SYSCFG_EXTICR1_EXTI2_Pos)

0x00000F00

Definition at line 9666 of file stm32g431xx.h.

◆ SYSCFG_EXTICR1_EXTI2_PA

#define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U)

EXTI2 configuration.

PA[2] pin

Definition at line 9697 of file stm32g431xx.h.

◆ SYSCFG_EXTICR1_EXTI2_PB

#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U)

PB[2] pin

Definition at line 9698 of file stm32g431xx.h.

◆ SYSCFG_EXTICR1_EXTI2_PC

#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U)

PC[2] pin

Definition at line 9699 of file stm32g431xx.h.

◆ SYSCFG_EXTICR1_EXTI2_PD

#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U)

PD[2] pin

Definition at line 9700 of file stm32g431xx.h.

◆ SYSCFG_EXTICR1_EXTI2_PE

#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U)

PE[2] pin

Definition at line 9701 of file stm32g431xx.h.

◆ SYSCFG_EXTICR1_EXTI2_PF

#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U)

PF[2] pin

Definition at line 9702 of file stm32g431xx.h.

◆ SYSCFG_EXTICR1_EXTI2_PG

#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U)

PG[2] pin

Definition at line 9703 of file stm32g431xx.h.

◆ SYSCFG_EXTICR1_EXTI2_Pos

#define SYSCFG_EXTICR1_EXTI2_Pos (8U)

Definition at line 9665 of file stm32g431xx.h.

◆ SYSCFG_EXTICR1_EXTI3

#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk

EXTI 3 configuration

Definition at line 9670 of file stm32g431xx.h.

◆ SYSCFG_EXTICR1_EXTI3_Msk

#define SYSCFG_EXTICR1_EXTI3_Msk (0x7UL << SYSCFG_EXTICR1_EXTI3_Pos)

0x0000F000

Definition at line 9669 of file stm32g431xx.h.

◆ SYSCFG_EXTICR1_EXTI3_PA

#define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U)

EXTI3 configuration.

PA[3] pin

Definition at line 9708 of file stm32g431xx.h.

◆ SYSCFG_EXTICR1_EXTI3_PB

#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U)

PB[3] pin

Definition at line 9709 of file stm32g431xx.h.

◆ SYSCFG_EXTICR1_EXTI3_PC

#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U)

PC[3] pin

Definition at line 9710 of file stm32g431xx.h.

◆ SYSCFG_EXTICR1_EXTI3_PD

#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U)

PD[3] pin

Definition at line 9711 of file stm32g431xx.h.

◆ SYSCFG_EXTICR1_EXTI3_PE

#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U)

PE[3] pin

Definition at line 9712 of file stm32g431xx.h.

◆ SYSCFG_EXTICR1_EXTI3_PF

#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U)

PF[3] pin

Definition at line 9713 of file stm32g431xx.h.

◆ SYSCFG_EXTICR1_EXTI3_PG

#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U)

PG[3] pin

Definition at line 9714 of file stm32g431xx.h.

◆ SYSCFG_EXTICR1_EXTI3_Pos

#define SYSCFG_EXTICR1_EXTI3_Pos (12U)

Definition at line 9668 of file stm32g431xx.h.

◆ SYSCFG_EXTICR2_EXTI4

#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk

EXTI 4 configuration

Definition at line 9719 of file stm32g431xx.h.

◆ SYSCFG_EXTICR2_EXTI4_Msk

#define SYSCFG_EXTICR2_EXTI4_Msk (0x7UL << SYSCFG_EXTICR2_EXTI4_Pos)

0x0000000F

Definition at line 9718 of file stm32g431xx.h.

◆ SYSCFG_EXTICR2_EXTI4_PA

#define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U)

EXTI4 configuration.

PA[4] pin

Definition at line 9733 of file stm32g431xx.h.

◆ SYSCFG_EXTICR2_EXTI4_PB

#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U)

PB[4] pin

Definition at line 9734 of file stm32g431xx.h.

◆ SYSCFG_EXTICR2_EXTI4_PC

#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U)

PC[4] pin

Definition at line 9735 of file stm32g431xx.h.

◆ SYSCFG_EXTICR2_EXTI4_PD

#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U)

PD[4] pin

Definition at line 9736 of file stm32g431xx.h.

◆ SYSCFG_EXTICR2_EXTI4_PE

#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U)

PE[4] pin

Definition at line 9737 of file stm32g431xx.h.

◆ SYSCFG_EXTICR2_EXTI4_PF

#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U)

PF[4] pin

Definition at line 9738 of file stm32g431xx.h.

◆ SYSCFG_EXTICR2_EXTI4_PG

#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U)

PG[4] pin

Definition at line 9739 of file stm32g431xx.h.

◆ SYSCFG_EXTICR2_EXTI4_Pos

#define SYSCFG_EXTICR2_EXTI4_Pos (0U)

Definition at line 9717 of file stm32g431xx.h.

◆ SYSCFG_EXTICR2_EXTI5

#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk

EXTI 5 configuration

Definition at line 9722 of file stm32g431xx.h.

◆ SYSCFG_EXTICR2_EXTI5_Msk

#define SYSCFG_EXTICR2_EXTI5_Msk (0x7UL << SYSCFG_EXTICR2_EXTI5_Pos)

0x000000F0

Definition at line 9721 of file stm32g431xx.h.

◆ SYSCFG_EXTICR2_EXTI5_PA

#define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U)

EXTI5 configuration.

PA[5] pin

Definition at line 9744 of file stm32g431xx.h.

◆ SYSCFG_EXTICR2_EXTI5_PB

#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U)

PB[5] pin

Definition at line 9745 of file stm32g431xx.h.

◆ SYSCFG_EXTICR2_EXTI5_PC

#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U)

PC[5] pin

Definition at line 9746 of file stm32g431xx.h.

◆ SYSCFG_EXTICR2_EXTI5_PD

#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U)

PD[5] pin

Definition at line 9747 of file stm32g431xx.h.

◆ SYSCFG_EXTICR2_EXTI5_PE

#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U)

PE[5] pin

Definition at line 9748 of file stm32g431xx.h.

◆ SYSCFG_EXTICR2_EXTI5_PF

#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U)

PF[5] pin

Definition at line 9749 of file stm32g431xx.h.

◆ SYSCFG_EXTICR2_EXTI5_PG

#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U)

PG[5] pin

Definition at line 9750 of file stm32g431xx.h.

◆ SYSCFG_EXTICR2_EXTI5_Pos

#define SYSCFG_EXTICR2_EXTI5_Pos (4U)

Definition at line 9720 of file stm32g431xx.h.

◆ SYSCFG_EXTICR2_EXTI6

#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk

EXTI 6 configuration

Definition at line 9725 of file stm32g431xx.h.

◆ SYSCFG_EXTICR2_EXTI6_Msk

#define SYSCFG_EXTICR2_EXTI6_Msk (0x7UL << SYSCFG_EXTICR2_EXTI6_Pos)

0x00000F00

Definition at line 9724 of file stm32g431xx.h.

◆ SYSCFG_EXTICR2_EXTI6_PA

#define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U)

EXTI6 configuration.

PA[6] pin

Definition at line 9755 of file stm32g431xx.h.

◆ SYSCFG_EXTICR2_EXTI6_PB

#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U)

PB[6] pin

Definition at line 9756 of file stm32g431xx.h.

◆ SYSCFG_EXTICR2_EXTI6_PC

#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U)

PC[6] pin

Definition at line 9757 of file stm32g431xx.h.

◆ SYSCFG_EXTICR2_EXTI6_PD

#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U)

PD[6] pin

Definition at line 9758 of file stm32g431xx.h.

◆ SYSCFG_EXTICR2_EXTI6_PE

#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U)

PE[6] pin

Definition at line 9759 of file stm32g431xx.h.

◆ SYSCFG_EXTICR2_EXTI6_PF

#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U)

PF[6] pin

Definition at line 9760 of file stm32g431xx.h.

◆ SYSCFG_EXTICR2_EXTI6_PG

#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U)

PG[6] pin

Definition at line 9761 of file stm32g431xx.h.

◆ SYSCFG_EXTICR2_EXTI6_Pos

#define SYSCFG_EXTICR2_EXTI6_Pos (8U)

Definition at line 9723 of file stm32g431xx.h.

◆ SYSCFG_EXTICR2_EXTI7

#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk

EXTI 7 configuration

Definition at line 9728 of file stm32g431xx.h.

◆ SYSCFG_EXTICR2_EXTI7_Msk

#define SYSCFG_EXTICR2_EXTI7_Msk (0x7UL << SYSCFG_EXTICR2_EXTI7_Pos)

0x0000F000

Definition at line 9727 of file stm32g431xx.h.

◆ SYSCFG_EXTICR2_EXTI7_PA

#define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U)

EXTI7 configuration.

PA[7] pin

Definition at line 9766 of file stm32g431xx.h.

◆ SYSCFG_EXTICR2_EXTI7_PB

#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U)

PB[7] pin

Definition at line 9767 of file stm32g431xx.h.

◆ SYSCFG_EXTICR2_EXTI7_PC

#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U)

PC[7] pin

Definition at line 9768 of file stm32g431xx.h.

◆ SYSCFG_EXTICR2_EXTI7_PD

#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U)

PD[7] pin

Definition at line 9769 of file stm32g431xx.h.

◆ SYSCFG_EXTICR2_EXTI7_PE

#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U)

PE[7] pin

Definition at line 9770 of file stm32g431xx.h.

◆ SYSCFG_EXTICR2_EXTI7_PF

#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U)

PF[7] pin

Definition at line 9771 of file stm32g431xx.h.

◆ SYSCFG_EXTICR2_EXTI7_PG

#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U)

PG[7] pin

Definition at line 9772 of file stm32g431xx.h.

◆ SYSCFG_EXTICR2_EXTI7_Pos

#define SYSCFG_EXTICR2_EXTI7_Pos (12U)

Definition at line 9726 of file stm32g431xx.h.

◆ SYSCFG_EXTICR3_EXTI10

#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk

EXTI 10 configuration

Definition at line 9783 of file stm32g431xx.h.

◆ SYSCFG_EXTICR3_EXTI10_Msk

#define SYSCFG_EXTICR3_EXTI10_Msk (0x7UL << SYSCFG_EXTICR3_EXTI10_Pos)

0x00000F00

Definition at line 9782 of file stm32g431xx.h.

◆ SYSCFG_EXTICR3_EXTI10_PA

#define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U)

EXTI10 configuration.

PA[10] pin

Definition at line 9813 of file stm32g431xx.h.

◆ SYSCFG_EXTICR3_EXTI10_PB

#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U)

PB[10] pin

Definition at line 9814 of file stm32g431xx.h.

◆ SYSCFG_EXTICR3_EXTI10_PC

#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U)

PC[10] pin

Definition at line 9815 of file stm32g431xx.h.

◆ SYSCFG_EXTICR3_EXTI10_PD

#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U)

PD[10] pin

Definition at line 9816 of file stm32g431xx.h.

◆ SYSCFG_EXTICR3_EXTI10_PE

#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U)

PE[10] pin

Definition at line 9817 of file stm32g431xx.h.

◆ SYSCFG_EXTICR3_EXTI10_PF

#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U)

PF[10] pin

Definition at line 9818 of file stm32g431xx.h.

◆ SYSCFG_EXTICR3_EXTI10_Pos

#define SYSCFG_EXTICR3_EXTI10_Pos (8U)

Definition at line 9781 of file stm32g431xx.h.

◆ SYSCFG_EXTICR3_EXTI11

#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk

EXTI 11 configuration

Definition at line 9786 of file stm32g431xx.h.

◆ SYSCFG_EXTICR3_EXTI11_Msk

#define SYSCFG_EXTICR3_EXTI11_Msk (0x7UL << SYSCFG_EXTICR3_EXTI11_Pos)

0x0000F000

Definition at line 9785 of file stm32g431xx.h.

◆ SYSCFG_EXTICR3_EXTI11_PA

#define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U)

EXTI11 configuration.

PA[11] pin

Definition at line 9823 of file stm32g431xx.h.

◆ SYSCFG_EXTICR3_EXTI11_PB

#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U)

PB[11] pin

Definition at line 9824 of file stm32g431xx.h.

◆ SYSCFG_EXTICR3_EXTI11_PC

#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U)

PC[11] pin

Definition at line 9825 of file stm32g431xx.h.

◆ SYSCFG_EXTICR3_EXTI11_PD

#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U)

PD[11] pin

Definition at line 9826 of file stm32g431xx.h.

◆ SYSCFG_EXTICR3_EXTI11_PE

#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U)

PE[11] pin

Definition at line 9827 of file stm32g431xx.h.

◆ SYSCFG_EXTICR3_EXTI11_PF

#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U)

PF[11] pin

Definition at line 9828 of file stm32g431xx.h.

◆ SYSCFG_EXTICR3_EXTI11_Pos

#define SYSCFG_EXTICR3_EXTI11_Pos (12U)

Definition at line 9784 of file stm32g431xx.h.

◆ SYSCFG_EXTICR3_EXTI8

#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk

EXTI 8 configuration

Definition at line 9777 of file stm32g431xx.h.

◆ SYSCFG_EXTICR3_EXTI8_Msk

#define SYSCFG_EXTICR3_EXTI8_Msk (0x7UL << SYSCFG_EXTICR3_EXTI8_Pos)

0x0000000F

Definition at line 9776 of file stm32g431xx.h.

◆ SYSCFG_EXTICR3_EXTI8_PA

#define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U)

EXTI8 configuration.

PA[8] pin

Definition at line 9791 of file stm32g431xx.h.

◆ SYSCFG_EXTICR3_EXTI8_PB

#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U)

PB[8] pin

Definition at line 9792 of file stm32g431xx.h.

◆ SYSCFG_EXTICR3_EXTI8_PC

#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U)

PC[8] pin

Definition at line 9793 of file stm32g431xx.h.

◆ SYSCFG_EXTICR3_EXTI8_PD

#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U)

PD[8] pin

Definition at line 9794 of file stm32g431xx.h.

◆ SYSCFG_EXTICR3_EXTI8_PE

#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U)

PE[8] pin

Definition at line 9795 of file stm32g431xx.h.

◆ SYSCFG_EXTICR3_EXTI8_PF

#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U)

PF[8] pin

Definition at line 9796 of file stm32g431xx.h.

◆ SYSCFG_EXTICR3_EXTI8_PG

#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U)

PG[8] pin

Definition at line 9797 of file stm32g431xx.h.

◆ SYSCFG_EXTICR3_EXTI8_Pos

#define SYSCFG_EXTICR3_EXTI8_Pos (0U)

Definition at line 9775 of file stm32g431xx.h.

◆ SYSCFG_EXTICR3_EXTI9

#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk

EXTI 9 configuration

Definition at line 9780 of file stm32g431xx.h.

◆ SYSCFG_EXTICR3_EXTI9_Msk

#define SYSCFG_EXTICR3_EXTI9_Msk (0x7UL << SYSCFG_EXTICR3_EXTI9_Pos)

0x000000F0

Definition at line 9779 of file stm32g431xx.h.

◆ SYSCFG_EXTICR3_EXTI9_PA

#define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U)

EXTI9 configuration.

PA[9] pin

Definition at line 9802 of file stm32g431xx.h.

◆ SYSCFG_EXTICR3_EXTI9_PB

#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U)

PB[9] pin

Definition at line 9803 of file stm32g431xx.h.

◆ SYSCFG_EXTICR3_EXTI9_PC

#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U)

PC[9] pin

Definition at line 9804 of file stm32g431xx.h.

◆ SYSCFG_EXTICR3_EXTI9_PD

#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U)

PD[9] pin

Definition at line 9805 of file stm32g431xx.h.

◆ SYSCFG_EXTICR3_EXTI9_PE

#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U)

PE[9] pin

Definition at line 9806 of file stm32g431xx.h.

◆ SYSCFG_EXTICR3_EXTI9_PF

#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U)

PF[9] pin

Definition at line 9807 of file stm32g431xx.h.

◆ SYSCFG_EXTICR3_EXTI9_PG

#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U)

PG[9] pin

Definition at line 9808 of file stm32g431xx.h.

◆ SYSCFG_EXTICR3_EXTI9_Pos

#define SYSCFG_EXTICR3_EXTI9_Pos (4U)

Definition at line 9778 of file stm32g431xx.h.

◆ SYSCFG_EXTICR4_EXTI12

#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk

EXTI 12 configuration

Definition at line 9833 of file stm32g431xx.h.

◆ SYSCFG_EXTICR4_EXTI12_Msk

#define SYSCFG_EXTICR4_EXTI12_Msk (0x7UL << SYSCFG_EXTICR4_EXTI12_Pos)

0x00000007

Definition at line 9832 of file stm32g431xx.h.

◆ SYSCFG_EXTICR4_EXTI12_PA

#define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U)

EXTI12 configuration.

PA[12] pin

Definition at line 9847 of file stm32g431xx.h.

◆ SYSCFG_EXTICR4_EXTI12_PB

#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U)

PB[12] pin

Definition at line 9848 of file stm32g431xx.h.

◆ SYSCFG_EXTICR4_EXTI12_PC

#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U)

PC[12] pin

Definition at line 9849 of file stm32g431xx.h.

◆ SYSCFG_EXTICR4_EXTI12_PD

#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U)

PD[12] pin

Definition at line 9850 of file stm32g431xx.h.

◆ SYSCFG_EXTICR4_EXTI12_PE

#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U)

PE[12] pin

Definition at line 9851 of file stm32g431xx.h.

◆ SYSCFG_EXTICR4_EXTI12_PF

#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U)

PF[12] pin

Definition at line 9852 of file stm32g431xx.h.

◆ SYSCFG_EXTICR4_EXTI12_Pos

#define SYSCFG_EXTICR4_EXTI12_Pos (0U)

Definition at line 9831 of file stm32g431xx.h.

◆ SYSCFG_EXTICR4_EXTI13

#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk

EXTI 13 configuration

Definition at line 9836 of file stm32g431xx.h.

◆ SYSCFG_EXTICR4_EXTI13_Msk

#define SYSCFG_EXTICR4_EXTI13_Msk (0x7UL << SYSCFG_EXTICR4_EXTI13_Pos)

0x00000070

Definition at line 9835 of file stm32g431xx.h.

◆ SYSCFG_EXTICR4_EXTI13_PA

#define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U)

EXTI13 configuration.

PA[13] pin

Definition at line 9857 of file stm32g431xx.h.

◆ SYSCFG_EXTICR4_EXTI13_PB

#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U)

PB[13] pin

Definition at line 9858 of file stm32g431xx.h.

◆ SYSCFG_EXTICR4_EXTI13_PC

#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U)

PC[13] pin

Definition at line 9859 of file stm32g431xx.h.

◆ SYSCFG_EXTICR4_EXTI13_PD

#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U)

PD[13] pin

Definition at line 9860 of file stm32g431xx.h.

◆ SYSCFG_EXTICR4_EXTI13_PE

#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U)

PE[13] pin

Definition at line 9861 of file stm32g431xx.h.

◆ SYSCFG_EXTICR4_EXTI13_PF

#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U)

PF[13] pin

Definition at line 9862 of file stm32g431xx.h.

◆ SYSCFG_EXTICR4_EXTI13_Pos

#define SYSCFG_EXTICR4_EXTI13_Pos (4U)

Definition at line 9834 of file stm32g431xx.h.

◆ SYSCFG_EXTICR4_EXTI14

#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk

EXTI 14 configuration

Definition at line 9839 of file stm32g431xx.h.

◆ SYSCFG_EXTICR4_EXTI14_Msk

#define SYSCFG_EXTICR4_EXTI14_Msk (0x7UL << SYSCFG_EXTICR4_EXTI14_Pos)

0x00000700

Definition at line 9838 of file stm32g431xx.h.

◆ SYSCFG_EXTICR4_EXTI14_PA

#define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U)

EXTI14 configuration.

PA[14] pin

Definition at line 9867 of file stm32g431xx.h.

◆ SYSCFG_EXTICR4_EXTI14_PB

#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U)

PB[14] pin

Definition at line 9868 of file stm32g431xx.h.

◆ SYSCFG_EXTICR4_EXTI14_PC

#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U)

PC[14] pin

Definition at line 9869 of file stm32g431xx.h.

◆ SYSCFG_EXTICR4_EXTI14_PD

#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U)

PD[14] pin

Definition at line 9870 of file stm32g431xx.h.

◆ SYSCFG_EXTICR4_EXTI14_PE

#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U)

PE[14] pin

Definition at line 9871 of file stm32g431xx.h.

◆ SYSCFG_EXTICR4_EXTI14_PF

#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U)

PF[14] pin

Definition at line 9872 of file stm32g431xx.h.

◆ SYSCFG_EXTICR4_EXTI14_Pos

#define SYSCFG_EXTICR4_EXTI14_Pos (8U)

Definition at line 9837 of file stm32g431xx.h.

◆ SYSCFG_EXTICR4_EXTI15

#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk

EXTI 15 configuration

Definition at line 9842 of file stm32g431xx.h.

◆ SYSCFG_EXTICR4_EXTI15_Msk

#define SYSCFG_EXTICR4_EXTI15_Msk (0x7UL << SYSCFG_EXTICR4_EXTI15_Pos)

0x00007000

Definition at line 9841 of file stm32g431xx.h.

◆ SYSCFG_EXTICR4_EXTI15_PA

#define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U)

EXTI15 configuration.

PA[15] pin

Definition at line 9877 of file stm32g431xx.h.

◆ SYSCFG_EXTICR4_EXTI15_PB

#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U)

PB[15] pin

Definition at line 9878 of file stm32g431xx.h.

◆ SYSCFG_EXTICR4_EXTI15_PC

#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U)

PC[15] pin

Definition at line 9879 of file stm32g431xx.h.

◆ SYSCFG_EXTICR4_EXTI15_PD

#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U)

PD[15] pin

Definition at line 9880 of file stm32g431xx.h.

◆ SYSCFG_EXTICR4_EXTI15_PE

#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U)

PE[15] pin

Definition at line 9881 of file stm32g431xx.h.

◆ SYSCFG_EXTICR4_EXTI15_PF

#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U)

PF[15] pin

Definition at line 9882 of file stm32g431xx.h.

◆ SYSCFG_EXTICR4_EXTI15_Pos

#define SYSCFG_EXTICR4_EXTI15_Pos (12U)

Definition at line 9840 of file stm32g431xx.h.

◆ SYSCFG_MEMRMP_FB_MODE

#define SYSCFG_MEMRMP_FB_MODE SYSCFG_MEMRMP_FB_MODE_Msk

User Flash Bank mode selection

Definition at line 9621 of file stm32g431xx.h.

◆ SYSCFG_MEMRMP_FB_MODE_Msk

#define SYSCFG_MEMRMP_FB_MODE_Msk (0x1UL << SYSCFG_MEMRMP_FB_MODE_Pos)

0x00000100

Definition at line 9620 of file stm32g431xx.h.

◆ SYSCFG_MEMRMP_FB_MODE_Pos

#define SYSCFG_MEMRMP_FB_MODE_Pos (8U)

Definition at line 9619 of file stm32g431xx.h.

◆ SYSCFG_MEMRMP_MEM_MODE

#define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk

SYSCFG_Memory Remap Config

Definition at line 9614 of file stm32g431xx.h.

◆ SYSCFG_MEMRMP_MEM_MODE_0

#define SYSCFG_MEMRMP_MEM_MODE_0 (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)

0x00000001

Definition at line 9615 of file stm32g431xx.h.

◆ SYSCFG_MEMRMP_MEM_MODE_1

#define SYSCFG_MEMRMP_MEM_MODE_1 (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)

0x00000002

Definition at line 9616 of file stm32g431xx.h.

◆ SYSCFG_MEMRMP_MEM_MODE_2

#define SYSCFG_MEMRMP_MEM_MODE_2 (0x4UL << SYSCFG_MEMRMP_MEM_MODE_Pos)

0x00000004

Definition at line 9617 of file stm32g431xx.h.

◆ SYSCFG_MEMRMP_MEM_MODE_Msk

#define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7UL << SYSCFG_MEMRMP_MEM_MODE_Pos)

0x00000007

Definition at line 9613 of file stm32g431xx.h.

◆ SYSCFG_MEMRMP_MEM_MODE_Pos

#define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)

Definition at line 9612 of file stm32g431xx.h.

◆ SYSCFG_SCSR_CCMBSY

#define SYSCFG_SCSR_CCMBSY SYSCFG_SCSR_CCMBSY_Msk

CCMSRAM Erase Ongoing

Definition at line 9890 of file stm32g431xx.h.

◆ SYSCFG_SCSR_CCMBSY_Msk

#define SYSCFG_SCSR_CCMBSY_Msk (0x1UL << SYSCFG_SCSR_CCMBSY_Pos)

0x00000002

Definition at line 9889 of file stm32g431xx.h.

◆ SYSCFG_SCSR_CCMBSY_Pos

#define SYSCFG_SCSR_CCMBSY_Pos (1U)

Definition at line 9888 of file stm32g431xx.h.

◆ SYSCFG_SCSR_CCMER

#define SYSCFG_SCSR_CCMER SYSCFG_SCSR_CCMER_Msk

CCMSRAM Erase Request

Definition at line 9887 of file stm32g431xx.h.

◆ SYSCFG_SCSR_CCMER_Msk

#define SYSCFG_SCSR_CCMER_Msk (0x1UL << SYSCFG_SCSR_CCMER_Pos)

0x00000001

Definition at line 9886 of file stm32g431xx.h.

◆ SYSCFG_SCSR_CCMER_Pos

#define SYSCFG_SCSR_CCMER_Pos (0U)

Definition at line 9885 of file stm32g431xx.h.

◆ SYSCFG_SKR_KEY

#define SYSCFG_SKR_KEY SYSCFG_SKR_KEY_Msk

CCMSRAM write protection key for software erase

Definition at line 9944 of file stm32g431xx.h.

◆ SYSCFG_SKR_KEY_Msk

#define SYSCFG_SKR_KEY_Msk (0xFFUL << SYSCFG_SKR_KEY_Pos)

0x000000FF

Definition at line 9943 of file stm32g431xx.h.

◆ SYSCFG_SKR_KEY_Pos

#define SYSCFG_SKR_KEY_Pos (0U)

Definition at line 9942 of file stm32g431xx.h.

◆ SYSCFG_SWPR_PAGE0

#define SYSCFG_SWPR_PAGE0 (SYSCFG_SWPR_PAGE0_Msk)

CCMSRAM Write protection page 0

Definition at line 9912 of file stm32g431xx.h.

◆ SYSCFG_SWPR_PAGE0_Msk

#define SYSCFG_SWPR_PAGE0_Msk (0x1UL << SYSCFG_SWPR_PAGE0_Pos)

0x00000001

Definition at line 9911 of file stm32g431xx.h.

◆ SYSCFG_SWPR_PAGE0_Pos

#define SYSCFG_SWPR_PAGE0_Pos (0U)

Definition at line 9910 of file stm32g431xx.h.

◆ SYSCFG_SWPR_PAGE1

#define SYSCFG_SWPR_PAGE1 (SYSCFG_SWPR_PAGE1_Msk)

CCMSRAM Write protection page 1

Definition at line 9915 of file stm32g431xx.h.

◆ SYSCFG_SWPR_PAGE1_Msk

#define SYSCFG_SWPR_PAGE1_Msk (0x1UL << SYSCFG_SWPR_PAGE1_Pos)

0x00000002

Definition at line 9914 of file stm32g431xx.h.

◆ SYSCFG_SWPR_PAGE1_Pos

#define SYSCFG_SWPR_PAGE1_Pos (1U)

Definition at line 9913 of file stm32g431xx.h.

◆ SYSCFG_SWPR_PAGE2

#define SYSCFG_SWPR_PAGE2 (SYSCFG_SWPR_PAGE2_Msk)

CCMSRAM Write protection page 2

Definition at line 9918 of file stm32g431xx.h.

◆ SYSCFG_SWPR_PAGE2_Msk

#define SYSCFG_SWPR_PAGE2_Msk (0x1UL << SYSCFG_SWPR_PAGE2_Pos)

0x00000004

Definition at line 9917 of file stm32g431xx.h.

◆ SYSCFG_SWPR_PAGE2_Pos

#define SYSCFG_SWPR_PAGE2_Pos (2U)

Definition at line 9916 of file stm32g431xx.h.

◆ SYSCFG_SWPR_PAGE3

#define SYSCFG_SWPR_PAGE3 (SYSCFG_SWPR_PAGE3_Msk)

CCMSRAM Write protection page 3

Definition at line 9921 of file stm32g431xx.h.

◆ SYSCFG_SWPR_PAGE3_Msk

#define SYSCFG_SWPR_PAGE3_Msk (0x1UL << SYSCFG_SWPR_PAGE3_Pos)

0x00000008

Definition at line 9920 of file stm32g431xx.h.

◆ SYSCFG_SWPR_PAGE3_Pos

#define SYSCFG_SWPR_PAGE3_Pos (3U)

Definition at line 9919 of file stm32g431xx.h.

◆ SYSCFG_SWPR_PAGE4

#define SYSCFG_SWPR_PAGE4 (SYSCFG_SWPR_PAGE4_Msk)

CCMSRAM Write protection page 4

Definition at line 9924 of file stm32g431xx.h.

◆ SYSCFG_SWPR_PAGE4_Msk

#define SYSCFG_SWPR_PAGE4_Msk (0x1UL << SYSCFG_SWPR_PAGE4_Pos)

0x00000010

Definition at line 9923 of file stm32g431xx.h.

◆ SYSCFG_SWPR_PAGE4_Pos

#define SYSCFG_SWPR_PAGE4_Pos (4U)

Definition at line 9922 of file stm32g431xx.h.

◆ SYSCFG_SWPR_PAGE5

#define SYSCFG_SWPR_PAGE5 (SYSCFG_SWPR_PAGE5_Msk)

CCMSRAM Write protection page 5

Definition at line 9927 of file stm32g431xx.h.

◆ SYSCFG_SWPR_PAGE5_Msk

#define SYSCFG_SWPR_PAGE5_Msk (0x1UL << SYSCFG_SWPR_PAGE5_Pos)

0x00000020

Definition at line 9926 of file stm32g431xx.h.

◆ SYSCFG_SWPR_PAGE5_Pos

#define SYSCFG_SWPR_PAGE5_Pos (5U)

Definition at line 9925 of file stm32g431xx.h.

◆ SYSCFG_SWPR_PAGE6

#define SYSCFG_SWPR_PAGE6 (SYSCFG_SWPR_PAGE6_Msk)

CCMSRAM Write protection page 6

Definition at line 9930 of file stm32g431xx.h.

◆ SYSCFG_SWPR_PAGE6_Msk

#define SYSCFG_SWPR_PAGE6_Msk (0x1UL << SYSCFG_SWPR_PAGE6_Pos)

0x00000040

Definition at line 9929 of file stm32g431xx.h.

◆ SYSCFG_SWPR_PAGE6_Pos

#define SYSCFG_SWPR_PAGE6_Pos (6U)

Definition at line 9928 of file stm32g431xx.h.

◆ SYSCFG_SWPR_PAGE7

#define SYSCFG_SWPR_PAGE7 (SYSCFG_SWPR_PAGE7_Msk)

CCMSRAM Write protection page 7

Definition at line 9933 of file stm32g431xx.h.

◆ SYSCFG_SWPR_PAGE7_Msk

#define SYSCFG_SWPR_PAGE7_Msk (0x1UL << SYSCFG_SWPR_PAGE7_Pos)

0x00000080

Definition at line 9932 of file stm32g431xx.h.

◆ SYSCFG_SWPR_PAGE7_Pos

#define SYSCFG_SWPR_PAGE7_Pos (7U)

Definition at line 9931 of file stm32g431xx.h.

◆ SYSCFG_SWPR_PAGE8

#define SYSCFG_SWPR_PAGE8 (SYSCFG_SWPR_PAGE8_Msk)

CCMSRAM Write protection page 8

Definition at line 9936 of file stm32g431xx.h.

◆ SYSCFG_SWPR_PAGE8_Msk

#define SYSCFG_SWPR_PAGE8_Msk (0x1UL << SYSCFG_SWPR_PAGE8_Pos)

0x00000100

Definition at line 9935 of file stm32g431xx.h.

◆ SYSCFG_SWPR_PAGE8_Pos

#define SYSCFG_SWPR_PAGE8_Pos (8U)

Definition at line 9934 of file stm32g431xx.h.

◆ SYSCFG_SWPR_PAGE9

#define SYSCFG_SWPR_PAGE9 (SYSCFG_SWPR_PAGE9_Msk)

CCMSRAM Write protection page 9

Definition at line 9939 of file stm32g431xx.h.

◆ SYSCFG_SWPR_PAGE9_Msk

#define SYSCFG_SWPR_PAGE9_Msk (0x1UL << SYSCFG_SWPR_PAGE9_Pos)

0x00000200

Definition at line 9938 of file stm32g431xx.h.

◆ SYSCFG_SWPR_PAGE9_Pos

#define SYSCFG_SWPR_PAGE9_Pos (9U)

Definition at line 9937 of file stm32g431xx.h.

◆ TAMP_BKP0R

#define TAMP_BKP0R TAMP_BKP0R_Msk

Definition at line 8970 of file stm32g431xx.h.

◆ TAMP_BKP0R_Msk

#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos)

0xFFFFFFFF

Definition at line 8969 of file stm32g431xx.h.

◆ TAMP_BKP0R_Pos

#define TAMP_BKP0R_Pos (0U)

Definition at line 8968 of file stm32g431xx.h.

◆ TAMP_BKP10R

#define TAMP_BKP10R TAMP_BKP10R_Msk

Definition at line 9020 of file stm32g431xx.h.

◆ TAMP_BKP10R_Msk

#define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos)

0xFFFFFFFF

Definition at line 9019 of file stm32g431xx.h.

◆ TAMP_BKP10R_Pos

#define TAMP_BKP10R_Pos (0U)

Definition at line 9018 of file stm32g431xx.h.

◆ TAMP_BKP11R

#define TAMP_BKP11R TAMP_BKP11R_Msk

Definition at line 9025 of file stm32g431xx.h.

◆ TAMP_BKP11R_Msk

#define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos)

0xFFFFFFFF

Definition at line 9024 of file stm32g431xx.h.

◆ TAMP_BKP11R_Pos

#define TAMP_BKP11R_Pos (0U)

Definition at line 9023 of file stm32g431xx.h.

◆ TAMP_BKP12R

#define TAMP_BKP12R TAMP_BKP12R_Msk

Definition at line 9030 of file stm32g431xx.h.

◆ TAMP_BKP12R_Msk

#define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos)

0xFFFFFFFF

Definition at line 9029 of file stm32g431xx.h.

◆ TAMP_BKP12R_Pos

#define TAMP_BKP12R_Pos (0U)

Definition at line 9028 of file stm32g431xx.h.

◆ TAMP_BKP13R

#define TAMP_BKP13R TAMP_BKP13R_Msk

Definition at line 9035 of file stm32g431xx.h.

◆ TAMP_BKP13R_Msk

#define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos)

0xFFFFFFFF

Definition at line 9034 of file stm32g431xx.h.

◆ TAMP_BKP13R_Pos

#define TAMP_BKP13R_Pos (0U)

Definition at line 9033 of file stm32g431xx.h.

◆ TAMP_BKP14R

#define TAMP_BKP14R TAMP_BKP14R_Msk

Definition at line 9040 of file stm32g431xx.h.

◆ TAMP_BKP14R_Msk

#define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos)

0xFFFFFFFF

Definition at line 9039 of file stm32g431xx.h.

◆ TAMP_BKP14R_Pos

#define TAMP_BKP14R_Pos (0U)

Definition at line 9038 of file stm32g431xx.h.

◆ TAMP_BKP15R

#define TAMP_BKP15R TAMP_BKP15R_Msk

Definition at line 9045 of file stm32g431xx.h.

◆ TAMP_BKP15R_Msk

#define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos)

0xFFFFFFFF

Definition at line 9044 of file stm32g431xx.h.

◆ TAMP_BKP15R_Pos

#define TAMP_BKP15R_Pos (0U)

Definition at line 9043 of file stm32g431xx.h.

◆ TAMP_BKP1R

#define TAMP_BKP1R TAMP_BKP1R_Msk

Definition at line 8975 of file stm32g431xx.h.

◆ TAMP_BKP1R_Msk

#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos)

0xFFFFFFFF

Definition at line 8974 of file stm32g431xx.h.

◆ TAMP_BKP1R_Pos

#define TAMP_BKP1R_Pos (0U)

Definition at line 8973 of file stm32g431xx.h.

◆ TAMP_BKP2R

#define TAMP_BKP2R TAMP_BKP2R_Msk

Definition at line 8980 of file stm32g431xx.h.

◆ TAMP_BKP2R_Msk

#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos)

0xFFFFFFFF

Definition at line 8979 of file stm32g431xx.h.

◆ TAMP_BKP2R_Pos

#define TAMP_BKP2R_Pos (0U)

Definition at line 8978 of file stm32g431xx.h.

◆ TAMP_BKP3R

#define TAMP_BKP3R TAMP_BKP3R_Msk

Definition at line 8985 of file stm32g431xx.h.

◆ TAMP_BKP3R_Msk

#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos)

0xFFFFFFFF

Definition at line 8984 of file stm32g431xx.h.

◆ TAMP_BKP3R_Pos

#define TAMP_BKP3R_Pos (0U)

Definition at line 8983 of file stm32g431xx.h.

◆ TAMP_BKP4R

#define TAMP_BKP4R TAMP_BKP4R_Msk

Definition at line 8990 of file stm32g431xx.h.

◆ TAMP_BKP4R_Msk

#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos)

0xFFFFFFFF

Definition at line 8989 of file stm32g431xx.h.

◆ TAMP_BKP4R_Pos

#define TAMP_BKP4R_Pos (0U)

Definition at line 8988 of file stm32g431xx.h.

◆ TAMP_BKP5R

#define TAMP_BKP5R TAMP_BKP5R_Msk

Definition at line 8995 of file stm32g431xx.h.

◆ TAMP_BKP5R_Msk

#define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos)

0xFFFFFFFF

Definition at line 8994 of file stm32g431xx.h.

◆ TAMP_BKP5R_Pos

#define TAMP_BKP5R_Pos (0U)

Definition at line 8993 of file stm32g431xx.h.

◆ TAMP_BKP6R

#define TAMP_BKP6R TAMP_BKP6R_Msk

Definition at line 9000 of file stm32g431xx.h.

◆ TAMP_BKP6R_Msk

#define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos)

0xFFFFFFFF

Definition at line 8999 of file stm32g431xx.h.

◆ TAMP_BKP6R_Pos

#define TAMP_BKP6R_Pos (0U)

Definition at line 8998 of file stm32g431xx.h.

◆ TAMP_BKP7R

#define TAMP_BKP7R TAMP_BKP7R_Msk

Definition at line 9005 of file stm32g431xx.h.

◆ TAMP_BKP7R_Msk

#define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos)

0xFFFFFFFF

Definition at line 9004 of file stm32g431xx.h.

◆ TAMP_BKP7R_Pos

#define TAMP_BKP7R_Pos (0U)

Definition at line 9003 of file stm32g431xx.h.

◆ TAMP_BKP8R

#define TAMP_BKP8R TAMP_BKP8R_Msk

Definition at line 9010 of file stm32g431xx.h.

◆ TAMP_BKP8R_Msk

#define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos)

0xFFFFFFFF

Definition at line 9009 of file stm32g431xx.h.

◆ TAMP_BKP8R_Pos

#define TAMP_BKP8R_Pos (0U)

Definition at line 9008 of file stm32g431xx.h.

◆ TAMP_BKP9R

#define TAMP_BKP9R TAMP_BKP9R_Msk

Definition at line 9015 of file stm32g431xx.h.

◆ TAMP_BKP9R_Msk

#define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos)

0xFFFFFFFF

Definition at line 9014 of file stm32g431xx.h.

◆ TAMP_BKP9R_Pos

#define TAMP_BKP9R_Pos (0U)

Definition at line 9013 of file stm32g431xx.h.

◆ TAMP_CR1_ITAMP3E

#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk

Definition at line 8814 of file stm32g431xx.h.

◆ TAMP_CR1_ITAMP3E_Msk

#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos)

0x00040000

Definition at line 8813 of file stm32g431xx.h.

◆ TAMP_CR1_ITAMP3E_Pos

#define TAMP_CR1_ITAMP3E_Pos (18U)

Definition at line 8812 of file stm32g431xx.h.

◆ TAMP_CR1_ITAMP4E

#define TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk

Definition at line 8817 of file stm32g431xx.h.

◆ TAMP_CR1_ITAMP4E_Msk

#define TAMP_CR1_ITAMP4E_Msk (0x1UL << TAMP_CR1_ITAMP4E_Pos)

0x00080000

Definition at line 8816 of file stm32g431xx.h.

◆ TAMP_CR1_ITAMP4E_Pos

#define TAMP_CR1_ITAMP4E_Pos (19U)

Definition at line 8815 of file stm32g431xx.h.

◆ TAMP_CR1_ITAMP5E

#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk

Definition at line 8820 of file stm32g431xx.h.

◆ TAMP_CR1_ITAMP5E_Msk

#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos)

0x00100000

Definition at line 8819 of file stm32g431xx.h.

◆ TAMP_CR1_ITAMP5E_Pos

#define TAMP_CR1_ITAMP5E_Pos (20U)

Definition at line 8818 of file stm32g431xx.h.

◆ TAMP_CR1_ITAMP6E

#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk

Definition at line 8823 of file stm32g431xx.h.

◆ TAMP_CR1_ITAMP6E_Msk

#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos)

0x00200000

Definition at line 8822 of file stm32g431xx.h.

◆ TAMP_CR1_ITAMP6E_Pos

#define TAMP_CR1_ITAMP6E_Pos (21U)

Definition at line 8821 of file stm32g431xx.h.

◆ TAMP_CR1_TAMP1E

#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk

Definition at line 8805 of file stm32g431xx.h.

◆ TAMP_CR1_TAMP1E_Msk

#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos)

0x00000001

Definition at line 8804 of file stm32g431xx.h.

◆ TAMP_CR1_TAMP1E_Pos

#define TAMP_CR1_TAMP1E_Pos (0U)

Definition at line 8803 of file stm32g431xx.h.

◆ TAMP_CR1_TAMP2E

#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk

Definition at line 8808 of file stm32g431xx.h.

◆ TAMP_CR1_TAMP2E_Msk

#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos)

0x00000002

Definition at line 8807 of file stm32g431xx.h.

◆ TAMP_CR1_TAMP2E_Pos

#define TAMP_CR1_TAMP2E_Pos (1U)

Definition at line 8806 of file stm32g431xx.h.

◆ TAMP_CR1_TAMP3E

#define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk

Definition at line 8811 of file stm32g431xx.h.

◆ TAMP_CR1_TAMP3E_Msk

#define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos)

0x00000004

Definition at line 8810 of file stm32g431xx.h.

◆ TAMP_CR1_TAMP3E_Pos

#define TAMP_CR1_TAMP3E_Pos (2U)

Definition at line 8809 of file stm32g431xx.h.

◆ TAMP_CR2_TAMP1MF

#define TAMP_CR2_TAMP1MF TAMP_CR2_TAMP1MF_Msk

Definition at line 8837 of file stm32g431xx.h.

◆ TAMP_CR2_TAMP1MF_Msk

#define TAMP_CR2_TAMP1MF_Msk (0x1UL << TAMP_CR2_TAMP1MF_Pos)

0x00010000

Definition at line 8836 of file stm32g431xx.h.

◆ TAMP_CR2_TAMP1MF_Pos

#define TAMP_CR2_TAMP1MF_Pos (16U)

Definition at line 8835 of file stm32g431xx.h.

◆ TAMP_CR2_TAMP1NOERASE

#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk

Definition at line 8828 of file stm32g431xx.h.

◆ TAMP_CR2_TAMP1NOERASE_Msk

#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos)

0x00000001

Definition at line 8827 of file stm32g431xx.h.

◆ TAMP_CR2_TAMP1NOERASE_Pos

#define TAMP_CR2_TAMP1NOERASE_Pos (0U)

Definition at line 8826 of file stm32g431xx.h.

◆ TAMP_CR2_TAMP1TRG

#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk

Definition at line 8846 of file stm32g431xx.h.

◆ TAMP_CR2_TAMP1TRG_Msk

#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos)

0x01000000

Definition at line 8845 of file stm32g431xx.h.

◆ TAMP_CR2_TAMP1TRG_Pos

#define TAMP_CR2_TAMP1TRG_Pos (24U)

Definition at line 8844 of file stm32g431xx.h.

◆ TAMP_CR2_TAMP2MF

#define TAMP_CR2_TAMP2MF TAMP_CR2_TAMP2MF_Msk

Definition at line 8840 of file stm32g431xx.h.

◆ TAMP_CR2_TAMP2MF_Msk

#define TAMP_CR2_TAMP2MF_Msk (0x1UL << TAMP_CR2_TAMP2MF_Pos)

0x00020000

Definition at line 8839 of file stm32g431xx.h.

◆ TAMP_CR2_TAMP2MF_Pos

#define TAMP_CR2_TAMP2MF_Pos (17U)

Definition at line 8838 of file stm32g431xx.h.

◆ TAMP_CR2_TAMP2NOERASE

#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk

Definition at line 8831 of file stm32g431xx.h.

◆ TAMP_CR2_TAMP2NOERASE_Msk

#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos)

0x00000002

Definition at line 8830 of file stm32g431xx.h.

◆ TAMP_CR2_TAMP2NOERASE_Pos

#define TAMP_CR2_TAMP2NOERASE_Pos (1U)

Definition at line 8829 of file stm32g431xx.h.

◆ TAMP_CR2_TAMP2TRG

#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk

Definition at line 8849 of file stm32g431xx.h.

◆ TAMP_CR2_TAMP2TRG_Msk

#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos)

0x02000000

Definition at line 8848 of file stm32g431xx.h.

◆ TAMP_CR2_TAMP2TRG_Pos

#define TAMP_CR2_TAMP2TRG_Pos (25U)

Definition at line 8847 of file stm32g431xx.h.

◆ TAMP_CR2_TAMP3MF

#define TAMP_CR2_TAMP3MF TAMP_CR2_TAMP3MF_Msk

Definition at line 8843 of file stm32g431xx.h.

◆ TAMP_CR2_TAMP3MF_Msk

#define TAMP_CR2_TAMP3MF_Msk (0x1UL << TAMP_CR2_TAMP3MF_Pos)

0x00040000

Definition at line 8842 of file stm32g431xx.h.

◆ TAMP_CR2_TAMP3MF_Pos

#define TAMP_CR2_TAMP3MF_Pos (18U)

Definition at line 8841 of file stm32g431xx.h.

◆ TAMP_CR2_TAMP3NOERASE

#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk

Definition at line 8834 of file stm32g431xx.h.

◆ TAMP_CR2_TAMP3NOERASE_Msk

#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos)

0x00000004

Definition at line 8833 of file stm32g431xx.h.

◆ TAMP_CR2_TAMP3NOERASE_Pos

#define TAMP_CR2_TAMP3NOERASE_Pos (2U)

Definition at line 8832 of file stm32g431xx.h.

◆ TAMP_CR2_TAMP3TRG

#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk

Definition at line 8852 of file stm32g431xx.h.

◆ TAMP_CR2_TAMP3TRG_Msk

#define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos)

0x04000000

Definition at line 8851 of file stm32g431xx.h.

◆ TAMP_CR2_TAMP3TRG_Pos

#define TAMP_CR2_TAMP3TRG_Pos (26U)

Definition at line 8850 of file stm32g431xx.h.

◆ TAMP_FLTCR_TAMPFLT

#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk

Definition at line 8865 of file stm32g431xx.h.

◆ TAMP_FLTCR_TAMPFLT_0

#define TAMP_FLTCR_TAMPFLT_0 (0x00000008UL)

Definition at line 8861 of file stm32g431xx.h.

◆ TAMP_FLTCR_TAMPFLT_1

#define TAMP_FLTCR_TAMPFLT_1 (0x00000010UL)

Definition at line 8862 of file stm32g431xx.h.

◆ TAMP_FLTCR_TAMPFLT_Msk

#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos)

0x00000018

Definition at line 8864 of file stm32g431xx.h.

◆ TAMP_FLTCR_TAMPFLT_Pos

#define TAMP_FLTCR_TAMPFLT_Pos (3U)

Definition at line 8863 of file stm32g431xx.h.

◆ TAMP_FLTCR_TAMPFREQ

#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk

Definition at line 8860 of file stm32g431xx.h.

◆ TAMP_FLTCR_TAMPFREQ_0

#define TAMP_FLTCR_TAMPFREQ_0 (0x00000001UL)

Definition at line 8855 of file stm32g431xx.h.

◆ TAMP_FLTCR_TAMPFREQ_1

#define TAMP_FLTCR_TAMPFREQ_1 (0x00000002UL)

Definition at line 8856 of file stm32g431xx.h.

◆ TAMP_FLTCR_TAMPFREQ_2

#define TAMP_FLTCR_TAMPFREQ_2 (0x00000004UL)

Definition at line 8857 of file stm32g431xx.h.

◆ TAMP_FLTCR_TAMPFREQ_Msk

#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos)

0x00000007

Definition at line 8859 of file stm32g431xx.h.

◆ TAMP_FLTCR_TAMPFREQ_Pos

#define TAMP_FLTCR_TAMPFREQ_Pos (0U)

Definition at line 8858 of file stm32g431xx.h.

◆ TAMP_FLTCR_TAMPPRCH

#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk

Definition at line 8870 of file stm32g431xx.h.

◆ TAMP_FLTCR_TAMPPRCH_0

#define TAMP_FLTCR_TAMPPRCH_0 (0x00000020UL)

Definition at line 8866 of file stm32g431xx.h.

◆ TAMP_FLTCR_TAMPPRCH_1

#define TAMP_FLTCR_TAMPPRCH_1 (0x00000040UL)

Definition at line 8867 of file stm32g431xx.h.

◆ TAMP_FLTCR_TAMPPRCH_Msk

#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos)

0x00000060

Definition at line 8869 of file stm32g431xx.h.

◆ TAMP_FLTCR_TAMPPRCH_Pos

#define TAMP_FLTCR_TAMPPRCH_Pos (5U)

Definition at line 8868 of file stm32g431xx.h.

◆ TAMP_FLTCR_TAMPPUDIS

#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk

Definition at line 8873 of file stm32g431xx.h.

◆ TAMP_FLTCR_TAMPPUDIS_Msk

#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos)

0x00000080

Definition at line 8872 of file stm32g431xx.h.

◆ TAMP_FLTCR_TAMPPUDIS_Pos

#define TAMP_FLTCR_TAMPPUDIS_Pos (7U)

Definition at line 8871 of file stm32g431xx.h.

◆ TAMP_IER_ITAMP3IE

#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk

Definition at line 8887 of file stm32g431xx.h.

◆ TAMP_IER_ITAMP3IE_Msk

#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos)

0x00040000

Definition at line 8886 of file stm32g431xx.h.

◆ TAMP_IER_ITAMP3IE_Pos

#define TAMP_IER_ITAMP3IE_Pos (18U)

Definition at line 8885 of file stm32g431xx.h.

◆ TAMP_IER_ITAMP4IE

#define TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk

Definition at line 8890 of file stm32g431xx.h.

◆ TAMP_IER_ITAMP4IE_Msk

#define TAMP_IER_ITAMP4IE_Msk (0x1UL << TAMP_IER_ITAMP4IE_Pos)

0x00080000

Definition at line 8889 of file stm32g431xx.h.

◆ TAMP_IER_ITAMP4IE_Pos

#define TAMP_IER_ITAMP4IE_Pos (19U)

Definition at line 8888 of file stm32g431xx.h.

◆ TAMP_IER_ITAMP5IE

#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk

Definition at line 8893 of file stm32g431xx.h.

◆ TAMP_IER_ITAMP5IE_Msk

#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos)

0x00100000

Definition at line 8892 of file stm32g431xx.h.

◆ TAMP_IER_ITAMP5IE_Pos

#define TAMP_IER_ITAMP5IE_Pos (20U)

Definition at line 8891 of file stm32g431xx.h.

◆ TAMP_IER_ITAMP6IE

#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk

Definition at line 8896 of file stm32g431xx.h.

◆ TAMP_IER_ITAMP6IE_Msk

#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos)

0x00200000

Definition at line 8895 of file stm32g431xx.h.

◆ TAMP_IER_ITAMP6IE_Pos

#define TAMP_IER_ITAMP6IE_Pos (21U)

Definition at line 8894 of file stm32g431xx.h.

◆ TAMP_IER_TAMP1IE

#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk

Definition at line 8878 of file stm32g431xx.h.

◆ TAMP_IER_TAMP1IE_Msk

#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos)

0x00000001

Definition at line 8877 of file stm32g431xx.h.

◆ TAMP_IER_TAMP1IE_Pos

#define TAMP_IER_TAMP1IE_Pos (0U)

Definition at line 8876 of file stm32g431xx.h.

◆ TAMP_IER_TAMP2IE

#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk

Definition at line 8881 of file stm32g431xx.h.

◆ TAMP_IER_TAMP2IE_Msk

#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos)

0x00000002

Definition at line 8880 of file stm32g431xx.h.

◆ TAMP_IER_TAMP2IE_Pos

#define TAMP_IER_TAMP2IE_Pos (1U)

Definition at line 8879 of file stm32g431xx.h.

◆ TAMP_IER_TAMP3IE

#define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk

Definition at line 8884 of file stm32g431xx.h.

◆ TAMP_IER_TAMP3IE_Msk

#define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos)

0x00000004

Definition at line 8883 of file stm32g431xx.h.

◆ TAMP_IER_TAMP3IE_Pos

#define TAMP_IER_TAMP3IE_Pos (2U)

Definition at line 8882 of file stm32g431xx.h.

◆ TAMP_MISR_ITAMP3MF

#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk

Definition at line 8933 of file stm32g431xx.h.

◆ TAMP_MISR_ITAMP3MF_Msk

#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos)

0x00040000

Definition at line 8932 of file stm32g431xx.h.

◆ TAMP_MISR_ITAMP3MF_Pos

#define TAMP_MISR_ITAMP3MF_Pos (18U)

Definition at line 8931 of file stm32g431xx.h.

◆ TAMP_MISR_ITAMP4MF

#define TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk

Definition at line 8936 of file stm32g431xx.h.

◆ TAMP_MISR_ITAMP4MF_Msk

#define TAMP_MISR_ITAMP4MF_Msk (0x1UL << TAMP_MISR_ITAMP4MF_Pos)

0x00080000

Definition at line 8935 of file stm32g431xx.h.

◆ TAMP_MISR_ITAMP4MF_Pos

#define TAMP_MISR_ITAMP4MF_Pos (19U)

Definition at line 8934 of file stm32g431xx.h.

◆ TAMP_MISR_ITAMP5MF

#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk

Definition at line 8939 of file stm32g431xx.h.

◆ TAMP_MISR_ITAMP5MF_Msk

#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos)

0x00100000

Definition at line 8938 of file stm32g431xx.h.

◆ TAMP_MISR_ITAMP5MF_Pos

#define TAMP_MISR_ITAMP5MF_Pos (20U)

Definition at line 8937 of file stm32g431xx.h.

◆ TAMP_MISR_ITAMP6MF

#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk

Definition at line 8942 of file stm32g431xx.h.

◆ TAMP_MISR_ITAMP6MF_Msk

#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos)

0x00200000

Definition at line 8941 of file stm32g431xx.h.

◆ TAMP_MISR_ITAMP6MF_Pos

#define TAMP_MISR_ITAMP6MF_Pos (21U)

Definition at line 8940 of file stm32g431xx.h.

◆ TAMP_MISR_TAMP1MF

#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk

Definition at line 8924 of file stm32g431xx.h.

◆ TAMP_MISR_TAMP1MF_Msk

#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos)

0x00000001

Definition at line 8923 of file stm32g431xx.h.

◆ TAMP_MISR_TAMP1MF_Pos

#define TAMP_MISR_TAMP1MF_Pos (0U)

Definition at line 8922 of file stm32g431xx.h.

◆ TAMP_MISR_TAMP2MF

#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk

Definition at line 8927 of file stm32g431xx.h.

◆ TAMP_MISR_TAMP2MF_Msk

#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos)

0x00000002

Definition at line 8926 of file stm32g431xx.h.

◆ TAMP_MISR_TAMP2MF_Pos

#define TAMP_MISR_TAMP2MF_Pos (1U)

Definition at line 8925 of file stm32g431xx.h.

◆ TAMP_MISR_TAMP3MF

#define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk

Definition at line 8930 of file stm32g431xx.h.

◆ TAMP_MISR_TAMP3MF_Msk

#define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos)

0x00000004

Definition at line 8929 of file stm32g431xx.h.

◆ TAMP_MISR_TAMP3MF_Pos

#define TAMP_MISR_TAMP3MF_Pos (2U)

Definition at line 8928 of file stm32g431xx.h.

◆ TAMP_SCR_CITAMP3F

#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk

Definition at line 8956 of file stm32g431xx.h.

◆ TAMP_SCR_CITAMP3F_Msk

#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos)

0x00040000

Definition at line 8955 of file stm32g431xx.h.

◆ TAMP_SCR_CITAMP3F_Pos

#define TAMP_SCR_CITAMP3F_Pos (18U)

Definition at line 8954 of file stm32g431xx.h.

◆ TAMP_SCR_CITAMP4F

#define TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk

Definition at line 8959 of file stm32g431xx.h.

◆ TAMP_SCR_CITAMP4F_Msk

#define TAMP_SCR_CITAMP4F_Msk (0x1UL << TAMP_SCR_CITAMP4F_Pos)

0x00080000

Definition at line 8958 of file stm32g431xx.h.

◆ TAMP_SCR_CITAMP4F_Pos

#define TAMP_SCR_CITAMP4F_Pos (19U)

Definition at line 8957 of file stm32g431xx.h.

◆ TAMP_SCR_CITAMP5F

#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk

Definition at line 8962 of file stm32g431xx.h.

◆ TAMP_SCR_CITAMP5F_Msk

#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos)

0x00100000

Definition at line 8961 of file stm32g431xx.h.

◆ TAMP_SCR_CITAMP5F_Pos

#define TAMP_SCR_CITAMP5F_Pos (20U)

Definition at line 8960 of file stm32g431xx.h.

◆ TAMP_SCR_CITAMP6F

#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk

Definition at line 8965 of file stm32g431xx.h.

◆ TAMP_SCR_CITAMP6F_Msk

#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos)

0x00200000

Definition at line 8964 of file stm32g431xx.h.

◆ TAMP_SCR_CITAMP6F_Pos

#define TAMP_SCR_CITAMP6F_Pos (21U)

Definition at line 8963 of file stm32g431xx.h.

◆ TAMP_SCR_CTAMP1F

#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk

Definition at line 8947 of file stm32g431xx.h.

◆ TAMP_SCR_CTAMP1F_Msk

#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos)

0x00000001

Definition at line 8946 of file stm32g431xx.h.

◆ TAMP_SCR_CTAMP1F_Pos

#define TAMP_SCR_CTAMP1F_Pos (0U)

Definition at line 8945 of file stm32g431xx.h.

◆ TAMP_SCR_CTAMP2F

#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk

Definition at line 8950 of file stm32g431xx.h.

◆ TAMP_SCR_CTAMP2F_Msk

#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos)

0x00000002

Definition at line 8949 of file stm32g431xx.h.

◆ TAMP_SCR_CTAMP2F_Pos

#define TAMP_SCR_CTAMP2F_Pos (1U)

Definition at line 8948 of file stm32g431xx.h.

◆ TAMP_SCR_CTAMP3F

#define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk

Definition at line 8953 of file stm32g431xx.h.

◆ TAMP_SCR_CTAMP3F_Msk

#define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos)

0x00000004

Definition at line 8952 of file stm32g431xx.h.

◆ TAMP_SCR_CTAMP3F_Pos

#define TAMP_SCR_CTAMP3F_Pos (2U)

Definition at line 8951 of file stm32g431xx.h.

◆ TAMP_SR_ITAMP3F

#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk

Definition at line 8910 of file stm32g431xx.h.

◆ TAMP_SR_ITAMP3F_Msk

#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos)

0x00040000

Definition at line 8909 of file stm32g431xx.h.

◆ TAMP_SR_ITAMP3F_Pos

#define TAMP_SR_ITAMP3F_Pos (18U)

Definition at line 8908 of file stm32g431xx.h.

◆ TAMP_SR_ITAMP4F

#define TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk

Definition at line 8913 of file stm32g431xx.h.

◆ TAMP_SR_ITAMP4F_Msk

#define TAMP_SR_ITAMP4F_Msk (0x1UL << TAMP_SR_ITAMP4F_Pos)

0x00080000

Definition at line 8912 of file stm32g431xx.h.

◆ TAMP_SR_ITAMP4F_Pos

#define TAMP_SR_ITAMP4F_Pos (19U)

Definition at line 8911 of file stm32g431xx.h.

◆ TAMP_SR_ITAMP5F

#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk

Definition at line 8916 of file stm32g431xx.h.

◆ TAMP_SR_ITAMP5F_Msk

#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos)

0x00100000

Definition at line 8915 of file stm32g431xx.h.

◆ TAMP_SR_ITAMP5F_Pos

#define TAMP_SR_ITAMP5F_Pos (20U)

Definition at line 8914 of file stm32g431xx.h.

◆ TAMP_SR_ITAMP6F

#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk

Definition at line 8919 of file stm32g431xx.h.

◆ TAMP_SR_ITAMP6F_Msk

#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos)

0x00200000

Definition at line 8918 of file stm32g431xx.h.

◆ TAMP_SR_ITAMP6F_Pos

#define TAMP_SR_ITAMP6F_Pos (21U)

Definition at line 8917 of file stm32g431xx.h.

◆ TAMP_SR_TAMP1F

#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk

Definition at line 8901 of file stm32g431xx.h.

◆ TAMP_SR_TAMP1F_Msk

#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos)

0x00000001

Definition at line 8900 of file stm32g431xx.h.

◆ TAMP_SR_TAMP1F_Pos

#define TAMP_SR_TAMP1F_Pos (0U)

Definition at line 8899 of file stm32g431xx.h.

◆ TAMP_SR_TAMP2F

#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk

Definition at line 8904 of file stm32g431xx.h.

◆ TAMP_SR_TAMP2F_Msk

#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos)

0x00000002

Definition at line 8903 of file stm32g431xx.h.

◆ TAMP_SR_TAMP2F_Pos

#define TAMP_SR_TAMP2F_Pos (1U)

Definition at line 8902 of file stm32g431xx.h.

◆ TAMP_SR_TAMP3F

#define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk

Definition at line 8907 of file stm32g431xx.h.

◆ TAMP_SR_TAMP3F_Msk

#define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos)

0x00000004

Definition at line 8906 of file stm32g431xx.h.

◆ TAMP_SR_TAMP3F_Pos

#define TAMP_SR_TAMP3F_Pos (2U)

Definition at line 8905 of file stm32g431xx.h.

◆ TIM1_AF1_BKCMP1E

#define TIM1_AF1_BKCMP1E TIM1_AF1_BKCMP1E_Msk

BRK COMP1 enable

Definition at line 10673 of file stm32g431xx.h.

◆ TIM1_AF1_BKCMP1E_Msk

#define TIM1_AF1_BKCMP1E_Msk (0x1UL << TIM1_AF1_BKCMP1E_Pos)

0x00000002

Definition at line 10672 of file stm32g431xx.h.

◆ TIM1_AF1_BKCMP1E_Pos

#define TIM1_AF1_BKCMP1E_Pos (1U)

Definition at line 10671 of file stm32g431xx.h.

◆ TIM1_AF1_BKCMP1P

#define TIM1_AF1_BKCMP1P TIM1_AF1_BKCMP1P_Msk

BRK COMP1 input polarity

Definition at line 10688 of file stm32g431xx.h.

◆ TIM1_AF1_BKCMP1P_Msk

#define TIM1_AF1_BKCMP1P_Msk (0x1UL << TIM1_AF1_BKCMP1P_Pos)

0x00000400

Definition at line 10687 of file stm32g431xx.h.

◆ TIM1_AF1_BKCMP1P_Pos

#define TIM1_AF1_BKCMP1P_Pos (10U)

Definition at line 10686 of file stm32g431xx.h.

◆ TIM1_AF1_BKCMP2E

#define TIM1_AF1_BKCMP2E TIM1_AF1_BKCMP2E_Msk

BRK COMP2 enable

Definition at line 10676 of file stm32g431xx.h.

◆ TIM1_AF1_BKCMP2E_Msk

#define TIM1_AF1_BKCMP2E_Msk (0x1UL << TIM1_AF1_BKCMP2E_Pos)

0x00000004

Definition at line 10675 of file stm32g431xx.h.

◆ TIM1_AF1_BKCMP2E_Pos

#define TIM1_AF1_BKCMP2E_Pos (2U)

Definition at line 10674 of file stm32g431xx.h.

◆ TIM1_AF1_BKCMP2P

#define TIM1_AF1_BKCMP2P TIM1_AF1_BKCMP2P_Msk

BRK COMP2 input polarity

Definition at line 10691 of file stm32g431xx.h.

◆ TIM1_AF1_BKCMP2P_Msk

#define TIM1_AF1_BKCMP2P_Msk (0x1UL << TIM1_AF1_BKCMP2P_Pos)

0x00000800

Definition at line 10690 of file stm32g431xx.h.

◆ TIM1_AF1_BKCMP2P_Pos

#define TIM1_AF1_BKCMP2P_Pos (11U)

Definition at line 10689 of file stm32g431xx.h.

◆ TIM1_AF1_BKCMP3E

#define TIM1_AF1_BKCMP3E TIM1_AF1_BKCMP3E_Msk

BRK COMP3 enable

Definition at line 10679 of file stm32g431xx.h.

◆ TIM1_AF1_BKCMP3E_Msk

#define TIM1_AF1_BKCMP3E_Msk (0x1UL << TIM1_AF1_BKCMP3E_Pos)

0x00000008

Definition at line 10678 of file stm32g431xx.h.

◆ TIM1_AF1_BKCMP3E_Pos

#define TIM1_AF1_BKCMP3E_Pos (3U)

Definition at line 10677 of file stm32g431xx.h.

◆ TIM1_AF1_BKCMP3P

#define TIM1_AF1_BKCMP3P TIM1_AF1_BKCMP3P_Msk

BRK COMP3 input polarity

Definition at line 10694 of file stm32g431xx.h.

◆ TIM1_AF1_BKCMP3P_Msk

#define TIM1_AF1_BKCMP3P_Msk (0x1UL << TIM1_AF1_BKCMP3P_Pos)

0x00001000

Definition at line 10693 of file stm32g431xx.h.

◆ TIM1_AF1_BKCMP3P_Pos

#define TIM1_AF1_BKCMP3P_Pos (12U)

Definition at line 10692 of file stm32g431xx.h.

◆ TIM1_AF1_BKCMP4E

#define TIM1_AF1_BKCMP4E TIM1_AF1_BKCMP4E_Msk

BRK COMP4 enable

Definition at line 10682 of file stm32g431xx.h.

◆ TIM1_AF1_BKCMP4E_Msk

#define TIM1_AF1_BKCMP4E_Msk (0x1UL << TIM1_AF1_BKCMP4E_Pos)

0x00000010

Definition at line 10681 of file stm32g431xx.h.

◆ TIM1_AF1_BKCMP4E_Pos

#define TIM1_AF1_BKCMP4E_Pos (4U)

Definition at line 10680 of file stm32g431xx.h.

◆ TIM1_AF1_BKCMP4P

#define TIM1_AF1_BKCMP4P TIM1_AF1_BKCMP4P_Msk

BRK COMP4 input polarity

Definition at line 10697 of file stm32g431xx.h.

◆ TIM1_AF1_BKCMP4P_Msk

#define TIM1_AF1_BKCMP4P_Msk (0x1UL << TIM1_AF1_BKCMP4P_Pos)

0x00002000

Definition at line 10696 of file stm32g431xx.h.

◆ TIM1_AF1_BKCMP4P_Pos

#define TIM1_AF1_BKCMP4P_Pos (13U)

Definition at line 10695 of file stm32g431xx.h.

◆ TIM1_AF1_BKINE

#define TIM1_AF1_BKINE TIM1_AF1_BKINE_Msk

BRK BKIN input enable

Definition at line 10670 of file stm32g431xx.h.

◆ TIM1_AF1_BKINE_Msk

#define TIM1_AF1_BKINE_Msk (0x1UL << TIM1_AF1_BKINE_Pos)

0x00000001

Definition at line 10669 of file stm32g431xx.h.

◆ TIM1_AF1_BKINE_Pos

#define TIM1_AF1_BKINE_Pos (0U)

Definition at line 10668 of file stm32g431xx.h.

◆ TIM1_AF1_BKINP

#define TIM1_AF1_BKINP TIM1_AF1_BKINP_Msk

BRK BKIN input polarity

Definition at line 10685 of file stm32g431xx.h.

◆ TIM1_AF1_BKINP_Msk

#define TIM1_AF1_BKINP_Msk (0x1UL << TIM1_AF1_BKINP_Pos)

0x00000200

Definition at line 10684 of file stm32g431xx.h.

◆ TIM1_AF1_BKINP_Pos

#define TIM1_AF1_BKINP_Pos (9U)

Definition at line 10683 of file stm32g431xx.h.

◆ TIM1_AF1_ETRSEL

#define TIM1_AF1_ETRSEL TIM1_AF1_ETRSEL_Msk

ETRSEL[3:0] bits (TIM1 ETR source selection)

Definition at line 10700 of file stm32g431xx.h.

◆ TIM1_AF1_ETRSEL_0

#define TIM1_AF1_ETRSEL_0 (0x1UL << TIM1_AF1_ETRSEL_Pos)

0x00004000

Definition at line 10701 of file stm32g431xx.h.

◆ TIM1_AF1_ETRSEL_1

#define TIM1_AF1_ETRSEL_1 (0x2UL << TIM1_AF1_ETRSEL_Pos)

0x00008000

Definition at line 10702 of file stm32g431xx.h.

◆ TIM1_AF1_ETRSEL_2

#define TIM1_AF1_ETRSEL_2 (0x4UL << TIM1_AF1_ETRSEL_Pos)

0x00010000

Definition at line 10703 of file stm32g431xx.h.

◆ TIM1_AF1_ETRSEL_3

#define TIM1_AF1_ETRSEL_3 (0x8UL << TIM1_AF1_ETRSEL_Pos)

0x00020000

Definition at line 10704 of file stm32g431xx.h.

◆ TIM1_AF1_ETRSEL_Msk

#define TIM1_AF1_ETRSEL_Msk (0xFUL << TIM1_AF1_ETRSEL_Pos)

0x0003C000

Definition at line 10699 of file stm32g431xx.h.

◆ TIM1_AF1_ETRSEL_Pos

#define TIM1_AF1_ETRSEL_Pos (14U)

Definition at line 10698 of file stm32g431xx.h.

◆ TIM1_AF2_BK2CMP1E

#define TIM1_AF2_BK2CMP1E TIM1_AF2_BK2CMP1E_Msk

BRK2 COMP1 enable

Definition at line 10712 of file stm32g431xx.h.

◆ TIM1_AF2_BK2CMP1E_Msk

#define TIM1_AF2_BK2CMP1E_Msk (0x1UL << TIM1_AF2_BK2CMP1E_Pos)

0x00000002

Definition at line 10711 of file stm32g431xx.h.

◆ TIM1_AF2_BK2CMP1E_Pos

#define TIM1_AF2_BK2CMP1E_Pos (1U)

Definition at line 10710 of file stm32g431xx.h.

◆ TIM1_AF2_BK2CMP1P

#define TIM1_AF2_BK2CMP1P TIM1_AF2_BK2CMP1P_Msk

BRK2 COMP1 input polarity

Definition at line 10727 of file stm32g431xx.h.

◆ TIM1_AF2_BK2CMP1P_Msk

#define TIM1_AF2_BK2CMP1P_Msk (0x1UL << TIM1_AF2_BK2CMP1P_Pos)

0x00000400

Definition at line 10726 of file stm32g431xx.h.

◆ TIM1_AF2_BK2CMP1P_Pos

#define TIM1_AF2_BK2CMP1P_Pos (10U)

Definition at line 10725 of file stm32g431xx.h.

◆ TIM1_AF2_BK2CMP2E

#define TIM1_AF2_BK2CMP2E TIM1_AF2_BK2CMP2E_Msk

BRK2 COMP2 enable

Definition at line 10715 of file stm32g431xx.h.

◆ TIM1_AF2_BK2CMP2E_Msk

#define TIM1_AF2_BK2CMP2E_Msk (0x1UL << TIM1_AF2_BK2CMP2E_Pos)

0x00000004

Definition at line 10714 of file stm32g431xx.h.

◆ TIM1_AF2_BK2CMP2E_Pos

#define TIM1_AF2_BK2CMP2E_Pos (2U)

Definition at line 10713 of file stm32g431xx.h.

◆ TIM1_AF2_BK2CMP2P

#define TIM1_AF2_BK2CMP2P TIM1_AF2_BK2CMP2P_Msk

BRK2 COMP2 input polarity

Definition at line 10730 of file stm32g431xx.h.

◆ TIM1_AF2_BK2CMP2P_Msk

#define TIM1_AF2_BK2CMP2P_Msk (0x1UL << TIM1_AF2_BK2CMP2P_Pos)

0x00000800

Definition at line 10729 of file stm32g431xx.h.

◆ TIM1_AF2_BK2CMP2P_Pos

#define TIM1_AF2_BK2CMP2P_Pos (11U)

Definition at line 10728 of file stm32g431xx.h.

◆ TIM1_AF2_BK2CMP3E

#define TIM1_AF2_BK2CMP3E TIM1_AF2_BK2CMP3E_Msk

BRK2 COMP3 enable

Definition at line 10718 of file stm32g431xx.h.

◆ TIM1_AF2_BK2CMP3E_Msk

#define TIM1_AF2_BK2CMP3E_Msk (0x1UL << TIM1_AF2_BK2CMP3E_Pos)

0x00000008

Definition at line 10717 of file stm32g431xx.h.

◆ TIM1_AF2_BK2CMP3E_Pos

#define TIM1_AF2_BK2CMP3E_Pos (3U)

Definition at line 10716 of file stm32g431xx.h.

◆ TIM1_AF2_BK2CMP3P

#define TIM1_AF2_BK2CMP3P TIM1_AF2_BK2CMP3P_Msk

BRK2 COMP3 input polarity

Definition at line 10733 of file stm32g431xx.h.

◆ TIM1_AF2_BK2CMP3P_Msk

#define TIM1_AF2_BK2CMP3P_Msk (0x1UL << TIM1_AF2_BK2CMP3P_Pos)

0x00000400

Definition at line 10732 of file stm32g431xx.h.

◆ TIM1_AF2_BK2CMP3P_Pos

#define TIM1_AF2_BK2CMP3P_Pos (12U)

Definition at line 10731 of file stm32g431xx.h.

◆ TIM1_AF2_BK2CMP4E

#define TIM1_AF2_BK2CMP4E TIM1_AF2_BK2CMP4E_Msk

BRK2 COMP4 enable

Definition at line 10721 of file stm32g431xx.h.

◆ TIM1_AF2_BK2CMP4E_Msk

#define TIM1_AF2_BK2CMP4E_Msk (0x1UL << TIM1_AF2_BK2CMP4E_Pos)

0x00000010

Definition at line 10720 of file stm32g431xx.h.

◆ TIM1_AF2_BK2CMP4E_Pos

#define TIM1_AF2_BK2CMP4E_Pos (4U)

Definition at line 10719 of file stm32g431xx.h.

◆ TIM1_AF2_BK2CMP4P

#define TIM1_AF2_BK2CMP4P TIM1_AF2_BK2CMP4P_Msk

BRK2 COMP4 input polarity

Definition at line 10736 of file stm32g431xx.h.

◆ TIM1_AF2_BK2CMP4P_Msk

#define TIM1_AF2_BK2CMP4P_Msk (0x1UL << TIM1_AF2_BK2CMP4P_Pos)

0x00000800

Definition at line 10735 of file stm32g431xx.h.

◆ TIM1_AF2_BK2CMP4P_Pos

#define TIM1_AF2_BK2CMP4P_Pos (13U)

Definition at line 10734 of file stm32g431xx.h.

◆ TIM1_AF2_BK2INE

#define TIM1_AF2_BK2INE TIM1_AF2_BK2INE_Msk

BRK2 BKIN input enable

Definition at line 10709 of file stm32g431xx.h.

◆ TIM1_AF2_BK2INE_Msk

#define TIM1_AF2_BK2INE_Msk (0x1UL << TIM1_AF2_BK2INE_Pos)

0x00000001

Definition at line 10708 of file stm32g431xx.h.

◆ TIM1_AF2_BK2INE_Pos

#define TIM1_AF2_BK2INE_Pos (0U)

Definition at line 10707 of file stm32g431xx.h.

◆ TIM1_AF2_BK2INP

#define TIM1_AF2_BK2INP TIM1_AF2_BK2INP_Msk

BRK2 BKIN input polarity

Definition at line 10724 of file stm32g431xx.h.

◆ TIM1_AF2_BK2INP_Msk

#define TIM1_AF2_BK2INP_Msk (0x1UL << TIM1_AF2_BK2INP_Pos)

0x00000200

Definition at line 10723 of file stm32g431xx.h.

◆ TIM1_AF2_BK2INP_Pos

#define TIM1_AF2_BK2INP_Pos (9U)

Definition at line 10722 of file stm32g431xx.h.

◆ TIM1_AF2_OCRSEL

#define TIM1_AF2_OCRSEL TIM1_AF2_OCRSEL_Msk

BRK2 COMP2 input polarity

Definition at line 10739 of file stm32g431xx.h.

◆ TIM1_AF2_OCRSEL_0

#define TIM1_AF2_OCRSEL_0 (0x1UL << TIM1_AF2_OCRSEL_Pos)

0x00010000

Definition at line 10740 of file stm32g431xx.h.

◆ TIM1_AF2_OCRSEL_1

#define TIM1_AF2_OCRSEL_1 (0x2UL << TIM1_AF2_OCRSEL_Pos)

0x00020000

Definition at line 10741 of file stm32g431xx.h.

◆ TIM1_AF2_OCRSEL_2

#define TIM1_AF2_OCRSEL_2 (0x4UL << TIM1_AF2_OCRSEL_Pos)

0x00040000

Definition at line 10742 of file stm32g431xx.h.

◆ TIM1_AF2_OCRSEL_Msk

#define TIM1_AF2_OCRSEL_Msk (0x7UL << TIM1_AF2_OCRSEL_Pos)

0x00070000

Definition at line 10738 of file stm32g431xx.h.

◆ TIM1_AF2_OCRSEL_Pos

#define TIM1_AF2_OCRSEL_Pos (16U)

Definition at line 10737 of file stm32g431xx.h.

◆ TIM_ARR_ARR

#define TIM_ARR_ARR TIM_ARR_ARR_Msk

Actual auto-reload Value

Definition at line 10536 of file stm32g431xx.h.

◆ TIM_ARR_ARR_Msk

#define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)

0xFFFFFFFF

Definition at line 10535 of file stm32g431xx.h.

◆ TIM_ARR_ARR_Pos

#define TIM_ARR_ARR_Pos (0U)

Definition at line 10534 of file stm32g431xx.h.

◆ TIM_BDTR_AOE

#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk

Automatic Output enable

Definition at line 10615 of file stm32g431xx.h.

◆ TIM_BDTR_AOE_Msk

#define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos)

0x00004000

Definition at line 10614 of file stm32g431xx.h.

◆ TIM_BDTR_AOE_Pos

#define TIM_BDTR_AOE_Pos (14U)

Definition at line 10613 of file stm32g431xx.h.

◆ TIM_BDTR_BK2BID

#define TIM_BDTR_BK2BID TIM_BDTR_BK2BID_Msk

Break2 BIDirectional

Definition at line 10646 of file stm32g431xx.h.

◆ TIM_BDTR_BK2BID_Msk

#define TIM_BDTR_BK2BID_Msk (0x1UL << TIM_BDTR_BK2BID_Pos)

0x20000000

Definition at line 10645 of file stm32g431xx.h.

◆ TIM_BDTR_BK2BID_Pos

#define TIM_BDTR_BK2BID_Pos (29U)

Definition at line 10644 of file stm32g431xx.h.

◆ TIM_BDTR_BK2DSRM

#define TIM_BDTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk

Break2 disarming/re-arming

Definition at line 10639 of file stm32g431xx.h.

◆ TIM_BDTR_BK2DSRM_Msk

#define TIM_BDTR_BK2DSRM_Msk (0x1UL << TIM_BDTR_BK2DSRM_Pos)

0x08000000

Definition at line 10638 of file stm32g431xx.h.

◆ TIM_BDTR_BK2DSRM_Pos

#define TIM_BDTR_BK2DSRM_Pos (27U)

Definition at line 10637 of file stm32g431xx.h.

◆ TIM_BDTR_BK2E

#define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk

Break enable for Break 2

Definition at line 10629 of file stm32g431xx.h.

◆ TIM_BDTR_BK2E_Msk

#define TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos)

0x01000000

Definition at line 10628 of file stm32g431xx.h.

◆ TIM_BDTR_BK2E_Pos

#define TIM_BDTR_BK2E_Pos (24U)

Definition at line 10627 of file stm32g431xx.h.

◆ TIM_BDTR_BK2F

#define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk

Break Filter for Break 2

Definition at line 10625 of file stm32g431xx.h.

◆ TIM_BDTR_BK2F_Msk

#define TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos)

0x00F00000

Definition at line 10624 of file stm32g431xx.h.

◆ TIM_BDTR_BK2F_Pos

#define TIM_BDTR_BK2F_Pos (20U)

Definition at line 10623 of file stm32g431xx.h.

◆ TIM_BDTR_BK2P

#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk

Break Polarity for Break 2

Definition at line 10632 of file stm32g431xx.h.

◆ TIM_BDTR_BK2P_Msk

#define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos)

0x02000000

Definition at line 10631 of file stm32g431xx.h.

◆ TIM_BDTR_BK2P_Pos

#define TIM_BDTR_BK2P_Pos (25U)

Definition at line 10630 of file stm32g431xx.h.

◆ TIM_BDTR_BKBID

#define TIM_BDTR_BKBID TIM_BDTR_BKBID_Msk

Break BIDirectional

Definition at line 10643 of file stm32g431xx.h.

◆ TIM_BDTR_BKBID_Msk

#define TIM_BDTR_BKBID_Msk (0x1UL << TIM_BDTR_BKBID_Pos)

0x10000000

Definition at line 10642 of file stm32g431xx.h.

◆ TIM_BDTR_BKBID_Pos

#define TIM_BDTR_BKBID_Pos (28U)

Definition at line 10641 of file stm32g431xx.h.

◆ TIM_BDTR_BKDSRM

#define TIM_BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk

Break disarming/re-arming

Definition at line 10636 of file stm32g431xx.h.

◆ TIM_BDTR_BKDSRM_Msk

#define TIM_BDTR_BKDSRM_Msk (0x1UL << TIM_BDTR_BKDSRM_Pos)

0x04000000

Definition at line 10635 of file stm32g431xx.h.

◆ TIM_BDTR_BKDSRM_Pos

#define TIM_BDTR_BKDSRM_Pos (26U)

Definition at line 10634 of file stm32g431xx.h.

◆ TIM_BDTR_BKE

#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk

Break enable for Break 1

Definition at line 10609 of file stm32g431xx.h.

◆ TIM_BDTR_BKE_Msk

#define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos)

0x00001000

Definition at line 10608 of file stm32g431xx.h.

◆ TIM_BDTR_BKE_Pos

#define TIM_BDTR_BKE_Pos (12U)

Definition at line 10607 of file stm32g431xx.h.

◆ TIM_BDTR_BKF

#define TIM_BDTR_BKF TIM_BDTR_BKF_Msk

Break Filter for Break 1

Definition at line 10622 of file stm32g431xx.h.

◆ TIM_BDTR_BKF_Msk

#define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos)

0x000F0000

Definition at line 10621 of file stm32g431xx.h.

◆ TIM_BDTR_BKF_Pos

#define TIM_BDTR_BKF_Pos (16U)

Definition at line 10620 of file stm32g431xx.h.

◆ TIM_BDTR_BKP

#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk

Break Polarity for Break 1

Definition at line 10612 of file stm32g431xx.h.

◆ TIM_BDTR_BKP_Msk

#define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos)

0x00002000

Definition at line 10611 of file stm32g431xx.h.

◆ TIM_BDTR_BKP_Pos

#define TIM_BDTR_BKP_Pos (13U)

Definition at line 10610 of file stm32g431xx.h.

◆ TIM_BDTR_DTG

#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk

DTG[0:7] bits (Dead-Time Generator set-up)

Definition at line 10585 of file stm32g431xx.h.

◆ TIM_BDTR_DTG_0

#define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos)

0x00000001

Definition at line 10586 of file stm32g431xx.h.

◆ TIM_BDTR_DTG_1

#define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos)

0x00000002

Definition at line 10587 of file stm32g431xx.h.

◆ TIM_BDTR_DTG_2

#define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos)

0x00000004

Definition at line 10588 of file stm32g431xx.h.

◆ TIM_BDTR_DTG_3

#define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos)

0x00000008

Definition at line 10589 of file stm32g431xx.h.

◆ TIM_BDTR_DTG_4

#define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos)

0x00000010

Definition at line 10590 of file stm32g431xx.h.

◆ TIM_BDTR_DTG_5

#define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos)

0x00000020

Definition at line 10591 of file stm32g431xx.h.

◆ TIM_BDTR_DTG_6

#define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos)

0x00000040

Definition at line 10592 of file stm32g431xx.h.

◆ TIM_BDTR_DTG_7

#define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos)

0x00000080

Definition at line 10593 of file stm32g431xx.h.

◆ TIM_BDTR_DTG_Msk

#define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos)

0x000000FF

Definition at line 10584 of file stm32g431xx.h.

◆ TIM_BDTR_DTG_Pos

#define TIM_BDTR_DTG_Pos (0U)

Definition at line 10583 of file stm32g431xx.h.

◆ TIM_BDTR_LOCK

#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk

LOCK[1:0] bits (Lock Configuration)

Definition at line 10597 of file stm32g431xx.h.

◆ TIM_BDTR_LOCK_0

#define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos)

0x00000100

Definition at line 10598 of file stm32g431xx.h.

◆ TIM_BDTR_LOCK_1

#define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos)

0x00000200

Definition at line 10599 of file stm32g431xx.h.

◆ TIM_BDTR_LOCK_Msk

#define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos)

0x00000300

Definition at line 10596 of file stm32g431xx.h.

◆ TIM_BDTR_LOCK_Pos

#define TIM_BDTR_LOCK_Pos (8U)

Definition at line 10595 of file stm32g431xx.h.

◆ TIM_BDTR_MOE

#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk

Main Output enable

Definition at line 10618 of file stm32g431xx.h.

◆ TIM_BDTR_MOE_Msk

#define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos)

0x00008000

Definition at line 10617 of file stm32g431xx.h.

◆ TIM_BDTR_MOE_Pos

#define TIM_BDTR_MOE_Pos (15U)

Definition at line 10616 of file stm32g431xx.h.

◆ TIM_BDTR_OSSI

#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk

Off-State Selection for Idle mode

Definition at line 10603 of file stm32g431xx.h.

◆ TIM_BDTR_OSSI_Msk

#define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos)

0x00000400

Definition at line 10602 of file stm32g431xx.h.

◆ TIM_BDTR_OSSI_Pos

#define TIM_BDTR_OSSI_Pos (10U)

Definition at line 10601 of file stm32g431xx.h.

◆ TIM_BDTR_OSSR

#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk

Off-State Selection for Run mode

Definition at line 10606 of file stm32g431xx.h.

◆ TIM_BDTR_OSSR_Msk

#define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos)

0x00000800

Definition at line 10605 of file stm32g431xx.h.

◆ TIM_BDTR_OSSR_Pos

#define TIM_BDTR_OSSR_Pos (11U)

Definition at line 10604 of file stm32g431xx.h.

◆ TIM_CCER_CC1E

#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk

Capture/Compare 1 output enable

Definition at line 10461 of file stm32g431xx.h.

◆ TIM_CCER_CC1E_Msk

#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos)

0x00000001

Definition at line 10460 of file stm32g431xx.h.

◆ TIM_CCER_CC1E_Pos

#define TIM_CCER_CC1E_Pos (0U)

Definition at line 10459 of file stm32g431xx.h.

◆ TIM_CCER_CC1NE

#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk

Capture/Compare 1 Complementary output enable

Definition at line 10467 of file stm32g431xx.h.

◆ TIM_CCER_CC1NE_Msk

#define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos)

0x00000004

Definition at line 10466 of file stm32g431xx.h.

◆ TIM_CCER_CC1NE_Pos

#define TIM_CCER_CC1NE_Pos (2U)

Definition at line 10465 of file stm32g431xx.h.

◆ TIM_CCER_CC1NP

#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk

Capture/Compare 1 Complementary output Polarity

Definition at line 10470 of file stm32g431xx.h.

◆ TIM_CCER_CC1NP_Msk

#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos)

0x00000008

Definition at line 10469 of file stm32g431xx.h.

◆ TIM_CCER_CC1NP_Pos

#define TIM_CCER_CC1NP_Pos (3U)

Definition at line 10468 of file stm32g431xx.h.

◆ TIM_CCER_CC1P

#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk

Capture/Compare 1 output Polarity

Definition at line 10464 of file stm32g431xx.h.

◆ TIM_CCER_CC1P_Msk

#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos)

0x00000002

Definition at line 10463 of file stm32g431xx.h.

◆ TIM_CCER_CC1P_Pos

#define TIM_CCER_CC1P_Pos (1U)

Definition at line 10462 of file stm32g431xx.h.

◆ TIM_CCER_CC2E

#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk

Capture/Compare 2 output enable

Definition at line 10473 of file stm32g431xx.h.

◆ TIM_CCER_CC2E_Msk

#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos)

0x00000010

Definition at line 10472 of file stm32g431xx.h.

◆ TIM_CCER_CC2E_Pos

#define TIM_CCER_CC2E_Pos (4U)

Definition at line 10471 of file stm32g431xx.h.

◆ TIM_CCER_CC2NE

#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk

Capture/Compare 2 Complementary output enable

Definition at line 10479 of file stm32g431xx.h.

◆ TIM_CCER_CC2NE_Msk

#define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos)

0x00000040

Definition at line 10478 of file stm32g431xx.h.

◆ TIM_CCER_CC2NE_Pos

#define TIM_CCER_CC2NE_Pos (6U)

Definition at line 10477 of file stm32g431xx.h.

◆ TIM_CCER_CC2NP

#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk

Capture/Compare 2 Complementary output Polarity

Definition at line 10482 of file stm32g431xx.h.

◆ TIM_CCER_CC2NP_Msk

#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos)

0x00000080

Definition at line 10481 of file stm32g431xx.h.

◆ TIM_CCER_CC2NP_Pos

#define TIM_CCER_CC2NP_Pos (7U)

Definition at line 10480 of file stm32g431xx.h.

◆ TIM_CCER_CC2P

#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk

Capture/Compare 2 output Polarity

Definition at line 10476 of file stm32g431xx.h.

◆ TIM_CCER_CC2P_Msk

#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos)

0x00000020

Definition at line 10475 of file stm32g431xx.h.

◆ TIM_CCER_CC2P_Pos

#define TIM_CCER_CC2P_Pos (5U)

Definition at line 10474 of file stm32g431xx.h.

◆ TIM_CCER_CC3E

#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk

Capture/Compare 3 output enable

Definition at line 10485 of file stm32g431xx.h.

◆ TIM_CCER_CC3E_Msk

#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos)

0x00000100

Definition at line 10484 of file stm32g431xx.h.

◆ TIM_CCER_CC3E_Pos

#define TIM_CCER_CC3E_Pos (8U)

Definition at line 10483 of file stm32g431xx.h.

◆ TIM_CCER_CC3NE

#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk

Capture/Compare 3 Complementary output enable

Definition at line 10491 of file stm32g431xx.h.

◆ TIM_CCER_CC3NE_Msk

#define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos)

0x00000400

Definition at line 10490 of file stm32g431xx.h.

◆ TIM_CCER_CC3NE_Pos

#define TIM_CCER_CC3NE_Pos (10U)

Definition at line 10489 of file stm32g431xx.h.

◆ TIM_CCER_CC3NP

#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk

Capture/Compare 3 Complementary output Polarity

Definition at line 10494 of file stm32g431xx.h.

◆ TIM_CCER_CC3NP_Msk

#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos)

0x00000800

Definition at line 10493 of file stm32g431xx.h.

◆ TIM_CCER_CC3NP_Pos

#define TIM_CCER_CC3NP_Pos (11U)

Definition at line 10492 of file stm32g431xx.h.

◆ TIM_CCER_CC3P

#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk

Capture/Compare 3 output Polarity

Definition at line 10488 of file stm32g431xx.h.

◆ TIM_CCER_CC3P_Msk

#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos)

0x00000200

Definition at line 10487 of file stm32g431xx.h.

◆ TIM_CCER_CC3P_Pos

#define TIM_CCER_CC3P_Pos (9U)

Definition at line 10486 of file stm32g431xx.h.

◆ TIM_CCER_CC4E

#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk

Capture/Compare 4 output enable

Definition at line 10497 of file stm32g431xx.h.

◆ TIM_CCER_CC4E_Msk

#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos)

0x00001000

Definition at line 10496 of file stm32g431xx.h.

◆ TIM_CCER_CC4E_Pos

#define TIM_CCER_CC4E_Pos (12U)

Definition at line 10495 of file stm32g431xx.h.

◆ TIM_CCER_CC4NE

#define TIM_CCER_CC4NE TIM_CCER_CC4NE_Msk

Capture/Compare 4 Complementary output enable

Definition at line 10503 of file stm32g431xx.h.

◆ TIM_CCER_CC4NE_Msk

#define TIM_CCER_CC4NE_Msk (0x1UL << TIM_CCER_CC4NE_Pos)

0x00004000

Definition at line 10502 of file stm32g431xx.h.

◆ TIM_CCER_CC4NE_Pos

#define TIM_CCER_CC4NE_Pos (14U)

Definition at line 10501 of file stm32g431xx.h.

◆ TIM_CCER_CC4NP

#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk

Capture/Compare 4 Complementary output Polarity

Definition at line 10506 of file stm32g431xx.h.

◆ TIM_CCER_CC4NP_Msk

#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos)

0x00008000

Definition at line 10505 of file stm32g431xx.h.

◆ TIM_CCER_CC4NP_Pos

#define TIM_CCER_CC4NP_Pos (15U)

Definition at line 10504 of file stm32g431xx.h.

◆ TIM_CCER_CC4P

#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk

Capture/Compare 4 output Polarity

Definition at line 10500 of file stm32g431xx.h.

◆ TIM_CCER_CC4P_Msk

#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos)

0x00002000

Definition at line 10499 of file stm32g431xx.h.

◆ TIM_CCER_CC4P_Pos

#define TIM_CCER_CC4P_Pos (13U)

Definition at line 10498 of file stm32g431xx.h.

◆ TIM_CCER_CC5E

#define TIM_CCER_CC5E TIM_CCER_CC5E_Msk

Capture/Compare 5 output enable

Definition at line 10509 of file stm32g431xx.h.

◆ TIM_CCER_CC5E_Msk

#define TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos)

0x00010000

Definition at line 10508 of file stm32g431xx.h.

◆ TIM_CCER_CC5E_Pos

#define TIM_CCER_CC5E_Pos (16U)

Definition at line 10507 of file stm32g431xx.h.

◆ TIM_CCER_CC5P

#define TIM_CCER_CC5P TIM_CCER_CC5P_Msk

Capture/Compare 5 output Polarity

Definition at line 10512 of file stm32g431xx.h.

◆ TIM_CCER_CC5P_Msk

#define TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos)

0x00020000

Definition at line 10511 of file stm32g431xx.h.

◆ TIM_CCER_CC5P_Pos

#define TIM_CCER_CC5P_Pos (17U)

Definition at line 10510 of file stm32g431xx.h.

◆ TIM_CCER_CC6E

#define TIM_CCER_CC6E TIM_CCER_CC6E_Msk

Capture/Compare 6 output enable

Definition at line 10515 of file stm32g431xx.h.

◆ TIM_CCER_CC6E_Msk

#define TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos)

0x00100000

Definition at line 10514 of file stm32g431xx.h.

◆ TIM_CCER_CC6E_Pos

#define TIM_CCER_CC6E_Pos (20U)

Definition at line 10513 of file stm32g431xx.h.

◆ TIM_CCER_CC6P

#define TIM_CCER_CC6P TIM_CCER_CC6P_Msk

Capture/Compare 6 output Polarity

Definition at line 10518 of file stm32g431xx.h.

◆ TIM_CCER_CC6P_Msk

#define TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos)

0x00200000

Definition at line 10517 of file stm32g431xx.h.

◆ TIM_CCER_CC6P_Pos

#define TIM_CCER_CC6P_Pos (21U)

Definition at line 10516 of file stm32g431xx.h.

◆ TIM_CCMR1_CC1S

#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk

CC1S[1:0] bits (Capture/Compare 1 Selection)

Definition at line 10262 of file stm32g431xx.h.

◆ TIM_CCMR1_CC1S_0

#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos)

0x00000001

Definition at line 10263 of file stm32g431xx.h.

◆ TIM_CCMR1_CC1S_1

#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos)

0x00000002

Definition at line 10264 of file stm32g431xx.h.

◆ TIM_CCMR1_CC1S_Msk

#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos)

0x00000003

Definition at line 10261 of file stm32g431xx.h.

◆ TIM_CCMR1_CC1S_Pos

#define TIM_CCMR1_CC1S_Pos (0U)

Definition at line 10260 of file stm32g431xx.h.

◆ TIM_CCMR1_CC2S

#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk

CC2S[1:0] bits (Capture/Compare 2 Selection)

Definition at line 10287 of file stm32g431xx.h.

◆ TIM_CCMR1_CC2S_0

#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos)

0x00000100

Definition at line 10288 of file stm32g431xx.h.

◆ TIM_CCMR1_CC2S_1

#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos)

0x00000200

Definition at line 10289 of file stm32g431xx.h.

◆ TIM_CCMR1_CC2S_Msk

#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos)

0x00000300

Definition at line 10286 of file stm32g431xx.h.

◆ TIM_CCMR1_CC2S_Pos

#define TIM_CCMR1_CC2S_Pos (8U)

Definition at line 10285 of file stm32g431xx.h.

◆ TIM_CCMR1_IC1F

#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk

IC1F[3:0] bits (Input Capture 1 Filter)

Definition at line 10319 of file stm32g431xx.h.

◆ TIM_CCMR1_IC1F_0

#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos)

0x00000010

Definition at line 10320 of file stm32g431xx.h.

◆ TIM_CCMR1_IC1F_1

#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos)

0x00000020

Definition at line 10321 of file stm32g431xx.h.

◆ TIM_CCMR1_IC1F_2

#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos)

0x00000040

Definition at line 10322 of file stm32g431xx.h.

◆ TIM_CCMR1_IC1F_3

#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos)

0x00000080

Definition at line 10323 of file stm32g431xx.h.

◆ TIM_CCMR1_IC1F_Msk

#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos)

0x000000F0

Definition at line 10318 of file stm32g431xx.h.

◆ TIM_CCMR1_IC1F_Pos

#define TIM_CCMR1_IC1F_Pos (4U)

Definition at line 10317 of file stm32g431xx.h.

◆ TIM_CCMR1_IC1PSC

#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk

IC1PSC[1:0] bits (Input Capture 1 Prescaler)

Definition at line 10313 of file stm32g431xx.h.

◆ TIM_CCMR1_IC1PSC_0

#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos)

0x00000004

Definition at line 10314 of file stm32g431xx.h.

◆ TIM_CCMR1_IC1PSC_1

#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos)

0x00000008

Definition at line 10315 of file stm32g431xx.h.

◆ TIM_CCMR1_IC1PSC_Msk

#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos)

0x0000000C

Definition at line 10312 of file stm32g431xx.h.

◆ TIM_CCMR1_IC1PSC_Pos

#define TIM_CCMR1_IC1PSC_Pos (2U)

Definition at line 10311 of file stm32g431xx.h.

◆ TIM_CCMR1_IC2F

#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk

IC2F[3:0] bits (Input Capture 2 Filter)

Definition at line 10333 of file stm32g431xx.h.

◆ TIM_CCMR1_IC2F_0

#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos)

0x00001000

Definition at line 10334 of file stm32g431xx.h.

◆ TIM_CCMR1_IC2F_1

#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos)

0x00002000

Definition at line 10335 of file stm32g431xx.h.

◆ TIM_CCMR1_IC2F_2

#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos)

0x00004000

Definition at line 10336 of file stm32g431xx.h.

◆ TIM_CCMR1_IC2F_3

#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos)

0x00008000

Definition at line 10337 of file stm32g431xx.h.

◆ TIM_CCMR1_IC2F_Msk

#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos)

0x0000F000

Definition at line 10332 of file stm32g431xx.h.

◆ TIM_CCMR1_IC2F_Pos

#define TIM_CCMR1_IC2F_Pos (12U)

Definition at line 10331 of file stm32g431xx.h.

◆ TIM_CCMR1_IC2PSC

#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk

IC2PSC[1:0] bits (Input Capture 2 Prescaler)

Definition at line 10327 of file stm32g431xx.h.

◆ TIM_CCMR1_IC2PSC_0

#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos)

0x00000400

Definition at line 10328 of file stm32g431xx.h.

◆ TIM_CCMR1_IC2PSC_1

#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos)

0x00000800

Definition at line 10329 of file stm32g431xx.h.

◆ TIM_CCMR1_IC2PSC_Msk

#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos)

0x00000C00

Definition at line 10326 of file stm32g431xx.h.

◆ TIM_CCMR1_IC2PSC_Pos

#define TIM_CCMR1_IC2PSC_Pos (10U)

Definition at line 10325 of file stm32g431xx.h.

◆ TIM_CCMR1_OC1CE

#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk

Output Compare 1 Clear Enable

Definition at line 10283 of file stm32g431xx.h.

◆ TIM_CCMR1_OC1CE_Msk

#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos)

0x00000080

Definition at line 10282 of file stm32g431xx.h.

◆ TIM_CCMR1_OC1CE_Pos

#define TIM_CCMR1_OC1CE_Pos (7U)

Definition at line 10281 of file stm32g431xx.h.

◆ TIM_CCMR1_OC1FE

#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk

Output Compare 1 Fast enable

Definition at line 10268 of file stm32g431xx.h.

◆ TIM_CCMR1_OC1FE_Msk

#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos)

0x00000004

Definition at line 10267 of file stm32g431xx.h.

◆ TIM_CCMR1_OC1FE_Pos

#define TIM_CCMR1_OC1FE_Pos (2U)

Definition at line 10266 of file stm32g431xx.h.

◆ TIM_CCMR1_OC1M

#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk

OC1M[2:0] bits (Output Compare 1 Mode)

Definition at line 10275 of file stm32g431xx.h.

◆ TIM_CCMR1_OC1M_0

#define TIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos)

0x00000010

Definition at line 10276 of file stm32g431xx.h.

◆ TIM_CCMR1_OC1M_1

#define TIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos)

0x00000020

Definition at line 10277 of file stm32g431xx.h.

◆ TIM_CCMR1_OC1M_2

#define TIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos)

0x00000040

Definition at line 10278 of file stm32g431xx.h.

◆ TIM_CCMR1_OC1M_3

#define TIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos)

0x00010000

Definition at line 10279 of file stm32g431xx.h.

◆ TIM_CCMR1_OC1M_Msk

#define TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos)

0x00010070

Definition at line 10274 of file stm32g431xx.h.

◆ TIM_CCMR1_OC1M_Pos

#define TIM_CCMR1_OC1M_Pos (4U)

Definition at line 10273 of file stm32g431xx.h.

◆ TIM_CCMR1_OC1PE

#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk

Output Compare 1 Preload enable

Definition at line 10271 of file stm32g431xx.h.

◆ TIM_CCMR1_OC1PE_Msk

#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos)

0x00000008

Definition at line 10270 of file stm32g431xx.h.

◆ TIM_CCMR1_OC1PE_Pos

#define TIM_CCMR1_OC1PE_Pos (3U)

Definition at line 10269 of file stm32g431xx.h.

◆ TIM_CCMR1_OC2CE

#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk

Output Compare 2 Clear Enable

Definition at line 10308 of file stm32g431xx.h.

◆ TIM_CCMR1_OC2CE_Msk

#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos)

0x00008000

Definition at line 10307 of file stm32g431xx.h.

◆ TIM_CCMR1_OC2CE_Pos

#define TIM_CCMR1_OC2CE_Pos (15U)

Definition at line 10306 of file stm32g431xx.h.

◆ TIM_CCMR1_OC2FE

#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk

Output Compare 2 Fast enable

Definition at line 10293 of file stm32g431xx.h.

◆ TIM_CCMR1_OC2FE_Msk

#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos)

0x00000400

Definition at line 10292 of file stm32g431xx.h.

◆ TIM_CCMR1_OC2FE_Pos

#define TIM_CCMR1_OC2FE_Pos (10U)

Definition at line 10291 of file stm32g431xx.h.

◆ TIM_CCMR1_OC2M

#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk

OC2M[2:0] bits (Output Compare 2 Mode)

Definition at line 10300 of file stm32g431xx.h.

◆ TIM_CCMR1_OC2M_0

#define TIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos)

0x00001000

Definition at line 10301 of file stm32g431xx.h.

◆ TIM_CCMR1_OC2M_1

#define TIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos)

0x00002000

Definition at line 10302 of file stm32g431xx.h.

◆ TIM_CCMR1_OC2M_2

#define TIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos)

0x00004000

Definition at line 10303 of file stm32g431xx.h.

◆ TIM_CCMR1_OC2M_3

#define TIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos)

0x01000000

Definition at line 10304 of file stm32g431xx.h.

◆ TIM_CCMR1_OC2M_Msk

#define TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos)

0x01007000

Definition at line 10299 of file stm32g431xx.h.

◆ TIM_CCMR1_OC2M_Pos

#define TIM_CCMR1_OC2M_Pos (12U)

Definition at line 10298 of file stm32g431xx.h.

◆ TIM_CCMR1_OC2PE

#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk

Output Compare 2 Preload enable

Definition at line 10296 of file stm32g431xx.h.

◆ TIM_CCMR1_OC2PE_Msk

#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos)

0x00000800

Definition at line 10295 of file stm32g431xx.h.

◆ TIM_CCMR1_OC2PE_Pos

#define TIM_CCMR1_OC2PE_Pos (11U)

Definition at line 10294 of file stm32g431xx.h.

◆ TIM_CCMR2_CC3S

#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk

CC3S[1:0] bits (Capture/Compare 3 Selection)

Definition at line 10342 of file stm32g431xx.h.

◆ TIM_CCMR2_CC3S_0

#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos)

0x00000001

Definition at line 10343 of file stm32g431xx.h.

◆ TIM_CCMR2_CC3S_1

#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos)

0x00000002

Definition at line 10344 of file stm32g431xx.h.

◆ TIM_CCMR2_CC3S_Msk

#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos)

0x00000003

Definition at line 10341 of file stm32g431xx.h.

◆ TIM_CCMR2_CC3S_Pos

#define TIM_CCMR2_CC3S_Pos (0U)

Definition at line 10340 of file stm32g431xx.h.

◆ TIM_CCMR2_CC4S

#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk

CC4S[1:0] bits (Capture/Compare 4 Selection)

Definition at line 10367 of file stm32g431xx.h.

◆ TIM_CCMR2_CC4S_0

#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos)

0x00000100

Definition at line 10368 of file stm32g431xx.h.

◆ TIM_CCMR2_CC4S_1

#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos)

0x00000200

Definition at line 10369 of file stm32g431xx.h.

◆ TIM_CCMR2_CC4S_Msk

#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos)

0x00000300

Definition at line 10366 of file stm32g431xx.h.

◆ TIM_CCMR2_CC4S_Pos

#define TIM_CCMR2_CC4S_Pos (8U)

Definition at line 10365 of file stm32g431xx.h.

◆ TIM_CCMR2_IC3F

#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk

IC3F[3:0] bits (Input Capture 3 Filter)

Definition at line 10399 of file stm32g431xx.h.

◆ TIM_CCMR2_IC3F_0

#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos)

0x00000010

Definition at line 10400 of file stm32g431xx.h.

◆ TIM_CCMR2_IC3F_1

#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos)

0x00000020

Definition at line 10401 of file stm32g431xx.h.

◆ TIM_CCMR2_IC3F_2

#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos)

0x00000040

Definition at line 10402 of file stm32g431xx.h.

◆ TIM_CCMR2_IC3F_3

#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos)

0x00000080

Definition at line 10403 of file stm32g431xx.h.

◆ TIM_CCMR2_IC3F_Msk

#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos)

0x000000F0

Definition at line 10398 of file stm32g431xx.h.

◆ TIM_CCMR2_IC3F_Pos

#define TIM_CCMR2_IC3F_Pos (4U)

Definition at line 10397 of file stm32g431xx.h.

◆ TIM_CCMR2_IC3PSC

#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk

IC3PSC[1:0] bits (Input Capture 3 Prescaler)

Definition at line 10393 of file stm32g431xx.h.

◆ TIM_CCMR2_IC3PSC_0

#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos)

0x00000004

Definition at line 10394 of file stm32g431xx.h.

◆ TIM_CCMR2_IC3PSC_1

#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos)

0x00000008

Definition at line 10395 of file stm32g431xx.h.

◆ TIM_CCMR2_IC3PSC_Msk

#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos)

0x0000000C

Definition at line 10392 of file stm32g431xx.h.

◆ TIM_CCMR2_IC3PSC_Pos

#define TIM_CCMR2_IC3PSC_Pos (2U)

Definition at line 10391 of file stm32g431xx.h.

◆ TIM_CCMR2_IC4F

#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk

IC4F[3:0] bits (Input Capture 4 Filter)

Definition at line 10413 of file stm32g431xx.h.

◆ TIM_CCMR2_IC4F_0

#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos)

0x00001000

Definition at line 10414 of file stm32g431xx.h.

◆ TIM_CCMR2_IC4F_1

#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos)

0x00002000

Definition at line 10415 of file stm32g431xx.h.

◆ TIM_CCMR2_IC4F_2

#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos)

0x00004000

Definition at line 10416 of file stm32g431xx.h.

◆ TIM_CCMR2_IC4F_3

#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos)

0x00008000

Definition at line 10417 of file stm32g431xx.h.

◆ TIM_CCMR2_IC4F_Msk

#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos)

0x0000F000

Definition at line 10412 of file stm32g431xx.h.

◆ TIM_CCMR2_IC4F_Pos

#define TIM_CCMR2_IC4F_Pos (12U)

Definition at line 10411 of file stm32g431xx.h.

◆ TIM_CCMR2_IC4PSC

#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk

IC4PSC[1:0] bits (Input Capture 4 Prescaler)

Definition at line 10407 of file stm32g431xx.h.

◆ TIM_CCMR2_IC4PSC_0

#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos)

0x00000400

Definition at line 10408 of file stm32g431xx.h.

◆ TIM_CCMR2_IC4PSC_1

#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos)

0x00000800

Definition at line 10409 of file stm32g431xx.h.

◆ TIM_CCMR2_IC4PSC_Msk

#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos)

0x00000C00

Definition at line 10406 of file stm32g431xx.h.

◆ TIM_CCMR2_IC4PSC_Pos

#define TIM_CCMR2_IC4PSC_Pos (10U)

Definition at line 10405 of file stm32g431xx.h.

◆ TIM_CCMR2_OC3CE

#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk

Output Compare 3 Clear Enable

Definition at line 10363 of file stm32g431xx.h.

◆ TIM_CCMR2_OC3CE_Msk

#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos)

0x00000080

Definition at line 10362 of file stm32g431xx.h.

◆ TIM_CCMR2_OC3CE_Pos

#define TIM_CCMR2_OC3CE_Pos (7U)

Definition at line 10361 of file stm32g431xx.h.

◆ TIM_CCMR2_OC3FE

#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk

Output Compare 3 Fast enable

Definition at line 10348 of file stm32g431xx.h.

◆ TIM_CCMR2_OC3FE_Msk

#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos)

0x00000004

Definition at line 10347 of file stm32g431xx.h.

◆ TIM_CCMR2_OC3FE_Pos

#define TIM_CCMR2_OC3FE_Pos (2U)

Definition at line 10346 of file stm32g431xx.h.

◆ TIM_CCMR2_OC3M

#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk

OC3M[2:0] bits (Output Compare 3 Mode)

Definition at line 10355 of file stm32g431xx.h.

◆ TIM_CCMR2_OC3M_0

#define TIM_CCMR2_OC3M_0 (0x0001UL << TIM_CCMR2_OC3M_Pos)

0x00000010

Definition at line 10356 of file stm32g431xx.h.

◆ TIM_CCMR2_OC3M_1

#define TIM_CCMR2_OC3M_1 (0x0002UL << TIM_CCMR2_OC3M_Pos)

0x00000020

Definition at line 10357 of file stm32g431xx.h.

◆ TIM_CCMR2_OC3M_2

#define TIM_CCMR2_OC3M_2 (0x0004UL << TIM_CCMR2_OC3M_Pos)

0x00000040

Definition at line 10358 of file stm32g431xx.h.

◆ TIM_CCMR2_OC3M_3

#define TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos)

0x00010000

Definition at line 10359 of file stm32g431xx.h.

◆ TIM_CCMR2_OC3M_Msk

#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos)

0x00010070

Definition at line 10354 of file stm32g431xx.h.

◆ TIM_CCMR2_OC3M_Pos

#define TIM_CCMR2_OC3M_Pos (4U)

Definition at line 10353 of file stm32g431xx.h.

◆ TIM_CCMR2_OC3PE

#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk

Output Compare 3 Preload enable

Definition at line 10351 of file stm32g431xx.h.

◆ TIM_CCMR2_OC3PE_Msk

#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos)

0x00000008

Definition at line 10350 of file stm32g431xx.h.

◆ TIM_CCMR2_OC3PE_Pos

#define TIM_CCMR2_OC3PE_Pos (3U)

Definition at line 10349 of file stm32g431xx.h.

◆ TIM_CCMR2_OC4CE

#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk

Output Compare 4 Clear Enable

Definition at line 10388 of file stm32g431xx.h.

◆ TIM_CCMR2_OC4CE_Msk

#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos)

0x00008000

Definition at line 10387 of file stm32g431xx.h.

◆ TIM_CCMR2_OC4CE_Pos

#define TIM_CCMR2_OC4CE_Pos (15U)

Definition at line 10386 of file stm32g431xx.h.

◆ TIM_CCMR2_OC4FE

#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk

Output Compare 4 Fast enable

Definition at line 10373 of file stm32g431xx.h.

◆ TIM_CCMR2_OC4FE_Msk

#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos)

0x00000400

Definition at line 10372 of file stm32g431xx.h.

◆ TIM_CCMR2_OC4FE_Pos

#define TIM_CCMR2_OC4FE_Pos (10U)

Definition at line 10371 of file stm32g431xx.h.

◆ TIM_CCMR2_OC4M

#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk

OC4M[2:0] bits (Output Compare 4 Mode)

Definition at line 10380 of file stm32g431xx.h.

◆ TIM_CCMR2_OC4M_0

#define TIM_CCMR2_OC4M_0 (0x0001UL << TIM_CCMR2_OC4M_Pos)

0x00001000

Definition at line 10381 of file stm32g431xx.h.

◆ TIM_CCMR2_OC4M_1

#define TIM_CCMR2_OC4M_1 (0x0002UL << TIM_CCMR2_OC4M_Pos)

0x00002000

Definition at line 10382 of file stm32g431xx.h.

◆ TIM_CCMR2_OC4M_2

#define TIM_CCMR2_OC4M_2 (0x0004UL << TIM_CCMR2_OC4M_Pos)

0x00004000

Definition at line 10383 of file stm32g431xx.h.

◆ TIM_CCMR2_OC4M_3

#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos)

0x01000000

Definition at line 10384 of file stm32g431xx.h.

◆ TIM_CCMR2_OC4M_Msk

#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos)

0x01007000

Definition at line 10379 of file stm32g431xx.h.

◆ TIM_CCMR2_OC4M_Pos

#define TIM_CCMR2_OC4M_Pos (12U)

Definition at line 10378 of file stm32g431xx.h.

◆ TIM_CCMR2_OC4PE

#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk

Output Compare 4 Preload enable

Definition at line 10376 of file stm32g431xx.h.

◆ TIM_CCMR2_OC4PE_Msk

#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos)

0x00000800

Definition at line 10375 of file stm32g431xx.h.

◆ TIM_CCMR2_OC4PE_Pos

#define TIM_CCMR2_OC4PE_Pos (11U)

Definition at line 10374 of file stm32g431xx.h.

◆ TIM_CCMR3_OC5CE

#define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk

Output Compare 5 Clear Enable

Definition at line 10437 of file stm32g431xx.h.

◆ TIM_CCMR3_OC5CE_Msk

#define TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos)

0x00000080

Definition at line 10436 of file stm32g431xx.h.

◆ TIM_CCMR3_OC5CE_Pos

#define TIM_CCMR3_OC5CE_Pos (7U)

Definition at line 10435 of file stm32g431xx.h.

◆ TIM_CCMR3_OC5FE

#define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk

Output Compare 5 Fast enable

Definition at line 10422 of file stm32g431xx.h.

◆ TIM_CCMR3_OC5FE_Msk

#define TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos)

0x00000004

Definition at line 10421 of file stm32g431xx.h.

◆ TIM_CCMR3_OC5FE_Pos

#define TIM_CCMR3_OC5FE_Pos (2U)

Definition at line 10420 of file stm32g431xx.h.

◆ TIM_CCMR3_OC5M

#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk

OC5M[3:0] bits (Output Compare 5 Mode)

Definition at line 10429 of file stm32g431xx.h.

◆ TIM_CCMR3_OC5M_0

#define TIM_CCMR3_OC5M_0 (0x0001UL << TIM_CCMR3_OC5M_Pos)

0x00000010

Definition at line 10430 of file stm32g431xx.h.

◆ TIM_CCMR3_OC5M_1

#define TIM_CCMR3_OC5M_1 (0x0002UL << TIM_CCMR3_OC5M_Pos)

0x00000020

Definition at line 10431 of file stm32g431xx.h.

◆ TIM_CCMR3_OC5M_2

#define TIM_CCMR3_OC5M_2 (0x0004UL << TIM_CCMR3_OC5M_Pos)

0x00000040

Definition at line 10432 of file stm32g431xx.h.

◆ TIM_CCMR3_OC5M_3

#define TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos)

0x00010000

Definition at line 10433 of file stm32g431xx.h.

◆ TIM_CCMR3_OC5M_Msk

#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos)

0x00010070

Definition at line 10428 of file stm32g431xx.h.

◆ TIM_CCMR3_OC5M_Pos

#define TIM_CCMR3_OC5M_Pos (4U)

Definition at line 10427 of file stm32g431xx.h.

◆ TIM_CCMR3_OC5PE

#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk

Output Compare 5 Preload enable

Definition at line 10425 of file stm32g431xx.h.

◆ TIM_CCMR3_OC5PE_Msk

#define TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos)

0x00000008

Definition at line 10424 of file stm32g431xx.h.

◆ TIM_CCMR3_OC5PE_Pos

#define TIM_CCMR3_OC5PE_Pos (3U)

Definition at line 10423 of file stm32g431xx.h.

◆ TIM_CCMR3_OC6CE

#define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk

Output Compare 6 Clear Enable

Definition at line 10456 of file stm32g431xx.h.

◆ TIM_CCMR3_OC6CE_Msk

#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos)

0x00008000

Definition at line 10455 of file stm32g431xx.h.

◆ TIM_CCMR3_OC6CE_Pos

#define TIM_CCMR3_OC6CE_Pos (15U)

Definition at line 10454 of file stm32g431xx.h.

◆ TIM_CCMR3_OC6FE

#define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk

Output Compare 6 Fast enable

Definition at line 10441 of file stm32g431xx.h.

◆ TIM_CCMR3_OC6FE_Msk

#define TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos)

0x00000400

Definition at line 10440 of file stm32g431xx.h.

◆ TIM_CCMR3_OC6FE_Pos

#define TIM_CCMR3_OC6FE_Pos (10U)

Definition at line 10439 of file stm32g431xx.h.

◆ TIM_CCMR3_OC6M

#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk

OC6M[3:0] bits (Output Compare 6 Mode)

Definition at line 10448 of file stm32g431xx.h.

◆ TIM_CCMR3_OC6M_0

#define TIM_CCMR3_OC6M_0 (0x0001UL << TIM_CCMR3_OC6M_Pos)

0x00001000

Definition at line 10449 of file stm32g431xx.h.

◆ TIM_CCMR3_OC6M_1

#define TIM_CCMR3_OC6M_1 (0x0002UL << TIM_CCMR3_OC6M_Pos)

0x00002000

Definition at line 10450 of file stm32g431xx.h.

◆ TIM_CCMR3_OC6M_2

#define TIM_CCMR3_OC6M_2 (0x0004UL << TIM_CCMR3_OC6M_Pos)

0x00004000

Definition at line 10451 of file stm32g431xx.h.

◆ TIM_CCMR3_OC6M_3

#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos)

0x01000000

Definition at line 10452 of file stm32g431xx.h.

◆ TIM_CCMR3_OC6M_Msk

#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos)

0x01007000

Definition at line 10447 of file stm32g431xx.h.

◆ TIM_CCMR3_OC6M_Pos

#define TIM_CCMR3_OC6M_Pos (12U)

Definition at line 10446 of file stm32g431xx.h.

◆ TIM_CCMR3_OC6PE

#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk

Output Compare 6 Preload enable

Definition at line 10444 of file stm32g431xx.h.

◆ TIM_CCMR3_OC6PE_Msk

#define TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos)

0x00000800

Definition at line 10443 of file stm32g431xx.h.

◆ TIM_CCMR3_OC6PE_Pos

#define TIM_CCMR3_OC6PE_Pos (11U)

Definition at line 10442 of file stm32g431xx.h.

◆ TIM_CCR1_CCR1

#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk

Capture/Compare 1 Value

Definition at line 10546 of file stm32g431xx.h.

◆ TIM_CCR1_CCR1_Msk

#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos)

0x0000FFFF

Definition at line 10545 of file stm32g431xx.h.

◆ TIM_CCR1_CCR1_Pos

#define TIM_CCR1_CCR1_Pos (0U)

Definition at line 10544 of file stm32g431xx.h.

◆ TIM_CCR2_CCR2

#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk

Capture/Compare 2 Value

Definition at line 10551 of file stm32g431xx.h.

◆ TIM_CCR2_CCR2_Msk

#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos)

0x0000FFFF

Definition at line 10550 of file stm32g431xx.h.

◆ TIM_CCR2_CCR2_Pos

#define TIM_CCR2_CCR2_Pos (0U)

Definition at line 10549 of file stm32g431xx.h.

◆ TIM_CCR3_CCR3

#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk

Capture/Compare 3 Value

Definition at line 10556 of file stm32g431xx.h.

◆ TIM_CCR3_CCR3_Msk

#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos)

0x0000FFFF

Definition at line 10555 of file stm32g431xx.h.

◆ TIM_CCR3_CCR3_Pos

#define TIM_CCR3_CCR3_Pos (0U)

Definition at line 10554 of file stm32g431xx.h.

◆ TIM_CCR4_CCR4

#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk

Capture/Compare 4 Value

Definition at line 10561 of file stm32g431xx.h.

◆ TIM_CCR4_CCR4_Msk

#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos)

0x0000FFFF

Definition at line 10560 of file stm32g431xx.h.

◆ TIM_CCR4_CCR4_Pos

#define TIM_CCR4_CCR4_Pos (0U)

Definition at line 10559 of file stm32g431xx.h.

◆ TIM_CCR5_CCR5

#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk

Capture/Compare 5 Value

Definition at line 10566 of file stm32g431xx.h.

◆ TIM_CCR5_CCR5_Msk

#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)

0xFFFFFFFF

Definition at line 10565 of file stm32g431xx.h.

◆ TIM_CCR5_CCR5_Pos

#define TIM_CCR5_CCR5_Pos (0U)

Definition at line 10564 of file stm32g431xx.h.

◆ TIM_CCR5_GC5C1

#define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk

Group Channel 5 and Channel 1

Definition at line 10569 of file stm32g431xx.h.

◆ TIM_CCR5_GC5C1_Msk

#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos)

0x20000000

Definition at line 10568 of file stm32g431xx.h.

◆ TIM_CCR5_GC5C1_Pos

#define TIM_CCR5_GC5C1_Pos (29U)

Definition at line 10567 of file stm32g431xx.h.

◆ TIM_CCR5_GC5C2

#define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk

Group Channel 5 and Channel 2

Definition at line 10572 of file stm32g431xx.h.

◆ TIM_CCR5_GC5C2_Msk

#define TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos)

0x40000000

Definition at line 10571 of file stm32g431xx.h.

◆ TIM_CCR5_GC5C2_Pos

#define TIM_CCR5_GC5C2_Pos (30U)

Definition at line 10570 of file stm32g431xx.h.

◆ TIM_CCR5_GC5C3

#define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk

Group Channel 5 and Channel 3

Definition at line 10575 of file stm32g431xx.h.

◆ TIM_CCR5_GC5C3_Msk

#define TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos)

0x80000000

Definition at line 10574 of file stm32g431xx.h.

◆ TIM_CCR5_GC5C3_Pos

#define TIM_CCR5_GC5C3_Pos (31U)

Definition at line 10573 of file stm32g431xx.h.

◆ TIM_CCR6_CCR6

#define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk

Capture/Compare 6 Value

Definition at line 10580 of file stm32g431xx.h.

◆ TIM_CCR6_CCR6_Msk

#define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos)

0x0000FFFF

Definition at line 10579 of file stm32g431xx.h.

◆ TIM_CCR6_CCR6_Pos

#define TIM_CCR6_CCR6_Pos (0U)

Definition at line 10578 of file stm32g431xx.h.

◆ TIM_CNT_CNT

#define TIM_CNT_CNT TIM_CNT_CNT_Msk

Counter Value

Definition at line 10523 of file stm32g431xx.h.

◆ TIM_CNT_CNT_Msk

#define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)

0xFFFFFFFF

Definition at line 10522 of file stm32g431xx.h.

◆ TIM_CNT_CNT_Pos

#define TIM_CNT_CNT_Pos (0U)

Definition at line 10521 of file stm32g431xx.h.

◆ TIM_CNT_UIFCPY

#define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk

Update interrupt flag copy (if UIFREMAP=1)

Definition at line 10526 of file stm32g431xx.h.

◆ TIM_CNT_UIFCPY_Msk

#define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos)

0x80000000

Definition at line 10525 of file stm32g431xx.h.

◆ TIM_CNT_UIFCPY_Pos

#define TIM_CNT_UIFCPY_Pos (31U)

Definition at line 10524 of file stm32g431xx.h.

◆ TIM_CR1_ARPE

#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk

Auto-reload preload enable

Definition at line 9976 of file stm32g431xx.h.

◆ TIM_CR1_ARPE_Msk

#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos)

0x00000080

Definition at line 9975 of file stm32g431xx.h.

◆ TIM_CR1_ARPE_Pos

#define TIM_CR1_ARPE_Pos (7U)

Definition at line 9974 of file stm32g431xx.h.

◆ TIM_CR1_CEN

#define TIM_CR1_CEN TIM_CR1_CEN_Msk

Counter enable

Definition at line 9954 of file stm32g431xx.h.

◆ TIM_CR1_CEN_Msk

#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos)

0x00000001

Definition at line 9953 of file stm32g431xx.h.

◆ TIM_CR1_CEN_Pos

#define TIM_CR1_CEN_Pos (0U)

Definition at line 9952 of file stm32g431xx.h.

◆ TIM_CR1_CKD

#define TIM_CR1_CKD TIM_CR1_CKD_Msk

CKD[1:0] bits (clock division)

Definition at line 9980 of file stm32g431xx.h.

◆ TIM_CR1_CKD_0

#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos)

0x00000100

Definition at line 9981 of file stm32g431xx.h.

◆ TIM_CR1_CKD_1

#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos)

0x00000200

Definition at line 9982 of file stm32g431xx.h.

◆ TIM_CR1_CKD_Msk

#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos)

0x00000300

Definition at line 9979 of file stm32g431xx.h.

◆ TIM_CR1_CKD_Pos

#define TIM_CR1_CKD_Pos (8U)

Definition at line 9978 of file stm32g431xx.h.

◆ TIM_CR1_CMS

#define TIM_CR1_CMS TIM_CR1_CMS_Msk

CMS[1:0] bits (Center-aligned mode selection)

Definition at line 9970 of file stm32g431xx.h.

◆ TIM_CR1_CMS_0

#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos)

0x00000020

Definition at line 9971 of file stm32g431xx.h.

◆ TIM_CR1_CMS_1

#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos)

0x00000040

Definition at line 9972 of file stm32g431xx.h.

◆ TIM_CR1_CMS_Msk

#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos)

0x00000060

Definition at line 9969 of file stm32g431xx.h.

◆ TIM_CR1_CMS_Pos

#define TIM_CR1_CMS_Pos (5U)

Definition at line 9968 of file stm32g431xx.h.

◆ TIM_CR1_DIR

#define TIM_CR1_DIR TIM_CR1_DIR_Msk

Direction

Definition at line 9966 of file stm32g431xx.h.

◆ TIM_CR1_DIR_Msk

#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos)

0x00000010

Definition at line 9965 of file stm32g431xx.h.

◆ TIM_CR1_DIR_Pos

#define TIM_CR1_DIR_Pos (4U)

Definition at line 9964 of file stm32g431xx.h.

◆ TIM_CR1_DITHEN

#define TIM_CR1_DITHEN TIM_CR1_DITHEN_Msk

Dithering enable

Definition at line 9990 of file stm32g431xx.h.

◆ TIM_CR1_DITHEN_Msk

#define TIM_CR1_DITHEN_Msk (0x1UL << TIM_CR1_DITHEN_Pos)

0x00001000

Definition at line 9989 of file stm32g431xx.h.

◆ TIM_CR1_DITHEN_Pos

#define TIM_CR1_DITHEN_Pos (12U)

Definition at line 9988 of file stm32g431xx.h.

◆ TIM_CR1_OPM

#define TIM_CR1_OPM TIM_CR1_OPM_Msk

One pulse mode

Definition at line 9963 of file stm32g431xx.h.

◆ TIM_CR1_OPM_Msk

#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos)

0x00000008

Definition at line 9962 of file stm32g431xx.h.

◆ TIM_CR1_OPM_Pos

#define TIM_CR1_OPM_Pos (3U)

Definition at line 9961 of file stm32g431xx.h.

◆ TIM_CR1_UDIS

#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk

Update disable

Definition at line 9957 of file stm32g431xx.h.

◆ TIM_CR1_UDIS_Msk

#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos)

0x00000002

Definition at line 9956 of file stm32g431xx.h.

◆ TIM_CR1_UDIS_Pos

#define TIM_CR1_UDIS_Pos (1U)

Definition at line 9955 of file stm32g431xx.h.

◆ TIM_CR1_UIFREMAP

#define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk

Update interrupt flag remap

Definition at line 9986 of file stm32g431xx.h.

◆ TIM_CR1_UIFREMAP_Msk

#define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos)

0x00000800

Definition at line 9985 of file stm32g431xx.h.

◆ TIM_CR1_UIFREMAP_Pos

#define TIM_CR1_UIFREMAP_Pos (11U)

Definition at line 9984 of file stm32g431xx.h.

◆ TIM_CR1_URS

#define TIM_CR1_URS TIM_CR1_URS_Msk

Update request source

Definition at line 9960 of file stm32g431xx.h.

◆ TIM_CR1_URS_Msk

#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos)

0x00000004

Definition at line 9959 of file stm32g431xx.h.

◆ TIM_CR1_URS_Pos

#define TIM_CR1_URS_Pos (2U)

Definition at line 9958 of file stm32g431xx.h.

◆ TIM_CR2_CCDS

#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk

Capture/Compare DMA Selection

Definition at line 10001 of file stm32g431xx.h.

◆ TIM_CR2_CCDS_Msk

#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos)

0x00000008

Definition at line 10000 of file stm32g431xx.h.

◆ TIM_CR2_CCDS_Pos

#define TIM_CR2_CCDS_Pos (3U)

Definition at line 9999 of file stm32g431xx.h.

◆ TIM_CR2_CCPC

#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk

Capture/Compare Preloaded Control

Definition at line 9995 of file stm32g431xx.h.

◆ TIM_CR2_CCPC_Msk

#define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos)

0x00000001

Definition at line 9994 of file stm32g431xx.h.

◆ TIM_CR2_CCPC_Pos

#define TIM_CR2_CCPC_Pos (0U)

Definition at line 9993 of file stm32g431xx.h.

◆ TIM_CR2_CCUS

#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk

Capture/Compare Control Update Selection

Definition at line 9998 of file stm32g431xx.h.

◆ TIM_CR2_CCUS_Msk

#define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos)

0x00000004

Definition at line 9997 of file stm32g431xx.h.

◆ TIM_CR2_CCUS_Pos

#define TIM_CR2_CCUS_Pos (2U)

Definition at line 9996 of file stm32g431xx.h.

◆ TIM_CR2_MMS

#define TIM_CR2_MMS TIM_CR2_MMS_Msk

MMS[3:0] bits (Master Mode Selection)

Definition at line 10005 of file stm32g431xx.h.

◆ TIM_CR2_MMS2

#define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk

MMS[2:0] bits (Master Mode Selection)

Definition at line 10047 of file stm32g431xx.h.

◆ TIM_CR2_MMS2_0

#define TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos)

0x00100000

Definition at line 10048 of file stm32g431xx.h.

◆ TIM_CR2_MMS2_1

#define TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos)

0x00200000

Definition at line 10049 of file stm32g431xx.h.

◆ TIM_CR2_MMS2_2

#define TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos)

0x00400000

Definition at line 10050 of file stm32g431xx.h.

◆ TIM_CR2_MMS2_3

#define TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos)

0x00800000

Definition at line 10051 of file stm32g431xx.h.

◆ TIM_CR2_MMS2_Msk

#define TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos)

0x00F00000

Definition at line 10046 of file stm32g431xx.h.

◆ TIM_CR2_MMS2_Pos

#define TIM_CR2_MMS2_Pos (20U)

Definition at line 10045 of file stm32g431xx.h.

◆ TIM_CR2_MMS_0

#define TIM_CR2_MMS_0 (0x000001UL << TIM_CR2_MMS_Pos)

0x00000010

Definition at line 10006 of file stm32g431xx.h.

◆ TIM_CR2_MMS_1

#define TIM_CR2_MMS_1 (0x000002UL << TIM_CR2_MMS_Pos)

0x00000020

Definition at line 10007 of file stm32g431xx.h.

◆ TIM_CR2_MMS_2

#define TIM_CR2_MMS_2 (0x000004UL << TIM_CR2_MMS_Pos)

0x00000040

Definition at line 10008 of file stm32g431xx.h.

◆ TIM_CR2_MMS_3

#define TIM_CR2_MMS_3 (0x200000UL << TIM_CR2_MMS_Pos)

0x02000000

Definition at line 10009 of file stm32g431xx.h.

◆ TIM_CR2_MMS_Msk

#define TIM_CR2_MMS_Msk (0x200007UL << TIM_CR2_MMS_Pos)

0x02000070

Definition at line 10004 of file stm32g431xx.h.

◆ TIM_CR2_MMS_Pos

#define TIM_CR2_MMS_Pos (4U)

Definition at line 10003 of file stm32g431xx.h.

◆ TIM_CR2_OIS1

#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk

Output Idle state 1 (OC1 output)

Definition at line 10016 of file stm32g431xx.h.

◆ TIM_CR2_OIS1_Msk

#define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos)

0x00000100

Definition at line 10015 of file stm32g431xx.h.

◆ TIM_CR2_OIS1_Pos

#define TIM_CR2_OIS1_Pos (8U)

Definition at line 10014 of file stm32g431xx.h.

◆ TIM_CR2_OIS1N

#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk

Output Idle state 1 (OC1N output)

Definition at line 10019 of file stm32g431xx.h.

◆ TIM_CR2_OIS1N_Msk

#define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos)

0x00000200

Definition at line 10018 of file stm32g431xx.h.

◆ TIM_CR2_OIS1N_Pos

#define TIM_CR2_OIS1N_Pos (9U)

Definition at line 10017 of file stm32g431xx.h.

◆ TIM_CR2_OIS2

#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk

Output Idle state 2 (OC2 output)

Definition at line 10022 of file stm32g431xx.h.

◆ TIM_CR2_OIS2_Msk

#define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos)

0x00000400

Definition at line 10021 of file stm32g431xx.h.

◆ TIM_CR2_OIS2_Pos

#define TIM_CR2_OIS2_Pos (10U)

Definition at line 10020 of file stm32g431xx.h.

◆ TIM_CR2_OIS2N

#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk

Output Idle state 2 (OC2N output)

Definition at line 10025 of file stm32g431xx.h.

◆ TIM_CR2_OIS2N_Msk

#define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos)

0x00000800

Definition at line 10024 of file stm32g431xx.h.

◆ TIM_CR2_OIS2N_Pos

#define TIM_CR2_OIS2N_Pos (11U)

Definition at line 10023 of file stm32g431xx.h.

◆ TIM_CR2_OIS3

#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk

Output Idle state 3 (OC3 output)

Definition at line 10028 of file stm32g431xx.h.

◆ TIM_CR2_OIS3_Msk

#define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos)

0x00001000

Definition at line 10027 of file stm32g431xx.h.

◆ TIM_CR2_OIS3_Pos

#define TIM_CR2_OIS3_Pos (12U)

Definition at line 10026 of file stm32g431xx.h.

◆ TIM_CR2_OIS3N

#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk

Output Idle state 3 (OC3N output)

Definition at line 10031 of file stm32g431xx.h.

◆ TIM_CR2_OIS3N_Msk

#define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos)

0x00002000

Definition at line 10030 of file stm32g431xx.h.

◆ TIM_CR2_OIS3N_Pos

#define TIM_CR2_OIS3N_Pos (13U)

Definition at line 10029 of file stm32g431xx.h.

◆ TIM_CR2_OIS4

#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk

Output Idle state 4 (OC4 output)

Definition at line 10034 of file stm32g431xx.h.

◆ TIM_CR2_OIS4_Msk

#define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos)

0x00004000

Definition at line 10033 of file stm32g431xx.h.

◆ TIM_CR2_OIS4_Pos

#define TIM_CR2_OIS4_Pos (14U)

Definition at line 10032 of file stm32g431xx.h.

◆ TIM_CR2_OIS4N

#define TIM_CR2_OIS4N TIM_CR2_OIS4N_Msk

Output Idle state 4 (OC4N output)

Definition at line 10037 of file stm32g431xx.h.

◆ TIM_CR2_OIS4N_Msk

#define TIM_CR2_OIS4N_Msk (0x1UL << TIM_CR2_OIS4N_Pos)

0x00008000

Definition at line 10036 of file stm32g431xx.h.

◆ TIM_CR2_OIS4N_Pos

#define TIM_CR2_OIS4N_Pos (15U)

Definition at line 10035 of file stm32g431xx.h.

◆ TIM_CR2_OIS5

#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk

Output Idle state 5 (OC5 output)

Definition at line 10040 of file stm32g431xx.h.

◆ TIM_CR2_OIS5_Msk

#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos)

0x00010000

Definition at line 10039 of file stm32g431xx.h.

◆ TIM_CR2_OIS5_Pos

#define TIM_CR2_OIS5_Pos (16U)

Definition at line 10038 of file stm32g431xx.h.

◆ TIM_CR2_OIS6

#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk

Output Idle state 6 (OC6 output)

Definition at line 10043 of file stm32g431xx.h.

◆ TIM_CR2_OIS6_Msk

#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos)

0x00040000

Definition at line 10042 of file stm32g431xx.h.

◆ TIM_CR2_OIS6_Pos

#define TIM_CR2_OIS6_Pos (18U)

Definition at line 10041 of file stm32g431xx.h.

◆ TIM_CR2_TI1S

#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk

TI1 Selection

Definition at line 10013 of file stm32g431xx.h.

◆ TIM_CR2_TI1S_Msk

#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos)

0x00000080

Definition at line 10012 of file stm32g431xx.h.

◆ TIM_CR2_TI1S_Pos

#define TIM_CR2_TI1S_Pos (7U)

Definition at line 10011 of file stm32g431xx.h.

◆ TIM_DCR_DBA

#define TIM_DCR_DBA TIM_DCR_DBA_Msk

DBA[4:0] bits (DMA Base Address)

Definition at line 10651 of file stm32g431xx.h.

◆ TIM_DCR_DBA_0

#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos)

0x00000001

Definition at line 10652 of file stm32g431xx.h.

◆ TIM_DCR_DBA_1

#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos)

0x00000002

Definition at line 10653 of file stm32g431xx.h.

◆ TIM_DCR_DBA_2

#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos)

0x00000004

Definition at line 10654 of file stm32g431xx.h.

◆ TIM_DCR_DBA_3

#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos)

0x00000008

Definition at line 10655 of file stm32g431xx.h.

◆ TIM_DCR_DBA_4

#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos)

0x00000010

Definition at line 10656 of file stm32g431xx.h.

◆ TIM_DCR_DBA_Msk

#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos)

0x0000001F

Definition at line 10650 of file stm32g431xx.h.

◆ TIM_DCR_DBA_Pos

#define TIM_DCR_DBA_Pos (0U)

Definition at line 10649 of file stm32g431xx.h.

◆ TIM_DCR_DBL

#define TIM_DCR_DBL TIM_DCR_DBL_Msk

DBL[4:0] bits (DMA Burst Length)

Definition at line 10660 of file stm32g431xx.h.

◆ TIM_DCR_DBL_0

#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos)

0x00000100

Definition at line 10661 of file stm32g431xx.h.

◆ TIM_DCR_DBL_1

#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos)

0x00000200

Definition at line 10662 of file stm32g431xx.h.

◆ TIM_DCR_DBL_2

#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos)

0x00000400

Definition at line 10663 of file stm32g431xx.h.

◆ TIM_DCR_DBL_3

#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos)

0x00000800

Definition at line 10664 of file stm32g431xx.h.

◆ TIM_DCR_DBL_4

#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos)

0x00001000

Definition at line 10665 of file stm32g431xx.h.

◆ TIM_DCR_DBL_Msk

#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos)

0x00001F00

Definition at line 10659 of file stm32g431xx.h.

◆ TIM_DCR_DBL_Pos

#define TIM_DCR_DBL_Pos (8U)

Definition at line 10658 of file stm32g431xx.h.

◆ TIM_DIER_BIE

#define TIM_DIER_BIE TIM_DIER_BIE_Msk

Break interrupt enable

Definition at line 10132 of file stm32g431xx.h.

◆ TIM_DIER_BIE_Msk

#define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos)

0x00000080

Definition at line 10131 of file stm32g431xx.h.

◆ TIM_DIER_BIE_Pos

#define TIM_DIER_BIE_Pos (7U)

Definition at line 10130 of file stm32g431xx.h.

◆ TIM_DIER_CC1DE

#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk

Capture/Compare 1 DMA request enable

Definition at line 10138 of file stm32g431xx.h.

◆ TIM_DIER_CC1DE_Msk

#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos)

0x00000200

Definition at line 10137 of file stm32g431xx.h.

◆ TIM_DIER_CC1DE_Pos

#define TIM_DIER_CC1DE_Pos (9U)

Definition at line 10136 of file stm32g431xx.h.

◆ TIM_DIER_CC1IE

#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk

Capture/Compare 1 interrupt enable

Definition at line 10114 of file stm32g431xx.h.

◆ TIM_DIER_CC1IE_Msk

#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos)

0x00000002

Definition at line 10113 of file stm32g431xx.h.

◆ TIM_DIER_CC1IE_Pos

#define TIM_DIER_CC1IE_Pos (1U)

Definition at line 10112 of file stm32g431xx.h.

◆ TIM_DIER_CC2DE

#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk

Capture/Compare 2 DMA request enable

Definition at line 10141 of file stm32g431xx.h.

◆ TIM_DIER_CC2DE_Msk

#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos)

0x00000400

Definition at line 10140 of file stm32g431xx.h.

◆ TIM_DIER_CC2DE_Pos

#define TIM_DIER_CC2DE_Pos (10U)

Definition at line 10139 of file stm32g431xx.h.

◆ TIM_DIER_CC2IE

#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk

Capture/Compare 2 interrupt enable

Definition at line 10117 of file stm32g431xx.h.

◆ TIM_DIER_CC2IE_Msk

#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos)

0x00000004

Definition at line 10116 of file stm32g431xx.h.

◆ TIM_DIER_CC2IE_Pos

#define TIM_DIER_CC2IE_Pos (2U)

Definition at line 10115 of file stm32g431xx.h.

◆ TIM_DIER_CC3DE

#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk

Capture/Compare 3 DMA request enable

Definition at line 10144 of file stm32g431xx.h.

◆ TIM_DIER_CC3DE_Msk

#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos)

0x00000800

Definition at line 10143 of file stm32g431xx.h.

◆ TIM_DIER_CC3DE_Pos

#define TIM_DIER_CC3DE_Pos (11U)

Definition at line 10142 of file stm32g431xx.h.

◆ TIM_DIER_CC3IE

#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk

Capture/Compare 3 interrupt enable

Definition at line 10120 of file stm32g431xx.h.

◆ TIM_DIER_CC3IE_Msk

#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos)

0x00000008

Definition at line 10119 of file stm32g431xx.h.

◆ TIM_DIER_CC3IE_Pos

#define TIM_DIER_CC3IE_Pos (3U)

Definition at line 10118 of file stm32g431xx.h.

◆ TIM_DIER_CC4DE

#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk

Capture/Compare 4 DMA request enable

Definition at line 10147 of file stm32g431xx.h.

◆ TIM_DIER_CC4DE_Msk

#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos)

0x00001000

Definition at line 10146 of file stm32g431xx.h.

◆ TIM_DIER_CC4DE_Pos

#define TIM_DIER_CC4DE_Pos (12U)

Definition at line 10145 of file stm32g431xx.h.

◆ TIM_DIER_CC4IE

#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk

Capture/Compare 4 interrupt enable

Definition at line 10123 of file stm32g431xx.h.

◆ TIM_DIER_CC4IE_Msk

#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos)

0x00000010

Definition at line 10122 of file stm32g431xx.h.

◆ TIM_DIER_CC4IE_Pos

#define TIM_DIER_CC4IE_Pos (4U)

Definition at line 10121 of file stm32g431xx.h.

◆ TIM_DIER_COMDE

#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk

COM DMA request enable

Definition at line 10150 of file stm32g431xx.h.

◆ TIM_DIER_COMDE_Msk

#define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos)

0x00002000

Definition at line 10149 of file stm32g431xx.h.

◆ TIM_DIER_COMDE_Pos

#define TIM_DIER_COMDE_Pos (13U)

Definition at line 10148 of file stm32g431xx.h.

◆ TIM_DIER_COMIE

#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk

COM interrupt enable

Definition at line 10126 of file stm32g431xx.h.

◆ TIM_DIER_COMIE_Msk

#define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos)

0x00000020

Definition at line 10125 of file stm32g431xx.h.

◆ TIM_DIER_COMIE_Pos

#define TIM_DIER_COMIE_Pos (5U)

Definition at line 10124 of file stm32g431xx.h.

◆ TIM_DIER_DIRIE

#define TIM_DIER_DIRIE TIM_DIER_DIRIE_Msk

Encoder direction change interrupt enable

Definition at line 10159 of file stm32g431xx.h.

◆ TIM_DIER_DIRIE_Msk

#define TIM_DIER_DIRIE_Msk (0x1UL << TIM_DIER_DIRIE_Pos)

0x00200000

Definition at line 10158 of file stm32g431xx.h.

◆ TIM_DIER_DIRIE_Pos

#define TIM_DIER_DIRIE_Pos (21U)

Definition at line 10157 of file stm32g431xx.h.

◆ TIM_DIER_IDXIE

#define TIM_DIER_IDXIE TIM_DIER_IDXIE_Msk

Encoder index interrupt enable

Definition at line 10156 of file stm32g431xx.h.

◆ TIM_DIER_IDXIE_Msk

#define TIM_DIER_IDXIE_Msk (0x1UL << TIM_DIER_IDXIE_Pos)

0x00100000

Definition at line 10155 of file stm32g431xx.h.

◆ TIM_DIER_IDXIE_Pos

#define TIM_DIER_IDXIE_Pos (20U)

Definition at line 10154 of file stm32g431xx.h.

◆ TIM_DIER_IERRIE

#define TIM_DIER_IERRIE TIM_DIER_IERRIE_Msk

Encoder index error enable

Definition at line 10162 of file stm32g431xx.h.

◆ TIM_DIER_IERRIE_Msk

#define TIM_DIER_IERRIE_Msk (0x1UL << TIM_DIER_IERRIE_Pos)

0x00400000

Definition at line 10161 of file stm32g431xx.h.

◆ TIM_DIER_IERRIE_Pos

#define TIM_DIER_IERRIE_Pos (22U)

Definition at line 10160 of file stm32g431xx.h.

◆ TIM_DIER_TDE

#define TIM_DIER_TDE TIM_DIER_TDE_Msk

Trigger DMA request enable

Definition at line 10153 of file stm32g431xx.h.

◆ TIM_DIER_TDE_Msk

#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos)

0x00004000

Definition at line 10152 of file stm32g431xx.h.

◆ TIM_DIER_TDE_Pos

#define TIM_DIER_TDE_Pos (14U)

Definition at line 10151 of file stm32g431xx.h.

◆ TIM_DIER_TERRIE

#define TIM_DIER_TERRIE TIM_DIER_TERRIE_Msk

Encoder transition error enable

Definition at line 10165 of file stm32g431xx.h.

◆ TIM_DIER_TERRIE_Msk

#define TIM_DIER_TERRIE_Msk (0x1UL << TIM_DIER_TERRIE_Pos)

0x00800000

Definition at line 10164 of file stm32g431xx.h.

◆ TIM_DIER_TERRIE_Pos

#define TIM_DIER_TERRIE_Pos (23U)

Definition at line 10163 of file stm32g431xx.h.

◆ TIM_DIER_TIE

#define TIM_DIER_TIE TIM_DIER_TIE_Msk

Trigger interrupt enable

Definition at line 10129 of file stm32g431xx.h.

◆ TIM_DIER_TIE_Msk

#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos)

0x00000040

Definition at line 10128 of file stm32g431xx.h.

◆ TIM_DIER_TIE_Pos

#define TIM_DIER_TIE_Pos (6U)

Definition at line 10127 of file stm32g431xx.h.

◆ TIM_DIER_UDE

#define TIM_DIER_UDE TIM_DIER_UDE_Msk

Update DMA request enable

Definition at line 10135 of file stm32g431xx.h.

◆ TIM_DIER_UDE_Msk

#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos)

0x00000100

Definition at line 10134 of file stm32g431xx.h.

◆ TIM_DIER_UDE_Pos

#define TIM_DIER_UDE_Pos (8U)

Definition at line 10133 of file stm32g431xx.h.

◆ TIM_DIER_UIE

#define TIM_DIER_UIE TIM_DIER_UIE_Msk

Update interrupt enable

Definition at line 10111 of file stm32g431xx.h.

◆ TIM_DIER_UIE_Msk

#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos)

0x00000001

Definition at line 10110 of file stm32g431xx.h.

◆ TIM_DIER_UIE_Pos

#define TIM_DIER_UIE_Pos (0U)

Definition at line 10109 of file stm32g431xx.h.

◆ TIM_DMAR_DMAB

#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk

DMA register for burst accesses

Definition at line 10845 of file stm32g431xx.h.

◆ TIM_DMAR_DMAB_Msk

#define TIM_DMAR_DMAB_Msk (0xFFFFFFFFUL << TIM_DMAR_DMAB_Pos)

0xFFFFFFFF

Definition at line 10844 of file stm32g431xx.h.

◆ TIM_DMAR_DMAB_Pos

#define TIM_DMAR_DMAB_Pos (0U)

Definition at line 10843 of file stm32g431xx.h.

◆ TIM_DTR2_DTAE

#define TIM_DTR2_DTAE TIM_DTR2_DTAE_Msk

Deadtime asymmetric enable

Definition at line 10797 of file stm32g431xx.h.

◆ TIM_DTR2_DTAE_Msk

#define TIM_DTR2_DTAE_Msk (0x1UL << TIM_DTR2_DTAE_Pos)

0x00004000

Definition at line 10796 of file stm32g431xx.h.

◆ TIM_DTR2_DTAE_Pos

#define TIM_DTR2_DTAE_Pos (16U)

Definition at line 10795 of file stm32g431xx.h.

◆ TIM_DTR2_DTGF

#define TIM_DTR2_DTGF TIM_DTR2_DTGF_Msk

DTGF[7:0] bits (Deadtime falling edge generator setup)

Definition at line 10785 of file stm32g431xx.h.

◆ TIM_DTR2_DTGF_0

#define TIM_DTR2_DTGF_0 (0x01UL << TIM_DTR2_DTGF_Pos)

0x00000001

Definition at line 10786 of file stm32g431xx.h.

◆ TIM_DTR2_DTGF_1

#define TIM_DTR2_DTGF_1 (0x02UL << TIM_DTR2_DTGF_Pos)

0x00000002

Definition at line 10787 of file stm32g431xx.h.

◆ TIM_DTR2_DTGF_2

#define TIM_DTR2_DTGF_2 (0x04UL << TIM_DTR2_DTGF_Pos)

0x00000004

Definition at line 10788 of file stm32g431xx.h.

◆ TIM_DTR2_DTGF_3

#define TIM_DTR2_DTGF_3 (0x08UL << TIM_DTR2_DTGF_Pos)

0x00000008

Definition at line 10789 of file stm32g431xx.h.

◆ TIM_DTR2_DTGF_4

#define TIM_DTR2_DTGF_4 (0x10UL << TIM_DTR2_DTGF_Pos)

0x00000010

Definition at line 10790 of file stm32g431xx.h.

◆ TIM_DTR2_DTGF_5

#define TIM_DTR2_DTGF_5 (0x20UL << TIM_DTR2_DTGF_Pos)

0x00000020

Definition at line 10791 of file stm32g431xx.h.

◆ TIM_DTR2_DTGF_6

#define TIM_DTR2_DTGF_6 (0x40UL << TIM_DTR2_DTGF_Pos)

0x00000040

Definition at line 10792 of file stm32g431xx.h.

◆ TIM_DTR2_DTGF_7

#define TIM_DTR2_DTGF_7 (0x80UL << TIM_DTR2_DTGF_Pos)

0x00000080

Definition at line 10793 of file stm32g431xx.h.

◆ TIM_DTR2_DTGF_Msk

#define TIM_DTR2_DTGF_Msk (0xFFUL << TIM_DTR2_DTGF_Pos)

0x0000000F

Definition at line 10784 of file stm32g431xx.h.

◆ TIM_DTR2_DTGF_Pos

#define TIM_DTR2_DTGF_Pos (0U)

Definition at line 10783 of file stm32g431xx.h.

◆ TIM_DTR2_DTPE

#define TIM_DTR2_DTPE TIM_DTR2_DTPE_Msk

Deadtime prelaod enable

Definition at line 10800 of file stm32g431xx.h.

◆ TIM_DTR2_DTPE_Msk

#define TIM_DTR2_DTPE_Msk (0x1UL << TIM_DTR2_DTPE_Pos)

0x00008000

Definition at line 10799 of file stm32g431xx.h.

◆ TIM_DTR2_DTPE_Pos

#define TIM_DTR2_DTPE_Pos (17U)

Definition at line 10798 of file stm32g431xx.h.

◆ TIM_ECR_FIDX

#define TIM_ECR_FIDX TIM_ECR_FIDX_Msk

First index enable

Definition at line 10815 of file stm32g431xx.h.

◆ TIM_ECR_FIDX_Msk

#define TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos)

0x00000020

Definition at line 10814 of file stm32g431xx.h.

◆ TIM_ECR_FIDX_Pos

#define TIM_ECR_FIDX_Pos (5U)

Definition at line 10813 of file stm32g431xx.h.

◆ TIM_ECR_IDIR

#define TIM_ECR_IDIR TIM_ECR_IDIR_Msk

IDIR[1:0] bits (Index direction)

Definition at line 10809 of file stm32g431xx.h.

◆ TIM_ECR_IDIR_0

#define TIM_ECR_IDIR_0 (0x01UL << TIM_ECR_IDIR_Pos)

0x00000001

Definition at line 10810 of file stm32g431xx.h.

◆ TIM_ECR_IDIR_1

#define TIM_ECR_IDIR_1 (0x02UL << TIM_ECR_IDIR_Pos)

0x00000002

Definition at line 10811 of file stm32g431xx.h.

◆ TIM_ECR_IDIR_Msk

#define TIM_ECR_IDIR_Msk (0x3UL << TIM_ECR_IDIR_Pos)

0x00000006

Definition at line 10808 of file stm32g431xx.h.

◆ TIM_ECR_IDIR_Pos

#define TIM_ECR_IDIR_Pos (1U)

Definition at line 10807 of file stm32g431xx.h.

◆ TIM_ECR_IE

#define TIM_ECR_IE TIM_ECR_IE_Msk

Index enable

Definition at line 10805 of file stm32g431xx.h.

◆ TIM_ECR_IE_Msk

#define TIM_ECR_IE_Msk (0x1UL << TIM_ECR_IE_Pos)

0x00000001

Definition at line 10804 of file stm32g431xx.h.

◆ TIM_ECR_IE_Pos

#define TIM_ECR_IE_Pos (0U)

Definition at line 10803 of file stm32g431xx.h.

◆ TIM_ECR_IPOS

#define TIM_ECR_IPOS TIM_ECR_IPOS_Msk

IPOS[1:0] bits (Index positioning)

Definition at line 10819 of file stm32g431xx.h.

◆ TIM_ECR_IPOS_0

#define TIM_ECR_IPOS_0 (0x01UL << TIM_ECR_IPOS_Pos)

0x00000001

Definition at line 10820 of file stm32g431xx.h.

◆ TIM_ECR_IPOS_1

#define TIM_ECR_IPOS_1 (0x02UL << TIM_ECR_IPOS_Pos)

0x00000002

Definition at line 10821 of file stm32g431xx.h.

◆ TIM_ECR_IPOS_Msk

#define TIM_ECR_IPOS_Msk (0x3UL << TIM_ECR_IPOS_Pos)

0x0000000C0

Definition at line 10818 of file stm32g431xx.h.

◆ TIM_ECR_IPOS_Pos

#define TIM_ECR_IPOS_Pos (6U)

Definition at line 10817 of file stm32g431xx.h.

◆ TIM_ECR_PW

#define TIM_ECR_PW TIM_ECR_PW_Msk

PW[7:0] bits (Pulse width)

Definition at line 10825 of file stm32g431xx.h.

◆ TIM_ECR_PW_0

#define TIM_ECR_PW_0 (0x01UL << TIM_ECR_PW_Pos)

0x00010000

Definition at line 10826 of file stm32g431xx.h.

◆ TIM_ECR_PW_1

#define TIM_ECR_PW_1 (0x02UL << TIM_ECR_PW_Pos)

0x00020000

Definition at line 10827 of file stm32g431xx.h.

◆ TIM_ECR_PW_2

#define TIM_ECR_PW_2 (0x04UL << TIM_ECR_PW_Pos)

0x00040000

Definition at line 10828 of file stm32g431xx.h.

◆ TIM_ECR_PW_3

#define TIM_ECR_PW_3 (0x08UL << TIM_ECR_PW_Pos)

0x00080000

Definition at line 10829 of file stm32g431xx.h.

◆ TIM_ECR_PW_4

#define TIM_ECR_PW_4 (0x10UL << TIM_ECR_PW_Pos)

0x00100000

Definition at line 10830 of file stm32g431xx.h.

◆ TIM_ECR_PW_5

#define TIM_ECR_PW_5 (0x20UL << TIM_ECR_PW_Pos)

0x00200000

Definition at line 10831 of file stm32g431xx.h.

◆ TIM_ECR_PW_6

#define TIM_ECR_PW_6 (0x40UL << TIM_ECR_PW_Pos)

0x00400000

Definition at line 10832 of file stm32g431xx.h.

◆ TIM_ECR_PW_7

#define TIM_ECR_PW_7 (0x80UL << TIM_ECR_PW_Pos)

0x00800000

Definition at line 10833 of file stm32g431xx.h.

◆ TIM_ECR_PW_Msk

#define TIM_ECR_PW_Msk (0xFFUL << TIM_ECR_PW_Pos)

0x00FF0000

Definition at line 10824 of file stm32g431xx.h.

◆ TIM_ECR_PW_Pos

#define TIM_ECR_PW_Pos (16U)

Definition at line 10823 of file stm32g431xx.h.

◆ TIM_ECR_PWPRSC

#define TIM_ECR_PWPRSC TIM_ECR_PWPRSC_Msk

PWPRSC[2:0] bits (Pulse width prescaler)

Definition at line 10837 of file stm32g431xx.h.

◆ TIM_ECR_PWPRSC_0

#define TIM_ECR_PWPRSC_0 (0x01UL << TIM_ECR_PWPRSC_Pos)

0x01000000

Definition at line 10838 of file stm32g431xx.h.

◆ TIM_ECR_PWPRSC_1

#define TIM_ECR_PWPRSC_1 (0x02UL << TIM_ECR_PWPRSC_Pos)

0x02000000

Definition at line 10839 of file stm32g431xx.h.

◆ TIM_ECR_PWPRSC_2

#define TIM_ECR_PWPRSC_2 (0x04UL << TIM_ECR_PWPRSC_Pos)

0x04000000

Definition at line 10840 of file stm32g431xx.h.

◆ TIM_ECR_PWPRSC_Msk

#define TIM_ECR_PWPRSC_Msk (0x7UL << TIM_ECR_PWPRSC_Pos)

0x07000000

Definition at line 10836 of file stm32g431xx.h.

◆ TIM_ECR_PWPRSC_Pos

#define TIM_ECR_PWPRSC_Pos (24U)

Definition at line 10835 of file stm32g431xx.h.

◆ TIM_EGR_B2G

#define TIM_EGR_B2G TIM_EGR_B2G_Msk

Break 2 Generation

Definition at line 10256 of file stm32g431xx.h.

◆ TIM_EGR_B2G_Msk

#define TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos)

0x00000100

Definition at line 10255 of file stm32g431xx.h.

◆ TIM_EGR_B2G_Pos

#define TIM_EGR_B2G_Pos (8U)

Definition at line 10254 of file stm32g431xx.h.

◆ TIM_EGR_BG

#define TIM_EGR_BG TIM_EGR_BG_Msk

Break Generation

Definition at line 10253 of file stm32g431xx.h.

◆ TIM_EGR_BG_Msk

#define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos)

0x00000080

Definition at line 10252 of file stm32g431xx.h.

◆ TIM_EGR_BG_Pos

#define TIM_EGR_BG_Pos (7U)

Definition at line 10251 of file stm32g431xx.h.

◆ TIM_EGR_CC1G

#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk

Capture/Compare 1 Generation

Definition at line 10235 of file stm32g431xx.h.

◆ TIM_EGR_CC1G_Msk

#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos)

0x00000002

Definition at line 10234 of file stm32g431xx.h.

◆ TIM_EGR_CC1G_Pos

#define TIM_EGR_CC1G_Pos (1U)

Definition at line 10233 of file stm32g431xx.h.

◆ TIM_EGR_CC2G

#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk

Capture/Compare 2 Generation

Definition at line 10238 of file stm32g431xx.h.

◆ TIM_EGR_CC2G_Msk

#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos)

0x00000004

Definition at line 10237 of file stm32g431xx.h.

◆ TIM_EGR_CC2G_Pos

#define TIM_EGR_CC2G_Pos (2U)

Definition at line 10236 of file stm32g431xx.h.

◆ TIM_EGR_CC3G

#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk

Capture/Compare 3 Generation

Definition at line 10241 of file stm32g431xx.h.

◆ TIM_EGR_CC3G_Msk

#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos)

0x00000008

Definition at line 10240 of file stm32g431xx.h.

◆ TIM_EGR_CC3G_Pos

#define TIM_EGR_CC3G_Pos (3U)

Definition at line 10239 of file stm32g431xx.h.

◆ TIM_EGR_CC4G

#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk

Capture/Compare 4 Generation

Definition at line 10244 of file stm32g431xx.h.

◆ TIM_EGR_CC4G_Msk

#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos)

0x00000010

Definition at line 10243 of file stm32g431xx.h.

◆ TIM_EGR_CC4G_Pos

#define TIM_EGR_CC4G_Pos (4U)

Definition at line 10242 of file stm32g431xx.h.

◆ TIM_EGR_COMG

#define TIM_EGR_COMG TIM_EGR_COMG_Msk

Capture/Compare Control Update Generation

Definition at line 10247 of file stm32g431xx.h.

◆ TIM_EGR_COMG_Msk

#define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos)

0x00000020

Definition at line 10246 of file stm32g431xx.h.

◆ TIM_EGR_COMG_Pos

#define TIM_EGR_COMG_Pos (5U)

Definition at line 10245 of file stm32g431xx.h.

◆ TIM_EGR_TG

#define TIM_EGR_TG TIM_EGR_TG_Msk

Trigger Generation

Definition at line 10250 of file stm32g431xx.h.

◆ TIM_EGR_TG_Msk

#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos)

0x00000040

Definition at line 10249 of file stm32g431xx.h.

◆ TIM_EGR_TG_Pos

#define TIM_EGR_TG_Pos (6U)

Definition at line 10248 of file stm32g431xx.h.

◆ TIM_EGR_UG

#define TIM_EGR_UG TIM_EGR_UG_Msk

Update Generation

Definition at line 10232 of file stm32g431xx.h.

◆ TIM_EGR_UG_Msk

#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos)

0x00000001

Definition at line 10231 of file stm32g431xx.h.

◆ TIM_EGR_UG_Pos

#define TIM_EGR_UG_Pos (0U)

Definition at line 10230 of file stm32g431xx.h.

◆ TIM_OR_HSE32EN

#define TIM_OR_HSE32EN TIM_OR_HSE32EN_Msk

HSE/32 clock enable

Definition at line 10747 of file stm32g431xx.h.

◆ TIM_OR_HSE32EN_Msk

#define TIM_OR_HSE32EN_Msk (0x1UL << TIM_OR_HSE32EN_Pos)

0x00000001

Definition at line 10746 of file stm32g431xx.h.

◆ TIM_OR_HSE32EN_Pos

#define TIM_OR_HSE32EN_Pos (0U)

Definition at line 10745 of file stm32g431xx.h.

◆ TIM_PSC_PSC

#define TIM_PSC_PSC TIM_PSC_PSC_Msk

Prescaler Value

Definition at line 10531 of file stm32g431xx.h.

◆ TIM_PSC_PSC_Msk

#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos)

0x0000FFFF

Definition at line 10530 of file stm32g431xx.h.

◆ TIM_PSC_PSC_Pos

#define TIM_PSC_PSC_Pos (0U)

Definition at line 10529 of file stm32g431xx.h.

◆ TIM_RCR_REP

#define TIM_RCR_REP TIM_RCR_REP_Msk

Repetition Counter Value

Definition at line 10541 of file stm32g431xx.h.

◆ TIM_RCR_REP_Msk

#define TIM_RCR_REP_Msk (0xFFFFUL << TIM_RCR_REP_Pos)

0x0000FFFF

Definition at line 10540 of file stm32g431xx.h.

◆ TIM_RCR_REP_Pos

#define TIM_RCR_REP_Pos (0U)

Definition at line 10539 of file stm32g431xx.h.

◆ TIM_SMCR_ECE

#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk

External clock enable

Definition at line 10095 of file stm32g431xx.h.

◆ TIM_SMCR_ECE_Msk

#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos)

0x00004000

Definition at line 10094 of file stm32g431xx.h.

◆ TIM_SMCR_ECE_Pos

#define TIM_SMCR_ECE_Pos (14U)

Definition at line 10093 of file stm32g431xx.h.

◆ TIM_SMCR_ETF

#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk

ETF[3:0] bits (External trigger filter)

Definition at line 10081 of file stm32g431xx.h.

◆ TIM_SMCR_ETF_0

#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos)

0x00000100

Definition at line 10082 of file stm32g431xx.h.

◆ TIM_SMCR_ETF_1

#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos)

0x00000200

Definition at line 10083 of file stm32g431xx.h.

◆ TIM_SMCR_ETF_2

#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos)

0x00000400

Definition at line 10084 of file stm32g431xx.h.

◆ TIM_SMCR_ETF_3

#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos)

0x00000800

Definition at line 10085 of file stm32g431xx.h.

◆ TIM_SMCR_ETF_Msk

#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos)

0x00000F00

Definition at line 10080 of file stm32g431xx.h.

◆ TIM_SMCR_ETF_Pos

#define TIM_SMCR_ETF_Pos (8U)

Definition at line 10079 of file stm32g431xx.h.

◆ TIM_SMCR_ETP

#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk

External trigger polarity

Definition at line 10098 of file stm32g431xx.h.

◆ TIM_SMCR_ETP_Msk

#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos)

0x00008000

Definition at line 10097 of file stm32g431xx.h.

◆ TIM_SMCR_ETP_Pos

#define TIM_SMCR_ETP_Pos (15U)

Definition at line 10096 of file stm32g431xx.h.

◆ TIM_SMCR_ETPS

#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk

ETPS[1:0] bits (External trigger prescaler)

Definition at line 10089 of file stm32g431xx.h.

◆ TIM_SMCR_ETPS_0

#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos)

0x00001000

Definition at line 10090 of file stm32g431xx.h.

◆ TIM_SMCR_ETPS_1

#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos)

0x00002000

Definition at line 10091 of file stm32g431xx.h.

◆ TIM_SMCR_ETPS_Msk

#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos)

0x00003000

Definition at line 10088 of file stm32g431xx.h.

◆ TIM_SMCR_ETPS_Pos

#define TIM_SMCR_ETPS_Pos (12U)

Definition at line 10087 of file stm32g431xx.h.

◆ TIM_SMCR_MSM

#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk

Master/slave mode

Definition at line 10077 of file stm32g431xx.h.

◆ TIM_SMCR_MSM_Msk

#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos)

0x00000080

Definition at line 10076 of file stm32g431xx.h.

◆ TIM_SMCR_MSM_Pos

#define TIM_SMCR_MSM_Pos (7U)

Definition at line 10075 of file stm32g431xx.h.

◆ TIM_SMCR_OCCS

#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk

OCREF clear selection

Definition at line 10064 of file stm32g431xx.h.

◆ TIM_SMCR_OCCS_Msk

#define TIM_SMCR_OCCS_Msk (0x1UL << TIM_SMCR_OCCS_Pos)

0x00000008

Definition at line 10063 of file stm32g431xx.h.

◆ TIM_SMCR_OCCS_Pos

#define TIM_SMCR_OCCS_Pos (3U)

Definition at line 10062 of file stm32g431xx.h.

◆ TIM_SMCR_SMS

#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk

SMS[2:0] bits (Slave mode selection)

Definition at line 10056 of file stm32g431xx.h.

◆ TIM_SMCR_SMS_0

#define TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos)

0x00000001

Definition at line 10057 of file stm32g431xx.h.

◆ TIM_SMCR_SMS_1

#define TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos)

0x00000002

Definition at line 10058 of file stm32g431xx.h.

◆ TIM_SMCR_SMS_2

#define TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos)

0x00000004

Definition at line 10059 of file stm32g431xx.h.

◆ TIM_SMCR_SMS_3

#define TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos)

0x00010000

Definition at line 10060 of file stm32g431xx.h.

◆ TIM_SMCR_SMS_Msk

#define TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos)

0x00010007

Definition at line 10055 of file stm32g431xx.h.

◆ TIM_SMCR_SMS_Pos

#define TIM_SMCR_SMS_Pos (0U)

Definition at line 10054 of file stm32g431xx.h.

◆ TIM_SMCR_SMSPE

#define TIM_SMCR_SMSPE TIM_SMCR_SMSPE_Msk

SMS preload enable

Definition at line 10102 of file stm32g431xx.h.

◆ TIM_SMCR_SMSPE_Msk

#define TIM_SMCR_SMSPE_Msk (0x1UL << TIM_SMCR_SMSPE_Pos)

0x02000000

Definition at line 10101 of file stm32g431xx.h.

◆ TIM_SMCR_SMSPE_Pos

#define TIM_SMCR_SMSPE_Pos (24U)

Definition at line 10100 of file stm32g431xx.h.

◆ TIM_SMCR_SMSPS

#define TIM_SMCR_SMSPS TIM_SMCR_SMSPS_Msk

SMS preload source

Definition at line 10106 of file stm32g431xx.h.

◆ TIM_SMCR_SMSPS_Msk

#define TIM_SMCR_SMSPS_Msk (0x1UL << TIM_SMCR_SMSPS_Pos)

0x04000000

Definition at line 10105 of file stm32g431xx.h.

◆ TIM_SMCR_SMSPS_Pos

#define TIM_SMCR_SMSPS_Pos (25U)

Definition at line 10104 of file stm32g431xx.h.

◆ TIM_SMCR_TS

#define TIM_SMCR_TS TIM_SMCR_TS_Msk

TS[2:0] bits (Trigger selection)

Definition at line 10068 of file stm32g431xx.h.

◆ TIM_SMCR_TS_0

#define TIM_SMCR_TS_0 (0x00001UL << TIM_SMCR_TS_Pos)

0x00000010

Definition at line 10069 of file stm32g431xx.h.

◆ TIM_SMCR_TS_1

#define TIM_SMCR_TS_1 (0x00002UL << TIM_SMCR_TS_Pos)

0x00000020

Definition at line 10070 of file stm32g431xx.h.

◆ TIM_SMCR_TS_2

#define TIM_SMCR_TS_2 (0x00004UL << TIM_SMCR_TS_Pos)

0x00000040

Definition at line 10071 of file stm32g431xx.h.

◆ TIM_SMCR_TS_3

#define TIM_SMCR_TS_3 (0x10000UL << TIM_SMCR_TS_Pos)

0x00100000

Definition at line 10072 of file stm32g431xx.h.

◆ TIM_SMCR_TS_4

#define TIM_SMCR_TS_4 (0x20000UL << TIM_SMCR_TS_Pos)

0x00200000

Definition at line 10073 of file stm32g431xx.h.

◆ TIM_SMCR_TS_Msk

#define TIM_SMCR_TS_Msk (0x30007UL << TIM_SMCR_TS_Pos)

0x00300070

Definition at line 10067 of file stm32g431xx.h.

◆ TIM_SMCR_TS_Pos

#define TIM_SMCR_TS_Pos (4U)

Definition at line 10066 of file stm32g431xx.h.

◆ TIM_SR_B2IF

#define TIM_SR_B2IF TIM_SR_B2IF_Msk

Break 2 interrupt Flag

Definition at line 10194 of file stm32g431xx.h.

◆ TIM_SR_B2IF_Msk

#define TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos)

0x00000100

Definition at line 10193 of file stm32g431xx.h.

◆ TIM_SR_B2IF_Pos

#define TIM_SR_B2IF_Pos (8U)

Definition at line 10192 of file stm32g431xx.h.

◆ TIM_SR_BIF

#define TIM_SR_BIF TIM_SR_BIF_Msk

Break interrupt Flag

Definition at line 10191 of file stm32g431xx.h.

◆ TIM_SR_BIF_Msk

#define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos)

0x00000080

Definition at line 10190 of file stm32g431xx.h.

◆ TIM_SR_BIF_Pos

#define TIM_SR_BIF_Pos (7U)

Definition at line 10189 of file stm32g431xx.h.

◆ TIM_SR_CC1IF

#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk

Capture/Compare 1 interrupt Flag

Definition at line 10173 of file stm32g431xx.h.

◆ TIM_SR_CC1IF_Msk

#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos)

0x00000002

Definition at line 10172 of file stm32g431xx.h.

◆ TIM_SR_CC1IF_Pos

#define TIM_SR_CC1IF_Pos (1U)

Definition at line 10171 of file stm32g431xx.h.

◆ TIM_SR_CC1OF

#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk

Capture/Compare 1 Overcapture Flag

Definition at line 10197 of file stm32g431xx.h.

◆ TIM_SR_CC1OF_Msk

#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos)

0x00000200

Definition at line 10196 of file stm32g431xx.h.

◆ TIM_SR_CC1OF_Pos

#define TIM_SR_CC1OF_Pos (9U)

Definition at line 10195 of file stm32g431xx.h.

◆ TIM_SR_CC2IF

#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk

Capture/Compare 2 interrupt Flag

Definition at line 10176 of file stm32g431xx.h.

◆ TIM_SR_CC2IF_Msk

#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos)

0x00000004

Definition at line 10175 of file stm32g431xx.h.

◆ TIM_SR_CC2IF_Pos

#define TIM_SR_CC2IF_Pos (2U)

Definition at line 10174 of file stm32g431xx.h.

◆ TIM_SR_CC2OF

#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk

Capture/Compare 2 Overcapture Flag

Definition at line 10200 of file stm32g431xx.h.

◆ TIM_SR_CC2OF_Msk

#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos)

0x00000400

Definition at line 10199 of file stm32g431xx.h.

◆ TIM_SR_CC2OF_Pos

#define TIM_SR_CC2OF_Pos (10U)

Definition at line 10198 of file stm32g431xx.h.

◆ TIM_SR_CC3IF

#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk

Capture/Compare 3 interrupt Flag

Definition at line 10179 of file stm32g431xx.h.

◆ TIM_SR_CC3IF_Msk

#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos)

0x00000008

Definition at line 10178 of file stm32g431xx.h.

◆ TIM_SR_CC3IF_Pos

#define TIM_SR_CC3IF_Pos (3U)

Definition at line 10177 of file stm32g431xx.h.

◆ TIM_SR_CC3OF

#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk

Capture/Compare 3 Overcapture Flag

Definition at line 10203 of file stm32g431xx.h.

◆ TIM_SR_CC3OF_Msk

#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos)

0x00000800

Definition at line 10202 of file stm32g431xx.h.

◆ TIM_SR_CC3OF_Pos

#define TIM_SR_CC3OF_Pos (11U)

Definition at line 10201 of file stm32g431xx.h.

◆ TIM_SR_CC4IF

#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk

Capture/Compare 4 interrupt Flag

Definition at line 10182 of file stm32g431xx.h.

◆ TIM_SR_CC4IF_Msk

#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos)

0x00000010

Definition at line 10181 of file stm32g431xx.h.

◆ TIM_SR_CC4IF_Pos

#define TIM_SR_CC4IF_Pos (4U)

Definition at line 10180 of file stm32g431xx.h.

◆ TIM_SR_CC4OF

#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk

Capture/Compare 4 Overcapture Flag

Definition at line 10206 of file stm32g431xx.h.

◆ TIM_SR_CC4OF_Msk

#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos)

0x00001000

Definition at line 10205 of file stm32g431xx.h.

◆ TIM_SR_CC4OF_Pos

#define TIM_SR_CC4OF_Pos (12U)

Definition at line 10204 of file stm32g431xx.h.

◆ TIM_SR_CC5IF

#define TIM_SR_CC5IF TIM_SR_CC5IF_Msk

Capture/Compare 5 interrupt Flag

Definition at line 10212 of file stm32g431xx.h.

◆ TIM_SR_CC5IF_Msk

#define TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos)

0x00010000

Definition at line 10211 of file stm32g431xx.h.

◆ TIM_SR_CC5IF_Pos

#define TIM_SR_CC5IF_Pos (16U)

Definition at line 10210 of file stm32g431xx.h.

◆ TIM_SR_CC6IF

#define TIM_SR_CC6IF TIM_SR_CC6IF_Msk

Capture/Compare 6 interrupt Flag

Definition at line 10215 of file stm32g431xx.h.

◆ TIM_SR_CC6IF_Msk

#define TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos)

0x00020000

Definition at line 10214 of file stm32g431xx.h.

◆ TIM_SR_CC6IF_Pos

#define TIM_SR_CC6IF_Pos (17U)

Definition at line 10213 of file stm32g431xx.h.

◆ TIM_SR_COMIF

#define TIM_SR_COMIF TIM_SR_COMIF_Msk

COM interrupt Flag

Definition at line 10185 of file stm32g431xx.h.

◆ TIM_SR_COMIF_Msk

#define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos)

0x00000020

Definition at line 10184 of file stm32g431xx.h.

◆ TIM_SR_COMIF_Pos

#define TIM_SR_COMIF_Pos (5U)

Definition at line 10183 of file stm32g431xx.h.

◆ TIM_SR_DIRF

#define TIM_SR_DIRF TIM_SR_DIRF_Msk

Encoder direction change interrupt flag

Definition at line 10221 of file stm32g431xx.h.

◆ TIM_SR_DIRF_Msk

#define TIM_SR_DIRF_Msk (0x1UL << TIM_SR_DIRF_Pos)

0x00200000

Definition at line 10220 of file stm32g431xx.h.

◆ TIM_SR_DIRF_Pos

#define TIM_SR_DIRF_Pos (21U)

Definition at line 10219 of file stm32g431xx.h.

◆ TIM_SR_IDXF

#define TIM_SR_IDXF TIM_SR_IDXF_Msk

Encoder index interrupt flag

Definition at line 10218 of file stm32g431xx.h.

◆ TIM_SR_IDXF_Msk

#define TIM_SR_IDXF_Msk (0x1UL << TIM_SR_IDXF_Pos)

0x00100000

Definition at line 10217 of file stm32g431xx.h.

◆ TIM_SR_IDXF_Pos

#define TIM_SR_IDXF_Pos (20U)

Definition at line 10216 of file stm32g431xx.h.

◆ TIM_SR_IERRF

#define TIM_SR_IERRF TIM_SR_IERRF_Msk

Encoder index error flag

Definition at line 10224 of file stm32g431xx.h.

◆ TIM_SR_IERRF_Msk

#define TIM_SR_IERRF_Msk (0x1UL << TIM_SR_IERRF_Pos)

0x00400000

Definition at line 10223 of file stm32g431xx.h.

◆ TIM_SR_IERRF_Pos

#define TIM_SR_IERRF_Pos (22U)

Definition at line 10222 of file stm32g431xx.h.

◆ TIM_SR_SBIF

#define TIM_SR_SBIF TIM_SR_SBIF_Msk

System Break interrupt Flag

Definition at line 10209 of file stm32g431xx.h.

◆ TIM_SR_SBIF_Msk

#define TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos)

0x00002000

Definition at line 10208 of file stm32g431xx.h.

◆ TIM_SR_SBIF_Pos

#define TIM_SR_SBIF_Pos (13U)

Definition at line 10207 of file stm32g431xx.h.

◆ TIM_SR_TERRF

#define TIM_SR_TERRF TIM_SR_TERRF_Msk

Encoder transition error flag

Definition at line 10227 of file stm32g431xx.h.

◆ TIM_SR_TERRF_Msk

#define TIM_SR_TERRF_Msk (0x1UL << TIM_SR_TERRF_Pos)

0x00800000

Definition at line 10226 of file stm32g431xx.h.

◆ TIM_SR_TERRF_Pos

#define TIM_SR_TERRF_Pos (23U)

Definition at line 10225 of file stm32g431xx.h.

◆ TIM_SR_TIF

#define TIM_SR_TIF TIM_SR_TIF_Msk

Trigger interrupt Flag

Definition at line 10188 of file stm32g431xx.h.

◆ TIM_SR_TIF_Msk

#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos)

0x00000040

Definition at line 10187 of file stm32g431xx.h.

◆ TIM_SR_TIF_Pos

#define TIM_SR_TIF_Pos (6U)

Definition at line 10186 of file stm32g431xx.h.

◆ TIM_SR_UIF

#define TIM_SR_UIF TIM_SR_UIF_Msk

Update interrupt Flag

Definition at line 10170 of file stm32g431xx.h.

◆ TIM_SR_UIF_Msk

#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos)

0x00000001

Definition at line 10169 of file stm32g431xx.h.

◆ TIM_SR_UIF_Pos

#define TIM_SR_UIF_Pos (0U)

Definition at line 10168 of file stm32g431xx.h.

◆ TIM_TISEL_TI1SEL

#define TIM_TISEL_TI1SEL TIM_TISEL_TI1SEL_Msk

TI1SEL[3:0] bits (TIM1 TI1 SEL)

Definition at line 10752 of file stm32g431xx.h.

◆ TIM_TISEL_TI1SEL_0

#define TIM_TISEL_TI1SEL_0 (0x1UL << TIM_TISEL_TI1SEL_Pos)

0x00000001

Definition at line 10753 of file stm32g431xx.h.

◆ TIM_TISEL_TI1SEL_1

#define TIM_TISEL_TI1SEL_1 (0x2UL << TIM_TISEL_TI1SEL_Pos)

0x00000002

Definition at line 10754 of file stm32g431xx.h.

◆ TIM_TISEL_TI1SEL_2

#define TIM_TISEL_TI1SEL_2 (0x4UL << TIM_TISEL_TI1SEL_Pos)

0x00000004

Definition at line 10755 of file stm32g431xx.h.

◆ TIM_TISEL_TI1SEL_3

#define TIM_TISEL_TI1SEL_3 (0x8UL << TIM_TISEL_TI1SEL_Pos)

0x00000008

Definition at line 10756 of file stm32g431xx.h.

◆ TIM_TISEL_TI1SEL_Msk

#define TIM_TISEL_TI1SEL_Msk (0xFUL << TIM_TISEL_TI1SEL_Pos)

0x0000000F

Definition at line 10751 of file stm32g431xx.h.

◆ TIM_TISEL_TI1SEL_Pos

#define TIM_TISEL_TI1SEL_Pos (0U)

Definition at line 10750 of file stm32g431xx.h.

◆ TIM_TISEL_TI2SEL

#define TIM_TISEL_TI2SEL TIM_TISEL_TI2SEL_Msk

TI2SEL[3:0] bits (TIM1 TI2 SEL)

Definition at line 10760 of file stm32g431xx.h.

◆ TIM_TISEL_TI2SEL_0

#define TIM_TISEL_TI2SEL_0 (0x1UL << TIM_TISEL_TI2SEL_Pos)

0x00000100

Definition at line 10761 of file stm32g431xx.h.

◆ TIM_TISEL_TI2SEL_1

#define TIM_TISEL_TI2SEL_1 (0x2UL << TIM_TISEL_TI2SEL_Pos)

0x00000200

Definition at line 10762 of file stm32g431xx.h.

◆ TIM_TISEL_TI2SEL_2

#define TIM_TISEL_TI2SEL_2 (0x4UL << TIM_TISEL_TI2SEL_Pos)

0x00000400

Definition at line 10763 of file stm32g431xx.h.

◆ TIM_TISEL_TI2SEL_3

#define TIM_TISEL_TI2SEL_3 (0x8UL << TIM_TISEL_TI2SEL_Pos)

0x00000800

Definition at line 10764 of file stm32g431xx.h.

◆ TIM_TISEL_TI2SEL_Msk

#define TIM_TISEL_TI2SEL_Msk (0xFUL << TIM_TISEL_TI2SEL_Pos)

0x00000F00

Definition at line 10759 of file stm32g431xx.h.

◆ TIM_TISEL_TI2SEL_Pos

#define TIM_TISEL_TI2SEL_Pos (8U)

Definition at line 10758 of file stm32g431xx.h.

◆ TIM_TISEL_TI3SEL

#define TIM_TISEL_TI3SEL TIM_TISEL_TI3SEL_Msk

TI3SEL[3:0] bits (TIM1 TI3 SEL)

Definition at line 10768 of file stm32g431xx.h.

◆ TIM_TISEL_TI3SEL_0

#define TIM_TISEL_TI3SEL_0 (0x1UL << TIM_TISEL_TI3SEL_Pos)

0x00010000

Definition at line 10769 of file stm32g431xx.h.

◆ TIM_TISEL_TI3SEL_1

#define TIM_TISEL_TI3SEL_1 (0x2UL << TIM_TISEL_TI3SEL_Pos)

0x00020000

Definition at line 10770 of file stm32g431xx.h.

◆ TIM_TISEL_TI3SEL_2

#define TIM_TISEL_TI3SEL_2 (0x4UL << TIM_TISEL_TI3SEL_Pos)

0x00040000

Definition at line 10771 of file stm32g431xx.h.

◆ TIM_TISEL_TI3SEL_3

#define TIM_TISEL_TI3SEL_3 (0x8UL << TIM_TISEL_TI3SEL_Pos)

0x00080000

Definition at line 10772 of file stm32g431xx.h.

◆ TIM_TISEL_TI3SEL_Msk

#define TIM_TISEL_TI3SEL_Msk (0xFUL << TIM_TISEL_TI3SEL_Pos)

0x000F0000

Definition at line 10767 of file stm32g431xx.h.

◆ TIM_TISEL_TI3SEL_Pos

#define TIM_TISEL_TI3SEL_Pos (16U)

Definition at line 10766 of file stm32g431xx.h.

◆ TIM_TISEL_TI4SEL

#define TIM_TISEL_TI4SEL TIM_TISEL_TI4SEL_Msk

TI4SEL[3:0] bits (TIM1 TI4 SEL)

Definition at line 10776 of file stm32g431xx.h.

◆ TIM_TISEL_TI4SEL_0

#define TIM_TISEL_TI4SEL_0 (0x1UL << TIM_TISEL_TI4SEL_Pos)

0x01000000

Definition at line 10777 of file stm32g431xx.h.

◆ TIM_TISEL_TI4SEL_1

#define TIM_TISEL_TI4SEL_1 (0x2UL << TIM_TISEL_TI4SEL_Pos)

0x02000000

Definition at line 10778 of file stm32g431xx.h.

◆ TIM_TISEL_TI4SEL_2

#define TIM_TISEL_TI4SEL_2 (0x4UL << TIM_TISEL_TI4SEL_Pos)

0x04000000

Definition at line 10779 of file stm32g431xx.h.

◆ TIM_TISEL_TI4SEL_3

#define TIM_TISEL_TI4SEL_3 (0x8UL << TIM_TISEL_TI4SEL_Pos)

0x08000000

Definition at line 10780 of file stm32g431xx.h.

◆ TIM_TISEL_TI4SEL_Msk

#define TIM_TISEL_TI4SEL_Msk (0xFUL << TIM_TISEL_TI4SEL_Pos)

0x0F000000

Definition at line 10775 of file stm32g431xx.h.

◆ TIM_TISEL_TI4SEL_Pos

#define TIM_TISEL_TI4SEL_Pos (24U)

Definition at line 10774 of file stm32g431xx.h.

◆ UCPD_CFG1_HBITCLKDIV

#define UCPD_CFG1_HBITCLKDIV UCPD_CFG1_HBITCLKDIV_Msk

Number of cycles (minus 1) for a half bit clock

Definition at line 12173 of file stm32g431xx.h.

◆ UCPD_CFG1_HBITCLKDIV_0

#define UCPD_CFG1_HBITCLKDIV_0 (0x01UL << UCPD_CFG1_HBITCLKDIV_Pos)

0x00000001

Definition at line 12174 of file stm32g431xx.h.

◆ UCPD_CFG1_HBITCLKDIV_1

#define UCPD_CFG1_HBITCLKDIV_1 (0x02UL << UCPD_CFG1_HBITCLKDIV_Pos)

0x00000002

Definition at line 12175 of file stm32g431xx.h.

◆ UCPD_CFG1_HBITCLKDIV_2

#define UCPD_CFG1_HBITCLKDIV_2 (0x04UL << UCPD_CFG1_HBITCLKDIV_Pos)

0x00000004

Definition at line 12176 of file stm32g431xx.h.

◆ UCPD_CFG1_HBITCLKDIV_3

#define UCPD_CFG1_HBITCLKDIV_3 (0x08UL << UCPD_CFG1_HBITCLKDIV_Pos)

0x00000008

Definition at line 12177 of file stm32g431xx.h.

◆ UCPD_CFG1_HBITCLKDIV_4

#define UCPD_CFG1_HBITCLKDIV_4 (0x10UL << UCPD_CFG1_HBITCLKDIV_Pos)

0x00000010

Definition at line 12178 of file stm32g431xx.h.

◆ UCPD_CFG1_HBITCLKDIV_5

#define UCPD_CFG1_HBITCLKDIV_5 (0x20UL << UCPD_CFG1_HBITCLKDIV_Pos)

0x00000020

Definition at line 12179 of file stm32g431xx.h.

◆ UCPD_CFG1_HBITCLKDIV_Msk

#define UCPD_CFG1_HBITCLKDIV_Msk (0x3FUL << UCPD_CFG1_HBITCLKDIV_Pos)

0x0000003F

Definition at line 12172 of file stm32g431xx.h.

◆ UCPD_CFG1_HBITCLKDIV_Pos

#define UCPD_CFG1_HBITCLKDIV_Pos (0U)

Definition at line 12171 of file stm32g431xx.h.

◆ UCPD_CFG1_IFRGAP

#define UCPD_CFG1_IFRGAP UCPD_CFG1_IFRGAP_Msk

Clock divider value to generates Interframe gap

Definition at line 12182 of file stm32g431xx.h.

◆ UCPD_CFG1_IFRGAP_0

#define UCPD_CFG1_IFRGAP_0 (0x01UL << UCPD_CFG1_IFRGAP_Pos)

0x00000040

Definition at line 12183 of file stm32g431xx.h.

◆ UCPD_CFG1_IFRGAP_1

#define UCPD_CFG1_IFRGAP_1 (0x02UL << UCPD_CFG1_IFRGAP_Pos)

0x00000080

Definition at line 12184 of file stm32g431xx.h.

◆ UCPD_CFG1_IFRGAP_2

#define UCPD_CFG1_IFRGAP_2 (0x04UL << UCPD_CFG1_IFRGAP_Pos)

0x00000100

Definition at line 12185 of file stm32g431xx.h.

◆ UCPD_CFG1_IFRGAP_3

#define UCPD_CFG1_IFRGAP_3 (0x08UL << UCPD_CFG1_IFRGAP_Pos)

0x00000200

Definition at line 12186 of file stm32g431xx.h.

◆ UCPD_CFG1_IFRGAP_4

#define UCPD_CFG1_IFRGAP_4 (0x10UL << UCPD_CFG1_IFRGAP_Pos)

0x00000400

Definition at line 12187 of file stm32g431xx.h.

◆ UCPD_CFG1_IFRGAP_Msk

#define UCPD_CFG1_IFRGAP_Msk (0x1FUL << UCPD_CFG1_IFRGAP_Pos)

0x000007C0

Definition at line 12181 of file stm32g431xx.h.

◆ UCPD_CFG1_IFRGAP_Pos

#define UCPD_CFG1_IFRGAP_Pos (6U)

Definition at line 12180 of file stm32g431xx.h.

◆ UCPD_CFG1_PSC_UCPDCLK

#define UCPD_CFG1_PSC_UCPDCLK UCPD_CFG1_PSC_UCPDCLK_Msk

Prescaler for UCPDCLK

Definition at line 12198 of file stm32g431xx.h.

◆ UCPD_CFG1_PSC_UCPDCLK_0

#define UCPD_CFG1_PSC_UCPDCLK_0 (0x1UL << UCPD_CFG1_PSC_UCPDCLK_Pos)

0x00020000

Definition at line 12199 of file stm32g431xx.h.

◆ UCPD_CFG1_PSC_UCPDCLK_1

#define UCPD_CFG1_PSC_UCPDCLK_1 (0x2UL << UCPD_CFG1_PSC_UCPDCLK_Pos)

0x00040000

Definition at line 12200 of file stm32g431xx.h.

◆ UCPD_CFG1_PSC_UCPDCLK_2

#define UCPD_CFG1_PSC_UCPDCLK_2 (0x4UL << UCPD_CFG1_PSC_UCPDCLK_Pos)

0x00080000

Definition at line 12201 of file stm32g431xx.h.

◆ UCPD_CFG1_PSC_UCPDCLK_Msk

#define UCPD_CFG1_PSC_UCPDCLK_Msk (0x7UL << UCPD_CFG1_PSC_UCPDCLK_Pos)

0x000E0000

Definition at line 12197 of file stm32g431xx.h.

◆ UCPD_CFG1_PSC_UCPDCLK_Pos

#define UCPD_CFG1_PSC_UCPDCLK_Pos (17U)

Definition at line 12196 of file stm32g431xx.h.

◆ UCPD_CFG1_RXDMAEN

#define UCPD_CFG1_RXDMAEN UCPD_CFG1_RXDMAEN_Msk

DMA reception requests enable

Definition at line 12219 of file stm32g431xx.h.

◆ UCPD_CFG1_RXDMAEN_Msk

#define UCPD_CFG1_RXDMAEN_Msk (0x1UL << UCPD_CFG1_RXDMAEN_Pos)

0x40000000

Definition at line 12218 of file stm32g431xx.h.

◆ UCPD_CFG1_RXDMAEN_Pos

#define UCPD_CFG1_RXDMAEN_Pos (30U)

Definition at line 12217 of file stm32g431xx.h.

◆ UCPD_CFG1_RXORDSETEN

#define UCPD_CFG1_RXORDSETEN UCPD_CFG1_RXORDSETEN_Msk

Receiver ordered set detection enable

Definition at line 12204 of file stm32g431xx.h.

◆ UCPD_CFG1_RXORDSETEN_0

#define UCPD_CFG1_RXORDSETEN_0 (0x001UL << UCPD_CFG1_RXORDSETEN_Pos)

0x00100000

Definition at line 12205 of file stm32g431xx.h.

◆ UCPD_CFG1_RXORDSETEN_1

#define UCPD_CFG1_RXORDSETEN_1 (0x002UL << UCPD_CFG1_RXORDSETEN_Pos)

0x00200000

Definition at line 12206 of file stm32g431xx.h.

◆ UCPD_CFG1_RXORDSETEN_2

#define UCPD_CFG1_RXORDSETEN_2 (0x004UL << UCPD_CFG1_RXORDSETEN_Pos)

0x00400000

Definition at line 12207 of file stm32g431xx.h.

◆ UCPD_CFG1_RXORDSETEN_3

#define UCPD_CFG1_RXORDSETEN_3 (0x008UL << UCPD_CFG1_RXORDSETEN_Pos)

0x00800000

Definition at line 12208 of file stm32g431xx.h.

◆ UCPD_CFG1_RXORDSETEN_4

#define UCPD_CFG1_RXORDSETEN_4 (0x010UL << UCPD_CFG1_RXORDSETEN_Pos)

0x01000000

Definition at line 12209 of file stm32g431xx.h.

◆ UCPD_CFG1_RXORDSETEN_5

#define UCPD_CFG1_RXORDSETEN_5 (0x020UL << UCPD_CFG1_RXORDSETEN_Pos)

0x02000000

Definition at line 12210 of file stm32g431xx.h.

◆ UCPD_CFG1_RXORDSETEN_6

#define UCPD_CFG1_RXORDSETEN_6 (0x040UL << UCPD_CFG1_RXORDSETEN_Pos)

0x04000000

Definition at line 12211 of file stm32g431xx.h.

◆ UCPD_CFG1_RXORDSETEN_7

#define UCPD_CFG1_RXORDSETEN_7 (0x080UL << UCPD_CFG1_RXORDSETEN_Pos)

0x08000000

Definition at line 12212 of file stm32g431xx.h.

◆ UCPD_CFG1_RXORDSETEN_8

#define UCPD_CFG1_RXORDSETEN_8 (0x100UL << UCPD_CFG1_RXORDSETEN_Pos)

0x10000000

Definition at line 12213 of file stm32g431xx.h.

◆ UCPD_CFG1_RXORDSETEN_Msk

#define UCPD_CFG1_RXORDSETEN_Msk (0x1FFUL << UCPD_CFG1_RXORDSETEN_Pos)

0x1FF00000

Definition at line 12203 of file stm32g431xx.h.

◆ UCPD_CFG1_RXORDSETEN_Pos

#define UCPD_CFG1_RXORDSETEN_Pos (20U)

Definition at line 12202 of file stm32g431xx.h.

◆ UCPD_CFG1_TRANSWIN

#define UCPD_CFG1_TRANSWIN UCPD_CFG1_TRANSWIN_Msk

Number of cycles (minus 1) of the half bit clock

Definition at line 12190 of file stm32g431xx.h.

◆ UCPD_CFG1_TRANSWIN_0

#define UCPD_CFG1_TRANSWIN_0 (0x01UL << UCPD_CFG1_TRANSWIN_Pos)

0x00000800

Definition at line 12191 of file stm32g431xx.h.

◆ UCPD_CFG1_TRANSWIN_1

#define UCPD_CFG1_TRANSWIN_1 (0x02UL << UCPD_CFG1_TRANSWIN_Pos)

0x00001000

Definition at line 12192 of file stm32g431xx.h.

◆ UCPD_CFG1_TRANSWIN_2

#define UCPD_CFG1_TRANSWIN_2 (0x04UL << UCPD_CFG1_TRANSWIN_Pos)

0x00002000

Definition at line 12193 of file stm32g431xx.h.

◆ UCPD_CFG1_TRANSWIN_3

#define UCPD_CFG1_TRANSWIN_3 (0x08UL << UCPD_CFG1_TRANSWIN_Pos)

0x00004000

Definition at line 12194 of file stm32g431xx.h.

◆ UCPD_CFG1_TRANSWIN_4

#define UCPD_CFG1_TRANSWIN_4 (0x10UL << UCPD_CFG1_TRANSWIN_Pos)

0x00008000

Definition at line 12195 of file stm32g431xx.h.

◆ UCPD_CFG1_TRANSWIN_Msk

#define UCPD_CFG1_TRANSWIN_Msk (0x1FUL << UCPD_CFG1_TRANSWIN_Pos)

0x0000F800

Definition at line 12189 of file stm32g431xx.h.

◆ UCPD_CFG1_TRANSWIN_Pos

#define UCPD_CFG1_TRANSWIN_Pos (11U)

Definition at line 12188 of file stm32g431xx.h.

◆ UCPD_CFG1_TXDMAEN

#define UCPD_CFG1_TXDMAEN UCPD_CFG1_TXDMAEN_Msk

DMA transmission requests enable

Definition at line 12216 of file stm32g431xx.h.

◆ UCPD_CFG1_TXDMAEN_Msk

#define UCPD_CFG1_TXDMAEN_Msk (0x1UL << UCPD_CFG1_TXDMAEN_Pos)

0x20000000

Definition at line 12215 of file stm32g431xx.h.

◆ UCPD_CFG1_TXDMAEN_Pos

#define UCPD_CFG1_TXDMAEN_Pos (29U)

Definition at line 12214 of file stm32g431xx.h.

◆ UCPD_CFG1_UCPDEN

#define UCPD_CFG1_UCPDEN UCPD_CFG1_UCPDEN_Msk

USB Power Delivery Block Enable

Definition at line 12222 of file stm32g431xx.h.

◆ UCPD_CFG1_UCPDEN_Msk

#define UCPD_CFG1_UCPDEN_Msk (0x1UL << UCPD_CFG1_UCPDEN_Pos)

0x80000000

Definition at line 12221 of file stm32g431xx.h.

◆ UCPD_CFG1_UCPDEN_Pos

#define UCPD_CFG1_UCPDEN_Pos (31U)

Definition at line 12220 of file stm32g431xx.h.

◆ UCPD_CFG2_FORCECLK

#define UCPD_CFG2_FORCECLK UCPD_CFG2_FORCECLK_Msk

Controls forcing of the clock request UCPDCLK_REQ

Definition at line 12233 of file stm32g431xx.h.

◆ UCPD_CFG2_FORCECLK_Msk

#define UCPD_CFG2_FORCECLK_Msk (0x1UL << UCPD_CFG2_FORCECLK_Pos)

0x00000004

Definition at line 12232 of file stm32g431xx.h.

◆ UCPD_CFG2_FORCECLK_Pos

#define UCPD_CFG2_FORCECLK_Pos (2U)

Definition at line 12231 of file stm32g431xx.h.

◆ UCPD_CFG2_RXFILT2N3

#define UCPD_CFG2_RXFILT2N3 UCPD_CFG2_RXFILT2N3_Msk

Controls the sampling method for an Rx pre-filter for the BMC decode

Definition at line 12230 of file stm32g431xx.h.

◆ UCPD_CFG2_RXFILT2N3_Msk

#define UCPD_CFG2_RXFILT2N3_Msk (0x1UL << UCPD_CFG2_RXFILT2N3_Pos)

0x00000002

Definition at line 12229 of file stm32g431xx.h.

◆ UCPD_CFG2_RXFILT2N3_Pos

#define UCPD_CFG2_RXFILT2N3_Pos (1U)

Definition at line 12228 of file stm32g431xx.h.

◆ UCPD_CFG2_RXFILTDIS

#define UCPD_CFG2_RXFILTDIS UCPD_CFG2_RXFILTDIS_Msk

Enables an Rx pre-filter for the BMC decoder

Definition at line 12227 of file stm32g431xx.h.

◆ UCPD_CFG2_RXFILTDIS_Msk

#define UCPD_CFG2_RXFILTDIS_Msk (0x1UL << UCPD_CFG2_RXFILTDIS_Pos)

0x00000001

Definition at line 12226 of file stm32g431xx.h.

◆ UCPD_CFG2_RXFILTDIS_Pos

#define UCPD_CFG2_RXFILTDIS_Pos (0U)

Definition at line 12225 of file stm32g431xx.h.

◆ UCPD_CFG2_WUPEN

#define UCPD_CFG2_WUPEN UCPD_CFG2_WUPEN_Msk

Wakeup from STOP enable

Definition at line 12236 of file stm32g431xx.h.

◆ UCPD_CFG2_WUPEN_Msk

#define UCPD_CFG2_WUPEN_Msk (0x1UL << UCPD_CFG2_WUPEN_Pos)

0x00000008

Definition at line 12235 of file stm32g431xx.h.

◆ UCPD_CFG2_WUPEN_Pos

#define UCPD_CFG2_WUPEN_Pos (3U)

Definition at line 12234 of file stm32g431xx.h.

◆ UCPD_CR_ANAMODE

#define UCPD_CR_ANAMODE UCPD_CR_ANAMODE_Msk

Analog PHY working mode

Definition at line 12266 of file stm32g431xx.h.

◆ UCPD_CR_ANAMODE_Msk

#define UCPD_CR_ANAMODE_Msk (0x1UL << UCPD_CR_ANAMODE_Pos)

0x00000200

Definition at line 12265 of file stm32g431xx.h.

◆ UCPD_CR_ANAMODE_Pos

#define UCPD_CR_ANAMODE_Pos (9U)

Definition at line 12264 of file stm32g431xx.h.

◆ UCPD_CR_ANASUBMODE

#define UCPD_CR_ANASUBMODE UCPD_CR_ANASUBMODE_Msk

Analog PHY sub-mode

Definition at line 12261 of file stm32g431xx.h.

◆ UCPD_CR_ANASUBMODE_0

#define UCPD_CR_ANASUBMODE_0 (0x1UL << UCPD_CR_ANASUBMODE_Pos)

0x00000080

Definition at line 12262 of file stm32g431xx.h.

◆ UCPD_CR_ANASUBMODE_1

#define UCPD_CR_ANASUBMODE_1 (0x2UL << UCPD_CR_ANASUBMODE_Pos)

0x00000100

Definition at line 12263 of file stm32g431xx.h.

◆ UCPD_CR_ANASUBMODE_Msk

#define UCPD_CR_ANASUBMODE_Msk (0x3UL << UCPD_CR_ANASUBMODE_Pos)

0x00000180

Definition at line 12260 of file stm32g431xx.h.

◆ UCPD_CR_ANASUBMODE_Pos

#define UCPD_CR_ANASUBMODE_Pos (7U)

Definition at line 12259 of file stm32g431xx.h.

◆ UCPD_CR_CC1TCDIS

#define UCPD_CR_CC1TCDIS UCPD_CR_CC1TCDIS_Msk

The bit allows the Type-C detector for CC0 to be disabled.

Definition at line 12283 of file stm32g431xx.h.

◆ UCPD_CR_CC1TCDIS_Msk

#define UCPD_CR_CC1TCDIS_Msk (0x1UL << UCPD_CR_CC1TCDIS_Pos)

0x00100000

Definition at line 12282 of file stm32g431xx.h.

◆ UCPD_CR_CC1TCDIS_Pos

#define UCPD_CR_CC1TCDIS_Pos (20U)

Definition at line 12281 of file stm32g431xx.h.

◆ UCPD_CR_CC2TCDIS

#define UCPD_CR_CC2TCDIS UCPD_CR_CC2TCDIS_Msk

The bit allows the Type-C detector for CC2 to be disabled.

Definition at line 12286 of file stm32g431xx.h.

◆ UCPD_CR_CC2TCDIS_Msk

#define UCPD_CR_CC2TCDIS_Msk (0x1UL << UCPD_CR_CC2TCDIS_Pos)

0x00200000

Definition at line 12285 of file stm32g431xx.h.

◆ UCPD_CR_CC2TCDIS_Pos

#define UCPD_CR_CC2TCDIS_Pos (21U)

Definition at line 12284 of file stm32g431xx.h.

◆ UCPD_CR_CCENABLE

#define UCPD_CR_CCENABLE UCPD_CR_CCENABLE_Msk

Definition at line 12269 of file stm32g431xx.h.

◆ UCPD_CR_CCENABLE_0

#define UCPD_CR_CCENABLE_0 (0x1UL << UCPD_CR_CCENABLE_Pos)

0x00000400

Definition at line 12270 of file stm32g431xx.h.

◆ UCPD_CR_CCENABLE_1

#define UCPD_CR_CCENABLE_1 (0x2UL << UCPD_CR_CCENABLE_Pos)

0x00000800

Definition at line 12271 of file stm32g431xx.h.

◆ UCPD_CR_CCENABLE_Msk

#define UCPD_CR_CCENABLE_Msk (0x3UL << UCPD_CR_CCENABLE_Pos)

0x00000C00

Definition at line 12268 of file stm32g431xx.h.

◆ UCPD_CR_CCENABLE_Pos

#define UCPD_CR_CCENABLE_Pos (10U)

Definition at line 12267 of file stm32g431xx.h.

◆ UCPD_CR_FRSRXEN

#define UCPD_CR_FRSRXEN UCPD_CR_FRSRXEN_Msk

Enable FRS request detection function

Definition at line 12274 of file stm32g431xx.h.

◆ UCPD_CR_FRSRXEN_Msk

#define UCPD_CR_FRSRXEN_Msk (0x1UL << UCPD_CR_FRSRXEN_Pos)

0x00010000

Definition at line 12273 of file stm32g431xx.h.

◆ UCPD_CR_FRSRXEN_Pos

#define UCPD_CR_FRSRXEN_Pos (16U)

Definition at line 12272 of file stm32g431xx.h.

◆ UCPD_CR_FRSTX

#define UCPD_CR_FRSTX UCPD_CR_FRSTX_Msk

Signal Fast Role Swap request

Definition at line 12277 of file stm32g431xx.h.

◆ UCPD_CR_FRSTX_Msk

#define UCPD_CR_FRSTX_Msk (0x1UL << UCPD_CR_FRSTX_Pos)

0x00020000

Definition at line 12276 of file stm32g431xx.h.

◆ UCPD_CR_FRSTX_Pos

#define UCPD_CR_FRSTX_Pos (17U)

Definition at line 12275 of file stm32g431xx.h.

◆ UCPD_CR_PHYCCSEL

#define UCPD_CR_PHYCCSEL UCPD_CR_PHYCCSEL_Msk

Definition at line 12258 of file stm32g431xx.h.

◆ UCPD_CR_PHYCCSEL_Msk

#define UCPD_CR_PHYCCSEL_Msk (0x1UL << UCPD_CR_PHYCCSEL_Pos)

0x00000040

Definition at line 12257 of file stm32g431xx.h.

◆ UCPD_CR_PHYCCSEL_Pos

#define UCPD_CR_PHYCCSEL_Pos (6U)

Definition at line 12256 of file stm32g431xx.h.

◆ UCPD_CR_PHYRXEN

#define UCPD_CR_PHYRXEN UCPD_CR_PHYRXEN_Msk

Controls enable of USB Power Delivery receiver

Definition at line 12255 of file stm32g431xx.h.

◆ UCPD_CR_PHYRXEN_Msk

#define UCPD_CR_PHYRXEN_Msk (0x1UL << UCPD_CR_PHYRXEN_Pos)

0x00000020

Definition at line 12254 of file stm32g431xx.h.

◆ UCPD_CR_PHYRXEN_Pos

#define UCPD_CR_PHYRXEN_Pos (5U)

Definition at line 12253 of file stm32g431xx.h.

◆ UCPD_CR_RDCH

#define UCPD_CR_RDCH UCPD_CR_RDCH_Msk

Definition at line 12280 of file stm32g431xx.h.

◆ UCPD_CR_RDCH_Msk

#define UCPD_CR_RDCH_Msk (0x1UL << UCPD_CR_RDCH_Pos)

0x00040000

Definition at line 12279 of file stm32g431xx.h.

◆ UCPD_CR_RDCH_Pos

#define UCPD_CR_RDCH_Pos (18U)

Definition at line 12278 of file stm32g431xx.h.

◆ UCPD_CR_RXMODE

#define UCPD_CR_RXMODE UCPD_CR_RXMODE_Msk

Receiver mode

Definition at line 12252 of file stm32g431xx.h.

◆ UCPD_CR_RXMODE_Msk

#define UCPD_CR_RXMODE_Msk (0x1UL << UCPD_CR_RXMODE_Pos)

0x00000010

Definition at line 12251 of file stm32g431xx.h.

◆ UCPD_CR_RXMODE_Pos

#define UCPD_CR_RXMODE_Pos (4U)

Definition at line 12250 of file stm32g431xx.h.

◆ UCPD_CR_TXHRST

#define UCPD_CR_TXHRST UCPD_CR_TXHRST_Msk

Command to send a Tx Hard Reset

Definition at line 12249 of file stm32g431xx.h.

◆ UCPD_CR_TXHRST_Msk

#define UCPD_CR_TXHRST_Msk (0x1UL << UCPD_CR_TXHRST_Pos)

0x00000008

Definition at line 12248 of file stm32g431xx.h.

◆ UCPD_CR_TXHRST_Pos

#define UCPD_CR_TXHRST_Pos (3U)

Definition at line 12247 of file stm32g431xx.h.

◆ UCPD_CR_TXMODE

#define UCPD_CR_TXMODE UCPD_CR_TXMODE_Msk

Type of Tx packet

Definition at line 12241 of file stm32g431xx.h.

◆ UCPD_CR_TXMODE_0

#define UCPD_CR_TXMODE_0 (0x1UL << UCPD_CR_TXMODE_Pos)

0x00000001

Definition at line 12242 of file stm32g431xx.h.

◆ UCPD_CR_TXMODE_1

#define UCPD_CR_TXMODE_1 (0x2UL << UCPD_CR_TXMODE_Pos)

0x00000002

Definition at line 12243 of file stm32g431xx.h.

◆ UCPD_CR_TXMODE_Msk

#define UCPD_CR_TXMODE_Msk (0x3UL << UCPD_CR_TXMODE_Pos)

0x00000003

Definition at line 12240 of file stm32g431xx.h.

◆ UCPD_CR_TXMODE_Pos

#define UCPD_CR_TXMODE_Pos (0U)

Definition at line 12239 of file stm32g431xx.h.

◆ UCPD_CR_TXSEND

#define UCPD_CR_TXSEND UCPD_CR_TXSEND_Msk

Type of Tx packet

Definition at line 12246 of file stm32g431xx.h.

◆ UCPD_CR_TXSEND_Msk

#define UCPD_CR_TXSEND_Msk (0x1UL << UCPD_CR_TXSEND_Pos)

0x00000004

Definition at line 12245 of file stm32g431xx.h.

◆ UCPD_CR_TXSEND_Pos

#define UCPD_CR_TXSEND_Pos (2U)

Definition at line 12244 of file stm32g431xx.h.

◆ UCPD_ICR_FRSEVTCF

#define UCPD_ICR_FRSEVTCF UCPD_ICR_FRSEVTCF_Msk

Fast Role Swap event flag clear

Definition at line 12434 of file stm32g431xx.h.

◆ UCPD_ICR_FRSEVTCF_Msk

#define UCPD_ICR_FRSEVTCF_Msk (0x1UL << UCPD_ICR_FRSEVTCF_Pos)

0x00100000

Definition at line 12433 of file stm32g431xx.h.

◆ UCPD_ICR_FRSEVTCF_Pos

#define UCPD_ICR_FRSEVTCF_Pos (20U)

Definition at line 12432 of file stm32g431xx.h.

◆ UCPD_ICR_HRSTDISCCF

#define UCPD_ICR_HRSTDISCCF UCPD_ICR_HRSTDISCCF_Msk

Hard reset discarded flag (HRSTDISC) clear

Definition at line 12407 of file stm32g431xx.h.

◆ UCPD_ICR_HRSTDISCCF_Msk

#define UCPD_ICR_HRSTDISCCF_Msk (0x1UL << UCPD_ICR_HRSTDISCCF_Pos)

0x00000010

Definition at line 12406 of file stm32g431xx.h.

◆ UCPD_ICR_HRSTDISCCF_Pos

#define UCPD_ICR_HRSTDISCCF_Pos (4U)

Definition at line 12405 of file stm32g431xx.h.

◆ UCPD_ICR_HRSTSENTCF

#define UCPD_ICR_HRSTSENTCF UCPD_ICR_HRSTSENTCF_Msk

Hard reset sent flag (HRSTSENT) clear

Definition at line 12410 of file stm32g431xx.h.

◆ UCPD_ICR_HRSTSENTCF_Msk

#define UCPD_ICR_HRSTSENTCF_Msk (0x1UL << UCPD_ICR_HRSTSENTCF_Pos)

0x00000020

Definition at line 12409 of file stm32g431xx.h.

◆ UCPD_ICR_HRSTSENTCF_Pos

#define UCPD_ICR_HRSTSENTCF_Pos (5U)

Definition at line 12408 of file stm32g431xx.h.

◆ UCPD_ICR_RXHRSTDETCF

#define UCPD_ICR_RXHRSTDETCF UCPD_ICR_RXHRSTDETCF_Msk

Rx Hard Reset detected flag (RXHRSTDET) clear

Definition at line 12419 of file stm32g431xx.h.

◆ UCPD_ICR_RXHRSTDETCF_Msk

#define UCPD_ICR_RXHRSTDETCF_Msk (0x1UL << UCPD_ICR_RXHRSTDETCF_Pos)

0x00000400

Definition at line 12418 of file stm32g431xx.h.

◆ UCPD_ICR_RXHRSTDETCF_Pos

#define UCPD_ICR_RXHRSTDETCF_Pos (10U)

Definition at line 12417 of file stm32g431xx.h.

◆ UCPD_ICR_RXMSGENDCF

#define UCPD_ICR_RXMSGENDCF UCPD_ICR_RXMSGENDCF_Msk

Rx message received flag (RXMSGEND) clear

Definition at line 12425 of file stm32g431xx.h.

◆ UCPD_ICR_RXMSGENDCF_Msk

#define UCPD_ICR_RXMSGENDCF_Msk (0x1UL << UCPD_ICR_RXMSGENDCF_Pos)

0x00001000

Definition at line 12424 of file stm32g431xx.h.

◆ UCPD_ICR_RXMSGENDCF_Pos

#define UCPD_ICR_RXMSGENDCF_Pos (12U)

Definition at line 12423 of file stm32g431xx.h.

◆ UCPD_ICR_RXORDDETCF

#define UCPD_ICR_RXORDDETCF UCPD_ICR_RXORDDETCF_Msk

Rx ordered set detect flag (RXORDDET) clear

Definition at line 12416 of file stm32g431xx.h.

◆ UCPD_ICR_RXORDDETCF_Msk

#define UCPD_ICR_RXORDDETCF_Msk (0x1UL << UCPD_ICR_RXORDDETCF_Pos)

0x00000200

Definition at line 12415 of file stm32g431xx.h.

◆ UCPD_ICR_RXORDDETCF_Pos

#define UCPD_ICR_RXORDDETCF_Pos (9U)

Definition at line 12414 of file stm32g431xx.h.

◆ UCPD_ICR_RXOVRCF

#define UCPD_ICR_RXOVRCF UCPD_ICR_RXOVRCF_Msk

Rx overflow flag (RXOVR) clear

Definition at line 12422 of file stm32g431xx.h.

◆ UCPD_ICR_RXOVRCF_Msk

#define UCPD_ICR_RXOVRCF_Msk (0x1UL << UCPD_ICR_RXOVRCF_Pos)

0x00000800

Definition at line 12421 of file stm32g431xx.h.

◆ UCPD_ICR_RXOVRCF_Pos

#define UCPD_ICR_RXOVRCF_Pos (11U)

Definition at line 12420 of file stm32g431xx.h.

◆ UCPD_ICR_TXMSGABTCF

#define UCPD_ICR_TXMSGABTCF UCPD_ICR_TXMSGABTCF_Msk

Tx message abort flag (TXMSGABT) clear

Definition at line 12404 of file stm32g431xx.h.

◆ UCPD_ICR_TXMSGABTCF_Msk

#define UCPD_ICR_TXMSGABTCF_Msk (0x1UL << UCPD_ICR_TXMSGABTCF_Pos)

0x00000008

Definition at line 12403 of file stm32g431xx.h.

◆ UCPD_ICR_TXMSGABTCF_Pos

#define UCPD_ICR_TXMSGABTCF_Pos (3U)

Definition at line 12402 of file stm32g431xx.h.

◆ UCPD_ICR_TXMSGDISCCF

#define UCPD_ICR_TXMSGDISCCF UCPD_ICR_TXMSGDISCCF_Msk

Tx message discarded flag (TXMSGDISC) clear

Definition at line 12398 of file stm32g431xx.h.

◆ UCPD_ICR_TXMSGDISCCF_Msk

#define UCPD_ICR_TXMSGDISCCF_Msk (0x1UL << UCPD_ICR_TXMSGDISCCF_Pos)

0x00000002

Definition at line 12397 of file stm32g431xx.h.

◆ UCPD_ICR_TXMSGDISCCF_Pos

#define UCPD_ICR_TXMSGDISCCF_Pos (1U)

Definition at line 12396 of file stm32g431xx.h.

◆ UCPD_ICR_TXMSGSENTCF

#define UCPD_ICR_TXMSGSENTCF UCPD_ICR_TXMSGSENTCF_Msk

Tx message sent flag (TXMSGSENT) clear

Definition at line 12401 of file stm32g431xx.h.

◆ UCPD_ICR_TXMSGSENTCF_Msk

#define UCPD_ICR_TXMSGSENTCF_Msk (0x1UL << UCPD_ICR_TXMSGSENTCF_Pos)

0x00000004

Definition at line 12400 of file stm32g431xx.h.

◆ UCPD_ICR_TXMSGSENTCF_Pos

#define UCPD_ICR_TXMSGSENTCF_Pos (2U)

Definition at line 12399 of file stm32g431xx.h.

◆ UCPD_ICR_TXUNDCF

#define UCPD_ICR_TXUNDCF UCPD_ICR_TXUNDCF_Msk

Tx underflow flag (TXUND) clear

Definition at line 12413 of file stm32g431xx.h.

◆ UCPD_ICR_TXUNDCF_Msk

#define UCPD_ICR_TXUNDCF_Msk (0x1UL << UCPD_ICR_TXUNDCF_Pos)

0x00000040

Definition at line 12412 of file stm32g431xx.h.

◆ UCPD_ICR_TXUNDCF_Pos

#define UCPD_ICR_TXUNDCF_Pos (6U)

Definition at line 12411 of file stm32g431xx.h.

◆ UCPD_ICR_TYPECEVT1CF

#define UCPD_ICR_TYPECEVT1CF UCPD_ICR_TYPECEVT1CF_Msk

TypeC event (CC1) flag (TYPECEVT1) clear

Definition at line 12428 of file stm32g431xx.h.

◆ UCPD_ICR_TYPECEVT1CF_Msk

#define UCPD_ICR_TYPECEVT1CF_Msk (0x1UL << UCPD_ICR_TYPECEVT1CF_Pos)

0x00004000

Definition at line 12427 of file stm32g431xx.h.

◆ UCPD_ICR_TYPECEVT1CF_Pos

#define UCPD_ICR_TYPECEVT1CF_Pos (14U)

Definition at line 12426 of file stm32g431xx.h.

◆ UCPD_ICR_TYPECEVT2CF

#define UCPD_ICR_TYPECEVT2CF UCPD_ICR_TYPECEVT2CF_Msk

TypeC event (CC2) flag (TYPECEVT2) clear

Definition at line 12431 of file stm32g431xx.h.

◆ UCPD_ICR_TYPECEVT2CF_Msk

#define UCPD_ICR_TYPECEVT2CF_Msk (0x1UL << UCPD_ICR_TYPECEVT2CF_Pos)

0x00008000

Definition at line 12430 of file stm32g431xx.h.

◆ UCPD_ICR_TYPECEVT2CF_Pos

#define UCPD_ICR_TYPECEVT2CF_Pos (15U)

Definition at line 12429 of file stm32g431xx.h.

◆ UCPD_IMR_FRSEVTIE

#define UCPD_IMR_FRSEVTIE UCPD_IMR_FRSEVTIE_Msk

Fast Role Swap interrupt

Definition at line 12333 of file stm32g431xx.h.

◆ UCPD_IMR_FRSEVTIE_Msk

#define UCPD_IMR_FRSEVTIE_Msk (0x1UL << UCPD_IMR_FRSEVTIE_Pos)

0x00100000

Definition at line 12332 of file stm32g431xx.h.

◆ UCPD_IMR_FRSEVTIE_Pos

#define UCPD_IMR_FRSEVTIE_Pos (20U)

Definition at line 12331 of file stm32g431xx.h.

◆ UCPD_IMR_HRSTDISCIE

#define UCPD_IMR_HRSTDISCIE UCPD_IMR_HRSTDISCIE_Msk

Enable HRSTDISC interrupt

Definition at line 12303 of file stm32g431xx.h.

◆ UCPD_IMR_HRSTDISCIE_Msk

#define UCPD_IMR_HRSTDISCIE_Msk (0x1UL << UCPD_IMR_HRSTDISCIE_Pos)

0x00000010

Definition at line 12302 of file stm32g431xx.h.

◆ UCPD_IMR_HRSTDISCIE_Pos

#define UCPD_IMR_HRSTDISCIE_Pos (4U)

Definition at line 12301 of file stm32g431xx.h.

◆ UCPD_IMR_HRSTSENTIE

#define UCPD_IMR_HRSTSENTIE UCPD_IMR_HRSTSENTIE_Msk

Enable HRSTSENT interrupt

Definition at line 12306 of file stm32g431xx.h.

◆ UCPD_IMR_HRSTSENTIE_Msk

#define UCPD_IMR_HRSTSENTIE_Msk (0x1UL << UCPD_IMR_HRSTSENTIE_Pos)

0x00000020

Definition at line 12305 of file stm32g431xx.h.

◆ UCPD_IMR_HRSTSENTIE_Pos

#define UCPD_IMR_HRSTSENTIE_Pos (5U)

Definition at line 12304 of file stm32g431xx.h.

◆ UCPD_IMR_RXHRSTDETIE

#define UCPD_IMR_RXHRSTDETIE UCPD_IMR_RXHRSTDETIE_Msk

Enable RXHRSTDET interrupt

Definition at line 12318 of file stm32g431xx.h.

◆ UCPD_IMR_RXHRSTDETIE_Msk

#define UCPD_IMR_RXHRSTDETIE_Msk (0x1UL << UCPD_IMR_RXHRSTDETIE_Pos)

0x00000400

Definition at line 12317 of file stm32g431xx.h.

◆ UCPD_IMR_RXHRSTDETIE_Pos

#define UCPD_IMR_RXHRSTDETIE_Pos (10U)

Definition at line 12316 of file stm32g431xx.h.

◆ UCPD_IMR_RXMSGENDIE

#define UCPD_IMR_RXMSGENDIE UCPD_IMR_RXMSGENDIE_Msk

Enable RXMSGEND interrupt

Definition at line 12324 of file stm32g431xx.h.

◆ UCPD_IMR_RXMSGENDIE_Msk

#define UCPD_IMR_RXMSGENDIE_Msk (0x1UL << UCPD_IMR_RXMSGENDIE_Pos)

0x00001000

Definition at line 12323 of file stm32g431xx.h.

◆ UCPD_IMR_RXMSGENDIE_Pos

#define UCPD_IMR_RXMSGENDIE_Pos (12U)

Definition at line 12322 of file stm32g431xx.h.

◆ UCPD_IMR_RXNEIE

#define UCPD_IMR_RXNEIE UCPD_IMR_RXNEIE_Msk

Enable RXNE interrupt

Definition at line 12312 of file stm32g431xx.h.

◆ UCPD_IMR_RXNEIE_Msk

#define UCPD_IMR_RXNEIE_Msk (0x1UL << UCPD_IMR_RXNEIE_Pos)

0x00000100

Definition at line 12311 of file stm32g431xx.h.

◆ UCPD_IMR_RXNEIE_Pos

#define UCPD_IMR_RXNEIE_Pos (8U)

Definition at line 12310 of file stm32g431xx.h.

◆ UCPD_IMR_RXORDDETIE

#define UCPD_IMR_RXORDDETIE UCPD_IMR_RXORDDETIE_Msk

Enable RXORDDET interrupt

Definition at line 12315 of file stm32g431xx.h.

◆ UCPD_IMR_RXORDDETIE_Msk

#define UCPD_IMR_RXORDDETIE_Msk (0x1UL << UCPD_IMR_RXORDDETIE_Pos)

0x00000200

Definition at line 12314 of file stm32g431xx.h.

◆ UCPD_IMR_RXORDDETIE_Pos

#define UCPD_IMR_RXORDDETIE_Pos (9U)

Definition at line 12313 of file stm32g431xx.h.

◆ UCPD_IMR_RXOVRIE

#define UCPD_IMR_RXOVRIE UCPD_IMR_RXOVRIE_Msk

Enable RXOVR interrupt

Definition at line 12321 of file stm32g431xx.h.

◆ UCPD_IMR_RXOVRIE_Msk

#define UCPD_IMR_RXOVRIE_Msk (0x1UL << UCPD_IMR_RXOVRIE_Pos)

0x00000800

Definition at line 12320 of file stm32g431xx.h.

◆ UCPD_IMR_RXOVRIE_Pos

#define UCPD_IMR_RXOVRIE_Pos (11U)

Definition at line 12319 of file stm32g431xx.h.

◆ UCPD_IMR_TXISIE

#define UCPD_IMR_TXISIE UCPD_IMR_TXISIE_Msk

Enable TXIS interrupt

Definition at line 12291 of file stm32g431xx.h.

◆ UCPD_IMR_TXISIE_Msk

#define UCPD_IMR_TXISIE_Msk (0x1UL << UCPD_IMR_TXISIE_Pos)

0x00000001

Definition at line 12290 of file stm32g431xx.h.

◆ UCPD_IMR_TXISIE_Pos

#define UCPD_IMR_TXISIE_Pos (0U)

Definition at line 12289 of file stm32g431xx.h.

◆ UCPD_IMR_TXMSGABTIE

#define UCPD_IMR_TXMSGABTIE UCPD_IMR_TXMSGABTIE_Msk

Enable TXMSGABT interrupt

Definition at line 12300 of file stm32g431xx.h.

◆ UCPD_IMR_TXMSGABTIE_Msk

#define UCPD_IMR_TXMSGABTIE_Msk (0x1UL << UCPD_IMR_TXMSGABTIE_Pos)

0x00000008

Definition at line 12299 of file stm32g431xx.h.

◆ UCPD_IMR_TXMSGABTIE_Pos

#define UCPD_IMR_TXMSGABTIE_Pos (3U)

Definition at line 12298 of file stm32g431xx.h.

◆ UCPD_IMR_TXMSGDISCIE

#define UCPD_IMR_TXMSGDISCIE UCPD_IMR_TXMSGDISCIE_Msk

Enable TXMSGDISC interrupt

Definition at line 12294 of file stm32g431xx.h.

◆ UCPD_IMR_TXMSGDISCIE_Msk

#define UCPD_IMR_TXMSGDISCIE_Msk (0x1UL << UCPD_IMR_TXMSGDISCIE_Pos)

0x00000002

Definition at line 12293 of file stm32g431xx.h.

◆ UCPD_IMR_TXMSGDISCIE_Pos

#define UCPD_IMR_TXMSGDISCIE_Pos (1U)

Definition at line 12292 of file stm32g431xx.h.

◆ UCPD_IMR_TXMSGSENTIE

#define UCPD_IMR_TXMSGSENTIE UCPD_IMR_TXMSGSENTIE_Msk

Enable TXMSGSENT interrupt

Definition at line 12297 of file stm32g431xx.h.

◆ UCPD_IMR_TXMSGSENTIE_Msk

#define UCPD_IMR_TXMSGSENTIE_Msk (0x1UL << UCPD_IMR_TXMSGSENTIE_Pos)

0x00000004

Definition at line 12296 of file stm32g431xx.h.

◆ UCPD_IMR_TXMSGSENTIE_Pos

#define UCPD_IMR_TXMSGSENTIE_Pos (2U)

Definition at line 12295 of file stm32g431xx.h.

◆ UCPD_IMR_TXUNDIE

#define UCPD_IMR_TXUNDIE UCPD_IMR_TXUNDIE_Msk

Enable TXUND interrupt

Definition at line 12309 of file stm32g431xx.h.

◆ UCPD_IMR_TXUNDIE_Msk

#define UCPD_IMR_TXUNDIE_Msk (0x1UL << UCPD_IMR_TXUNDIE_Pos)

0x00000040

Definition at line 12308 of file stm32g431xx.h.

◆ UCPD_IMR_TXUNDIE_Pos

#define UCPD_IMR_TXUNDIE_Pos (6U)

Definition at line 12307 of file stm32g431xx.h.

◆ UCPD_IMR_TYPECEVT1IE

#define UCPD_IMR_TYPECEVT1IE UCPD_IMR_TYPECEVT1IE_Msk

Enable TYPECEVT1IE interrupt

Definition at line 12327 of file stm32g431xx.h.

◆ UCPD_IMR_TYPECEVT1IE_Msk

#define UCPD_IMR_TYPECEVT1IE_Msk (0x1UL << UCPD_IMR_TYPECEVT1IE_Pos)

0x00004000

Definition at line 12326 of file stm32g431xx.h.

◆ UCPD_IMR_TYPECEVT1IE_Pos

#define UCPD_IMR_TYPECEVT1IE_Pos (14U)

Definition at line 12325 of file stm32g431xx.h.

◆ UCPD_IMR_TYPECEVT2IE

#define UCPD_IMR_TYPECEVT2IE UCPD_IMR_TYPECEVT2IE_Msk

Enable TYPECEVT2IE interrupt

Definition at line 12330 of file stm32g431xx.h.

◆ UCPD_IMR_TYPECEVT2IE_Msk

#define UCPD_IMR_TYPECEVT2IE_Msk (0x1UL << UCPD_IMR_TYPECEVT2IE_Pos)

0x00008000

Definition at line 12329 of file stm32g431xx.h.

◆ UCPD_IMR_TYPECEVT2IE_Pos

#define UCPD_IMR_TYPECEVT2IE_Pos (15U)

Definition at line 12328 of file stm32g431xx.h.

◆ UCPD_RX_ORDEXT1_RXSOPX1

#define UCPD_RX_ORDEXT1_RXSOPX1 UCPD_RX_ORDEXT1_RXSOPX1_Msk

RX Ordered Set Extension Register 1

Definition at line 12478 of file stm32g431xx.h.

◆ UCPD_RX_ORDEXT1_RXSOPX1_Msk

#define UCPD_RX_ORDEXT1_RXSOPX1_Msk (0xFFFFFUL << UCPD_RX_ORDEXT1_RXSOPX1_Pos)

0x000FFFFF

Definition at line 12477 of file stm32g431xx.h.

◆ UCPD_RX_ORDEXT1_RXSOPX1_Pos

#define UCPD_RX_ORDEXT1_RXSOPX1_Pos (0U)

Definition at line 12476 of file stm32g431xx.h.

◆ UCPD_RX_ORDEXT2_RXSOPX2

#define UCPD_RX_ORDEXT2_RXSOPX2 UCPD_RX_ORDEXT2_RXSOPX2_Msk

RX Ordered Set Extension Register 1

Definition at line 12483 of file stm32g431xx.h.

◆ UCPD_RX_ORDEXT2_RXSOPX2_Msk

#define UCPD_RX_ORDEXT2_RXSOPX2_Msk (0xFFFFFUL << UCPD_RX_ORDEXT2_RXSOPX2_Pos)

0x000FFFFF

Definition at line 12482 of file stm32g431xx.h.

◆ UCPD_RX_ORDEXT2_RXSOPX2_Pos

#define UCPD_RX_ORDEXT2_RXSOPX2_Pos (0U)

Definition at line 12481 of file stm32g431xx.h.

◆ UCPD_RX_ORDSET_RXORDSET

#define UCPD_RX_ORDSET_RXORDSET UCPD_RX_ORDSET_RXORDSET_Msk

Rx Ordered Set Code detected

Definition at line 12454 of file stm32g431xx.h.

◆ UCPD_RX_ORDSET_RXORDSET_0

#define UCPD_RX_ORDSET_RXORDSET_0 (0x1UL << UCPD_RX_ORDSET_RXORDSET_Pos)

0x00000001

Definition at line 12455 of file stm32g431xx.h.

◆ UCPD_RX_ORDSET_RXORDSET_1

#define UCPD_RX_ORDSET_RXORDSET_1 (0x2UL << UCPD_RX_ORDSET_RXORDSET_Pos)

0x00000002

Definition at line 12456 of file stm32g431xx.h.

◆ UCPD_RX_ORDSET_RXORDSET_2

#define UCPD_RX_ORDSET_RXORDSET_2 (0x4UL << UCPD_RX_ORDSET_RXORDSET_Pos)

0x00000004

Definition at line 12457 of file stm32g431xx.h.

◆ UCPD_RX_ORDSET_RXORDSET_Msk

#define UCPD_RX_ORDSET_RXORDSET_Msk (0x7UL << UCPD_RX_ORDSET_RXORDSET_Pos)

0x00000007

Definition at line 12453 of file stm32g431xx.h.

◆ UCPD_RX_ORDSET_RXORDSET_Pos

#define UCPD_RX_ORDSET_RXORDSET_Pos (0U)

Definition at line 12452 of file stm32g431xx.h.

◆ UCPD_RX_ORDSET_RXSOP3OF4

#define UCPD_RX_ORDSET_RXSOP3OF4 UCPD_RX_ORDSET_RXSOP3OF4_Msk

Rx Ordered Set Debug indication

Definition at line 12460 of file stm32g431xx.h.

◆ UCPD_RX_ORDSET_RXSOP3OF4_Msk

#define UCPD_RX_ORDSET_RXSOP3OF4_Msk (0x1UL << UCPD_RX_ORDSET_RXSOP3OF4_Pos)

0x00000008

Definition at line 12459 of file stm32g431xx.h.

◆ UCPD_RX_ORDSET_RXSOP3OF4_Pos

#define UCPD_RX_ORDSET_RXSOP3OF4_Pos (3U)

Definition at line 12458 of file stm32g431xx.h.

◆ UCPD_RX_ORDSET_RXSOPKINVALID

#define UCPD_RX_ORDSET_RXSOPKINVALID UCPD_RX_ORDSET_RXSOPKINVALID_Msk

Rx Ordered Set corrupted K-Codes (Debug)

Definition at line 12463 of file stm32g431xx.h.

◆ UCPD_RX_ORDSET_RXSOPKINVALID_Msk

#define UCPD_RX_ORDSET_RXSOPKINVALID_Msk (0x7UL << UCPD_RX_ORDSET_RXSOPKINVALID_Pos)

0x00000070

Definition at line 12462 of file stm32g431xx.h.

◆ UCPD_RX_ORDSET_RXSOPKINVALID_Pos

#define UCPD_RX_ORDSET_RXSOPKINVALID_Pos (4U)

Definition at line 12461 of file stm32g431xx.h.

◆ UCPD_RX_PAYSZ_RXPAYSZ

#define UCPD_RX_PAYSZ_RXPAYSZ UCPD_RX_PAYSZ_RXPAYSZ_Msk

Rx payload size in bytes

Definition at line 12468 of file stm32g431xx.h.

◆ UCPD_RX_PAYSZ_RXPAYSZ_Msk

#define UCPD_RX_PAYSZ_RXPAYSZ_Msk (0x3FFUL << UCPD_RX_PAYSZ_RXPAYSZ_Pos)

0x000003FF

Definition at line 12467 of file stm32g431xx.h.

◆ UCPD_RX_PAYSZ_RXPAYSZ_Pos

#define UCPD_RX_PAYSZ_RXPAYSZ_Pos (0U)

Definition at line 12466 of file stm32g431xx.h.

◆ UCPD_RXDR_RXDATA

#define UCPD_RXDR_RXDATA UCPD_RXDR_RXDATA_Msk

8-bit receive data

Definition at line 12473 of file stm32g431xx.h.

◆ UCPD_RXDR_RXDATA_Msk

#define UCPD_RXDR_RXDATA_Msk (0xFFUL << UCPD_RXDR_RXDATA_Pos)

0x000000FF

Definition at line 12472 of file stm32g431xx.h.

◆ UCPD_RXDR_RXDATA_Pos

#define UCPD_RXDR_RXDATA_Pos (0U)

Definition at line 12471 of file stm32g431xx.h.

◆ UCPD_SR_FRSEVT

#define UCPD_SR_FRSEVT UCPD_SR_FRSEVT_Msk

Fast Role Swap detection event

Definition at line 12393 of file stm32g431xx.h.

◆ UCPD_SR_FRSEVT_Msk

#define UCPD_SR_FRSEVT_Msk (0x1UL << UCPD_SR_FRSEVT_Pos)

0x00100000

Definition at line 12392 of file stm32g431xx.h.

◆ UCPD_SR_FRSEVT_Pos

#define UCPD_SR_FRSEVT_Pos (20U)

Definition at line 12391 of file stm32g431xx.h.

◆ UCPD_SR_HRSTDISC

#define UCPD_SR_HRSTDISC UCPD_SR_HRSTDISC_Msk

HRST discarded interrupt

Definition at line 12350 of file stm32g431xx.h.

◆ UCPD_SR_HRSTDISC_Msk

#define UCPD_SR_HRSTDISC_Msk (0x1UL << UCPD_SR_HRSTDISC_Pos)

0x00000010

Definition at line 12349 of file stm32g431xx.h.

◆ UCPD_SR_HRSTDISC_Pos

#define UCPD_SR_HRSTDISC_Pos (4U)

Definition at line 12348 of file stm32g431xx.h.

◆ UCPD_SR_HRSTSENT

#define UCPD_SR_HRSTSENT UCPD_SR_HRSTSENT_Msk

HRST sent interrupt

Definition at line 12353 of file stm32g431xx.h.

◆ UCPD_SR_HRSTSENT_Msk

#define UCPD_SR_HRSTSENT_Msk (0x1UL << UCPD_SR_HRSTSENT_Pos)

0x00000020

Definition at line 12352 of file stm32g431xx.h.

◆ UCPD_SR_HRSTSENT_Pos

#define UCPD_SR_HRSTSENT_Pos (5U)

Definition at line 12351 of file stm32g431xx.h.

◆ UCPD_SR_RXERR

#define UCPD_SR_RXERR UCPD_SR_RXERR_Msk

RX Error

Definition at line 12374 of file stm32g431xx.h.

◆ UCPD_SR_RXERR_Msk

#define UCPD_SR_RXERR_Msk (0x1UL << UCPD_SR_RXERR_Pos)

0x00002000

Definition at line 12373 of file stm32g431xx.h.

◆ UCPD_SR_RXERR_Pos

#define UCPD_SR_RXERR_Pos (13U)

Definition at line 12372 of file stm32g431xx.h.

◆ UCPD_SR_RXHRSTDET

#define UCPD_SR_RXHRSTDET UCPD_SR_RXHRSTDET_Msk

Rx Hard Reset detect interrupt

Definition at line 12365 of file stm32g431xx.h.

◆ UCPD_SR_RXHRSTDET_Msk

#define UCPD_SR_RXHRSTDET_Msk (0x1UL << UCPD_SR_RXHRSTDET_Pos)

0x00000400

Definition at line 12364 of file stm32g431xx.h.

◆ UCPD_SR_RXHRSTDET_Pos

#define UCPD_SR_RXHRSTDET_Pos (10U)

Definition at line 12363 of file stm32g431xx.h.

◆ UCPD_SR_RXMSGEND

#define UCPD_SR_RXMSGEND UCPD_SR_RXMSGEND_Msk

Rx message received

Definition at line 12371 of file stm32g431xx.h.

◆ UCPD_SR_RXMSGEND_Msk

#define UCPD_SR_RXMSGEND_Msk (0x1UL << UCPD_SR_RXMSGEND_Pos)

0x00001000

Definition at line 12370 of file stm32g431xx.h.

◆ UCPD_SR_RXMSGEND_Pos

#define UCPD_SR_RXMSGEND_Pos (12U)

Definition at line 12369 of file stm32g431xx.h.

◆ UCPD_SR_RXNE

#define UCPD_SR_RXNE UCPD_SR_RXNE_Msk

Receive data register not empty interrupt

Definition at line 12359 of file stm32g431xx.h.

◆ UCPD_SR_RXNE_Msk

#define UCPD_SR_RXNE_Msk (0x1UL << UCPD_SR_RXNE_Pos)

0x00000100

Definition at line 12358 of file stm32g431xx.h.

◆ UCPD_SR_RXNE_Pos

#define UCPD_SR_RXNE_Pos (8U)

Definition at line 12357 of file stm32g431xx.h.

◆ UCPD_SR_RXORDDET

#define UCPD_SR_RXORDDET UCPD_SR_RXORDDET_Msk

Rx ordered set (4 K-codes) detected interrupt

Definition at line 12362 of file stm32g431xx.h.

◆ UCPD_SR_RXORDDET_Msk

#define UCPD_SR_RXORDDET_Msk (0x1UL << UCPD_SR_RXORDDET_Pos)

0x00000200

Definition at line 12361 of file stm32g431xx.h.

◆ UCPD_SR_RXORDDET_Pos

#define UCPD_SR_RXORDDET_Pos (9U)

Definition at line 12360 of file stm32g431xx.h.

◆ UCPD_SR_RXOVR

#define UCPD_SR_RXOVR UCPD_SR_RXOVR_Msk

Rx data overflow interrupt

Definition at line 12368 of file stm32g431xx.h.

◆ UCPD_SR_RXOVR_Msk

#define UCPD_SR_RXOVR_Msk (0x1UL << UCPD_SR_RXOVR_Pos)

0x00000800

Definition at line 12367 of file stm32g431xx.h.

◆ UCPD_SR_RXOVR_Pos

#define UCPD_SR_RXOVR_Pos (11U)

Definition at line 12366 of file stm32g431xx.h.

◆ UCPD_SR_TXIS

#define UCPD_SR_TXIS UCPD_SR_TXIS_Msk

Transmit interrupt status

Definition at line 12338 of file stm32g431xx.h.

◆ UCPD_SR_TXIS_Msk

#define UCPD_SR_TXIS_Msk (0x1UL << UCPD_SR_TXIS_Pos)

0x00000001

Definition at line 12337 of file stm32g431xx.h.

◆ UCPD_SR_TXIS_Pos

#define UCPD_SR_TXIS_Pos (0U)

Definition at line 12336 of file stm32g431xx.h.

◆ UCPD_SR_TXMSGABT

#define UCPD_SR_TXMSGABT UCPD_SR_TXMSGABT_Msk

Transmit message abort interrupt

Definition at line 12347 of file stm32g431xx.h.

◆ UCPD_SR_TXMSGABT_Msk

#define UCPD_SR_TXMSGABT_Msk (0x1UL << UCPD_SR_TXMSGABT_Pos)

0x00000008

Definition at line 12346 of file stm32g431xx.h.

◆ UCPD_SR_TXMSGABT_Pos

#define UCPD_SR_TXMSGABT_Pos (3U)

Definition at line 12345 of file stm32g431xx.h.

◆ UCPD_SR_TXMSGDISC

#define UCPD_SR_TXMSGDISC UCPD_SR_TXMSGDISC_Msk

Transmit message discarded interrupt

Definition at line 12341 of file stm32g431xx.h.

◆ UCPD_SR_TXMSGDISC_Msk

#define UCPD_SR_TXMSGDISC_Msk (0x1UL << UCPD_SR_TXMSGDISC_Pos)

0x00000002

Definition at line 12340 of file stm32g431xx.h.

◆ UCPD_SR_TXMSGDISC_Pos

#define UCPD_SR_TXMSGDISC_Pos (1U)

Definition at line 12339 of file stm32g431xx.h.

◆ UCPD_SR_TXMSGSENT

#define UCPD_SR_TXMSGSENT UCPD_SR_TXMSGSENT_Msk

Transmit message sent interrupt

Definition at line 12344 of file stm32g431xx.h.

◆ UCPD_SR_TXMSGSENT_Msk

#define UCPD_SR_TXMSGSENT_Msk (0x1UL << UCPD_SR_TXMSGSENT_Pos)

0x00000004

Definition at line 12343 of file stm32g431xx.h.

◆ UCPD_SR_TXMSGSENT_Pos

#define UCPD_SR_TXMSGSENT_Pos (2U)

Definition at line 12342 of file stm32g431xx.h.

◆ UCPD_SR_TXUND

#define UCPD_SR_TXUND UCPD_SR_TXUND_Msk

Tx data underrun condition interrupt

Definition at line 12356 of file stm32g431xx.h.

◆ UCPD_SR_TXUND_Msk

#define UCPD_SR_TXUND_Msk (0x1UL << UCPD_SR_TXUND_Pos)

0x00000040

Definition at line 12355 of file stm32g431xx.h.

◆ UCPD_SR_TXUND_Pos

#define UCPD_SR_TXUND_Pos (6U)

Definition at line 12354 of file stm32g431xx.h.

◆ UCPD_SR_TYPEC_VSTATE_CC1

#define UCPD_SR_TYPEC_VSTATE_CC1 UCPD_SR_TYPEC_VSTATE_CC1_Msk

Status of DC level on CC1 pin

Definition at line 12383 of file stm32g431xx.h.

◆ UCPD_SR_TYPEC_VSTATE_CC1_0

#define UCPD_SR_TYPEC_VSTATE_CC1_0 (0x1UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)

0x00010000

Definition at line 12384 of file stm32g431xx.h.

◆ UCPD_SR_TYPEC_VSTATE_CC1_1

#define UCPD_SR_TYPEC_VSTATE_CC1_1 (0x2UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)

0x00020000

Definition at line 12385 of file stm32g431xx.h.

◆ UCPD_SR_TYPEC_VSTATE_CC1_Msk

#define UCPD_SR_TYPEC_VSTATE_CC1_Msk (0x3UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)

0x00030000

Definition at line 12382 of file stm32g431xx.h.

◆ UCPD_SR_TYPEC_VSTATE_CC1_Pos

#define UCPD_SR_TYPEC_VSTATE_CC1_Pos (16U)

Definition at line 12381 of file stm32g431xx.h.

◆ UCPD_SR_TYPEC_VSTATE_CC2

#define UCPD_SR_TYPEC_VSTATE_CC2 UCPD_SR_TYPEC_VSTATE_CC2_Msk

Status of DC level on CC2 pin

Definition at line 12388 of file stm32g431xx.h.

◆ UCPD_SR_TYPEC_VSTATE_CC2_0

#define UCPD_SR_TYPEC_VSTATE_CC2_0 (0x1UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)

0x00040000

Definition at line 12389 of file stm32g431xx.h.

◆ UCPD_SR_TYPEC_VSTATE_CC2_1

#define UCPD_SR_TYPEC_VSTATE_CC2_1 (0x2UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)

0x00080000

Definition at line 12390 of file stm32g431xx.h.

◆ UCPD_SR_TYPEC_VSTATE_CC2_Msk

#define UCPD_SR_TYPEC_VSTATE_CC2_Msk (0x3UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)

0x000C0000

Definition at line 12387 of file stm32g431xx.h.

◆ UCPD_SR_TYPEC_VSTATE_CC2_Pos

#define UCPD_SR_TYPEC_VSTATE_CC2_Pos (18U)

Definition at line 12386 of file stm32g431xx.h.

◆ UCPD_SR_TYPECEVT1

#define UCPD_SR_TYPECEVT1 UCPD_SR_TYPECEVT1_Msk

Type C voltage level event on CC1

Definition at line 12377 of file stm32g431xx.h.

◆ UCPD_SR_TYPECEVT1_Msk

#define UCPD_SR_TYPECEVT1_Msk (0x1UL << UCPD_SR_TYPECEVT1_Pos)

0x00004000

Definition at line 12376 of file stm32g431xx.h.

◆ UCPD_SR_TYPECEVT1_Pos

#define UCPD_SR_TYPECEVT1_Pos (14U)

Definition at line 12375 of file stm32g431xx.h.

◆ UCPD_SR_TYPECEVT2

#define UCPD_SR_TYPECEVT2 UCPD_SR_TYPECEVT2_Msk

Type C voltage level event on CC2

Definition at line 12380 of file stm32g431xx.h.

◆ UCPD_SR_TYPECEVT2_Msk

#define UCPD_SR_TYPECEVT2_Msk (0x1UL << UCPD_SR_TYPECEVT2_Pos)

0x00008000

Definition at line 12379 of file stm32g431xx.h.

◆ UCPD_SR_TYPECEVT2_Pos

#define UCPD_SR_TYPECEVT2_Pos (15U)

Definition at line 12378 of file stm32g431xx.h.

◆ UCPD_TX_ORDSET_TXORDSET

#define UCPD_TX_ORDSET_TXORDSET UCPD_TX_ORDSET_TXORDSET_Msk

Tx Ordered Set

Definition at line 12439 of file stm32g431xx.h.

◆ UCPD_TX_ORDSET_TXORDSET_Msk

#define UCPD_TX_ORDSET_TXORDSET_Msk (0xFFFFFUL << UCPD_TX_ORDSET_TXORDSET_Pos)

0x000FFFFF

Definition at line 12438 of file stm32g431xx.h.

◆ UCPD_TX_ORDSET_TXORDSET_Pos

#define UCPD_TX_ORDSET_TXORDSET_Pos (0U)

Definition at line 12437 of file stm32g431xx.h.

◆ UCPD_TX_PAYSZ_TXPAYSZ

#define UCPD_TX_PAYSZ_TXPAYSZ UCPD_TX_PAYSZ_TXPAYSZ_Msk

Tx payload size in bytes

Definition at line 12444 of file stm32g431xx.h.

◆ UCPD_TX_PAYSZ_TXPAYSZ_Msk

#define UCPD_TX_PAYSZ_TXPAYSZ_Msk (0x3FFUL << UCPD_TX_PAYSZ_TXPAYSZ_Pos)

0x000003FF

Definition at line 12443 of file stm32g431xx.h.

◆ UCPD_TX_PAYSZ_TXPAYSZ_Pos

#define UCPD_TX_PAYSZ_TXPAYSZ_Pos (0U)

Definition at line 12442 of file stm32g431xx.h.

◆ UCPD_TXDR_TXDATA

#define UCPD_TXDR_TXDATA UCPD_TXDR_TXDATA_Msk

Tx Data Register

Definition at line 12449 of file stm32g431xx.h.

◆ UCPD_TXDR_TXDATA_Msk

#define UCPD_TXDR_TXDATA_Msk (0xFFUL << UCPD_TXDR_TXDATA_Pos)

0x000000FF

Definition at line 12448 of file stm32g431xx.h.

◆ UCPD_TXDR_TXDATA_Pos

#define UCPD_TXDR_TXDATA_Pos (0U)

Definition at line 12447 of file stm32g431xx.h.

◆ USART_BRR_BRR

#define USART_BRR_BRR USART_BRR_BRR_Msk

USART Baud rate register [15:0]

Definition at line 11285 of file stm32g431xx.h.

◆ USART_BRR_BRR_Msk

#define USART_BRR_BRR_Msk (0xFFFFUL << USART_BRR_BRR_Pos)

0x0000FFFF

Definition at line 11284 of file stm32g431xx.h.

◆ USART_BRR_BRR_Pos

#define USART_BRR_BRR_Pos (0U)

Definition at line 11283 of file stm32g431xx.h.

◆ USART_BRR_LPUART

#define USART_BRR_LPUART USART_BRR_LPUART_Msk

LPUART Baud rate register [19:0]

Definition at line 11282 of file stm32g431xx.h.

◆ USART_BRR_LPUART_Msk

#define USART_BRR_LPUART_Msk (0xFFFFFUL << USART_BRR_LPUART_Pos)

0x000FFFFF

Definition at line 11281 of file stm32g431xx.h.

◆ USART_BRR_LPUART_Pos

#define USART_BRR_LPUART_Pos (0U)

Definition at line 11280 of file stm32g431xx.h.

◆ USART_CR1_CMIE

#define USART_CR1_CMIE USART_CR1_CMIE_Msk

Character match interrupt enable

Definition at line 11089 of file stm32g431xx.h.

◆ USART_CR1_CMIE_Msk

#define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos)

0x00004000

Definition at line 11088 of file stm32g431xx.h.

◆ USART_CR1_CMIE_Pos

#define USART_CR1_CMIE_Pos (14U)

Definition at line 11087 of file stm32g431xx.h.

◆ USART_CR1_DEAT

#define USART_CR1_DEAT USART_CR1_DEAT_Msk

DEAT[4:0] bits (Driver Enable Assertion Time)

Definition at line 11103 of file stm32g431xx.h.

◆ USART_CR1_DEAT_0

#define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos)

0x00200000

Definition at line 11104 of file stm32g431xx.h.

◆ USART_CR1_DEAT_1

#define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos)

0x00400000

Definition at line 11105 of file stm32g431xx.h.

◆ USART_CR1_DEAT_2

#define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos)

0x00800000

Definition at line 11106 of file stm32g431xx.h.

◆ USART_CR1_DEAT_3

#define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos)

0x01000000

Definition at line 11107 of file stm32g431xx.h.

◆ USART_CR1_DEAT_4

#define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos)

0x02000000

Definition at line 11108 of file stm32g431xx.h.

◆ USART_CR1_DEAT_Msk

#define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos)

0x03E00000

Definition at line 11102 of file stm32g431xx.h.

◆ USART_CR1_DEAT_Pos

#define USART_CR1_DEAT_Pos (21U)

Definition at line 11101 of file stm32g431xx.h.

◆ USART_CR1_DEDT

#define USART_CR1_DEDT USART_CR1_DEDT_Msk

DEDT[4:0] bits (Driver Enable Deassertion Time)

Definition at line 11095 of file stm32g431xx.h.

◆ USART_CR1_DEDT_0

#define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos)

0x00010000

Definition at line 11096 of file stm32g431xx.h.

◆ USART_CR1_DEDT_1

#define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos)

0x00020000

Definition at line 11097 of file stm32g431xx.h.

◆ USART_CR1_DEDT_2

#define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos)

0x00040000

Definition at line 11098 of file stm32g431xx.h.

◆ USART_CR1_DEDT_3

#define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos)

0x00080000

Definition at line 11099 of file stm32g431xx.h.

◆ USART_CR1_DEDT_4

#define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos)

0x00100000

Definition at line 11100 of file stm32g431xx.h.

◆ USART_CR1_DEDT_Msk

#define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos)

0x001F0000

Definition at line 11094 of file stm32g431xx.h.

◆ USART_CR1_DEDT_Pos

#define USART_CR1_DEDT_Pos (16U)

Definition at line 11093 of file stm32g431xx.h.

◆ USART_CR1_EOBIE

#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk

End of Block interrupt enable

Definition at line 11114 of file stm32g431xx.h.

◆ USART_CR1_EOBIE_Msk

#define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos)

0x08000000

Definition at line 11113 of file stm32g431xx.h.

◆ USART_CR1_EOBIE_Pos

#define USART_CR1_EOBIE_Pos (27U)

Definition at line 11112 of file stm32g431xx.h.

◆ USART_CR1_FIFOEN

#define USART_CR1_FIFOEN USART_CR1_FIFOEN_Msk

FIFO mode enable

Definition at line 11120 of file stm32g431xx.h.

◆ USART_CR1_FIFOEN_Msk

#define USART_CR1_FIFOEN_Msk (0x1UL << USART_CR1_FIFOEN_Pos)

0x20000000

Definition at line 11119 of file stm32g431xx.h.

◆ USART_CR1_FIFOEN_Pos

#define USART_CR1_FIFOEN_Pos (29U)

Definition at line 11118 of file stm32g431xx.h.

◆ USART_CR1_IDLEIE

#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk

IDLE Interrupt Enable

Definition at line 11050 of file stm32g431xx.h.

◆ USART_CR1_IDLEIE_Msk

#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos)

0x00000010

Definition at line 11049 of file stm32g431xx.h.

◆ USART_CR1_IDLEIE_Pos

#define USART_CR1_IDLEIE_Pos (4U)

Definition at line 11048 of file stm32g431xx.h.

◆ USART_CR1_M

#define USART_CR1_M USART_CR1_M_Msk

Word length

Definition at line 11080 of file stm32g431xx.h.

◆ USART_CR1_M0

#define USART_CR1_M0 USART_CR1_M0_Msk

Word length - Bit 0

Definition at line 11083 of file stm32g431xx.h.

◆ USART_CR1_M0_Msk

#define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos)

0x00001000

Definition at line 11082 of file stm32g431xx.h.

◆ USART_CR1_M0_Pos

#define USART_CR1_M0_Pos (12U)

Definition at line 11081 of file stm32g431xx.h.

◆ USART_CR1_M1

#define USART_CR1_M1 USART_CR1_M1_Msk

Word length - Bit 1

Definition at line 11117 of file stm32g431xx.h.

◆ USART_CR1_M1_Msk

#define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos)

0x10000000

Definition at line 11116 of file stm32g431xx.h.

◆ USART_CR1_M1_Pos

#define USART_CR1_M1_Pos (28U)

Definition at line 11115 of file stm32g431xx.h.

◆ USART_CR1_M_Msk

#define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos)

0x10001000

Definition at line 11079 of file stm32g431xx.h.

◆ USART_CR1_M_Pos

#define USART_CR1_M_Pos (12U)

Definition at line 11078 of file stm32g431xx.h.

◆ USART_CR1_MME

#define USART_CR1_MME USART_CR1_MME_Msk

Mute Mode Enable

Definition at line 11086 of file stm32g431xx.h.

◆ USART_CR1_MME_Msk

#define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos)

0x00002000

Definition at line 11085 of file stm32g431xx.h.

◆ USART_CR1_MME_Pos

#define USART_CR1_MME_Pos (13U)

Definition at line 11084 of file stm32g431xx.h.

◆ USART_CR1_OVER8

#define USART_CR1_OVER8 USART_CR1_OVER8_Msk

Oversampling by 8-bit or 16-bit mode

Definition at line 11092 of file stm32g431xx.h.

◆ USART_CR1_OVER8_Msk

#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos)

0x00008000

Definition at line 11091 of file stm32g431xx.h.

◆ USART_CR1_OVER8_Pos

#define USART_CR1_OVER8_Pos (15U)

Definition at line 11090 of file stm32g431xx.h.

◆ USART_CR1_PCE

#define USART_CR1_PCE USART_CR1_PCE_Msk

Parity Control Enable

Definition at line 11074 of file stm32g431xx.h.

◆ USART_CR1_PCE_Msk

#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos)

0x00000400

Definition at line 11073 of file stm32g431xx.h.

◆ USART_CR1_PCE_Pos

#define USART_CR1_PCE_Pos (10U)

Definition at line 11072 of file stm32g431xx.h.

◆ USART_CR1_PEIE

#define USART_CR1_PEIE USART_CR1_PEIE_Msk

PE Interrupt Enable

Definition at line 11068 of file stm32g431xx.h.

◆ USART_CR1_PEIE_Msk

#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos)

0x00000100

Definition at line 11067 of file stm32g431xx.h.

◆ USART_CR1_PEIE_Pos

#define USART_CR1_PEIE_Pos (8U)

Definition at line 11066 of file stm32g431xx.h.

◆ USART_CR1_PS

#define USART_CR1_PS USART_CR1_PS_Msk

Parity Selection

Definition at line 11071 of file stm32g431xx.h.

◆ USART_CR1_PS_Msk

#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos)

0x00000200

Definition at line 11070 of file stm32g431xx.h.

◆ USART_CR1_PS_Pos

#define USART_CR1_PS_Pos (9U)

Definition at line 11069 of file stm32g431xx.h.

◆ USART_CR1_RE

#define USART_CR1_RE USART_CR1_RE_Msk

Receiver Enable

Definition at line 11044 of file stm32g431xx.h.

◆ USART_CR1_RE_Msk

#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos)

0x00000004

Definition at line 11043 of file stm32g431xx.h.

◆ USART_CR1_RE_Pos

#define USART_CR1_RE_Pos (2U)

Definition at line 11042 of file stm32g431xx.h.

◆ USART_CR1_RTOIE

#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk

Receive Time Out interrupt enable

Definition at line 11111 of file stm32g431xx.h.

◆ USART_CR1_RTOIE_Msk

#define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos)

0x04000000

Definition at line 11110 of file stm32g431xx.h.

◆ USART_CR1_RTOIE_Pos

#define USART_CR1_RTOIE_Pos (26U)

Definition at line 11109 of file stm32g431xx.h.

◆ USART_CR1_RXFFIE

#define USART_CR1_RXFFIE USART_CR1_RXFFIE_Msk

RXFIFO Full interrupt enable

Definition at line 11126 of file stm32g431xx.h.

◆ USART_CR1_RXFFIE_Msk

#define USART_CR1_RXFFIE_Msk (0x1UL << USART_CR1_RXFFIE_Pos)

0x80000000

Definition at line 11125 of file stm32g431xx.h.

◆ USART_CR1_RXFFIE_Pos

#define USART_CR1_RXFFIE_Pos (31U)

Definition at line 11124 of file stm32g431xx.h.

◆ USART_CR1_RXNEIE

#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk

RXNE Interrupt Enable

Definition at line 11053 of file stm32g431xx.h.

◆ USART_CR1_RXNEIE_Msk

#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos)

0x00000020

Definition at line 11052 of file stm32g431xx.h.

◆ USART_CR1_RXNEIE_Pos

#define USART_CR1_RXNEIE_Pos (5U)

Definition at line 11051 of file stm32g431xx.h.

◆ USART_CR1_RXNEIE_RXFNEIE

#define USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_Msk

RXNE and RX FIFO Not Empty Interrupt Enable

Definition at line 11056 of file stm32g431xx.h.

◆ USART_CR1_RXNEIE_RXFNEIE_Msk

#define USART_CR1_RXNEIE_RXFNEIE_Msk USART_CR1_RXNEIE_Msk

0x00000020

Definition at line 11055 of file stm32g431xx.h.

◆ USART_CR1_RXNEIE_RXFNEIE_Pos

#define USART_CR1_RXNEIE_RXFNEIE_Pos USART_CR1_RXNEIE_Pos

Definition at line 11054 of file stm32g431xx.h.

◆ USART_CR1_TCIE

#define USART_CR1_TCIE USART_CR1_TCIE_Msk

Transmission Complete Interrupt Enable

Definition at line 11059 of file stm32g431xx.h.

◆ USART_CR1_TCIE_Msk

#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos)

0x00000040

Definition at line 11058 of file stm32g431xx.h.

◆ USART_CR1_TCIE_Pos

#define USART_CR1_TCIE_Pos (6U)

Definition at line 11057 of file stm32g431xx.h.

◆ USART_CR1_TE

#define USART_CR1_TE USART_CR1_TE_Msk

Transmitter Enable

Definition at line 11047 of file stm32g431xx.h.

◆ USART_CR1_TE_Msk

#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos)

0x00000008

Definition at line 11046 of file stm32g431xx.h.

◆ USART_CR1_TE_Pos

#define USART_CR1_TE_Pos (3U)

Definition at line 11045 of file stm32g431xx.h.

◆ USART_CR1_TXEIE

#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk

TXE Interrupt Enable

Definition at line 11062 of file stm32g431xx.h.

◆ USART_CR1_TXEIE_Msk

#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos)

0x00000080

Definition at line 11061 of file stm32g431xx.h.

◆ USART_CR1_TXEIE_Pos

#define USART_CR1_TXEIE_Pos (7U)

Definition at line 11060 of file stm32g431xx.h.

◆ USART_CR1_TXEIE_TXFNFIE

#define USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_Msk

TXE and TX FIFO Not Full Interrupt Enable

Definition at line 11065 of file stm32g431xx.h.

◆ USART_CR1_TXEIE_TXFNFIE_Msk

#define USART_CR1_TXEIE_TXFNFIE_Msk USART_CR1_TXEIE_Msk

0x00000080

Definition at line 11064 of file stm32g431xx.h.

◆ USART_CR1_TXEIE_TXFNFIE_Pos

#define USART_CR1_TXEIE_TXFNFIE_Pos USART_CR1_TXEIE_Pos

Definition at line 11063 of file stm32g431xx.h.

◆ USART_CR1_TXFEIE

#define USART_CR1_TXFEIE USART_CR1_TXFEIE_Msk

TXFIFO empty interrupt enable

Definition at line 11123 of file stm32g431xx.h.

◆ USART_CR1_TXFEIE_Msk

#define USART_CR1_TXFEIE_Msk (0x1UL << USART_CR1_TXFEIE_Pos)

0x40000000

Definition at line 11122 of file stm32g431xx.h.

◆ USART_CR1_TXFEIE_Pos

#define USART_CR1_TXFEIE_Pos (30U)

Definition at line 11121 of file stm32g431xx.h.

◆ USART_CR1_UE

#define USART_CR1_UE USART_CR1_UE_Msk

USART Enable

Definition at line 11038 of file stm32g431xx.h.

◆ USART_CR1_UE_Msk

#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos)

0x00000001

Definition at line 11037 of file stm32g431xx.h.

◆ USART_CR1_UE_Pos

#define USART_CR1_UE_Pos (0U)

Definition at line 11036 of file stm32g431xx.h.

◆ USART_CR1_UESM

#define USART_CR1_UESM USART_CR1_UESM_Msk

USART Enable in STOP Mode

Definition at line 11041 of file stm32g431xx.h.

◆ USART_CR1_UESM_Msk

#define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos)

0x00000002

Definition at line 11040 of file stm32g431xx.h.

◆ USART_CR1_UESM_Pos

#define USART_CR1_UESM_Pos (1U)

Definition at line 11039 of file stm32g431xx.h.

◆ USART_CR1_WAKE

#define USART_CR1_WAKE USART_CR1_WAKE_Msk

Receiver Wakeup method

Definition at line 11077 of file stm32g431xx.h.

◆ USART_CR1_WAKE_Msk

#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos)

0x00000800

Definition at line 11076 of file stm32g431xx.h.

◆ USART_CR1_WAKE_Pos

#define USART_CR1_WAKE_Pos (11U)

Definition at line 11075 of file stm32g431xx.h.

◆ USART_CR2_ABREN

#define USART_CR2_ABREN USART_CR2_ABREN_Msk

Auto Baud-Rate Enable

Definition at line 11181 of file stm32g431xx.h.

◆ USART_CR2_ABREN_Msk

#define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos)

0x00100000

Definition at line 11180 of file stm32g431xx.h.

◆ USART_CR2_ABREN_Pos

#define USART_CR2_ABREN_Pos (20U)

Definition at line 11179 of file stm32g431xx.h.

◆ USART_CR2_ABRMODE

#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk

ABRMOD[1:0] bits (Auto Baud-Rate Mode)

Definition at line 11184 of file stm32g431xx.h.

◆ USART_CR2_ABRMODE_0

#define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos)

0x00200000

Definition at line 11185 of file stm32g431xx.h.

◆ USART_CR2_ABRMODE_1

#define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos)

0x00400000

Definition at line 11186 of file stm32g431xx.h.

◆ USART_CR2_ABRMODE_Msk

#define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos)

0x00600000

Definition at line 11183 of file stm32g431xx.h.

◆ USART_CR2_ABRMODE_Pos

#define USART_CR2_ABRMODE_Pos (21U)

Definition at line 11182 of file stm32g431xx.h.

◆ USART_CR2_ADD

#define USART_CR2_ADD USART_CR2_ADD_Msk

Address of the USART node

Definition at line 11192 of file stm32g431xx.h.

◆ USART_CR2_ADD_Msk

#define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos)

0xFF000000

Definition at line 11191 of file stm32g431xx.h.

◆ USART_CR2_ADD_Pos

#define USART_CR2_ADD_Pos (24U)

Definition at line 11190 of file stm32g431xx.h.

◆ USART_CR2_ADDM7

#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk

7-bit or 4-bit Address Detection

Definition at line 11137 of file stm32g431xx.h.

◆ USART_CR2_ADDM7_Msk

#define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos)

0x00000010

Definition at line 11136 of file stm32g431xx.h.

◆ USART_CR2_ADDM7_Pos

#define USART_CR2_ADDM7_Pos (4U)

Definition at line 11135 of file stm32g431xx.h.

◆ USART_CR2_CLKEN

#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk

Clock Enable

Definition at line 11155 of file stm32g431xx.h.

◆ USART_CR2_CLKEN_Msk

#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos)

0x00000800

Definition at line 11154 of file stm32g431xx.h.

◆ USART_CR2_CLKEN_Pos

#define USART_CR2_CLKEN_Pos (11U)

Definition at line 11153 of file stm32g431xx.h.

◆ USART_CR2_CPHA

#define USART_CR2_CPHA USART_CR2_CPHA_Msk

Clock Phase

Definition at line 11149 of file stm32g431xx.h.

◆ USART_CR2_CPHA_Msk

#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos)

0x00000200

Definition at line 11148 of file stm32g431xx.h.

◆ USART_CR2_CPHA_Pos

#define USART_CR2_CPHA_Pos (9U)

Definition at line 11147 of file stm32g431xx.h.

◆ USART_CR2_CPOL

#define USART_CR2_CPOL USART_CR2_CPOL_Msk

Clock Polarity

Definition at line 11152 of file stm32g431xx.h.

◆ USART_CR2_CPOL_Msk

#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos)

0x00000400

Definition at line 11151 of file stm32g431xx.h.

◆ USART_CR2_CPOL_Pos

#define USART_CR2_CPOL_Pos (10U)

Definition at line 11150 of file stm32g431xx.h.

◆ USART_CR2_DATAINV

#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk

Binary data inversion

Definition at line 11175 of file stm32g431xx.h.

◆ USART_CR2_DATAINV_Msk

#define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos)

0x00040000

Definition at line 11174 of file stm32g431xx.h.

◆ USART_CR2_DATAINV_Pos

#define USART_CR2_DATAINV_Pos (18U)

Definition at line 11173 of file stm32g431xx.h.

◆ USART_CR2_DIS_NSS

#define USART_CR2_DIS_NSS USART_CR2_DIS_NSS_Msk

Slave Select (NSS) pin management

Definition at line 11134 of file stm32g431xx.h.

◆ USART_CR2_DIS_NSS_Msk

#define USART_CR2_DIS_NSS_Msk (0x1UL << USART_CR2_DIS_NSS_Pos)

0x00000008

Definition at line 11133 of file stm32g431xx.h.

◆ USART_CR2_DIS_NSS_Pos

#define USART_CR2_DIS_NSS_Pos (3U)

Definition at line 11132 of file stm32g431xx.h.

◆ USART_CR2_LBCL

#define USART_CR2_LBCL USART_CR2_LBCL_Msk

Last Bit Clock pulse

Definition at line 11146 of file stm32g431xx.h.

◆ USART_CR2_LBCL_Msk

#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos)

0x00000100

Definition at line 11145 of file stm32g431xx.h.

◆ USART_CR2_LBCL_Pos

#define USART_CR2_LBCL_Pos (8U)

Definition at line 11144 of file stm32g431xx.h.

◆ USART_CR2_LBDIE

#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk

LIN Break Detection Interrupt Enable

Definition at line 11143 of file stm32g431xx.h.

◆ USART_CR2_LBDIE_Msk

#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos)

0x00000040

Definition at line 11142 of file stm32g431xx.h.

◆ USART_CR2_LBDIE_Pos

#define USART_CR2_LBDIE_Pos (6U)

Definition at line 11141 of file stm32g431xx.h.

◆ USART_CR2_LBDL

#define USART_CR2_LBDL USART_CR2_LBDL_Msk

LIN Break Detection Length

Definition at line 11140 of file stm32g431xx.h.

◆ USART_CR2_LBDL_Msk

#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos)

0x00000020

Definition at line 11139 of file stm32g431xx.h.

◆ USART_CR2_LBDL_Pos

#define USART_CR2_LBDL_Pos (5U)

Definition at line 11138 of file stm32g431xx.h.

◆ USART_CR2_LINEN

#define USART_CR2_LINEN USART_CR2_LINEN_Msk

LIN mode enable

Definition at line 11163 of file stm32g431xx.h.

◆ USART_CR2_LINEN_Msk

#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos)

0x00004000

Definition at line 11162 of file stm32g431xx.h.

◆ USART_CR2_LINEN_Pos

#define USART_CR2_LINEN_Pos (14U)

Definition at line 11161 of file stm32g431xx.h.

◆ USART_CR2_MSBFIRST

#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk

Most Significant Bit First

Definition at line 11178 of file stm32g431xx.h.

◆ USART_CR2_MSBFIRST_Msk

#define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos)

0x00080000

Definition at line 11177 of file stm32g431xx.h.

◆ USART_CR2_MSBFIRST_Pos

#define USART_CR2_MSBFIRST_Pos (19U)

Definition at line 11176 of file stm32g431xx.h.

◆ USART_CR2_RTOEN

#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk

Receiver Time-Out enable

Definition at line 11189 of file stm32g431xx.h.

◆ USART_CR2_RTOEN_Msk

#define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos)

0x00800000

Definition at line 11188 of file stm32g431xx.h.

◆ USART_CR2_RTOEN_Pos

#define USART_CR2_RTOEN_Pos (23U)

Definition at line 11187 of file stm32g431xx.h.

◆ USART_CR2_RXINV

#define USART_CR2_RXINV USART_CR2_RXINV_Msk

RX pin active level inversion

Definition at line 11169 of file stm32g431xx.h.

◆ USART_CR2_RXINV_Msk

#define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos)

0x00010000

Definition at line 11168 of file stm32g431xx.h.

◆ USART_CR2_RXINV_Pos

#define USART_CR2_RXINV_Pos (16U)

Definition at line 11167 of file stm32g431xx.h.

◆ USART_CR2_SLVEN

#define USART_CR2_SLVEN USART_CR2_SLVEN_Msk

Synchronous Slave mode enable

Definition at line 11131 of file stm32g431xx.h.

◆ USART_CR2_SLVEN_Msk

#define USART_CR2_SLVEN_Msk (0x1UL << USART_CR2_SLVEN_Pos)

0x00000001

Definition at line 11130 of file stm32g431xx.h.

◆ USART_CR2_SLVEN_Pos

#define USART_CR2_SLVEN_Pos (0U)

Definition at line 11129 of file stm32g431xx.h.

◆ USART_CR2_STOP

#define USART_CR2_STOP USART_CR2_STOP_Msk

STOP[1:0] bits (STOP bits)

Definition at line 11158 of file stm32g431xx.h.

◆ USART_CR2_STOP_0

#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos)

0x00001000

Definition at line 11159 of file stm32g431xx.h.

◆ USART_CR2_STOP_1

#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos)

0x00002000

Definition at line 11160 of file stm32g431xx.h.

◆ USART_CR2_STOP_Msk

#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos)

0x00003000

Definition at line 11157 of file stm32g431xx.h.

◆ USART_CR2_STOP_Pos

#define USART_CR2_STOP_Pos (12U)

Definition at line 11156 of file stm32g431xx.h.

◆ USART_CR2_SWAP

#define USART_CR2_SWAP USART_CR2_SWAP_Msk

SWAP TX/RX pins

Definition at line 11166 of file stm32g431xx.h.

◆ USART_CR2_SWAP_Msk

#define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos)

0x00008000

Definition at line 11165 of file stm32g431xx.h.

◆ USART_CR2_SWAP_Pos

#define USART_CR2_SWAP_Pos (15U)

Definition at line 11164 of file stm32g431xx.h.

◆ USART_CR2_TXINV

#define USART_CR2_TXINV USART_CR2_TXINV_Msk

TX pin active level inversion

Definition at line 11172 of file stm32g431xx.h.

◆ USART_CR2_TXINV_Msk

#define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos)

0x00020000

Definition at line 11171 of file stm32g431xx.h.

◆ USART_CR2_TXINV_Pos

#define USART_CR2_TXINV_Pos (17U)

Definition at line 11170 of file stm32g431xx.h.

◆ USART_CR3_CTSE

#define USART_CR3_CTSE USART_CR3_CTSE_Msk

CTS Enable

Definition at line 11224 of file stm32g431xx.h.

◆ USART_CR3_CTSE_Msk

#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos)

0x00000200

Definition at line 11223 of file stm32g431xx.h.

◆ USART_CR3_CTSE_Pos

#define USART_CR3_CTSE_Pos (9U)

Definition at line 11222 of file stm32g431xx.h.

◆ USART_CR3_CTSIE

#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk

CTS Interrupt Enable

Definition at line 11227 of file stm32g431xx.h.

◆ USART_CR3_CTSIE_Msk

#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos)

0x00000400

Definition at line 11226 of file stm32g431xx.h.

◆ USART_CR3_CTSIE_Pos

#define USART_CR3_CTSIE_Pos (10U)

Definition at line 11225 of file stm32g431xx.h.

◆ USART_CR3_DDRE

#define USART_CR3_DDRE USART_CR3_DDRE_Msk

DMA Disable on Reception Error

Definition at line 11236 of file stm32g431xx.h.

◆ USART_CR3_DDRE_Msk

#define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos)

0x00002000

Definition at line 11235 of file stm32g431xx.h.

◆ USART_CR3_DDRE_Pos

#define USART_CR3_DDRE_Pos (13U)

Definition at line 11234 of file stm32g431xx.h.

◆ USART_CR3_DEM

#define USART_CR3_DEM USART_CR3_DEM_Msk

Driver Enable Mode

Definition at line 11239 of file stm32g431xx.h.

◆ USART_CR3_DEM_Msk

#define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos)

0x00004000

Definition at line 11238 of file stm32g431xx.h.

◆ USART_CR3_DEM_Pos

#define USART_CR3_DEM_Pos (14U)

Definition at line 11237 of file stm32g431xx.h.

◆ USART_CR3_DEP

#define USART_CR3_DEP USART_CR3_DEP_Msk

Driver Enable Polarity Selection

Definition at line 11242 of file stm32g431xx.h.

◆ USART_CR3_DEP_Msk

#define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos)

0x00008000

Definition at line 11241 of file stm32g431xx.h.

◆ USART_CR3_DEP_Pos

#define USART_CR3_DEP_Pos (15U)

Definition at line 11240 of file stm32g431xx.h.

◆ USART_CR3_DMAR

#define USART_CR3_DMAR USART_CR3_DMAR_Msk

DMA Enable Receiver

Definition at line 11215 of file stm32g431xx.h.

◆ USART_CR3_DMAR_Msk

#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos)

0x00000040

Definition at line 11214 of file stm32g431xx.h.

◆ USART_CR3_DMAR_Pos

#define USART_CR3_DMAR_Pos (6U)

Definition at line 11213 of file stm32g431xx.h.

◆ USART_CR3_DMAT

#define USART_CR3_DMAT USART_CR3_DMAT_Msk

DMA Enable Transmitter

Definition at line 11218 of file stm32g431xx.h.

◆ USART_CR3_DMAT_Msk

#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos)

0x00000080

Definition at line 11217 of file stm32g431xx.h.

◆ USART_CR3_DMAT_Pos

#define USART_CR3_DMAT_Pos (7U)

Definition at line 11216 of file stm32g431xx.h.

◆ USART_CR3_EIE

#define USART_CR3_EIE USART_CR3_EIE_Msk

Error Interrupt Enable

Definition at line 11197 of file stm32g431xx.h.

◆ USART_CR3_EIE_Msk

#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos)

0x00000001

Definition at line 11196 of file stm32g431xx.h.

◆ USART_CR3_EIE_Pos

#define USART_CR3_EIE_Pos (0U)

Definition at line 11195 of file stm32g431xx.h.

◆ USART_CR3_HDSEL

#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk

Half-Duplex Selection

Definition at line 11206 of file stm32g431xx.h.

◆ USART_CR3_HDSEL_Msk

#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos)

0x00000008

Definition at line 11205 of file stm32g431xx.h.

◆ USART_CR3_HDSEL_Pos

#define USART_CR3_HDSEL_Pos (3U)

Definition at line 11204 of file stm32g431xx.h.

◆ USART_CR3_IREN

#define USART_CR3_IREN USART_CR3_IREN_Msk

IrDA mode Enable

Definition at line 11200 of file stm32g431xx.h.

◆ USART_CR3_IREN_Msk

#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos)

0x00000002

Definition at line 11199 of file stm32g431xx.h.

◆ USART_CR3_IREN_Pos

#define USART_CR3_IREN_Pos (1U)

Definition at line 11198 of file stm32g431xx.h.

◆ USART_CR3_IRLP

#define USART_CR3_IRLP USART_CR3_IRLP_Msk

IrDA Low-Power

Definition at line 11203 of file stm32g431xx.h.

◆ USART_CR3_IRLP_Msk

#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos)

0x00000004

Definition at line 11202 of file stm32g431xx.h.

◆ USART_CR3_IRLP_Pos

#define USART_CR3_IRLP_Pos (2U)

Definition at line 11201 of file stm32g431xx.h.

◆ USART_CR3_NACK

#define USART_CR3_NACK USART_CR3_NACK_Msk

SmartCard NACK enable

Definition at line 11209 of file stm32g431xx.h.

◆ USART_CR3_NACK_Msk

#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos)

0x00000010

Definition at line 11208 of file stm32g431xx.h.

◆ USART_CR3_NACK_Pos

#define USART_CR3_NACK_Pos (4U)

Definition at line 11207 of file stm32g431xx.h.

◆ USART_CR3_ONEBIT

#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk

One sample bit method enable

Definition at line 11230 of file stm32g431xx.h.

◆ USART_CR3_ONEBIT_Msk

#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos)

0x00000800

Definition at line 11229 of file stm32g431xx.h.

◆ USART_CR3_ONEBIT_Pos

#define USART_CR3_ONEBIT_Pos (11U)

Definition at line 11228 of file stm32g431xx.h.

◆ USART_CR3_OVRDIS

#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk

Overrun Disable

Definition at line 11233 of file stm32g431xx.h.

◆ USART_CR3_OVRDIS_Msk

#define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos)

0x00001000

Definition at line 11232 of file stm32g431xx.h.

◆ USART_CR3_OVRDIS_Pos

#define USART_CR3_OVRDIS_Pos (12U)

Definition at line 11231 of file stm32g431xx.h.

◆ USART_CR3_RTSE

#define USART_CR3_RTSE USART_CR3_RTSE_Msk

RTS Enable

Definition at line 11221 of file stm32g431xx.h.

◆ USART_CR3_RTSE_Msk

#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos)

0x00000100

Definition at line 11220 of file stm32g431xx.h.

◆ USART_CR3_RTSE_Pos

#define USART_CR3_RTSE_Pos (8U)

Definition at line 11219 of file stm32g431xx.h.

◆ USART_CR3_RXFTCFG

#define USART_CR3_RXFTCFG USART_CR3_RXFTCFG_Msk

RXFIFO FIFO threshold configuration

Definition at line 11265 of file stm32g431xx.h.

◆ USART_CR3_RXFTCFG_0

#define USART_CR3_RXFTCFG_0 (0x1UL << USART_CR3_RXFTCFG_Pos)

0x02000000

Definition at line 11266 of file stm32g431xx.h.

◆ USART_CR3_RXFTCFG_1

#define USART_CR3_RXFTCFG_1 (0x2UL << USART_CR3_RXFTCFG_Pos)

0x04000000

Definition at line 11267 of file stm32g431xx.h.

◆ USART_CR3_RXFTCFG_2

#define USART_CR3_RXFTCFG_2 (0x4UL << USART_CR3_RXFTCFG_Pos)

0x08000000

Definition at line 11268 of file stm32g431xx.h.

◆ USART_CR3_RXFTCFG_Msk

#define USART_CR3_RXFTCFG_Msk (0x7UL << USART_CR3_RXFTCFG_Pos)

0x0E000000

Definition at line 11264 of file stm32g431xx.h.

◆ USART_CR3_RXFTCFG_Pos

#define USART_CR3_RXFTCFG_Pos (25U)

Definition at line 11263 of file stm32g431xx.h.

◆ USART_CR3_RXFTIE

#define USART_CR3_RXFTIE USART_CR3_RXFTIE_Msk

RXFIFO threshold interrupt enable

Definition at line 11271 of file stm32g431xx.h.

◆ USART_CR3_RXFTIE_Msk

#define USART_CR3_RXFTIE_Msk (0x1UL << USART_CR3_RXFTIE_Pos)

0x10000000

Definition at line 11270 of file stm32g431xx.h.

◆ USART_CR3_RXFTIE_Pos

#define USART_CR3_RXFTIE_Pos (28U)

Definition at line 11269 of file stm32g431xx.h.

◆ USART_CR3_SCARCNT

#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk

SCARCNT[2:0] bits (SmartCard Auto-Retry Count)

Definition at line 11245 of file stm32g431xx.h.

◆ USART_CR3_SCARCNT_0

#define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos)

0x00020000

Definition at line 11246 of file stm32g431xx.h.

◆ USART_CR3_SCARCNT_1

#define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos)

0x00040000

Definition at line 11247 of file stm32g431xx.h.

◆ USART_CR3_SCARCNT_2

#define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos)

0x00080000

Definition at line 11248 of file stm32g431xx.h.

◆ USART_CR3_SCARCNT_Msk

#define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos)

0x000E0000

Definition at line 11244 of file stm32g431xx.h.

◆ USART_CR3_SCARCNT_Pos

#define USART_CR3_SCARCNT_Pos (17U)

Definition at line 11243 of file stm32g431xx.h.

◆ USART_CR3_SCEN

#define USART_CR3_SCEN USART_CR3_SCEN_Msk

SmartCard mode enable

Definition at line 11212 of file stm32g431xx.h.

◆ USART_CR3_SCEN_Msk

#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos)

0x00000020

Definition at line 11211 of file stm32g431xx.h.

◆ USART_CR3_SCEN_Pos

#define USART_CR3_SCEN_Pos (5U)

Definition at line 11210 of file stm32g431xx.h.

◆ USART_CR3_TCBGTIE

#define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk

Transmission Complete Before Guard Time Interrupt Enable

Definition at line 11262 of file stm32g431xx.h.

◆ USART_CR3_TCBGTIE_Msk

#define USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos)

0x01000000

Definition at line 11261 of file stm32g431xx.h.

◆ USART_CR3_TCBGTIE_Pos

#define USART_CR3_TCBGTIE_Pos (24U)

Definition at line 11260 of file stm32g431xx.h.

◆ USART_CR3_TXFTCFG

#define USART_CR3_TXFTCFG USART_CR3_TXFTCFG_Msk

TXFIFO threshold configuration

Definition at line 11274 of file stm32g431xx.h.

◆ USART_CR3_TXFTCFG_0

#define USART_CR3_TXFTCFG_0 (0x1UL << USART_CR3_TXFTCFG_Pos)

0x20000000

Definition at line 11275 of file stm32g431xx.h.

◆ USART_CR3_TXFTCFG_1

#define USART_CR3_TXFTCFG_1 (0x2UL << USART_CR3_TXFTCFG_Pos)

0x40000000

Definition at line 11276 of file stm32g431xx.h.

◆ USART_CR3_TXFTCFG_2

#define USART_CR3_TXFTCFG_2 (0x4UL << USART_CR3_TXFTCFG_Pos)

0x80000000

Definition at line 11277 of file stm32g431xx.h.

◆ USART_CR3_TXFTCFG_Msk

#define USART_CR3_TXFTCFG_Msk (0x7UL << USART_CR3_TXFTCFG_Pos)

0xE0000000

Definition at line 11273 of file stm32g431xx.h.

◆ USART_CR3_TXFTCFG_Pos

#define USART_CR3_TXFTCFG_Pos (29U)

Definition at line 11272 of file stm32g431xx.h.

◆ USART_CR3_TXFTIE

#define USART_CR3_TXFTIE USART_CR3_TXFTIE_Msk

TXFIFO threshold interrupt enable

Definition at line 11259 of file stm32g431xx.h.

◆ USART_CR3_TXFTIE_Msk

#define USART_CR3_TXFTIE_Msk (0x1UL << USART_CR3_TXFTIE_Pos)

0x00800000

Definition at line 11258 of file stm32g431xx.h.

◆ USART_CR3_TXFTIE_Pos

#define USART_CR3_TXFTIE_Pos (23U)

Definition at line 11257 of file stm32g431xx.h.

◆ USART_CR3_WUFIE

#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk

Wake Up Interrupt Enable

Definition at line 11256 of file stm32g431xx.h.

◆ USART_CR3_WUFIE_Msk

#define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos)

0x00400000

Definition at line 11255 of file stm32g431xx.h.

◆ USART_CR3_WUFIE_Pos

#define USART_CR3_WUFIE_Pos (22U)

Definition at line 11254 of file stm32g431xx.h.

◆ USART_CR3_WUS

#define USART_CR3_WUS USART_CR3_WUS_Msk

WUS[1:0] bits (Wake UP Interrupt Flag Selection)

Definition at line 11251 of file stm32g431xx.h.

◆ USART_CR3_WUS_0

#define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos)

0x00100000

Definition at line 11252 of file stm32g431xx.h.

◆ USART_CR3_WUS_1

#define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos)

0x00200000

Definition at line 11253 of file stm32g431xx.h.

◆ USART_CR3_WUS_Msk

#define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos)

0x00300000

Definition at line 11250 of file stm32g431xx.h.

◆ USART_CR3_WUS_Pos

#define USART_CR3_WUS_Pos (20U)

Definition at line 11249 of file stm32g431xx.h.

◆ USART_GTPR_GT

#define USART_GTPR_GT USART_GTPR_GT_Msk

GT[7:0] bits (Guard time value)

Definition at line 11293 of file stm32g431xx.h.

◆ USART_GTPR_GT_Msk

#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos)

0x0000FF00

Definition at line 11292 of file stm32g431xx.h.

◆ USART_GTPR_GT_Pos

#define USART_GTPR_GT_Pos (8U)

Definition at line 11291 of file stm32g431xx.h.

◆ USART_GTPR_PSC

#define USART_GTPR_PSC USART_GTPR_PSC_Msk

PSC[7:0] bits (Prescaler value)

Definition at line 11290 of file stm32g431xx.h.

◆ USART_GTPR_PSC_Msk

#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos)

0x000000FF

Definition at line 11289 of file stm32g431xx.h.

◆ USART_GTPR_PSC_Pos

#define USART_GTPR_PSC_Pos (0U)

Definition at line 11288 of file stm32g431xx.h.

◆ USART_ICR_CMCF

#define USART_ICR_CMCF USART_ICR_CMCF_Msk

Character Match Clear Flag

Definition at line 11454 of file stm32g431xx.h.

◆ USART_ICR_CMCF_Msk

#define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos)

0x00020000

Definition at line 11453 of file stm32g431xx.h.

◆ USART_ICR_CMCF_Pos

#define USART_ICR_CMCF_Pos (17U)

Definition at line 11452 of file stm32g431xx.h.

◆ USART_ICR_CTSCF

#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk

CTS Interrupt Clear Flag

Definition at line 11442 of file stm32g431xx.h.

◆ USART_ICR_CTSCF_Msk

#define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos)

0x00000200

Definition at line 11441 of file stm32g431xx.h.

◆ USART_ICR_CTSCF_Pos

#define USART_ICR_CTSCF_Pos (9U)

Definition at line 11440 of file stm32g431xx.h.

◆ USART_ICR_EOBCF

#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk

End Of Block Clear Flag

Definition at line 11448 of file stm32g431xx.h.

◆ USART_ICR_EOBCF_Msk

#define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos)

0x00001000

Definition at line 11447 of file stm32g431xx.h.

◆ USART_ICR_EOBCF_Pos

#define USART_ICR_EOBCF_Pos (12U)

Definition at line 11446 of file stm32g431xx.h.

◆ USART_ICR_FECF

#define USART_ICR_FECF USART_ICR_FECF_Msk

Framing Error Clear Flag

Definition at line 11418 of file stm32g431xx.h.

◆ USART_ICR_FECF_Msk

#define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos)

0x00000002

Definition at line 11417 of file stm32g431xx.h.

◆ USART_ICR_FECF_Pos

#define USART_ICR_FECF_Pos (1U)

Definition at line 11416 of file stm32g431xx.h.

◆ USART_ICR_IDLECF

#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk

IDLE line detected Clear Flag

Definition at line 11427 of file stm32g431xx.h.

◆ USART_ICR_IDLECF_Msk

#define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos)

0x00000010

Definition at line 11426 of file stm32g431xx.h.

◆ USART_ICR_IDLECF_Pos

#define USART_ICR_IDLECF_Pos (4U)

Definition at line 11425 of file stm32g431xx.h.

◆ USART_ICR_LBDCF

#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk

LIN Break Detection Clear Flag

Definition at line 11439 of file stm32g431xx.h.

◆ USART_ICR_LBDCF_Msk

#define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos)

0x00000100

Definition at line 11438 of file stm32g431xx.h.

◆ USART_ICR_LBDCF_Pos

#define USART_ICR_LBDCF_Pos (8U)

Definition at line 11437 of file stm32g431xx.h.

◆ USART_ICR_NECF

#define USART_ICR_NECF USART_ICR_NECF_Msk

Noise detected Clear Flag

Definition at line 11421 of file stm32g431xx.h.

◆ USART_ICR_NECF_Msk

#define USART_ICR_NECF_Msk (0x1UL << USART_ICR_NECF_Pos)

0x00000004

Definition at line 11420 of file stm32g431xx.h.

◆ USART_ICR_NECF_Pos

#define USART_ICR_NECF_Pos (2U)

Definition at line 11419 of file stm32g431xx.h.

◆ USART_ICR_ORECF

#define USART_ICR_ORECF USART_ICR_ORECF_Msk

OverRun Error Clear Flag

Definition at line 11424 of file stm32g431xx.h.

◆ USART_ICR_ORECF_Msk

#define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos)

0x00000008

Definition at line 11423 of file stm32g431xx.h.

◆ USART_ICR_ORECF_Pos

#define USART_ICR_ORECF_Pos (3U)

Definition at line 11422 of file stm32g431xx.h.

◆ USART_ICR_PECF

#define USART_ICR_PECF USART_ICR_PECF_Msk

Parity Error Clear Flag

Definition at line 11415 of file stm32g431xx.h.

◆ USART_ICR_PECF_Msk

#define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos)

0x00000001

Definition at line 11414 of file stm32g431xx.h.

◆ USART_ICR_PECF_Pos

#define USART_ICR_PECF_Pos (0U)

Definition at line 11413 of file stm32g431xx.h.

◆ USART_ICR_RTOCF

#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk

Receiver Time Out Clear Flag

Definition at line 11445 of file stm32g431xx.h.

◆ USART_ICR_RTOCF_Msk

#define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos)

0x00000800

Definition at line 11444 of file stm32g431xx.h.

◆ USART_ICR_RTOCF_Pos

#define USART_ICR_RTOCF_Pos (11U)

Definition at line 11443 of file stm32g431xx.h.

◆ USART_ICR_TCBGTCF

#define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk

Transmission Complete Before Guard Time Clear Flag

Definition at line 11436 of file stm32g431xx.h.

◆ USART_ICR_TCBGTCF_Msk

#define USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos)

0x00000080

Definition at line 11435 of file stm32g431xx.h.

◆ USART_ICR_TCBGTCF_Pos

#define USART_ICR_TCBGTCF_Pos (7U)

Definition at line 11434 of file stm32g431xx.h.

◆ USART_ICR_TCCF

#define USART_ICR_TCCF USART_ICR_TCCF_Msk

Transmission Complete Clear Flag

Definition at line 11433 of file stm32g431xx.h.

◆ USART_ICR_TCCF_Msk

#define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos)

0x00000040

Definition at line 11432 of file stm32g431xx.h.

◆ USART_ICR_TCCF_Pos

#define USART_ICR_TCCF_Pos (6U)

Definition at line 11431 of file stm32g431xx.h.

◆ USART_ICR_TXFECF

#define USART_ICR_TXFECF USART_ICR_TXFECF_Msk

TXFIFO empty Clear flag

Definition at line 11430 of file stm32g431xx.h.

◆ USART_ICR_TXFECF_Msk

#define USART_ICR_TXFECF_Msk (0x1UL << USART_ICR_TXFECF_Pos)

0x00000020

Definition at line 11429 of file stm32g431xx.h.

◆ USART_ICR_TXFECF_Pos

#define USART_ICR_TXFECF_Pos (5U)

Definition at line 11428 of file stm32g431xx.h.

◆ USART_ICR_UDRCF

#define USART_ICR_UDRCF USART_ICR_UDRCF_Msk

SPI Slave Underrun Clear Flag

Definition at line 11451 of file stm32g431xx.h.

◆ USART_ICR_UDRCF_Msk

#define USART_ICR_UDRCF_Msk (0x1UL << USART_ICR_UDRCF_Pos)

0x00002000

Definition at line 11450 of file stm32g431xx.h.

◆ USART_ICR_UDRCF_Pos

#define USART_ICR_UDRCF_Pos (13U)

Definition at line 11449 of file stm32g431xx.h.

◆ USART_ICR_WUCF

#define USART_ICR_WUCF USART_ICR_WUCF_Msk

Wake Up from stop mode Clear Flag

Definition at line 11457 of file stm32g431xx.h.

◆ USART_ICR_WUCF_Msk

#define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos)

0x00100000

Definition at line 11456 of file stm32g431xx.h.

◆ USART_ICR_WUCF_Pos

#define USART_ICR_WUCF_Pos (20U)

Definition at line 11455 of file stm32g431xx.h.

◆ USART_ISR_ABRE

#define USART_ISR_ABRE USART_ISR_ABRE_Msk

Auto-Baud Rate Error

Definition at line 11371 of file stm32g431xx.h.

◆ USART_ISR_ABRE_Msk

#define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos)

0x00004000

Definition at line 11370 of file stm32g431xx.h.

◆ USART_ISR_ABRE_Pos

#define USART_ISR_ABRE_Pos (14U)

Definition at line 11369 of file stm32g431xx.h.

◆ USART_ISR_ABRF

#define USART_ISR_ABRF USART_ISR_ABRF_Msk

Auto-Baud Rate Flag

Definition at line 11374 of file stm32g431xx.h.

◆ USART_ISR_ABRF_Msk

#define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos)

0x00008000

Definition at line 11373 of file stm32g431xx.h.

◆ USART_ISR_ABRF_Pos

#define USART_ISR_ABRF_Pos (15U)

Definition at line 11372 of file stm32g431xx.h.

◆ USART_ISR_BUSY

#define USART_ISR_BUSY USART_ISR_BUSY_Msk

Busy Flag

Definition at line 11377 of file stm32g431xx.h.

◆ USART_ISR_BUSY_Msk

#define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos)

0x00010000

Definition at line 11376 of file stm32g431xx.h.

◆ USART_ISR_BUSY_Pos

#define USART_ISR_BUSY_Pos (16U)

Definition at line 11375 of file stm32g431xx.h.

◆ USART_ISR_CMF

#define USART_ISR_CMF USART_ISR_CMF_Msk

Character Match Flag

Definition at line 11380 of file stm32g431xx.h.

◆ USART_ISR_CMF_Msk

#define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos)

0x00020000

Definition at line 11379 of file stm32g431xx.h.

◆ USART_ISR_CMF_Pos

#define USART_ISR_CMF_Pos (17U)

Definition at line 11378 of file stm32g431xx.h.

◆ USART_ISR_CTS

#define USART_ISR_CTS USART_ISR_CTS_Msk

CTS flag

Definition at line 11359 of file stm32g431xx.h.

◆ USART_ISR_CTS_Msk

#define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos)

0x00000400

Definition at line 11358 of file stm32g431xx.h.

◆ USART_ISR_CTS_Pos

#define USART_ISR_CTS_Pos (10U)

Definition at line 11357 of file stm32g431xx.h.

◆ USART_ISR_CTSIF

#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk

CTS interrupt flag

Definition at line 11356 of file stm32g431xx.h.

◆ USART_ISR_CTSIF_Msk

#define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos)

0x00000200

Definition at line 11355 of file stm32g431xx.h.

◆ USART_ISR_CTSIF_Pos

#define USART_ISR_CTSIF_Pos (9U)

Definition at line 11354 of file stm32g431xx.h.

◆ USART_ISR_EOBF

#define USART_ISR_EOBF USART_ISR_EOBF_Msk

End Of Block Flag

Definition at line 11365 of file stm32g431xx.h.

◆ USART_ISR_EOBF_Msk

#define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos)

0x00001000

Definition at line 11364 of file stm32g431xx.h.

◆ USART_ISR_EOBF_Pos

#define USART_ISR_EOBF_Pos (12U)

Definition at line 11363 of file stm32g431xx.h.

◆ USART_ISR_FE

#define USART_ISR_FE USART_ISR_FE_Msk

Framing Error

Definition at line 11326 of file stm32g431xx.h.

◆ USART_ISR_FE_Msk

#define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos)

0x00000002

Definition at line 11325 of file stm32g431xx.h.

◆ USART_ISR_FE_Pos

#define USART_ISR_FE_Pos (1U)

Definition at line 11324 of file stm32g431xx.h.

◆ USART_ISR_IDLE

#define USART_ISR_IDLE USART_ISR_IDLE_Msk

IDLE line detected

Definition at line 11335 of file stm32g431xx.h.

◆ USART_ISR_IDLE_Msk

#define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos)

0x00000010

Definition at line 11334 of file stm32g431xx.h.

◆ USART_ISR_IDLE_Pos

#define USART_ISR_IDLE_Pos (4U)

Definition at line 11333 of file stm32g431xx.h.

◆ USART_ISR_LBDF

#define USART_ISR_LBDF USART_ISR_LBDF_Msk

LIN Break Detection Flag

Definition at line 11353 of file stm32g431xx.h.

◆ USART_ISR_LBDF_Msk

#define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos)

0x00000100

Definition at line 11352 of file stm32g431xx.h.

◆ USART_ISR_LBDF_Pos

#define USART_ISR_LBDF_Pos (8U)

Definition at line 11351 of file stm32g431xx.h.

◆ USART_ISR_NE

#define USART_ISR_NE USART_ISR_NE_Msk

Noise detected Flag

Definition at line 11329 of file stm32g431xx.h.

◆ USART_ISR_NE_Msk

#define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos)

0x00000004

Definition at line 11328 of file stm32g431xx.h.

◆ USART_ISR_NE_Pos

#define USART_ISR_NE_Pos (2U)

Definition at line 11327 of file stm32g431xx.h.

◆ USART_ISR_ORE

#define USART_ISR_ORE USART_ISR_ORE_Msk

OverRun Error

Definition at line 11332 of file stm32g431xx.h.

◆ USART_ISR_ORE_Msk

#define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos)

0x00000008

Definition at line 11331 of file stm32g431xx.h.

◆ USART_ISR_ORE_Pos

#define USART_ISR_ORE_Pos (3U)

Definition at line 11330 of file stm32g431xx.h.

◆ USART_ISR_PE

#define USART_ISR_PE USART_ISR_PE_Msk

Parity Error

Definition at line 11323 of file stm32g431xx.h.

◆ USART_ISR_PE_Msk

#define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos)

0x00000001

Definition at line 11322 of file stm32g431xx.h.

◆ USART_ISR_PE_Pos

#define USART_ISR_PE_Pos (0U)

Definition at line 11321 of file stm32g431xx.h.

◆ USART_ISR_REACK

#define USART_ISR_REACK USART_ISR_REACK_Msk

Receive Enable Acknowledge Flag

Definition at line 11395 of file stm32g431xx.h.

◆ USART_ISR_REACK_Msk

#define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos)

0x00400000

Definition at line 11394 of file stm32g431xx.h.

◆ USART_ISR_REACK_Pos

#define USART_ISR_REACK_Pos (22U)

Definition at line 11393 of file stm32g431xx.h.

◆ USART_ISR_RTOF

#define USART_ISR_RTOF USART_ISR_RTOF_Msk

Receiver Time Out

Definition at line 11362 of file stm32g431xx.h.

◆ USART_ISR_RTOF_Msk

#define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos)

0x00000800

Definition at line 11361 of file stm32g431xx.h.

◆ USART_ISR_RTOF_Pos

#define USART_ISR_RTOF_Pos (11U)

Definition at line 11360 of file stm32g431xx.h.

◆ USART_ISR_RWU

#define USART_ISR_RWU USART_ISR_RWU_Msk

Receive Wake Up from mute mode Flag

Definition at line 11386 of file stm32g431xx.h.

◆ USART_ISR_RWU_Msk

#define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos)

0x00080000

Definition at line 11385 of file stm32g431xx.h.

◆ USART_ISR_RWU_Pos

#define USART_ISR_RWU_Pos (19U)

Definition at line 11384 of file stm32g431xx.h.

◆ USART_ISR_RXFF

#define USART_ISR_RXFF USART_ISR_RXFF_Msk

RXFIFO Full

Definition at line 11401 of file stm32g431xx.h.

◆ USART_ISR_RXFF_Msk

#define USART_ISR_RXFF_Msk (0x1UL << USART_ISR_RXFF_Pos)

0x01000000

Definition at line 11400 of file stm32g431xx.h.

◆ USART_ISR_RXFF_Pos

#define USART_ISR_RXFF_Pos (24U)

Definition at line 11399 of file stm32g431xx.h.

◆ USART_ISR_RXFT

#define USART_ISR_RXFT USART_ISR_RXFT_Msk

RXFIFO threshold flag

Definition at line 11407 of file stm32g431xx.h.

◆ USART_ISR_RXFT_Msk

#define USART_ISR_RXFT_Msk (0x1UL << USART_ISR_RXFT_Pos)

0x04000000

Definition at line 11406 of file stm32g431xx.h.

◆ USART_ISR_RXFT_Pos

#define USART_ISR_RXFT_Pos (26U)

Definition at line 11405 of file stm32g431xx.h.

◆ USART_ISR_RXNE

#define USART_ISR_RXNE USART_ISR_RXNE_Msk

Read Data Register Not Empty

Definition at line 11338 of file stm32g431xx.h.

◆ USART_ISR_RXNE_Msk

#define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos)

0x00000020

Definition at line 11337 of file stm32g431xx.h.

◆ USART_ISR_RXNE_Pos

#define USART_ISR_RXNE_Pos (5U)

Definition at line 11336 of file stm32g431xx.h.

◆ USART_ISR_RXNE_RXFNE

#define USART_ISR_RXNE_RXFNE USART_ISR_RXNE_Msk

Read Data Register or RX FIFO Not Empty

Definition at line 11341 of file stm32g431xx.h.

◆ USART_ISR_RXNE_RXFNE_Msk

#define USART_ISR_RXNE_RXFNE_Msk USART_ISR_RXNE_Msk

0x00000020

Definition at line 11340 of file stm32g431xx.h.

◆ USART_ISR_RXNE_RXFNE_Pos

#define USART_ISR_RXNE_RXFNE_Pos USART_ISR_RXNE_Pos

Definition at line 11339 of file stm32g431xx.h.

◆ USART_ISR_SBKF

#define USART_ISR_SBKF USART_ISR_SBKF_Msk

Send Break Flag

Definition at line 11383 of file stm32g431xx.h.

◆ USART_ISR_SBKF_Msk

#define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos)

0x00040000

Definition at line 11382 of file stm32g431xx.h.

◆ USART_ISR_SBKF_Pos

#define USART_ISR_SBKF_Pos (18U)

Definition at line 11381 of file stm32g431xx.h.

◆ USART_ISR_TC

#define USART_ISR_TC USART_ISR_TC_Msk

Transmission Complete

Definition at line 11344 of file stm32g431xx.h.

◆ USART_ISR_TC_Msk

#define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos)

0x00000040

Definition at line 11343 of file stm32g431xx.h.

◆ USART_ISR_TC_Pos

#define USART_ISR_TC_Pos (6U)

Definition at line 11342 of file stm32g431xx.h.

◆ USART_ISR_TCBGT

#define USART_ISR_TCBGT USART_ISR_TCBGT_Msk

Transmission Complete Before Guard Time completion

Definition at line 11404 of file stm32g431xx.h.

◆ USART_ISR_TCBGT_Msk

#define USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos)

0x02000000

Definition at line 11403 of file stm32g431xx.h.

◆ USART_ISR_TCBGT_Pos

#define USART_ISR_TCBGT_Pos (25U)

Definition at line 11402 of file stm32g431xx.h.

◆ USART_ISR_TEACK

#define USART_ISR_TEACK USART_ISR_TEACK_Msk

Transmit Enable Acknowledge Flag

Definition at line 11392 of file stm32g431xx.h.

◆ USART_ISR_TEACK_Msk

#define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos)

0x00200000

Definition at line 11391 of file stm32g431xx.h.

◆ USART_ISR_TEACK_Pos

#define USART_ISR_TEACK_Pos (21U)

Definition at line 11390 of file stm32g431xx.h.

◆ USART_ISR_TXE

#define USART_ISR_TXE USART_ISR_TXE_Msk

Transmit Data Register Empty

Definition at line 11347 of file stm32g431xx.h.

◆ USART_ISR_TXE_Msk

#define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos)

0x00000080

Definition at line 11346 of file stm32g431xx.h.

◆ USART_ISR_TXE_Pos

#define USART_ISR_TXE_Pos (7U)

Definition at line 11345 of file stm32g431xx.h.

◆ USART_ISR_TXE_TXFNF

#define USART_ISR_TXE_TXFNF USART_ISR_TXE_Msk

Transmit Data Register Empty or TX FIFO Not Full Flag

Definition at line 11350 of file stm32g431xx.h.

◆ USART_ISR_TXE_TXFNF_Msk

#define USART_ISR_TXE_TXFNF_Msk USART_ISR_TXE_Msk

0x00000080

Definition at line 11349 of file stm32g431xx.h.

◆ USART_ISR_TXE_TXFNF_Pos

#define USART_ISR_TXE_TXFNF_Pos USART_ISR_TXE_Pos

Definition at line 11348 of file stm32g431xx.h.

◆ USART_ISR_TXFE

#define USART_ISR_TXFE USART_ISR_TXFE_Msk

TXFIFO Empty

Definition at line 11398 of file stm32g431xx.h.

◆ USART_ISR_TXFE_Msk

#define USART_ISR_TXFE_Msk (0x1UL << USART_ISR_TXFE_Pos)

0x00800000

Definition at line 11397 of file stm32g431xx.h.

◆ USART_ISR_TXFE_Pos

#define USART_ISR_TXFE_Pos (23U)

Definition at line 11396 of file stm32g431xx.h.

◆ USART_ISR_TXFT

#define USART_ISR_TXFT USART_ISR_TXFT_Msk

TXFIFO threshold flag

Definition at line 11410 of file stm32g431xx.h.

◆ USART_ISR_TXFT_Msk

#define USART_ISR_TXFT_Msk (0x1UL << USART_ISR_TXFT_Pos)

0x08000000

Definition at line 11409 of file stm32g431xx.h.

◆ USART_ISR_TXFT_Pos

#define USART_ISR_TXFT_Pos (27U)

Definition at line 11408 of file stm32g431xx.h.

◆ USART_ISR_UDR

#define USART_ISR_UDR USART_ISR_UDR_Msk

SPI slave underrun error flag

Definition at line 11368 of file stm32g431xx.h.

◆ USART_ISR_UDR_Msk

#define USART_ISR_UDR_Msk (0x1UL << USART_ISR_UDR_Pos)

0x00002000

Definition at line 11367 of file stm32g431xx.h.

◆ USART_ISR_UDR_Pos

#define USART_ISR_UDR_Pos (13U)

Definition at line 11366 of file stm32g431xx.h.

◆ USART_ISR_WUF

#define USART_ISR_WUF USART_ISR_WUF_Msk

Wake Up from stop mode Flag

Definition at line 11389 of file stm32g431xx.h.

◆ USART_ISR_WUF_Msk

#define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos)

0x00100000

Definition at line 11388 of file stm32g431xx.h.

◆ USART_ISR_WUF_Pos

#define USART_ISR_WUF_Pos (20U)

Definition at line 11387 of file stm32g431xx.h.

◆ USART_PRESC_PRESCALER

#define USART_PRESC_PRESCALER USART_PRESC_PRESCALER_Msk

PRESCALER[3:0] bits (Clock prescaler)

Definition at line 11472 of file stm32g431xx.h.

◆ USART_PRESC_PRESCALER_0

#define USART_PRESC_PRESCALER_0 (0x1UL << USART_PRESC_PRESCALER_Pos)

0x00000001

Definition at line 11473 of file stm32g431xx.h.

◆ USART_PRESC_PRESCALER_1

#define USART_PRESC_PRESCALER_1 (0x2UL << USART_PRESC_PRESCALER_Pos)

0x00000002

Definition at line 11474 of file stm32g431xx.h.

◆ USART_PRESC_PRESCALER_2

#define USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos)

0x00000004

Definition at line 11475 of file stm32g431xx.h.

◆ USART_PRESC_PRESCALER_3

#define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos)

0x00000008

Definition at line 11476 of file stm32g431xx.h.

◆ USART_PRESC_PRESCALER_Msk

#define USART_PRESC_PRESCALER_Msk (0xFUL << USART_PRESC_PRESCALER_Pos)

0x0000000F

Definition at line 11471 of file stm32g431xx.h.

◆ USART_PRESC_PRESCALER_Pos

#define USART_PRESC_PRESCALER_Pos (0U)

Definition at line 11470 of file stm32g431xx.h.

◆ USART_RDR_RDR

#define USART_RDR_RDR USART_RDR_RDR_Msk

RDR[8:0] bits (Receive Data value)

Definition at line 11462 of file stm32g431xx.h.

◆ USART_RDR_RDR_Msk

#define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos)

0x000001FF

Definition at line 11461 of file stm32g431xx.h.

◆ USART_RDR_RDR_Pos

#define USART_RDR_RDR_Pos (0U)

Definition at line 11460 of file stm32g431xx.h.

◆ USART_RQR_ABRRQ

#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk

Auto-Baud Rate Request

Definition at line 11306 of file stm32g431xx.h.

◆ USART_RQR_ABRRQ_Msk

#define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos)

0x00000001

Definition at line 11305 of file stm32g431xx.h.

◆ USART_RQR_ABRRQ_Pos

#define USART_RQR_ABRRQ_Pos (0U)

Definition at line 11304 of file stm32g431xx.h.

◆ USART_RQR_MMRQ

#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk

Mute Mode Request

Definition at line 11312 of file stm32g431xx.h.

◆ USART_RQR_MMRQ_Msk

#define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos)

0x00000004

Definition at line 11311 of file stm32g431xx.h.

◆ USART_RQR_MMRQ_Pos

#define USART_RQR_MMRQ_Pos (2U)

Definition at line 11310 of file stm32g431xx.h.

◆ USART_RQR_RXFRQ

#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk

Receive Data flush Request

Definition at line 11315 of file stm32g431xx.h.

◆ USART_RQR_RXFRQ_Msk

#define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos)

0x00000008

Definition at line 11314 of file stm32g431xx.h.

◆ USART_RQR_RXFRQ_Pos

#define USART_RQR_RXFRQ_Pos (3U)

Definition at line 11313 of file stm32g431xx.h.

◆ USART_RQR_SBKRQ

#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk

Send Break Request

Definition at line 11309 of file stm32g431xx.h.

◆ USART_RQR_SBKRQ_Msk

#define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos)

0x00000002

Definition at line 11308 of file stm32g431xx.h.

◆ USART_RQR_SBKRQ_Pos

#define USART_RQR_SBKRQ_Pos (1U)

Definition at line 11307 of file stm32g431xx.h.

◆ USART_RQR_TXFRQ

#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk

Transmit data flush Request

Definition at line 11318 of file stm32g431xx.h.

◆ USART_RQR_TXFRQ_Msk

#define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos)

0x00000010

Definition at line 11317 of file stm32g431xx.h.

◆ USART_RQR_TXFRQ_Pos

#define USART_RQR_TXFRQ_Pos (4U)

Definition at line 11316 of file stm32g431xx.h.

◆ USART_RTOR_BLEN

#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk

Block Length

Definition at line 11301 of file stm32g431xx.h.

◆ USART_RTOR_BLEN_Msk

#define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos)

0xFF000000

Definition at line 11300 of file stm32g431xx.h.

◆ USART_RTOR_BLEN_Pos

#define USART_RTOR_BLEN_Pos (24U)

Definition at line 11299 of file stm32g431xx.h.

◆ USART_RTOR_RTO

#define USART_RTOR_RTO USART_RTOR_RTO_Msk

Receiver Time Out Value

Definition at line 11298 of file stm32g431xx.h.

◆ USART_RTOR_RTO_Msk

#define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos)

0x00FFFFFF

Definition at line 11297 of file stm32g431xx.h.

◆ USART_RTOR_RTO_Pos

#define USART_RTOR_RTO_Pos (0U)

Definition at line 11296 of file stm32g431xx.h.

◆ USART_TDR_TDR

#define USART_TDR_TDR USART_TDR_TDR_Msk

TDR[8:0] bits (Transmit Data value)

Definition at line 11467 of file stm32g431xx.h.

◆ USART_TDR_TDR_Msk

#define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos)

0x000001FF

Definition at line 11466 of file stm32g431xx.h.

◆ USART_TDR_TDR_Pos

#define USART_TDR_TDR_Pos (0U)

Definition at line 11465 of file stm32g431xx.h.

◆ USB_ADDR0_RX_ADDR0_RX

#define USB_ADDR0_RX_ADDR0_RX USB_ADDR0_RX_ADDR0_RX_Msk

Reception Buffer Address 0

Definition at line 11788 of file stm32g431xx.h.

◆ USB_ADDR0_RX_ADDR0_RX_Msk

#define USB_ADDR0_RX_ADDR0_RX_Msk (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos)

0x0000FFFE

Definition at line 11787 of file stm32g431xx.h.

◆ USB_ADDR0_RX_ADDR0_RX_Pos

#define USB_ADDR0_RX_ADDR0_RX_Pos (1U)

Definition at line 11786 of file stm32g431xx.h.

◆ USB_ADDR0_TX_ADDR0_TX

#define USB_ADDR0_TX_ADDR0_TX USB_ADDR0_TX_ADDR0_TX_Msk

Transmission Buffer Address 0

Definition at line 11654 of file stm32g431xx.h.

◆ USB_ADDR0_TX_ADDR0_TX_Msk

#define USB_ADDR0_TX_ADDR0_TX_Msk (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos)

0x0000FFFE

Definition at line 11653 of file stm32g431xx.h.

◆ USB_ADDR0_TX_ADDR0_TX_Pos

#define USB_ADDR0_TX_ADDR0_TX_Pos (1U)

Definition at line 11652 of file stm32g431xx.h.

◆ USB_ADDR1_RX_ADDR1_RX

#define USB_ADDR1_RX_ADDR1_RX USB_ADDR1_RX_ADDR1_RX_Msk

Reception Buffer Address 1

Definition at line 11793 of file stm32g431xx.h.

◆ USB_ADDR1_RX_ADDR1_RX_Msk

#define USB_ADDR1_RX_ADDR1_RX_Msk (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos)

0x0000FFFE

Definition at line 11792 of file stm32g431xx.h.

◆ USB_ADDR1_RX_ADDR1_RX_Pos

#define USB_ADDR1_RX_ADDR1_RX_Pos (1U)

Definition at line 11791 of file stm32g431xx.h.

◆ USB_ADDR1_TX_ADDR1_TX

#define USB_ADDR1_TX_ADDR1_TX USB_ADDR1_TX_ADDR1_TX_Msk

Transmission Buffer Address 1

Definition at line 11659 of file stm32g431xx.h.

◆ USB_ADDR1_TX_ADDR1_TX_Msk

#define USB_ADDR1_TX_ADDR1_TX_Msk (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos)

0x0000FFFE

Definition at line 11658 of file stm32g431xx.h.

◆ USB_ADDR1_TX_ADDR1_TX_Pos

#define USB_ADDR1_TX_ADDR1_TX_Pos (1U)

Definition at line 11657 of file stm32g431xx.h.

◆ USB_ADDR2_RX_ADDR2_RX

#define USB_ADDR2_RX_ADDR2_RX USB_ADDR2_RX_ADDR2_RX_Msk

Reception Buffer Address 2

Definition at line 11798 of file stm32g431xx.h.

◆ USB_ADDR2_RX_ADDR2_RX_Msk

#define USB_ADDR2_RX_ADDR2_RX_Msk (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos)

0x0000FFFE

Definition at line 11797 of file stm32g431xx.h.

◆ USB_ADDR2_RX_ADDR2_RX_Pos

#define USB_ADDR2_RX_ADDR2_RX_Pos (1U)

Definition at line 11796 of file stm32g431xx.h.

◆ USB_ADDR2_TX_ADDR2_TX

#define USB_ADDR2_TX_ADDR2_TX USB_ADDR2_TX_ADDR2_TX_Msk

Transmission Buffer Address 2

Definition at line 11664 of file stm32g431xx.h.

◆ USB_ADDR2_TX_ADDR2_TX_Msk

#define USB_ADDR2_TX_ADDR2_TX_Msk (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos)

0x0000FFFE

Definition at line 11663 of file stm32g431xx.h.

◆ USB_ADDR2_TX_ADDR2_TX_Pos

#define USB_ADDR2_TX_ADDR2_TX_Pos (1U)

Definition at line 11662 of file stm32g431xx.h.

◆ USB_ADDR3_RX_ADDR3_RX

#define USB_ADDR3_RX_ADDR3_RX USB_ADDR3_RX_ADDR3_RX_Msk

Reception Buffer Address 3

Definition at line 11803 of file stm32g431xx.h.

◆ USB_ADDR3_RX_ADDR3_RX_Msk

#define USB_ADDR3_RX_ADDR3_RX_Msk (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos)

0x0000FFFE

Definition at line 11802 of file stm32g431xx.h.

◆ USB_ADDR3_RX_ADDR3_RX_Pos

#define USB_ADDR3_RX_ADDR3_RX_Pos (1U)

Definition at line 11801 of file stm32g431xx.h.

◆ USB_ADDR3_TX_ADDR3_TX

#define USB_ADDR3_TX_ADDR3_TX USB_ADDR3_TX_ADDR3_TX_Msk

Transmission Buffer Address 3

Definition at line 11669 of file stm32g431xx.h.

◆ USB_ADDR3_TX_ADDR3_TX_Msk

#define USB_ADDR3_TX_ADDR3_TX_Msk (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos)

0x0000FFFE

Definition at line 11668 of file stm32g431xx.h.

◆ USB_ADDR3_TX_ADDR3_TX_Pos

#define USB_ADDR3_TX_ADDR3_TX_Pos (1U)

Definition at line 11667 of file stm32g431xx.h.

◆ USB_ADDR4_RX_ADDR4_RX

#define USB_ADDR4_RX_ADDR4_RX USB_ADDR4_RX_ADDR4_RX_Msk

Reception Buffer Address 4

Definition at line 11808 of file stm32g431xx.h.

◆ USB_ADDR4_RX_ADDR4_RX_Msk

#define USB_ADDR4_RX_ADDR4_RX_Msk (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos)

0x0000FFFE

Definition at line 11807 of file stm32g431xx.h.

◆ USB_ADDR4_RX_ADDR4_RX_Pos

#define USB_ADDR4_RX_ADDR4_RX_Pos (1U)

Definition at line 11806 of file stm32g431xx.h.

◆ USB_ADDR4_TX_ADDR4_TX

#define USB_ADDR4_TX_ADDR4_TX USB_ADDR4_TX_ADDR4_TX_Msk

Transmission Buffer Address 4

Definition at line 11674 of file stm32g431xx.h.

◆ USB_ADDR4_TX_ADDR4_TX_Msk

#define USB_ADDR4_TX_ADDR4_TX_Msk (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos)

0x0000FFFE

Definition at line 11673 of file stm32g431xx.h.

◆ USB_ADDR4_TX_ADDR4_TX_Pos

#define USB_ADDR4_TX_ADDR4_TX_Pos (1U)

Definition at line 11672 of file stm32g431xx.h.

◆ USB_ADDR5_RX_ADDR5_RX

#define USB_ADDR5_RX_ADDR5_RX USB_ADDR5_RX_ADDR5_RX_Msk

Reception Buffer Address 5

Definition at line 11813 of file stm32g431xx.h.

◆ USB_ADDR5_RX_ADDR5_RX_Msk

#define USB_ADDR5_RX_ADDR5_RX_Msk (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos)

0x0000FFFE

Definition at line 11812 of file stm32g431xx.h.

◆ USB_ADDR5_RX_ADDR5_RX_Pos

#define USB_ADDR5_RX_ADDR5_RX_Pos (1U)

Definition at line 11811 of file stm32g431xx.h.

◆ USB_ADDR5_TX_ADDR5_TX

#define USB_ADDR5_TX_ADDR5_TX USB_ADDR5_TX_ADDR5_TX_Msk

Transmission Buffer Address 5

Definition at line 11679 of file stm32g431xx.h.

◆ USB_ADDR5_TX_ADDR5_TX_Msk

#define USB_ADDR5_TX_ADDR5_TX_Msk (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos)

0x0000FFFE

Definition at line 11678 of file stm32g431xx.h.

◆ USB_ADDR5_TX_ADDR5_TX_Pos

#define USB_ADDR5_TX_ADDR5_TX_Pos (1U)

Definition at line 11677 of file stm32g431xx.h.

◆ USB_ADDR6_RX_ADDR6_RX

#define USB_ADDR6_RX_ADDR6_RX USB_ADDR6_RX_ADDR6_RX_Msk

Reception Buffer Address 6

Definition at line 11818 of file stm32g431xx.h.

◆ USB_ADDR6_RX_ADDR6_RX_Msk

#define USB_ADDR6_RX_ADDR6_RX_Msk (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos)

0x0000FFFE

Definition at line 11817 of file stm32g431xx.h.

◆ USB_ADDR6_RX_ADDR6_RX_Pos

#define USB_ADDR6_RX_ADDR6_RX_Pos (1U)

Definition at line 11816 of file stm32g431xx.h.

◆ USB_ADDR6_TX_ADDR6_TX

#define USB_ADDR6_TX_ADDR6_TX USB_ADDR6_TX_ADDR6_TX_Msk

Transmission Buffer Address 6

Definition at line 11684 of file stm32g431xx.h.

◆ USB_ADDR6_TX_ADDR6_TX_Msk

#define USB_ADDR6_TX_ADDR6_TX_Msk (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos)

0x0000FFFE

Definition at line 11683 of file stm32g431xx.h.

◆ USB_ADDR6_TX_ADDR6_TX_Pos

#define USB_ADDR6_TX_ADDR6_TX_Pos (1U)

Definition at line 11682 of file stm32g431xx.h.

◆ USB_ADDR7_RX_ADDR7_RX

#define USB_ADDR7_RX_ADDR7_RX USB_ADDR7_RX_ADDR7_RX_Msk

Reception Buffer Address 7

Definition at line 11823 of file stm32g431xx.h.

◆ USB_ADDR7_RX_ADDR7_RX_Msk

#define USB_ADDR7_RX_ADDR7_RX_Msk (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos)

0x0000FFFE

Definition at line 11822 of file stm32g431xx.h.

◆ USB_ADDR7_RX_ADDR7_RX_Pos

#define USB_ADDR7_RX_ADDR7_RX_Pos (1U)

Definition at line 11821 of file stm32g431xx.h.

◆ USB_ADDR7_TX_ADDR7_TX

#define USB_ADDR7_TX_ADDR7_TX USB_ADDR7_TX_ADDR7_TX_Msk

Transmission Buffer Address 7

Definition at line 11689 of file stm32g431xx.h.

◆ USB_ADDR7_TX_ADDR7_TX_Msk

#define USB_ADDR7_TX_ADDR7_TX_Msk (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos)

0x0000FFFE

Definition at line 11688 of file stm32g431xx.h.

◆ USB_ADDR7_TX_ADDR7_TX_Pos

#define USB_ADDR7_TX_ADDR7_TX_Pos (1U)

Definition at line 11687 of file stm32g431xx.h.

◆ USB_BCDR

#define USB_BCDR (USB_BASE + 0x00000058U)

Battery Charging detector register

Definition at line 11569 of file stm32g431xx.h.

◆ USB_BCDR_BCDEN

#define USB_BCDR_BCDEN ((uint16_t)0x0001U)

Battery charging detector (BCD) enable

Definition at line 11634 of file stm32g431xx.h.

◆ USB_BCDR_DCDEN

#define USB_BCDR_DCDEN ((uint16_t)0x0002U)

Data contact detection (DCD) mode enable

Definition at line 11635 of file stm32g431xx.h.

◆ USB_BCDR_DCDET

#define USB_BCDR_DCDET ((uint16_t)0x0010U)

Data contact detection (DCD) status

Definition at line 11638 of file stm32g431xx.h.

◆ USB_BCDR_DPPU

#define USB_BCDR_DPPU ((uint16_t)0x8000U)

DP Pull-up Enable

Definition at line 11642 of file stm32g431xx.h.

◆ USB_BCDR_PDEN

#define USB_BCDR_PDEN ((uint16_t)0x0004U)

Primary detection (PD) mode enable

Definition at line 11636 of file stm32g431xx.h.

◆ USB_BCDR_PDET

#define USB_BCDR_PDET ((uint16_t)0x0020U)

Primary detection (PD) status

Definition at line 11639 of file stm32g431xx.h.

◆ USB_BCDR_PS2DET

#define USB_BCDR_PS2DET ((uint16_t)0x0080U)

PS2 port or proprietary charger detected

Definition at line 11641 of file stm32g431xx.h.

◆ USB_BCDR_SDEN

#define USB_BCDR_SDEN ((uint16_t)0x0008U)

Secondary detection (SD) mode enable

Definition at line 11637 of file stm32g431xx.h.

◆ USB_BCDR_SDET

#define USB_BCDR_SDET ((uint16_t)0x0040U)

Secondary detection (SD) status

Definition at line 11640 of file stm32g431xx.h.

◆ USB_BTABLE

#define USB_BTABLE (USB_BASE + 0x00000050U)

Buffer Table address register

Definition at line 11567 of file stm32g431xx.h.

◆ USB_BTABLE_BTABLE

#define USB_BTABLE_BTABLE ((uint16_t)0xFFF8U)

Buffer Table

Definition at line 11631 of file stm32g431xx.h.

◆ USB_CLR_CTR

#define USB_CLR_CTR (~USB_ISTR_CTR)

clear Correct TRansfer bit

Definition at line 11609 of file stm32g431xx.h.

◆ USB_CLR_ERR

#define USB_CLR_ERR (~USB_ISTR_ERR)

clear ERRor bit

Definition at line 11607 of file stm32g431xx.h.

◆ USB_CLR_ESOF

#define USB_CLR_ESOF (~USB_ISTR_ESOF)

clear Expected Start Of Frame bit

Definition at line 11602 of file stm32g431xx.h.

◆ USB_CLR_L1REQ

#define USB_CLR_L1REQ (~USB_ISTR_L1REQ)

clear LPM L1 bit

Definition at line 11601 of file stm32g431xx.h.

◆ USB_CLR_PMAOVR

#define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR)

clear DMA OVeR/underrun bit

Definition at line 11608 of file stm32g431xx.h.

◆ USB_CLR_RESET

#define USB_CLR_RESET (~USB_ISTR_RESET)

clear RESET bit

Definition at line 11604 of file stm32g431xx.h.

◆ USB_CLR_SOF

#define USB_CLR_SOF (~USB_ISTR_SOF)

clear Start Of Frame bit

Definition at line 11603 of file stm32g431xx.h.

◆ USB_CLR_SUSP

#define USB_CLR_SUSP (~USB_ISTR_SUSP)

clear SUSPend bit

Definition at line 11605 of file stm32g431xx.h.

◆ USB_CLR_WKUP

#define USB_CLR_WKUP (~USB_ISTR_WKUP)

clear WaKe UP bit

Definition at line 11606 of file stm32g431xx.h.

◆ USB_CNTR

#define USB_CNTR (USB_BASE + 0x00000040U)

Control register

Definition at line 11563 of file stm32g431xx.h.

◆ USB_CNTR_CTRM

#define USB_CNTR_CTRM ((uint16_t)0x8000U)

Correct TRansfer Mask

Definition at line 11572 of file stm32g431xx.h.

◆ USB_CNTR_ERRM

#define USB_CNTR_ERRM ((uint16_t)0x2000U)

ERRor Mask

Definition at line 11574 of file stm32g431xx.h.

◆ USB_CNTR_ESOFM

#define USB_CNTR_ESOFM ((uint16_t)0x0100U)

Expected Start Of Frame Mask

Definition at line 11579 of file stm32g431xx.h.

◆ USB_CNTR_FRES

#define USB_CNTR_FRES ((uint16_t)0x0001U)

Force USB RESet

Definition at line 11586 of file stm32g431xx.h.

◆ USB_CNTR_FSUSP

#define USB_CNTR_FSUSP ((uint16_t)0x0008U)

Force SUSPend

Definition at line 11583 of file stm32g431xx.h.

◆ USB_CNTR_L1REQM

#define USB_CNTR_L1REQM ((uint16_t)0x0080U)

LPM L1 state request interrupt mask

Definition at line 11580 of file stm32g431xx.h.

◆ USB_CNTR_L1RESUME

#define USB_CNTR_L1RESUME ((uint16_t)0x0020U)

LPM L1 Resume request

Definition at line 11581 of file stm32g431xx.h.

◆ USB_CNTR_LPMODE

#define USB_CNTR_LPMODE ((uint16_t)0x0004U)

Low-power MODE

Definition at line 11584 of file stm32g431xx.h.

◆ USB_CNTR_PDWN

#define USB_CNTR_PDWN ((uint16_t)0x0002U)

Power DoWN

Definition at line 11585 of file stm32g431xx.h.

◆ USB_CNTR_PMAOVRM

#define USB_CNTR_PMAOVRM ((uint16_t)0x4000U)

DMA OVeR/underrun Mask

Definition at line 11573 of file stm32g431xx.h.

◆ USB_CNTR_RESETM

#define USB_CNTR_RESETM ((uint16_t)0x0400U)

RESET Mask

Definition at line 11577 of file stm32g431xx.h.

◆ USB_CNTR_RESUME

#define USB_CNTR_RESUME ((uint16_t)0x0010U)

RESUME request

Definition at line 11582 of file stm32g431xx.h.

◆ USB_CNTR_SOFM

#define USB_CNTR_SOFM ((uint16_t)0x0200U)

Start Of Frame Mask

Definition at line 11578 of file stm32g431xx.h.

◆ USB_CNTR_SUSPM

#define USB_CNTR_SUSPM ((uint16_t)0x0800U)

SUSPend Mask

Definition at line 11576 of file stm32g431xx.h.

◆ USB_CNTR_WKUPM

#define USB_CNTR_WKUPM ((uint16_t)0x1000U)

WaKe UP Mask

Definition at line 11575 of file stm32g431xx.h.

◆ USB_COUNT0_RX_0_BLSIZE_0

#define USB_COUNT0_RX_0_BLSIZE_0 (0x00008000U)

BLock SIZE (low)

Definition at line 11983 of file stm32g431xx.h.

◆ USB_COUNT0_RX_0_COUNT0_RX_0

#define USB_COUNT0_RX_0_COUNT0_RX_0 (0x000003FFU)

Reception Byte Count (low)

Definition at line 11974 of file stm32g431xx.h.

◆ USB_COUNT0_RX_0_NUM_BLOCK_0

#define USB_COUNT0_RX_0_NUM_BLOCK_0 (0x00007C00U)

NUM_BLOCK_0[4:0] bits (Number of blocks) (low)

Definition at line 11976 of file stm32g431xx.h.

◆ USB_COUNT0_RX_0_NUM_BLOCK_0_0

#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 (0x00000400U)

Bit 0

Definition at line 11977 of file stm32g431xx.h.

◆ USB_COUNT0_RX_0_NUM_BLOCK_0_1

#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 (0x00000800U)

Bit 1

Definition at line 11978 of file stm32g431xx.h.

◆ USB_COUNT0_RX_0_NUM_BLOCK_0_2

#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 (0x00001000U)

Bit 2

Definition at line 11979 of file stm32g431xx.h.

◆ USB_COUNT0_RX_0_NUM_BLOCK_0_3

#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 (0x00002000U)

Bit 3

Definition at line 11980 of file stm32g431xx.h.

◆ USB_COUNT0_RX_0_NUM_BLOCK_0_4

#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 (0x00004000U)

Bit 4

Definition at line 11981 of file stm32g431xx.h.

◆ USB_COUNT0_RX_1_BLSIZE_1

#define USB_COUNT0_RX_1_BLSIZE_1 (0x80000000U)

BLock SIZE (high)

Definition at line 11995 of file stm32g431xx.h.

◆ USB_COUNT0_RX_1_COUNT0_RX_1

#define USB_COUNT0_RX_1_COUNT0_RX_1 (0x03FF0000U)

Reception Byte Count (high)

Definition at line 11986 of file stm32g431xx.h.

◆ USB_COUNT0_RX_1_NUM_BLOCK_1

#define USB_COUNT0_RX_1_NUM_BLOCK_1 (0x7C000000U)

NUM_BLOCK_1[4:0] bits (Number of blocks) (high)

Definition at line 11988 of file stm32g431xx.h.

◆ USB_COUNT0_RX_1_NUM_BLOCK_1_0

#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 (0x04000000U)

Bit 1

Definition at line 11989 of file stm32g431xx.h.

◆ USB_COUNT0_RX_1_NUM_BLOCK_1_1

#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 (0x08000000U)

Bit 1

Definition at line 11990 of file stm32g431xx.h.

◆ USB_COUNT0_RX_1_NUM_BLOCK_1_2

#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 (0x10000000U)

Bit 2

Definition at line 11991 of file stm32g431xx.h.

◆ USB_COUNT0_RX_1_NUM_BLOCK_1_3

#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 (0x20000000U)

Bit 3

Definition at line 11992 of file stm32g431xx.h.

◆ USB_COUNT0_RX_1_NUM_BLOCK_1_4

#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 (0x40000000U)

Bit 4

Definition at line 11993 of file stm32g431xx.h.

◆ USB_COUNT0_RX_BLSIZE

#define USB_COUNT0_RX_BLSIZE USB_COUNT0_RX_BLSIZE_Msk

BLock SIZE

Definition at line 11843 of file stm32g431xx.h.

◆ USB_COUNT0_RX_BLSIZE_Msk

#define USB_COUNT0_RX_BLSIZE_Msk (0x1UL << USB_COUNT0_RX_BLSIZE_Pos)

0x00008000

Definition at line 11842 of file stm32g431xx.h.

◆ USB_COUNT0_RX_BLSIZE_Pos

#define USB_COUNT0_RX_BLSIZE_Pos (15U)

Definition at line 11841 of file stm32g431xx.h.

◆ USB_COUNT0_RX_COUNT0_RX

#define USB_COUNT0_RX_COUNT0_RX USB_COUNT0_RX_COUNT0_RX_Msk

Reception Byte Count

Definition at line 11830 of file stm32g431xx.h.

◆ USB_COUNT0_RX_COUNT0_RX_Msk

#define USB_COUNT0_RX_COUNT0_RX_Msk (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos)

0x000003FF

Definition at line 11829 of file stm32g431xx.h.

◆ USB_COUNT0_RX_COUNT0_RX_Pos

#define USB_COUNT0_RX_COUNT0_RX_Pos (0U)

Definition at line 11828 of file stm32g431xx.h.

◆ USB_COUNT0_RX_NUM_BLOCK

#define USB_COUNT0_RX_NUM_BLOCK USB_COUNT0_RX_NUM_BLOCK_Msk

NUM_BLOCK[4:0] bits (Number of blocks)

Definition at line 11834 of file stm32g431xx.h.

◆ USB_COUNT0_RX_NUM_BLOCK_0

#define USB_COUNT0_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos)

0x00000400

Definition at line 11835 of file stm32g431xx.h.

◆ USB_COUNT0_RX_NUM_BLOCK_1

#define USB_COUNT0_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos)

0x00000800

Definition at line 11836 of file stm32g431xx.h.

◆ USB_COUNT0_RX_NUM_BLOCK_2

#define USB_COUNT0_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos)

0x00001000

Definition at line 11837 of file stm32g431xx.h.

◆ USB_COUNT0_RX_NUM_BLOCK_3

#define USB_COUNT0_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos)

0x00002000

Definition at line 11838 of file stm32g431xx.h.

◆ USB_COUNT0_RX_NUM_BLOCK_4

#define USB_COUNT0_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos)

0x00004000

Definition at line 11839 of file stm32g431xx.h.

◆ USB_COUNT0_RX_NUM_BLOCK_Msk

#define USB_COUNT0_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos)

0x00007C00

Definition at line 11833 of file stm32g431xx.h.

◆ USB_COUNT0_RX_NUM_BLOCK_Pos

#define USB_COUNT0_RX_NUM_BLOCK_Pos (10U)

Definition at line 11832 of file stm32g431xx.h.

◆ USB_COUNT0_TX_0_COUNT0_TX_0

#define USB_COUNT0_TX_0_COUNT0_TX_0 (0x000003FFU)

Transmission Byte Count 0 (low)

Definition at line 11736 of file stm32g431xx.h.

◆ USB_COUNT0_TX_1_COUNT0_TX_1

#define USB_COUNT0_TX_1_COUNT0_TX_1 (0x03FF0000U)

Transmission Byte Count 0 (high)

Definition at line 11739 of file stm32g431xx.h.

◆ USB_COUNT0_TX_COUNT0_TX

#define USB_COUNT0_TX_COUNT0_TX USB_COUNT0_TX_COUNT0_TX_Msk

Transmission Byte Count 0

Definition at line 11696 of file stm32g431xx.h.

◆ USB_COUNT0_TX_COUNT0_TX_Msk

#define USB_COUNT0_TX_COUNT0_TX_Msk (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos)

0x000003FF

Definition at line 11695 of file stm32g431xx.h.

◆ USB_COUNT0_TX_COUNT0_TX_Pos

#define USB_COUNT0_TX_COUNT0_TX_Pos (0U)

Definition at line 11694 of file stm32g431xx.h.

◆ USB_COUNT1_RX_0_BLSIZE_0

#define USB_COUNT1_RX_0_BLSIZE_0 (0x00008000U)

BLock SIZE (low)

Definition at line 12007 of file stm32g431xx.h.

◆ USB_COUNT1_RX_0_COUNT1_RX_0

#define USB_COUNT1_RX_0_COUNT1_RX_0 (0x000003FFU)

Reception Byte Count (low)

Definition at line 11998 of file stm32g431xx.h.

◆ USB_COUNT1_RX_0_NUM_BLOCK_0

#define USB_COUNT1_RX_0_NUM_BLOCK_0 (0x00007C00U)

NUM_BLOCK_0[4:0] bits (Number of blocks) (low)

Definition at line 12000 of file stm32g431xx.h.

◆ USB_COUNT1_RX_0_NUM_BLOCK_0_0

#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 (0x00000400U)

Bit 0

Definition at line 12001 of file stm32g431xx.h.

◆ USB_COUNT1_RX_0_NUM_BLOCK_0_1

#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 (0x00000800U)

Bit 1

Definition at line 12002 of file stm32g431xx.h.

◆ USB_COUNT1_RX_0_NUM_BLOCK_0_2

#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 (0x00001000U)

Bit 2

Definition at line 12003 of file stm32g431xx.h.

◆ USB_COUNT1_RX_0_NUM_BLOCK_0_3

#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 (0x00002000U)

Bit 3

Definition at line 12004 of file stm32g431xx.h.

◆ USB_COUNT1_RX_0_NUM_BLOCK_0_4

#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 (0x00004000U)

Bit 4

Definition at line 12005 of file stm32g431xx.h.

◆ USB_COUNT1_RX_1_BLSIZE_1

#define USB_COUNT1_RX_1_BLSIZE_1 (0x80000000U)

BLock SIZE (high)

Definition at line 12019 of file stm32g431xx.h.

◆ USB_COUNT1_RX_1_COUNT1_RX_1

#define USB_COUNT1_RX_1_COUNT1_RX_1 (0x03FF0000U)

Reception Byte Count (high)

Definition at line 12010 of file stm32g431xx.h.

◆ USB_COUNT1_RX_1_NUM_BLOCK_1

#define USB_COUNT1_RX_1_NUM_BLOCK_1 (0x7C000000U)

NUM_BLOCK_1[4:0] bits (Number of blocks) (high)

Definition at line 12012 of file stm32g431xx.h.

◆ USB_COUNT1_RX_1_NUM_BLOCK_1_0

#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 (0x04000000U)

Bit 0

Definition at line 12013 of file stm32g431xx.h.

◆ USB_COUNT1_RX_1_NUM_BLOCK_1_1

#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 (0x08000000U)

Bit 1

Definition at line 12014 of file stm32g431xx.h.

◆ USB_COUNT1_RX_1_NUM_BLOCK_1_2

#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 (0x10000000U)

Bit 2

Definition at line 12015 of file stm32g431xx.h.

◆ USB_COUNT1_RX_1_NUM_BLOCK_1_3

#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 (0x20000000U)

Bit 3

Definition at line 12016 of file stm32g431xx.h.

◆ USB_COUNT1_RX_1_NUM_BLOCK_1_4

#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 (0x40000000U)

Bit 4

Definition at line 12017 of file stm32g431xx.h.

◆ USB_COUNT1_RX_BLSIZE

#define USB_COUNT1_RX_BLSIZE USB_COUNT1_RX_BLSIZE_Msk

BLock SIZE

Definition at line 11861 of file stm32g431xx.h.

◆ USB_COUNT1_RX_BLSIZE_Msk

#define USB_COUNT1_RX_BLSIZE_Msk (0x1UL << USB_COUNT1_RX_BLSIZE_Pos)

0x00008000

Definition at line 11860 of file stm32g431xx.h.

◆ USB_COUNT1_RX_BLSIZE_Pos

#define USB_COUNT1_RX_BLSIZE_Pos (15U)

Definition at line 11859 of file stm32g431xx.h.

◆ USB_COUNT1_RX_COUNT1_RX

#define USB_COUNT1_RX_COUNT1_RX USB_COUNT1_RX_COUNT1_RX_Msk

Reception Byte Count

Definition at line 11848 of file stm32g431xx.h.

◆ USB_COUNT1_RX_COUNT1_RX_Msk

#define USB_COUNT1_RX_COUNT1_RX_Msk (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos)

0x000003FF

Definition at line 11847 of file stm32g431xx.h.

◆ USB_COUNT1_RX_COUNT1_RX_Pos

#define USB_COUNT1_RX_COUNT1_RX_Pos (0U)

Definition at line 11846 of file stm32g431xx.h.

◆ USB_COUNT1_RX_NUM_BLOCK

#define USB_COUNT1_RX_NUM_BLOCK USB_COUNT1_RX_NUM_BLOCK_Msk

NUM_BLOCK[4:0] bits (Number of blocks)

Definition at line 11852 of file stm32g431xx.h.

◆ USB_COUNT1_RX_NUM_BLOCK_0

#define USB_COUNT1_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos)

0x00000400

Definition at line 11853 of file stm32g431xx.h.

◆ USB_COUNT1_RX_NUM_BLOCK_1

#define USB_COUNT1_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos)

0x00000800

Definition at line 11854 of file stm32g431xx.h.

◆ USB_COUNT1_RX_NUM_BLOCK_2

#define USB_COUNT1_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos)

0x00001000

Definition at line 11855 of file stm32g431xx.h.

◆ USB_COUNT1_RX_NUM_BLOCK_3

#define USB_COUNT1_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos)

0x00002000

Definition at line 11856 of file stm32g431xx.h.

◆ USB_COUNT1_RX_NUM_BLOCK_4

#define USB_COUNT1_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos)

0x00004000

Definition at line 11857 of file stm32g431xx.h.

◆ USB_COUNT1_RX_NUM_BLOCK_Msk

#define USB_COUNT1_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos)

0x00007C00

Definition at line 11851 of file stm32g431xx.h.

◆ USB_COUNT1_RX_NUM_BLOCK_Pos

#define USB_COUNT1_RX_NUM_BLOCK_Pos (10U)

Definition at line 11850 of file stm32g431xx.h.

◆ USB_COUNT1_TX_0_COUNT1_TX_0

#define USB_COUNT1_TX_0_COUNT1_TX_0 (0x000003FFU)

Transmission Byte Count 1 (low)

Definition at line 11742 of file stm32g431xx.h.

◆ USB_COUNT1_TX_1_COUNT1_TX_1

#define USB_COUNT1_TX_1_COUNT1_TX_1 (0x03FF0000U)

Transmission Byte Count 1 (high)

Definition at line 11745 of file stm32g431xx.h.

◆ USB_COUNT1_TX_COUNT1_TX

#define USB_COUNT1_TX_COUNT1_TX USB_COUNT1_TX_COUNT1_TX_Msk

Transmission Byte Count 1

Definition at line 11701 of file stm32g431xx.h.

◆ USB_COUNT1_TX_COUNT1_TX_Msk

#define USB_COUNT1_TX_COUNT1_TX_Msk (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos)

0x000003FF

Definition at line 11700 of file stm32g431xx.h.

◆ USB_COUNT1_TX_COUNT1_TX_Pos

#define USB_COUNT1_TX_COUNT1_TX_Pos (0U)

Definition at line 11699 of file stm32g431xx.h.

◆ USB_COUNT2_RX_0_BLSIZE_0

#define USB_COUNT2_RX_0_BLSIZE_0 (0x00008000U)

BLock SIZE (low)

Definition at line 12031 of file stm32g431xx.h.

◆ USB_COUNT2_RX_0_COUNT2_RX_0

#define USB_COUNT2_RX_0_COUNT2_RX_0 (0x000003FFU)

Reception Byte Count (low)

Definition at line 12022 of file stm32g431xx.h.

◆ USB_COUNT2_RX_0_NUM_BLOCK_0

#define USB_COUNT2_RX_0_NUM_BLOCK_0 (0x00007C00U)

NUM_BLOCK_0[4:0] bits (Number of blocks) (low)

Definition at line 12024 of file stm32g431xx.h.

◆ USB_COUNT2_RX_0_NUM_BLOCK_0_0

#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 (0x00000400U)

Bit 0

Definition at line 12025 of file stm32g431xx.h.

◆ USB_COUNT2_RX_0_NUM_BLOCK_0_1

#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 (0x00000800U)

Bit 1

Definition at line 12026 of file stm32g431xx.h.

◆ USB_COUNT2_RX_0_NUM_BLOCK_0_2

#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 (0x00001000U)

Bit 2

Definition at line 12027 of file stm32g431xx.h.

◆ USB_COUNT2_RX_0_NUM_BLOCK_0_3

#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 (0x00002000U)

Bit 3

Definition at line 12028 of file stm32g431xx.h.

◆ USB_COUNT2_RX_0_NUM_BLOCK_0_4

#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 (0x00004000U)

Bit 4

Definition at line 12029 of file stm32g431xx.h.

◆ USB_COUNT2_RX_1_BLSIZE_1

#define USB_COUNT2_RX_1_BLSIZE_1 (0x80000000U)

BLock SIZE (high)

Definition at line 12043 of file stm32g431xx.h.

◆ USB_COUNT2_RX_1_COUNT2_RX_1

#define USB_COUNT2_RX_1_COUNT2_RX_1 (0x03FF0000U)

Reception Byte Count (high)

Definition at line 12034 of file stm32g431xx.h.

◆ USB_COUNT2_RX_1_NUM_BLOCK_1

#define USB_COUNT2_RX_1_NUM_BLOCK_1 (0x7C000000U)

NUM_BLOCK_1[4:0] bits (Number of blocks) (high)

Definition at line 12036 of file stm32g431xx.h.

◆ USB_COUNT2_RX_1_NUM_BLOCK_1_0

#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 (0x04000000U)

Bit 0

Definition at line 12037 of file stm32g431xx.h.

◆ USB_COUNT2_RX_1_NUM_BLOCK_1_1

#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 (0x08000000U)

Bit 1

Definition at line 12038 of file stm32g431xx.h.

◆ USB_COUNT2_RX_1_NUM_BLOCK_1_2

#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 (0x10000000U)

Bit 2

Definition at line 12039 of file stm32g431xx.h.

◆ USB_COUNT2_RX_1_NUM_BLOCK_1_3

#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 (0x20000000U)

Bit 3

Definition at line 12040 of file stm32g431xx.h.

◆ USB_COUNT2_RX_1_NUM_BLOCK_1_4

#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 (0x40000000U)

Bit 4

Definition at line 12041 of file stm32g431xx.h.

◆ USB_COUNT2_RX_BLSIZE

#define USB_COUNT2_RX_BLSIZE USB_COUNT2_RX_BLSIZE_Msk

BLock SIZE

Definition at line 11879 of file stm32g431xx.h.

◆ USB_COUNT2_RX_BLSIZE_Msk

#define USB_COUNT2_RX_BLSIZE_Msk (0x1UL << USB_COUNT2_RX_BLSIZE_Pos)

0x00008000

Definition at line 11878 of file stm32g431xx.h.

◆ USB_COUNT2_RX_BLSIZE_Pos

#define USB_COUNT2_RX_BLSIZE_Pos (15U)

Definition at line 11877 of file stm32g431xx.h.

◆ USB_COUNT2_RX_COUNT2_RX

#define USB_COUNT2_RX_COUNT2_RX USB_COUNT2_RX_COUNT2_RX_Msk

Reception Byte Count

Definition at line 11866 of file stm32g431xx.h.

◆ USB_COUNT2_RX_COUNT2_RX_Msk

#define USB_COUNT2_RX_COUNT2_RX_Msk (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos)

0x000003FF

Definition at line 11865 of file stm32g431xx.h.

◆ USB_COUNT2_RX_COUNT2_RX_Pos

#define USB_COUNT2_RX_COUNT2_RX_Pos (0U)

Definition at line 11864 of file stm32g431xx.h.

◆ USB_COUNT2_RX_NUM_BLOCK

#define USB_COUNT2_RX_NUM_BLOCK USB_COUNT2_RX_NUM_BLOCK_Msk

NUM_BLOCK[4:0] bits (Number of blocks)

Definition at line 11870 of file stm32g431xx.h.

◆ USB_COUNT2_RX_NUM_BLOCK_0

#define USB_COUNT2_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos)

0x00000400

Definition at line 11871 of file stm32g431xx.h.

◆ USB_COUNT2_RX_NUM_BLOCK_1

#define USB_COUNT2_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos)

0x00000800

Definition at line 11872 of file stm32g431xx.h.

◆ USB_COUNT2_RX_NUM_BLOCK_2

#define USB_COUNT2_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos)

0x00001000

Definition at line 11873 of file stm32g431xx.h.

◆ USB_COUNT2_RX_NUM_BLOCK_3

#define USB_COUNT2_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos)

0x00002000

Definition at line 11874 of file stm32g431xx.h.

◆ USB_COUNT2_RX_NUM_BLOCK_4

#define USB_COUNT2_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos)

0x00004000

Definition at line 11875 of file stm32g431xx.h.

◆ USB_COUNT2_RX_NUM_BLOCK_Msk

#define USB_COUNT2_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos)

0x00007C00

Definition at line 11869 of file stm32g431xx.h.

◆ USB_COUNT2_RX_NUM_BLOCK_Pos

#define USB_COUNT2_RX_NUM_BLOCK_Pos (10U)

Definition at line 11868 of file stm32g431xx.h.

◆ USB_COUNT2_TX_0_COUNT2_TX_0

#define USB_COUNT2_TX_0_COUNT2_TX_0 (0x000003FFU)

Transmission Byte Count 2 (low)

Definition at line 11748 of file stm32g431xx.h.

◆ USB_COUNT2_TX_1_COUNT2_TX_1

#define USB_COUNT2_TX_1_COUNT2_TX_1 (0x03FF0000U)

Transmission Byte Count 2 (high)

Definition at line 11751 of file stm32g431xx.h.

◆ USB_COUNT2_TX_COUNT2_TX

#define USB_COUNT2_TX_COUNT2_TX USB_COUNT2_TX_COUNT2_TX_Msk

Transmission Byte Count 2

Definition at line 11706 of file stm32g431xx.h.

◆ USB_COUNT2_TX_COUNT2_TX_Msk

#define USB_COUNT2_TX_COUNT2_TX_Msk (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos)

0x000003FF

Definition at line 11705 of file stm32g431xx.h.

◆ USB_COUNT2_TX_COUNT2_TX_Pos

#define USB_COUNT2_TX_COUNT2_TX_Pos (0U)

Definition at line 11704 of file stm32g431xx.h.

◆ USB_COUNT3_RX_0_BLSIZE_0

#define USB_COUNT3_RX_0_BLSIZE_0 (0x00008000U)

BLock SIZE (low)

Definition at line 12055 of file stm32g431xx.h.

◆ USB_COUNT3_RX_0_COUNT3_RX_0

#define USB_COUNT3_RX_0_COUNT3_RX_0 (0x000003FFU)

Reception Byte Count (low)

Definition at line 12046 of file stm32g431xx.h.

◆ USB_COUNT3_RX_0_NUM_BLOCK_0

#define USB_COUNT3_RX_0_NUM_BLOCK_0 (0x00007C00U)

NUM_BLOCK_0[4:0] bits (Number of blocks) (low)

Definition at line 12048 of file stm32g431xx.h.

◆ USB_COUNT3_RX_0_NUM_BLOCK_0_0

#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 (0x00000400U)

Bit 0

Definition at line 12049 of file stm32g431xx.h.

◆ USB_COUNT3_RX_0_NUM_BLOCK_0_1

#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 (0x00000800U)

Bit 1

Definition at line 12050 of file stm32g431xx.h.

◆ USB_COUNT3_RX_0_NUM_BLOCK_0_2

#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 (0x00001000U)

Bit 2

Definition at line 12051 of file stm32g431xx.h.

◆ USB_COUNT3_RX_0_NUM_BLOCK_0_3

#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 (0x00002000U)

Bit 3

Definition at line 12052 of file stm32g431xx.h.

◆ USB_COUNT3_RX_0_NUM_BLOCK_0_4

#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 (0x00004000U)

Bit 4

Definition at line 12053 of file stm32g431xx.h.

◆ USB_COUNT3_RX_1_BLSIZE_1

#define USB_COUNT3_RX_1_BLSIZE_1 (0x80000000U)

BLock SIZE (high)

Definition at line 12067 of file stm32g431xx.h.

◆ USB_COUNT3_RX_1_COUNT3_RX_1

#define USB_COUNT3_RX_1_COUNT3_RX_1 (0x03FF0000U)

Reception Byte Count (high)

Definition at line 12058 of file stm32g431xx.h.

◆ USB_COUNT3_RX_1_NUM_BLOCK_1

#define USB_COUNT3_RX_1_NUM_BLOCK_1 (0x7C000000U)

NUM_BLOCK_1[4:0] bits (Number of blocks) (high)

Definition at line 12060 of file stm32g431xx.h.

◆ USB_COUNT3_RX_1_NUM_BLOCK_1_0

#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 (0x04000000U)

Bit 0

Definition at line 12061 of file stm32g431xx.h.

◆ USB_COUNT3_RX_1_NUM_BLOCK_1_1

#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 (0x08000000U)

Bit 1

Definition at line 12062 of file stm32g431xx.h.

◆ USB_COUNT3_RX_1_NUM_BLOCK_1_2

#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 (0x10000000U)

Bit 2

Definition at line 12063 of file stm32g431xx.h.

◆ USB_COUNT3_RX_1_NUM_BLOCK_1_3

#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 (0x20000000U)

Bit 3

Definition at line 12064 of file stm32g431xx.h.

◆ USB_COUNT3_RX_1_NUM_BLOCK_1_4

#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 (0x40000000U)

Bit 4

Definition at line 12065 of file stm32g431xx.h.

◆ USB_COUNT3_RX_BLSIZE

#define USB_COUNT3_RX_BLSIZE USB_COUNT3_RX_BLSIZE_Msk

BLock SIZE

Definition at line 11897 of file stm32g431xx.h.

◆ USB_COUNT3_RX_BLSIZE_Msk

#define USB_COUNT3_RX_BLSIZE_Msk (0x1UL << USB_COUNT3_RX_BLSIZE_Pos)

0x00008000

Definition at line 11896 of file stm32g431xx.h.

◆ USB_COUNT3_RX_BLSIZE_Pos

#define USB_COUNT3_RX_BLSIZE_Pos (15U)

Definition at line 11895 of file stm32g431xx.h.

◆ USB_COUNT3_RX_COUNT3_RX

#define USB_COUNT3_RX_COUNT3_RX USB_COUNT3_RX_COUNT3_RX_Msk

Reception Byte Count

Definition at line 11884 of file stm32g431xx.h.

◆ USB_COUNT3_RX_COUNT3_RX_Msk

#define USB_COUNT3_RX_COUNT3_RX_Msk (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos)

0x000003FF

Definition at line 11883 of file stm32g431xx.h.

◆ USB_COUNT3_RX_COUNT3_RX_Pos

#define USB_COUNT3_RX_COUNT3_RX_Pos (0U)

Definition at line 11882 of file stm32g431xx.h.

◆ USB_COUNT3_RX_NUM_BLOCK

#define USB_COUNT3_RX_NUM_BLOCK USB_COUNT3_RX_NUM_BLOCK_Msk

NUM_BLOCK[4:0] bits (Number of blocks)

Definition at line 11888 of file stm32g431xx.h.

◆ USB_COUNT3_RX_NUM_BLOCK_0

#define USB_COUNT3_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos)

0x00000400

Definition at line 11889 of file stm32g431xx.h.

◆ USB_COUNT3_RX_NUM_BLOCK_1

#define USB_COUNT3_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos)

0x00000800

Definition at line 11890 of file stm32g431xx.h.

◆ USB_COUNT3_RX_NUM_BLOCK_2

#define USB_COUNT3_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos)

0x00001000

Definition at line 11891 of file stm32g431xx.h.

◆ USB_COUNT3_RX_NUM_BLOCK_3

#define USB_COUNT3_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos)

0x00002000

Definition at line 11892 of file stm32g431xx.h.

◆ USB_COUNT3_RX_NUM_BLOCK_4

#define USB_COUNT3_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos)

0x00004000

Definition at line 11893 of file stm32g431xx.h.

◆ USB_COUNT3_RX_NUM_BLOCK_Msk

#define USB_COUNT3_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos)

0x00007C00

Definition at line 11887 of file stm32g431xx.h.

◆ USB_COUNT3_RX_NUM_BLOCK_Pos

#define USB_COUNT3_RX_NUM_BLOCK_Pos (10U)

Definition at line 11886 of file stm32g431xx.h.

◆ USB_COUNT3_TX_0_COUNT3_TX_0

#define USB_COUNT3_TX_0_COUNT3_TX_0 (0x000003FFU)

Transmission Byte Count 3 (low)

Definition at line 11754 of file stm32g431xx.h.

◆ USB_COUNT3_TX_1_COUNT3_TX_1

#define USB_COUNT3_TX_1_COUNT3_TX_1 (0x03FF0000U)

Transmission Byte Count 3 (high)

Definition at line 11757 of file stm32g431xx.h.

◆ USB_COUNT3_TX_COUNT3_TX

#define USB_COUNT3_TX_COUNT3_TX USB_COUNT3_TX_COUNT3_TX_Msk

Transmission Byte Count 3

Definition at line 11711 of file stm32g431xx.h.

◆ USB_COUNT3_TX_COUNT3_TX_Msk

#define USB_COUNT3_TX_COUNT3_TX_Msk (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos)

0x000003FF

Definition at line 11710 of file stm32g431xx.h.

◆ USB_COUNT3_TX_COUNT3_TX_Pos

#define USB_COUNT3_TX_COUNT3_TX_Pos (0U)

Definition at line 11709 of file stm32g431xx.h.

◆ USB_COUNT4_RX_0_BLSIZE_0

#define USB_COUNT4_RX_0_BLSIZE_0 (0x00008000U)

BLock SIZE (low)

Definition at line 12079 of file stm32g431xx.h.

◆ USB_COUNT4_RX_0_COUNT4_RX_0

#define USB_COUNT4_RX_0_COUNT4_RX_0 (0x000003FFU)

Reception Byte Count (low)

Definition at line 12070 of file stm32g431xx.h.

◆ USB_COUNT4_RX_0_NUM_BLOCK_0

#define USB_COUNT4_RX_0_NUM_BLOCK_0 (0x00007C00U)

NUM_BLOCK_0[4:0] bits (Number of blocks) (low)

Definition at line 12072 of file stm32g431xx.h.

◆ USB_COUNT4_RX_0_NUM_BLOCK_0_0

#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 (0x00000400U)

Bit 0

Definition at line 12073 of file stm32g431xx.h.

◆ USB_COUNT4_RX_0_NUM_BLOCK_0_1

#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 (0x00000800U)

Bit 1

Definition at line 12074 of file stm32g431xx.h.

◆ USB_COUNT4_RX_0_NUM_BLOCK_0_2

#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 (0x00001000U)

Bit 2

Definition at line 12075 of file stm32g431xx.h.

◆ USB_COUNT4_RX_0_NUM_BLOCK_0_3

#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 (0x00002000U)

Bit 3

Definition at line 12076 of file stm32g431xx.h.

◆ USB_COUNT4_RX_0_NUM_BLOCK_0_4

#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 (0x00004000U)

Bit 4

Definition at line 12077 of file stm32g431xx.h.

◆ USB_COUNT4_RX_1_BLSIZE_1

#define USB_COUNT4_RX_1_BLSIZE_1 (0x80000000U)

BLock SIZE (high)

Definition at line 12091 of file stm32g431xx.h.

◆ USB_COUNT4_RX_1_COUNT4_RX_1

#define USB_COUNT4_RX_1_COUNT4_RX_1 (0x03FF0000U)

Reception Byte Count (high)

Definition at line 12082 of file stm32g431xx.h.

◆ USB_COUNT4_RX_1_NUM_BLOCK_1

#define USB_COUNT4_RX_1_NUM_BLOCK_1 (0x7C000000U)

NUM_BLOCK_1[4:0] bits (Number of blocks) (high)

Definition at line 12084 of file stm32g431xx.h.

◆ USB_COUNT4_RX_1_NUM_BLOCK_1_0

#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 (0x04000000U)

Bit 0

Definition at line 12085 of file stm32g431xx.h.

◆ USB_COUNT4_RX_1_NUM_BLOCK_1_1

#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 (0x08000000U)

Bit 1

Definition at line 12086 of file stm32g431xx.h.

◆ USB_COUNT4_RX_1_NUM_BLOCK_1_2

#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 (0x10000000U)

Bit 2

Definition at line 12087 of file stm32g431xx.h.

◆ USB_COUNT4_RX_1_NUM_BLOCK_1_3

#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 (0x20000000U)

Bit 3

Definition at line 12088 of file stm32g431xx.h.

◆ USB_COUNT4_RX_1_NUM_BLOCK_1_4

#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 (0x40000000U)

Bit 4

Definition at line 12089 of file stm32g431xx.h.

◆ USB_COUNT4_RX_BLSIZE

#define USB_COUNT4_RX_BLSIZE USB_COUNT4_RX_BLSIZE_Msk

BLock SIZE

Definition at line 11915 of file stm32g431xx.h.

◆ USB_COUNT4_RX_BLSIZE_Msk

#define USB_COUNT4_RX_BLSIZE_Msk (0x1UL << USB_COUNT4_RX_BLSIZE_Pos)

0x00008000

Definition at line 11914 of file stm32g431xx.h.

◆ USB_COUNT4_RX_BLSIZE_Pos

#define USB_COUNT4_RX_BLSIZE_Pos (15U)

Definition at line 11913 of file stm32g431xx.h.

◆ USB_COUNT4_RX_COUNT4_RX

#define USB_COUNT4_RX_COUNT4_RX USB_COUNT4_RX_COUNT4_RX_Msk

Reception Byte Count

Definition at line 11902 of file stm32g431xx.h.

◆ USB_COUNT4_RX_COUNT4_RX_Msk

#define USB_COUNT4_RX_COUNT4_RX_Msk (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos)

0x000003FF

Definition at line 11901 of file stm32g431xx.h.

◆ USB_COUNT4_RX_COUNT4_RX_Pos

#define USB_COUNT4_RX_COUNT4_RX_Pos (0U)

Definition at line 11900 of file stm32g431xx.h.

◆ USB_COUNT4_RX_NUM_BLOCK

#define USB_COUNT4_RX_NUM_BLOCK USB_COUNT4_RX_NUM_BLOCK_Msk

NUM_BLOCK[4:0] bits (Number of blocks)

Definition at line 11906 of file stm32g431xx.h.

◆ USB_COUNT4_RX_NUM_BLOCK_0

#define USB_COUNT4_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos)

0x00000400

Definition at line 11907 of file stm32g431xx.h.

◆ USB_COUNT4_RX_NUM_BLOCK_1

#define USB_COUNT4_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos)

0x00000800

Definition at line 11908 of file stm32g431xx.h.

◆ USB_COUNT4_RX_NUM_BLOCK_2

#define USB_COUNT4_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos)

0x00001000

Definition at line 11909 of file stm32g431xx.h.

◆ USB_COUNT4_RX_NUM_BLOCK_3

#define USB_COUNT4_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos)

0x00002000

Definition at line 11910 of file stm32g431xx.h.

◆ USB_COUNT4_RX_NUM_BLOCK_4

#define USB_COUNT4_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos)

0x00004000

Definition at line 11911 of file stm32g431xx.h.

◆ USB_COUNT4_RX_NUM_BLOCK_Msk

#define USB_COUNT4_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos)

0x00007C00

Definition at line 11905 of file stm32g431xx.h.

◆ USB_COUNT4_RX_NUM_BLOCK_Pos

#define USB_COUNT4_RX_NUM_BLOCK_Pos (10U)

Definition at line 11904 of file stm32g431xx.h.

◆ USB_COUNT4_TX_0_COUNT4_TX_0

#define USB_COUNT4_TX_0_COUNT4_TX_0 (0x000003FFU)

Transmission Byte Count 4 (low)

Definition at line 11760 of file stm32g431xx.h.

◆ USB_COUNT4_TX_1_COUNT4_TX_1

#define USB_COUNT4_TX_1_COUNT4_TX_1 (0x03FF0000U)

Transmission Byte Count 4 (high)

Definition at line 11763 of file stm32g431xx.h.

◆ USB_COUNT4_TX_COUNT4_TX

#define USB_COUNT4_TX_COUNT4_TX USB_COUNT4_TX_COUNT4_TX_Msk

Transmission Byte Count 4

Definition at line 11716 of file stm32g431xx.h.

◆ USB_COUNT4_TX_COUNT4_TX_Msk

#define USB_COUNT4_TX_COUNT4_TX_Msk (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos)

0x000003FF

Definition at line 11715 of file stm32g431xx.h.

◆ USB_COUNT4_TX_COUNT4_TX_Pos

#define USB_COUNT4_TX_COUNT4_TX_Pos (0U)

Definition at line 11714 of file stm32g431xx.h.

◆ USB_COUNT5_RX_0_BLSIZE_0

#define USB_COUNT5_RX_0_BLSIZE_0 (0x00008000U)

BLock SIZE (low)

Definition at line 12103 of file stm32g431xx.h.

◆ USB_COUNT5_RX_0_COUNT5_RX_0

#define USB_COUNT5_RX_0_COUNT5_RX_0 (0x000003FFU)

Reception Byte Count (low)

Definition at line 12094 of file stm32g431xx.h.

◆ USB_COUNT5_RX_0_NUM_BLOCK_0

#define USB_COUNT5_RX_0_NUM_BLOCK_0 (0x00007C00U)

NUM_BLOCK_0[4:0] bits (Number of blocks) (low)

Definition at line 12096 of file stm32g431xx.h.

◆ USB_COUNT5_RX_0_NUM_BLOCK_0_0

#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 (0x00000400U)

Bit 0

Definition at line 12097 of file stm32g431xx.h.

◆ USB_COUNT5_RX_0_NUM_BLOCK_0_1

#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 (0x00000800U)

Bit 1

Definition at line 12098 of file stm32g431xx.h.

◆ USB_COUNT5_RX_0_NUM_BLOCK_0_2

#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 (0x00001000U)

Bit 2

Definition at line 12099 of file stm32g431xx.h.

◆ USB_COUNT5_RX_0_NUM_BLOCK_0_3

#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 (0x00002000U)

Bit 3

Definition at line 12100 of file stm32g431xx.h.

◆ USB_COUNT5_RX_0_NUM_BLOCK_0_4

#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 (0x00004000U)

Bit 4

Definition at line 12101 of file stm32g431xx.h.

◆ USB_COUNT5_RX_1_BLSIZE_1

#define USB_COUNT5_RX_1_BLSIZE_1 (0x80000000U)

BLock SIZE (high)

Definition at line 12115 of file stm32g431xx.h.

◆ USB_COUNT5_RX_1_COUNT5_RX_1

#define USB_COUNT5_RX_1_COUNT5_RX_1 (0x03FF0000U)

Reception Byte Count (high)

Definition at line 12106 of file stm32g431xx.h.

◆ USB_COUNT5_RX_1_NUM_BLOCK_1

#define USB_COUNT5_RX_1_NUM_BLOCK_1 (0x7C000000U)

NUM_BLOCK_1[4:0] bits (Number of blocks) (high)

Definition at line 12108 of file stm32g431xx.h.

◆ USB_COUNT5_RX_1_NUM_BLOCK_1_0

#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 (0x04000000U)

Bit 0

Definition at line 12109 of file stm32g431xx.h.

◆ USB_COUNT5_RX_1_NUM_BLOCK_1_1

#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 (0x08000000U)

Bit 1

Definition at line 12110 of file stm32g431xx.h.

◆ USB_COUNT5_RX_1_NUM_BLOCK_1_2

#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 (0x10000000U)

Bit 2

Definition at line 12111 of file stm32g431xx.h.

◆ USB_COUNT5_RX_1_NUM_BLOCK_1_3

#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 (0x20000000U)

Bit 3

Definition at line 12112 of file stm32g431xx.h.

◆ USB_COUNT5_RX_1_NUM_BLOCK_1_4

#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 (0x40000000U)

Bit 4

Definition at line 12113 of file stm32g431xx.h.

◆ USB_COUNT5_RX_BLSIZE

#define USB_COUNT5_RX_BLSIZE USB_COUNT5_RX_BLSIZE_Msk

BLock SIZE

Definition at line 11933 of file stm32g431xx.h.

◆ USB_COUNT5_RX_BLSIZE_Msk

#define USB_COUNT5_RX_BLSIZE_Msk (0x1UL << USB_COUNT5_RX_BLSIZE_Pos)

0x00008000

Definition at line 11932 of file stm32g431xx.h.

◆ USB_COUNT5_RX_BLSIZE_Pos

#define USB_COUNT5_RX_BLSIZE_Pos (15U)

Definition at line 11931 of file stm32g431xx.h.

◆ USB_COUNT5_RX_COUNT5_RX

#define USB_COUNT5_RX_COUNT5_RX USB_COUNT5_RX_COUNT5_RX_Msk

Reception Byte Count

Definition at line 11920 of file stm32g431xx.h.

◆ USB_COUNT5_RX_COUNT5_RX_Msk

#define USB_COUNT5_RX_COUNT5_RX_Msk (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos)

0x000003FF

Definition at line 11919 of file stm32g431xx.h.

◆ USB_COUNT5_RX_COUNT5_RX_Pos

#define USB_COUNT5_RX_COUNT5_RX_Pos (0U)

Definition at line 11918 of file stm32g431xx.h.

◆ USB_COUNT5_RX_NUM_BLOCK

#define USB_COUNT5_RX_NUM_BLOCK USB_COUNT5_RX_NUM_BLOCK_Msk

NUM_BLOCK[4:0] bits (Number of blocks)

Definition at line 11924 of file stm32g431xx.h.

◆ USB_COUNT5_RX_NUM_BLOCK_0

#define USB_COUNT5_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos)

0x00000400

Definition at line 11925 of file stm32g431xx.h.

◆ USB_COUNT5_RX_NUM_BLOCK_1

#define USB_COUNT5_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos)

0x00000800

Definition at line 11926 of file stm32g431xx.h.

◆ USB_COUNT5_RX_NUM_BLOCK_2

#define USB_COUNT5_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos)

0x00001000

Definition at line 11927 of file stm32g431xx.h.

◆ USB_COUNT5_RX_NUM_BLOCK_3

#define USB_COUNT5_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos)

0x00002000

Definition at line 11928 of file stm32g431xx.h.

◆ USB_COUNT5_RX_NUM_BLOCK_4

#define USB_COUNT5_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos)

0x00004000

Definition at line 11929 of file stm32g431xx.h.

◆ USB_COUNT5_RX_NUM_BLOCK_Msk

#define USB_COUNT5_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos)

0x00007C00

Definition at line 11923 of file stm32g431xx.h.

◆ USB_COUNT5_RX_NUM_BLOCK_Pos

#define USB_COUNT5_RX_NUM_BLOCK_Pos (10U)

Definition at line 11922 of file stm32g431xx.h.

◆ USB_COUNT5_TX_0_COUNT5_TX_0

#define USB_COUNT5_TX_0_COUNT5_TX_0 (0x000003FFU)

Transmission Byte Count 5 (low)

Definition at line 11766 of file stm32g431xx.h.

◆ USB_COUNT5_TX_1_COUNT5_TX_1

#define USB_COUNT5_TX_1_COUNT5_TX_1 (0x03FF0000U)

Transmission Byte Count 5 (high)

Definition at line 11769 of file stm32g431xx.h.

◆ USB_COUNT5_TX_COUNT5_TX

#define USB_COUNT5_TX_COUNT5_TX USB_COUNT5_TX_COUNT5_TX_Msk

Transmission Byte Count 5

Definition at line 11721 of file stm32g431xx.h.

◆ USB_COUNT5_TX_COUNT5_TX_Msk

#define USB_COUNT5_TX_COUNT5_TX_Msk (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos)

0x000003FF

Definition at line 11720 of file stm32g431xx.h.

◆ USB_COUNT5_TX_COUNT5_TX_Pos

#define USB_COUNT5_TX_COUNT5_TX_Pos (0U)

Definition at line 11719 of file stm32g431xx.h.

◆ USB_COUNT6_RX_0_BLSIZE_0

#define USB_COUNT6_RX_0_BLSIZE_0 (0x00008000U)

BLock SIZE (low)

Definition at line 12127 of file stm32g431xx.h.

◆ USB_COUNT6_RX_0_COUNT6_RX_0

#define USB_COUNT6_RX_0_COUNT6_RX_0 (0x000003FFU)

Reception Byte Count (low)

Definition at line 12118 of file stm32g431xx.h.

◆ USB_COUNT6_RX_0_NUM_BLOCK_0

#define USB_COUNT6_RX_0_NUM_BLOCK_0 (0x00007C00U)

NUM_BLOCK_0[4:0] bits (Number of blocks) (low)

Definition at line 12120 of file stm32g431xx.h.

◆ USB_COUNT6_RX_0_NUM_BLOCK_0_0

#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 (0x00000400U)

Bit 0

Definition at line 12121 of file stm32g431xx.h.

◆ USB_COUNT6_RX_0_NUM_BLOCK_0_1

#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 (0x00000800U)

Bit 1

Definition at line 12122 of file stm32g431xx.h.

◆ USB_COUNT6_RX_0_NUM_BLOCK_0_2

#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 (0x00001000U)

Bit 2

Definition at line 12123 of file stm32g431xx.h.

◆ USB_COUNT6_RX_0_NUM_BLOCK_0_3

#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 (0x00002000U)

Bit 3

Definition at line 12124 of file stm32g431xx.h.

◆ USB_COUNT6_RX_0_NUM_BLOCK_0_4

#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 (0x00004000U)

Bit 4

Definition at line 12125 of file stm32g431xx.h.

◆ USB_COUNT6_RX_1_BLSIZE_1

#define USB_COUNT6_RX_1_BLSIZE_1 (0x80000000U)

BLock SIZE (high)

Definition at line 12139 of file stm32g431xx.h.

◆ USB_COUNT6_RX_1_COUNT6_RX_1

#define USB_COUNT6_RX_1_COUNT6_RX_1 (0x03FF0000U)

Reception Byte Count (high)

Definition at line 12130 of file stm32g431xx.h.

◆ USB_COUNT6_RX_1_NUM_BLOCK_1

#define USB_COUNT6_RX_1_NUM_BLOCK_1 (0x7C000000U)

NUM_BLOCK_1[4:0] bits (Number of blocks) (high)

Definition at line 12132 of file stm32g431xx.h.

◆ USB_COUNT6_RX_1_NUM_BLOCK_1_0

#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 (0x04000000U)

Bit 0

Definition at line 12133 of file stm32g431xx.h.

◆ USB_COUNT6_RX_1_NUM_BLOCK_1_1

#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 (0x08000000U)

Bit 1

Definition at line 12134 of file stm32g431xx.h.

◆ USB_COUNT6_RX_1_NUM_BLOCK_1_2

#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 (0x10000000U)

Bit 2

Definition at line 12135 of file stm32g431xx.h.

◆ USB_COUNT6_RX_1_NUM_BLOCK_1_3

#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 (0x20000000U)

Bit 3

Definition at line 12136 of file stm32g431xx.h.

◆ USB_COUNT6_RX_1_NUM_BLOCK_1_4

#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 (0x40000000U)

Bit 4

Definition at line 12137 of file stm32g431xx.h.

◆ USB_COUNT6_RX_BLSIZE

#define USB_COUNT6_RX_BLSIZE USB_COUNT6_RX_BLSIZE_Msk

BLock SIZE

Definition at line 11951 of file stm32g431xx.h.

◆ USB_COUNT6_RX_BLSIZE_Msk

#define USB_COUNT6_RX_BLSIZE_Msk (0x1UL << USB_COUNT6_RX_BLSIZE_Pos)

0x00008000

Definition at line 11950 of file stm32g431xx.h.

◆ USB_COUNT6_RX_BLSIZE_Pos

#define USB_COUNT6_RX_BLSIZE_Pos (15U)

Definition at line 11949 of file stm32g431xx.h.

◆ USB_COUNT6_RX_COUNT6_RX

#define USB_COUNT6_RX_COUNT6_RX USB_COUNT6_RX_COUNT6_RX_Msk

Reception Byte Count

Definition at line 11938 of file stm32g431xx.h.

◆ USB_COUNT6_RX_COUNT6_RX_Msk

#define USB_COUNT6_RX_COUNT6_RX_Msk (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos)

0x000003FF

Definition at line 11937 of file stm32g431xx.h.

◆ USB_COUNT6_RX_COUNT6_RX_Pos

#define USB_COUNT6_RX_COUNT6_RX_Pos (0U)

Definition at line 11936 of file stm32g431xx.h.

◆ USB_COUNT6_RX_NUM_BLOCK

#define USB_COUNT6_RX_NUM_BLOCK USB_COUNT6_RX_NUM_BLOCK_Msk

NUM_BLOCK[4:0] bits (Number of blocks)

Definition at line 11942 of file stm32g431xx.h.

◆ USB_COUNT6_RX_NUM_BLOCK_0

#define USB_COUNT6_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos)

0x00000400

Definition at line 11943 of file stm32g431xx.h.

◆ USB_COUNT6_RX_NUM_BLOCK_1

#define USB_COUNT6_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos)

0x00000800

Definition at line 11944 of file stm32g431xx.h.

◆ USB_COUNT6_RX_NUM_BLOCK_2

#define USB_COUNT6_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos)

0x00001000

Definition at line 11945 of file stm32g431xx.h.

◆ USB_COUNT6_RX_NUM_BLOCK_3

#define USB_COUNT6_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos)

0x00002000

Definition at line 11946 of file stm32g431xx.h.

◆ USB_COUNT6_RX_NUM_BLOCK_4

#define USB_COUNT6_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos)

0x00004000

Definition at line 11947 of file stm32g431xx.h.

◆ USB_COUNT6_RX_NUM_BLOCK_Msk

#define USB_COUNT6_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos)

0x00007C00

Definition at line 11941 of file stm32g431xx.h.

◆ USB_COUNT6_RX_NUM_BLOCK_Pos

#define USB_COUNT6_RX_NUM_BLOCK_Pos (10U)

Definition at line 11940 of file stm32g431xx.h.

◆ USB_COUNT6_TX_0_COUNT6_TX_0

#define USB_COUNT6_TX_0_COUNT6_TX_0 (0x000003FFU)

Transmission Byte Count 6 (low)

Definition at line 11772 of file stm32g431xx.h.

◆ USB_COUNT6_TX_1_COUNT6_TX_1

#define USB_COUNT6_TX_1_COUNT6_TX_1 (0x03FF0000U)

Transmission Byte Count 6 (high)

Definition at line 11775 of file stm32g431xx.h.

◆ USB_COUNT6_TX_COUNT6_TX

#define USB_COUNT6_TX_COUNT6_TX USB_COUNT6_TX_COUNT6_TX_Msk

Transmission Byte Count 6

Definition at line 11726 of file stm32g431xx.h.

◆ USB_COUNT6_TX_COUNT6_TX_Msk

#define USB_COUNT6_TX_COUNT6_TX_Msk (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos)

0x000003FF

Definition at line 11725 of file stm32g431xx.h.

◆ USB_COUNT6_TX_COUNT6_TX_Pos

#define USB_COUNT6_TX_COUNT6_TX_Pos (0U)

Definition at line 11724 of file stm32g431xx.h.

◆ USB_COUNT7_RX_0_BLSIZE_0

#define USB_COUNT7_RX_0_BLSIZE_0 (0x00008000U)

BLock SIZE (low)

Definition at line 12151 of file stm32g431xx.h.

◆ USB_COUNT7_RX_0_COUNT7_RX_0

#define USB_COUNT7_RX_0_COUNT7_RX_0 (0x000003FFU)

Reception Byte Count (low)

Definition at line 12142 of file stm32g431xx.h.

◆ USB_COUNT7_RX_0_NUM_BLOCK_0

#define USB_COUNT7_RX_0_NUM_BLOCK_0 (0x00007C00U)

NUM_BLOCK_0[4:0] bits (Number of blocks) (low)

Definition at line 12144 of file stm32g431xx.h.

◆ USB_COUNT7_RX_0_NUM_BLOCK_0_0

#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 (0x00000400U)

Bit 0

Definition at line 12145 of file stm32g431xx.h.

◆ USB_COUNT7_RX_0_NUM_BLOCK_0_1

#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 (0x00000800U)

Bit 1

Definition at line 12146 of file stm32g431xx.h.

◆ USB_COUNT7_RX_0_NUM_BLOCK_0_2

#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 (0x00001000U)

Bit 2

Definition at line 12147 of file stm32g431xx.h.

◆ USB_COUNT7_RX_0_NUM_BLOCK_0_3

#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 (0x00002000U)

Bit 3

Definition at line 12148 of file stm32g431xx.h.

◆ USB_COUNT7_RX_0_NUM_BLOCK_0_4

#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 (0x00004000U)

Bit 4

Definition at line 12149 of file stm32g431xx.h.

◆ USB_COUNT7_RX_1_BLSIZE_1

#define USB_COUNT7_RX_1_BLSIZE_1 (0x80000000U)

BLock SIZE (high)

Definition at line 12163 of file stm32g431xx.h.

◆ USB_COUNT7_RX_1_COUNT7_RX_1

#define USB_COUNT7_RX_1_COUNT7_RX_1 (0x03FF0000U)

Reception Byte Count (high)

Definition at line 12154 of file stm32g431xx.h.

◆ USB_COUNT7_RX_1_NUM_BLOCK_1

#define USB_COUNT7_RX_1_NUM_BLOCK_1 (0x7C000000U)

NUM_BLOCK_1[4:0] bits (Number of blocks) (high)

Definition at line 12156 of file stm32g431xx.h.

◆ USB_COUNT7_RX_1_NUM_BLOCK_1_0

#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 (0x04000000U)

Bit 0

Definition at line 12157 of file stm32g431xx.h.

◆ USB_COUNT7_RX_1_NUM_BLOCK_1_1

#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 (0x08000000U)

Bit 1

Definition at line 12158 of file stm32g431xx.h.

◆ USB_COUNT7_RX_1_NUM_BLOCK_1_2

#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 (0x10000000U)

Bit 2

Definition at line 12159 of file stm32g431xx.h.

◆ USB_COUNT7_RX_1_NUM_BLOCK_1_3

#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 (0x20000000U)

Bit 3

Definition at line 12160 of file stm32g431xx.h.

◆ USB_COUNT7_RX_1_NUM_BLOCK_1_4

#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 (0x40000000U)

Bit 4

Definition at line 12161 of file stm32g431xx.h.

◆ USB_COUNT7_RX_BLSIZE

#define USB_COUNT7_RX_BLSIZE USB_COUNT7_RX_BLSIZE_Msk

BLock SIZE

Definition at line 11969 of file stm32g431xx.h.

◆ USB_COUNT7_RX_BLSIZE_Msk

#define USB_COUNT7_RX_BLSIZE_Msk (0x1UL << USB_COUNT7_RX_BLSIZE_Pos)

0x00008000

Definition at line 11968 of file stm32g431xx.h.

◆ USB_COUNT7_RX_BLSIZE_Pos

#define USB_COUNT7_RX_BLSIZE_Pos (15U)

Definition at line 11967 of file stm32g431xx.h.

◆ USB_COUNT7_RX_COUNT7_RX

#define USB_COUNT7_RX_COUNT7_RX USB_COUNT7_RX_COUNT7_RX_Msk

Reception Byte Count

Definition at line 11956 of file stm32g431xx.h.

◆ USB_COUNT7_RX_COUNT7_RX_Msk

#define USB_COUNT7_RX_COUNT7_RX_Msk (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos)

0x000003FF

Definition at line 11955 of file stm32g431xx.h.

◆ USB_COUNT7_RX_COUNT7_RX_Pos

#define USB_COUNT7_RX_COUNT7_RX_Pos (0U)

Definition at line 11954 of file stm32g431xx.h.

◆ USB_COUNT7_RX_NUM_BLOCK

#define USB_COUNT7_RX_NUM_BLOCK USB_COUNT7_RX_NUM_BLOCK_Msk

NUM_BLOCK[4:0] bits (Number of blocks)

Definition at line 11960 of file stm32g431xx.h.

◆ USB_COUNT7_RX_NUM_BLOCK_0

#define USB_COUNT7_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos)

0x00000400

Definition at line 11961 of file stm32g431xx.h.

◆ USB_COUNT7_RX_NUM_BLOCK_1

#define USB_COUNT7_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos)

0x00000800

Definition at line 11962 of file stm32g431xx.h.

◆ USB_COUNT7_RX_NUM_BLOCK_2

#define USB_COUNT7_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos)

0x00001000

Definition at line 11963 of file stm32g431xx.h.

◆ USB_COUNT7_RX_NUM_BLOCK_3

#define USB_COUNT7_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos)

0x00002000

Definition at line 11964 of file stm32g431xx.h.

◆ USB_COUNT7_RX_NUM_BLOCK_4

#define USB_COUNT7_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos)

0x00004000

Definition at line 11965 of file stm32g431xx.h.

◆ USB_COUNT7_RX_NUM_BLOCK_Msk

#define USB_COUNT7_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos)

0x00007C00

Definition at line 11959 of file stm32g431xx.h.

◆ USB_COUNT7_RX_NUM_BLOCK_Pos

#define USB_COUNT7_RX_NUM_BLOCK_Pos (10U)

Definition at line 11958 of file stm32g431xx.h.

◆ USB_COUNT7_TX_0_COUNT7_TX_0

#define USB_COUNT7_TX_0_COUNT7_TX_0 (0x000003FFU)

Transmission Byte Count 7 (low)

Definition at line 11778 of file stm32g431xx.h.

◆ USB_COUNT7_TX_1_COUNT7_TX_1

#define USB_COUNT7_TX_1_COUNT7_TX_1 (0x03FF0000U)

Transmission Byte Count 7 (high)

Definition at line 11781 of file stm32g431xx.h.

◆ USB_COUNT7_TX_COUNT7_TX

#define USB_COUNT7_TX_COUNT7_TX USB_COUNT7_TX_COUNT7_TX_Msk

Transmission Byte Count 7

Definition at line 11731 of file stm32g431xx.h.

◆ USB_COUNT7_TX_COUNT7_TX_Msk

#define USB_COUNT7_TX_COUNT7_TX_Msk (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos)

0x000003FF

Definition at line 11730 of file stm32g431xx.h.

◆ USB_COUNT7_TX_COUNT7_TX_Pos

#define USB_COUNT7_TX_COUNT7_TX_Pos (0U)

Definition at line 11729 of file stm32g431xx.h.

◆ USB_DADDR

#define USB_DADDR (USB_BASE + 0x0000004CU)

Device address register

Definition at line 11566 of file stm32g431xx.h.

◆ USB_DADDR_ADD

#define USB_DADDR_ADD ((uint8_t)0x7FU)

ADD[6:0] bits (Device Address)

Definition at line 11619 of file stm32g431xx.h.

◆ USB_DADDR_ADD0

#define USB_DADDR_ADD0 ((uint8_t)0x01U)

Bit 0

Definition at line 11620 of file stm32g431xx.h.

◆ USB_DADDR_ADD1

#define USB_DADDR_ADD1 ((uint8_t)0x02U)

Bit 1

Definition at line 11621 of file stm32g431xx.h.

◆ USB_DADDR_ADD2

#define USB_DADDR_ADD2 ((uint8_t)0x04U)

Bit 2

Definition at line 11622 of file stm32g431xx.h.

◆ USB_DADDR_ADD3

#define USB_DADDR_ADD3 ((uint8_t)0x08U)

Bit 3

Definition at line 11623 of file stm32g431xx.h.

◆ USB_DADDR_ADD4

#define USB_DADDR_ADD4 ((uint8_t)0x10U)

Bit 4

Definition at line 11624 of file stm32g431xx.h.

◆ USB_DADDR_ADD5

#define USB_DADDR_ADD5 ((uint8_t)0x20U)

Bit 5

Definition at line 11625 of file stm32g431xx.h.

◆ USB_DADDR_ADD6

#define USB_DADDR_ADD6 ((uint8_t)0x40U)

Bit 6

Definition at line 11626 of file stm32g431xx.h.

◆ USB_DADDR_EF

#define USB_DADDR_EF ((uint8_t)0x80U)

Enable Function

Definition at line 11628 of file stm32g431xx.h.

◆ USB_EP0R

#define USB_EP0R USB_BASE

endpoint 0 register address

Definition at line 11509 of file stm32g431xx.h.

◆ USB_EP1R

#define USB_EP1R (USB_BASE + 0x0x00000004)

endpoint 1 register address

Definition at line 11510 of file stm32g431xx.h.

◆ USB_EP2R

#define USB_EP2R (USB_BASE + 0x0x00000008)

endpoint 2 register address

Definition at line 11511 of file stm32g431xx.h.

◆ USB_EP3R

#define USB_EP3R (USB_BASE + 0x0x0000000C)

endpoint 3 register address

Definition at line 11512 of file stm32g431xx.h.

◆ USB_EP4R

#define USB_EP4R (USB_BASE + 0x0x00000010)

endpoint 4 register address

Definition at line 11513 of file stm32g431xx.h.

◆ USB_EP5R

#define USB_EP5R (USB_BASE + 0x0x00000014)

endpoint 5 register address

Definition at line 11514 of file stm32g431xx.h.

◆ USB_EP6R

#define USB_EP6R (USB_BASE + 0x0x00000018)

endpoint 6 register address

Definition at line 11515 of file stm32g431xx.h.

◆ USB_EP7R

#define USB_EP7R (USB_BASE + 0x0x0000001C)

endpoint 7 register address

Definition at line 11516 of file stm32g431xx.h.

◆ USB_EP_BULK

#define USB_EP_BULK ((uint16_t)0x0000U)

EndPoint BULK

Definition at line 11534 of file stm32g431xx.h.

◆ USB_EP_CONTROL

#define USB_EP_CONTROL ((uint16_t)0x0200U)

EndPoint CONTROL

Definition at line 11535 of file stm32g431xx.h.

◆ USB_EP_CTR_RX

#define USB_EP_CTR_RX ((uint16_t)0x8000U)

EndPoint Correct TRansfer RX

Definition at line 11519 of file stm32g431xx.h.

◆ USB_EP_CTR_TX

#define USB_EP_CTR_TX ((uint16_t)0x0080U)

EndPoint Correct TRansfer TX

Definition at line 11525 of file stm32g431xx.h.

◆ USB_EP_DTOG_RX

#define USB_EP_DTOG_RX ((uint16_t)0x4000U)

EndPoint Data TOGGLE RX

Definition at line 11520 of file stm32g431xx.h.

◆ USB_EP_DTOG_TX

#define USB_EP_DTOG_TX ((uint16_t)0x0040U)

EndPoint Data TOGGLE TX

Definition at line 11526 of file stm32g431xx.h.

◆ USB_EP_INTERRUPT

#define USB_EP_INTERRUPT ((uint16_t)0x0600U)

EndPoint INTERRUPT

Definition at line 11537 of file stm32g431xx.h.

◆ USB_EP_ISOCHRONOUS

#define USB_EP_ISOCHRONOUS ((uint16_t)0x0400U)

EndPoint ISOCHRONOUS

Definition at line 11536 of file stm32g431xx.h.

◆ USB_EP_KIND

#define USB_EP_KIND ((uint16_t)0x0100U)

EndPoint KIND

Definition at line 11524 of file stm32g431xx.h.

◆ USB_EP_RX_DIS

#define USB_EP_RX_DIS ((uint16_t)0x0000U)

EndPoint RX DISabled

Definition at line 11550 of file stm32g431xx.h.

◆ USB_EP_RX_NAK

#define USB_EP_RX_NAK ((uint16_t)0x2000U)

EndPoint RX NAKed

Definition at line 11552 of file stm32g431xx.h.

◆ USB_EP_RX_STALL

#define USB_EP_RX_STALL ((uint16_t)0x1000U)

EndPoint RX STALLed

Definition at line 11551 of file stm32g431xx.h.

◆ USB_EP_RX_VALID

#define USB_EP_RX_VALID ((uint16_t)0x3000U)

EndPoint RX VALID

Definition at line 11553 of file stm32g431xx.h.

◆ USB_EP_SETUP

#define USB_EP_SETUP ((uint16_t)0x0800U)

EndPoint SETUP

Definition at line 11522 of file stm32g431xx.h.

◆ USB_EP_T_FIELD

#define USB_EP_T_FIELD ((uint16_t)0x0600U)

EndPoint TYPE

Definition at line 11523 of file stm32g431xx.h.

◆ USB_EP_T_MASK

#define USB_EP_T_MASK ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)

Definition at line 11538 of file stm32g431xx.h.

◆ USB_EP_TX_DIS

#define USB_EP_TX_DIS ((uint16_t)0x0000U)

EndPoint TX DISabled

Definition at line 11542 of file stm32g431xx.h.

◆ USB_EP_TX_NAK

#define USB_EP_TX_NAK ((uint16_t)0x0020U)

EndPoint TX NAKed

Definition at line 11544 of file stm32g431xx.h.

◆ USB_EP_TX_STALL

#define USB_EP_TX_STALL ((uint16_t)0x0010U)

EndPoint TX STALLed

Definition at line 11543 of file stm32g431xx.h.

◆ USB_EP_TX_VALID

#define USB_EP_TX_VALID ((uint16_t)0x0030U)

EndPoint TX VALID

Definition at line 11545 of file stm32g431xx.h.

◆ USB_EP_TYPE_MASK

#define USB_EP_TYPE_MASK ((uint16_t)0x0600U)

EndPoint TYPE Mask

Definition at line 11533 of file stm32g431xx.h.

◆ USB_EPADDR_FIELD

#define USB_EPADDR_FIELD ((uint16_t)0x000FU)

EndPoint ADDRess FIELD

Definition at line 11528 of file stm32g431xx.h.

◆ USB_EPKIND_MASK

#define USB_EPKIND_MASK ((uint16_t)~USB_EP_KIND & USB_EPREG_MASK)

EP_KIND EndPoint KIND STAT_TX[1:0] STATus for TX transfer

Definition at line 11541 of file stm32g431xx.h.

◆ USB_EPREG_MASK

EP_TYPE[1:0] EndPoint TYPE

Definition at line 11532 of file stm32g431xx.h.

◆ USB_EPRX_DTOG1

#define USB_EPRX_DTOG1 ((uint16_t)0x1000U)

EndPoint RX Data TOGgle bit1

Definition at line 11554 of file stm32g431xx.h.

◆ USB_EPRX_DTOG2

#define USB_EPRX_DTOG2 ((uint16_t)0x2000U)

EndPoint RX Data TOGgle bit1

Definition at line 11555 of file stm32g431xx.h.

◆ USB_EPRX_DTOGMASK

#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)

Definition at line 11556 of file stm32g431xx.h.

◆ USB_EPRX_STAT

#define USB_EPRX_STAT ((uint16_t)0x3000U)

EndPoint RX STATus bit field

Definition at line 11521 of file stm32g431xx.h.

◆ USB_EPTX_DTOG1

#define USB_EPTX_DTOG1 ((uint16_t)0x0010U)

EndPoint TX Data TOGgle bit1

Definition at line 11546 of file stm32g431xx.h.

◆ USB_EPTX_DTOG2

#define USB_EPTX_DTOG2 ((uint16_t)0x0020U)

EndPoint TX Data TOGgle bit2

Definition at line 11547 of file stm32g431xx.h.

◆ USB_EPTX_DTOGMASK

#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)

STAT_RX[1:0] STATus for RX transfer

Definition at line 11549 of file stm32g431xx.h.

◆ USB_EPTX_STAT

#define USB_EPTX_STAT ((uint16_t)0x0030U)

EndPoint TX STATus bit field

Definition at line 11527 of file stm32g431xx.h.

◆ USB_FNR

#define USB_FNR (USB_BASE + 0x00000048U)

Frame number register

Definition at line 11565 of file stm32g431xx.h.

◆ USB_FNR_FN

#define USB_FNR_FN ((uint16_t)0x07FFU)

Frame Number

Definition at line 11612 of file stm32g431xx.h.

◆ USB_FNR_LCK

#define USB_FNR_LCK ((uint16_t)0x2000U)

LoCKed

Definition at line 11614 of file stm32g431xx.h.

◆ USB_FNR_LSOF

#define USB_FNR_LSOF ((uint16_t)0x1800U)

Lost SOF

Definition at line 11613 of file stm32g431xx.h.

◆ USB_FNR_RXDM

#define USB_FNR_RXDM ((uint16_t)0x4000U)

status of D- data line

Definition at line 11615 of file stm32g431xx.h.

◆ USB_FNR_RXDP

#define USB_FNR_RXDP ((uint16_t)0x8000U)

status of D+ data line

Definition at line 11616 of file stm32g431xx.h.

◆ USB_ISTR

#define USB_ISTR (USB_BASE + 0x00000044U)

Interrupt status register

Definition at line 11564 of file stm32g431xx.h.

◆ USB_ISTR_CTR

#define USB_ISTR_CTR ((uint16_t)0x8000U)

Correct TRansfer (clear-only bit)

Definition at line 11599 of file stm32g431xx.h.

◆ USB_ISTR_DIR

#define USB_ISTR_DIR ((uint16_t)0x0010U)

DIRection of transaction (read-only bit)

Definition at line 11590 of file stm32g431xx.h.

◆ USB_ISTR_EP_ID

#define USB_ISTR_EP_ID ((uint16_t)0x000FU)

EndPoint IDentifier (read-only bit)

Definition at line 11589 of file stm32g431xx.h.

◆ USB_ISTR_ERR

#define USB_ISTR_ERR ((uint16_t)0x2000U)

ERRor (clear-only bit)

Definition at line 11597 of file stm32g431xx.h.

◆ USB_ISTR_ESOF

#define USB_ISTR_ESOF ((uint16_t)0x0100U)

Expected Start Of Frame (clear-only bit)

Definition at line 11592 of file stm32g431xx.h.

◆ USB_ISTR_L1REQ

#define USB_ISTR_L1REQ ((uint16_t)0x0080U)

LPM L1 state request

Definition at line 11591 of file stm32g431xx.h.

◆ USB_ISTR_PMAOVR

#define USB_ISTR_PMAOVR ((uint16_t)0x4000U)

DMA OVeR/underrun (clear-only bit)

Definition at line 11598 of file stm32g431xx.h.

◆ USB_ISTR_RESET

#define USB_ISTR_RESET ((uint16_t)0x0400U)

RESET (clear-only bit)

Definition at line 11594 of file stm32g431xx.h.

◆ USB_ISTR_SOF

#define USB_ISTR_SOF ((uint16_t)0x0200U)

Start Of Frame (clear-only bit)

Definition at line 11593 of file stm32g431xx.h.

◆ USB_ISTR_SUSP

#define USB_ISTR_SUSP ((uint16_t)0x0800U)

SUSPend (clear-only bit)

Definition at line 11595 of file stm32g431xx.h.

◆ USB_ISTR_WKUP

#define USB_ISTR_WKUP ((uint16_t)0x1000U)

WaKe UP (clear-only bit)

Definition at line 11596 of file stm32g431xx.h.

◆ USB_LPMCSR

#define USB_LPMCSR (USB_BASE + 0x00000054U)

LPM Control and Status register

Definition at line 11568 of file stm32g431xx.h.

◆ USB_LPMCSR_BESL

#define USB_LPMCSR_BESL ((uint16_t)0x00F0U)

BESL value received with last ACKed LPM Token
Buffer descriptor table

Definition at line 11650 of file stm32g431xx.h.

◆ USB_LPMCSR_LMPEN

#define USB_LPMCSR_LMPEN ((uint16_t)0x0001U)

LPM support enable

Definition at line 11645 of file stm32g431xx.h.

◆ USB_LPMCSR_LPMACK

#define USB_LPMCSR_LPMACK ((uint16_t)0x0002U)

LPM Token acknowledge enable

Definition at line 11646 of file stm32g431xx.h.

◆ USB_LPMCSR_REMWAKE

#define USB_LPMCSR_REMWAKE ((uint16_t)0x0008U)

bRemoteWake value received with last ACKed LPM Token

Definition at line 11647 of file stm32g431xx.h.

◆ VREFBUF_CCR_TRIM

#define VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk

TRIM[5:0] bits (Trimming code)

Definition at line 11502 of file stm32g431xx.h.

◆ VREFBUF_CCR_TRIM_Msk

#define VREFBUF_CCR_TRIM_Msk (0x3FUL << VREFBUF_CCR_TRIM_Pos)

0x0000003F

Definition at line 11501 of file stm32g431xx.h.

◆ VREFBUF_CCR_TRIM_Pos

#define VREFBUF_CCR_TRIM_Pos (0U)

Definition at line 11500 of file stm32g431xx.h.

◆ VREFBUF_CSR_ENVR

#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk

Voltage reference buffer enable

Definition at line 11486 of file stm32g431xx.h.

◆ VREFBUF_CSR_ENVR_Msk

#define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos)

0x00000001

Definition at line 11485 of file stm32g431xx.h.

◆ VREFBUF_CSR_ENVR_Pos

#define VREFBUF_CSR_ENVR_Pos (0U)

Definition at line 11484 of file stm32g431xx.h.

◆ VREFBUF_CSR_HIZ

#define VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk

High impedance mode

Definition at line 11489 of file stm32g431xx.h.

◆ VREFBUF_CSR_HIZ_Msk

#define VREFBUF_CSR_HIZ_Msk (0x1UL << VREFBUF_CSR_HIZ_Pos)

0x00000002

Definition at line 11488 of file stm32g431xx.h.

◆ VREFBUF_CSR_HIZ_Pos

#define VREFBUF_CSR_HIZ_Pos (1U)

Definition at line 11487 of file stm32g431xx.h.

◆ VREFBUF_CSR_VRR

#define VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk

Voltage reference buffer ready

Definition at line 11492 of file stm32g431xx.h.

◆ VREFBUF_CSR_VRR_Msk

#define VREFBUF_CSR_VRR_Msk (0x1UL << VREFBUF_CSR_VRR_Pos)

0x00000008

Definition at line 11491 of file stm32g431xx.h.

◆ VREFBUF_CSR_VRR_Pos

#define VREFBUF_CSR_VRR_Pos (3U)

Definition at line 11490 of file stm32g431xx.h.

◆ VREFBUF_CSR_VRS

#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk

VRS[5:0] bits (Voltage reference scale)

Definition at line 11495 of file stm32g431xx.h.

◆ VREFBUF_CSR_VRS_0

#define VREFBUF_CSR_VRS_0 (0x1UL << VREFBUF_CSR_VRS_Pos)

0x00000010

Definition at line 11496 of file stm32g431xx.h.

◆ VREFBUF_CSR_VRS_1

#define VREFBUF_CSR_VRS_1 (0x2UL << VREFBUF_CSR_VRS_Pos)

0x00000020

Definition at line 11497 of file stm32g431xx.h.

◆ VREFBUF_CSR_VRS_Msk

#define VREFBUF_CSR_VRS_Msk (0x3UL << VREFBUF_CSR_VRS_Pos)

0x00000030

Definition at line 11494 of file stm32g431xx.h.

◆ VREFBUF_CSR_VRS_Pos

#define VREFBUF_CSR_VRS_Pos (4U)

Definition at line 11493 of file stm32g431xx.h.

◆ WWDG_CFR_EWI

#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk

Early Wakeup Interrupt

Definition at line 12527 of file stm32g431xx.h.

◆ WWDG_CFR_EWI_Msk

#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos)

0x00000200

Definition at line 12526 of file stm32g431xx.h.

◆ WWDG_CFR_EWI_Pos

#define WWDG_CFR_EWI_Pos (9U)

Definition at line 12525 of file stm32g431xx.h.

◆ WWDG_CFR_W

#define WWDG_CFR_W WWDG_CFR_W_Msk

W[6:0] bits (7-bit window value)

Definition at line 12509 of file stm32g431xx.h.

◆ WWDG_CFR_W_0

#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos)

0x00000001

Definition at line 12510 of file stm32g431xx.h.

◆ WWDG_CFR_W_1

#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos)

0x00000002

Definition at line 12511 of file stm32g431xx.h.

◆ WWDG_CFR_W_2

#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos)

0x00000004

Definition at line 12512 of file stm32g431xx.h.

◆ WWDG_CFR_W_3

#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos)

0x00000008

Definition at line 12513 of file stm32g431xx.h.

◆ WWDG_CFR_W_4

#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos)

0x00000010

Definition at line 12514 of file stm32g431xx.h.

◆ WWDG_CFR_W_5

#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos)

0x00000020

Definition at line 12515 of file stm32g431xx.h.

◆ WWDG_CFR_W_6

#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos)

0x00000040

Definition at line 12516 of file stm32g431xx.h.

◆ WWDG_CFR_W_Msk

#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos)

0x0000007F

Definition at line 12508 of file stm32g431xx.h.

◆ WWDG_CFR_W_Pos

#define WWDG_CFR_W_Pos (0U)

Definition at line 12507 of file stm32g431xx.h.

◆ WWDG_CFR_WDGTB

#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk

WDGTB[2:0] bits (Timer Base)

Definition at line 12520 of file stm32g431xx.h.

◆ WWDG_CFR_WDGTB_0

#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos)

0x00000800

Definition at line 12521 of file stm32g431xx.h.

◆ WWDG_CFR_WDGTB_1

#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos)

0x00001000

Definition at line 12522 of file stm32g431xx.h.

◆ WWDG_CFR_WDGTB_2

#define WWDG_CFR_WDGTB_2 (0x4UL << WWDG_CFR_WDGTB_Pos)

0x00002000

Definition at line 12523 of file stm32g431xx.h.

◆ WWDG_CFR_WDGTB_Msk

#define WWDG_CFR_WDGTB_Msk (0x7UL << WWDG_CFR_WDGTB_Pos)

0x00003800

Definition at line 12519 of file stm32g431xx.h.

◆ WWDG_CFR_WDGTB_Pos

#define WWDG_CFR_WDGTB_Pos (11U)

Definition at line 12518 of file stm32g431xx.h.

◆ WWDG_CR_T

#define WWDG_CR_T WWDG_CR_T_Msk

T[6:0] bits (7-Bit counter (MSB to LSB))

Definition at line 12493 of file stm32g431xx.h.

◆ WWDG_CR_T_0

#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos)

0x00000001

Definition at line 12494 of file stm32g431xx.h.

◆ WWDG_CR_T_1

#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos)

0x00000002

Definition at line 12495 of file stm32g431xx.h.

◆ WWDG_CR_T_2

#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos)

0x00000004

Definition at line 12496 of file stm32g431xx.h.

◆ WWDG_CR_T_3

#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos)

0x00000008

Definition at line 12497 of file stm32g431xx.h.

◆ WWDG_CR_T_4

#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos)

0x00000010

Definition at line 12498 of file stm32g431xx.h.

◆ WWDG_CR_T_5

#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos)

0x00000020

Definition at line 12499 of file stm32g431xx.h.

◆ WWDG_CR_T_6

#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos)

0x00000040

Definition at line 12500 of file stm32g431xx.h.

◆ WWDG_CR_T_Msk

#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos)

0x0000007F

Definition at line 12492 of file stm32g431xx.h.

◆ WWDG_CR_T_Pos

#define WWDG_CR_T_Pos (0U)

Definition at line 12491 of file stm32g431xx.h.

◆ WWDG_CR_WDGA

#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk

Activation bit

Definition at line 12504 of file stm32g431xx.h.

◆ WWDG_CR_WDGA_Msk

#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos)

0x00000080

Definition at line 12503 of file stm32g431xx.h.

◆ WWDG_CR_WDGA_Pos

#define WWDG_CR_WDGA_Pos (7U)

Definition at line 12502 of file stm32g431xx.h.

◆ WWDG_SR_EWIF

#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk

Early Wakeup Interrupt Flag

Definition at line 12532 of file stm32g431xx.h.

◆ WWDG_SR_EWIF_Msk

#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos)

0x00000001

Definition at line 12531 of file stm32g431xx.h.

◆ WWDG_SR_EWIF_Pos

#define WWDG_SR_EWIF_Pos (0U)

Definition at line 12530 of file stm32g431xx.h.

Macros

Detailed Description

Macro Definition Documentation

◆ ADC_AWD2CR_AWD2CH

◆ ADC_AWD2CR_AWD2CH_0

◆ ADC_AWD2CR_AWD2CH_1

◆ ADC_AWD2CR_AWD2CH_10

◆ ADC_AWD2CR_AWD2CH_11

◆ ADC_AWD2CR_AWD2CH_12

◆ ADC_AWD2CR_AWD2CH_13

◆ ADC_AWD2CR_AWD2CH_14

◆ ADC_AWD2CR_AWD2CH_15

◆ ADC_AWD2CR_AWD2CH_16

◆ ADC_AWD2CR_AWD2CH_17

◆ ADC_AWD2CR_AWD2CH_18

◆ ADC_AWD2CR_AWD2CH_2

◆ ADC_AWD2CR_AWD2CH_3

◆ ADC_AWD2CR_AWD2CH_4

◆ ADC_AWD2CR_AWD2CH_5

◆ ADC_AWD2CR_AWD2CH_6

◆ ADC_AWD2CR_AWD2CH_7

◆ ADC_AWD2CR_AWD2CH_8

◆ ADC_AWD2CR_AWD2CH_9

◆ ADC_AWD2CR_AWD2CH_Msk

◆ ADC_AWD2CR_AWD2CH_Pos

◆ ADC_AWD3CR_AWD3CH

◆ ADC_AWD3CR_AWD3CH_0

◆ ADC_AWD3CR_AWD3CH_1

◆ ADC_AWD3CR_AWD3CH_10

◆ ADC_AWD3CR_AWD3CH_11

◆ ADC_AWD3CR_AWD3CH_12

◆ ADC_AWD3CR_AWD3CH_13

◆ ADC_AWD3CR_AWD3CH_14

◆ ADC_AWD3CR_AWD3CH_15

◆ ADC_AWD3CR_AWD3CH_16

◆ ADC_AWD3CR_AWD3CH_17

◆ ADC_AWD3CR_AWD3CH_18

◆ ADC_AWD3CR_AWD3CH_2

◆ ADC_AWD3CR_AWD3CH_3

◆ ADC_AWD3CR_AWD3CH_4

◆ ADC_AWD3CR_AWD3CH_5

◆ ADC_AWD3CR_AWD3CH_6

◆ ADC_AWD3CR_AWD3CH_7

◆ ADC_AWD3CR_AWD3CH_8

◆ ADC_AWD3CR_AWD3CH_9

◆ ADC_AWD3CR_AWD3CH_Msk

◆ ADC_AWD3CR_AWD3CH_Pos

◆ ADC_CALFACT_CALFACT_D

◆ ADC_CALFACT_CALFACT_D_0

◆ ADC_CALFACT_CALFACT_D_1

◆ ADC_CALFACT_CALFACT_D_2

◆ ADC_CALFACT_CALFACT_D_3

◆ ADC_CALFACT_CALFACT_D_4

◆ ADC_CALFACT_CALFACT_D_5

◆ ADC_CALFACT_CALFACT_D_6

◆ ADC_CALFACT_CALFACT_D_Msk

◆ ADC_CALFACT_CALFACT_D_Pos

◆ ADC_CALFACT_CALFACT_S

◆ ADC_CALFACT_CALFACT_S_0

◆ ADC_CALFACT_CALFACT_S_1

◆ ADC_CALFACT_CALFACT_S_2

◆ ADC_CALFACT_CALFACT_S_3

◆ ADC_CALFACT_CALFACT_S_4

◆ ADC_CALFACT_CALFACT_S_5

◆ ADC_CALFACT_CALFACT_S_6

◆ ADC_CALFACT_CALFACT_S_Msk

◆ ADC_CALFACT_CALFACT_S_Pos

◆ ADC_CCR_CKMODE

◆ ADC_CCR_CKMODE_0

◆ ADC_CCR_CKMODE_1

◆ ADC_CCR_CKMODE_Msk

◆ ADC_CCR_CKMODE_Pos

◆ ADC_CCR_DELAY

◆ ADC_CCR_DELAY_0

◆ ADC_CCR_DELAY_1

◆ ADC_CCR_DELAY_2

◆ ADC_CCR_DELAY_3

◆ ADC_CCR_DELAY_Msk

◆ ADC_CCR_DELAY_Pos

◆ ADC_CCR_DMACFG